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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_txethmac.v] - Blame information for rev 43

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1 15 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_txethmac.v                                              ////
4
////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
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////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
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////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
14
////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
//
43
// CVS Revision History
44
//
45
// $Log: not supported by cvs2svn $
46 43 mohor
// Revision 1.4  2002/01/23 10:28:16  mohor
47
// Link in the header changed.
48
//
49 37 mohor
// Revision 1.3  2001/10/19 08:43:51  mohor
50
// eth_timescale.v changed to timescale.v This is done because of the
51
// simulation of the few cores in a one joined project.
52
//
53 22 mohor
// Revision 1.2  2001/09/11 14:17:00  mohor
54
// Few little NCSIM warnings fixed.
55
//
56 18 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
57
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
58
// Include files fixed to contain no path.
59
// File names and module names changed ta have a eth_ prologue in the name.
60
// File eth_timescale.v is used to define timescale
61
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
62
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
63
// and Mdo_OE. The bidirectional signal must be created on the top level. This
64
// is done due to the ASIC tools.
65
//
66 15 mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
67
// Directory structure changed. Files checked and joind together.
68
//
69
// Revision 1.3  2001/06/19 18:16:40  mohor
70
// TxClk changed to MTxClk (as discribed in the documentation).
71
// Crc changed so only one file can be used instead of two.
72
//
73
// Revision 1.2  2001/06/19 10:38:08  mohor
74
// Minor changes in header.
75
//
76
// Revision 1.1  2001/06/19 10:27:58  mohor
77
// TxEthMAC initial release.
78
//
79
//
80
//
81
 
82 22 mohor
`include "timescale.v"
83 15 mohor
 
84
 
85
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
86
                     Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
87
                     IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
88
                     MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
89 43 mohor
                     ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
90
                     LateCollision, StartDefer, StatePreamble, StateData
91
 
92 15 mohor
                    );
93
 
94
parameter Tp = 1;
95
 
96
 
97
input MTxClk;                   // Transmit clock (from PHY)
98
input Reset;                    // Reset
99
input TxStartFrm;               // Transmit packet start frame
100
input TxEndFrm;                 // Transmit packet end frame
101
input TxUnderRun;               // Transmit packet under-run
102
input [7:0] TxData;             // Transmit packet data byte
103
input CarrierSense;             // Carrier sense (synchronized)
104
input Collision;                // Collision (synchronized)
105
input Pad;                      // Pad enable (from register)
106
input CrcEn;                    // Crc enable (from register)
107
input FullD;                    // Full duplex (from register)
108
input HugEn;                    // Huge packets enable (from register)
109
input DlyCrcEn;                 // Delayed Crc enabled (from register)
110
input [15:0] MinFL;             // Minimum frame length (from register)
111
input [15:0] MaxFL;             // Maximum frame length (from register)
112
input [6:0] IPGT;               // Back to back transmit inter packet gap parameter (from register)
113
input [6:0] IPGR1;              // Non back to back transmit inter packet gap parameter IPGR1 (from register)
114
input [6:0] IPGR2;              // Non back to back transmit inter packet gap parameter IPGR2 (from register)
115
input [5:0] CollValid;          // Valid collision window (from register)
116
input [3:0] MaxRet;             // Maximum retry number (from register)
117
input NoBckof;                  // No backoff (from register)
118
input ExDfrEn;                  // Excessive defferal enable (from register)
119
 
120
output [3:0] MTxD;              // Transmit nibble (to PHY)
121
output MTxEn;                   // Transmit enable (to PHY)
122
output MTxErr;                  // Transmit error (to PHY)
123
output TxDone;                  // Transmit packet done (to RISC)
124
output TxRetry;                 // Transmit packet retry (to RISC)
125
output TxAbort;                 // Transmit packet abort (to RISC)
126
output TxUsedData;              // Transmit packet used data (to RISC)
127
output WillTransmit;            // Will transmit (to RxEthMAC)
128
output ResetCollision;          // Reset Collision (for synchronizing collision)
129 43 mohor
output [3:0] RetryCnt;          // Latched Retry Counter for tx status purposes
130
output StartTxDone;
131
output StartTxAbort;
132
output MaxCollisionOccured;
133
output LateCollision;
134
output StartDefer;
135
output StatePreamble;
136
output [1:0] StateData;
137 15 mohor
 
138
reg [3:0] MTxD;
139
reg MTxEn;
140
reg MTxErr;
141
reg TxDone;
142
reg TxRetry;
143
reg TxAbort;
144
reg TxUsedData;
145
reg WillTransmit;
146
reg ColWindow;
147
reg StopExcessiveDeferOccured;
148
reg [3:0] RetryCnt;
149
reg [3:0] MTxD_d;
150
reg StatusLatch;
151
reg PacketFinished_q;
152
reg PacketFinished;
153 43 mohor
reg [3:0] RetryCntLatched;
154 15 mohor
 
155
 
156
wire ExcessiveDeferOccured;
157
wire StartIPG;
158
wire StartPreamble;
159
wire [1:0] StartData;
160
wire StartFCS;
161
wire StartJam;
162
wire StartBackoff;
163
wire StateDefer;
164
wire StateIPG;
165
wire StateIdle;
166
wire StatePAD;
167
wire StateFCS;
168
wire StateJam;
169
wire StateBackOff;
170
wire StateSFD;
171
wire StartTxRetry;
172
wire UnderRun;
173
wire TooBig;
174
wire [31:0] Crc;
175
wire CrcError;
176
wire [2:0] DlyCrcCnt;
177
wire [15:0] NibCnt;
178
wire NibCntEq7;
179
wire NibCntEq15;
180
wire NibbleMinFl;
181
wire ExcessiveDefer;
182
wire [15:0] ByteCnt;
183
wire MaxFrame;
184
wire RetryMax;
185
wire RandomEq0;
186
wire RandomEqByteCnt;
187
wire PacketFinished_d;
188
 
189
 
190
 
191 18 mohor
assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
192 15 mohor
 
193
assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
194
 
195
assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & ~Pad & ~CrcEn);
196
 
197
assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
198
 
199
assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
200
 
201
assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
202
 
203
assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
204
 
205
assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
206
 
207
assign StateSFD = StatePreamble & NibCntEq15;
208
 
209
assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
210
 
211
 
212
// StopExcessiveDeferOccured
213
always @ (posedge MTxClk or posedge Reset)
214
begin
215
  if(Reset)
216
    StopExcessiveDeferOccured <= #Tp 1'b0;
217
  else
218
    begin
219
      if(~TxStartFrm)
220
        StopExcessiveDeferOccured <= #Tp 1'b0;
221
      else
222
      if(ExcessiveDeferOccured)
223
        StopExcessiveDeferOccured <= #Tp 1'b1;
224
    end
225
end
226
 
227
 
228
// Collision Window
229
always @ (posedge MTxClk or posedge Reset)
230
begin
231
  if(Reset)
232
    ColWindow <= #Tp 1'b1;
233
  else
234
    begin
235
      if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
236
        ColWindow <= #Tp 1'b0;
237
      else
238
      if(StateIdle | StateIPG)
239
        ColWindow <= #Tp 1'b1;
240
    end
241
end
242
 
243
 
244
// Start Window
245
always @ (posedge MTxClk or posedge Reset)
246
begin
247
  if(Reset)
248
    StatusLatch <= #Tp 1'b0;
249
  else
250
    begin
251
      if(~TxStartFrm)
252
        StatusLatch <= #Tp 1'b0;
253
      else
254
      if(ExcessiveDeferOccured | StateIdle)
255
        StatusLatch <= #Tp 1'b1;
256
     end
257
end
258
 
259
 
260
// Transmit packet used data
261
always @ (posedge MTxClk or posedge Reset)
262
begin
263
  if(Reset)
264
    TxUsedData <= #Tp 1'b0;
265
  else
266
    TxUsedData <= #Tp |StartData;
267
end
268
 
269
 
270
// Transmit packet done
271
always @ (posedge MTxClk or posedge Reset)
272
begin
273
  if(Reset)
274
    TxDone <= #Tp 1'b0;
275
  else
276
    begin
277
      if(TxStartFrm & ~StatusLatch)
278
        TxDone <= #Tp 1'b0;
279
      else
280
      if(StartTxDone)
281
        TxDone <= #Tp 1'b1;
282
    end
283
end
284
 
285
 
286
// Transmit packet retry
287
always @ (posedge MTxClk or posedge Reset)
288
begin
289
  if(Reset)
290
    TxRetry <= #Tp 1'b0;
291
  else
292
    begin
293
      if(TxStartFrm & ~StatusLatch)
294
        TxRetry <= #Tp 1'b0;
295
      else
296
      if(StartTxRetry)
297
        TxRetry <= #Tp 1'b1;
298
     end
299
end
300
 
301
 
302
// Transmit packet abort
303
always @ (posedge MTxClk or posedge Reset)
304
begin
305
  if(Reset)
306
    TxAbort <= #Tp 1'b0;
307
  else
308
    begin
309
      if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
310
        TxAbort <= #Tp 1'b0;
311
      else
312
      if(StartTxAbort)
313
        TxAbort <= #Tp 1'b1;
314
    end
315
end
316
 
317
 
318
// Retry counter
319
always @ (posedge MTxClk or posedge Reset)
320
begin
321
  if(Reset)
322
    RetryCnt[3:0] <= #Tp 4'h0;
323
  else
324
    begin
325
      if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
326
          | StateJam & NibCntEq7 & (~ColWindow | RetryMax))
327
        RetryCnt[3:0] <= #Tp 4'h0;
328
      else
329
      if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
330
        RetryCnt[3:0] <= #Tp RetryCnt[3:0] + 1'b1;
331
    end
332
end
333
 
334
 
335
assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
336
 
337
 
338
// Transmit nibble
339
always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
340
          Crc or NibCnt or NibCntEq15)
341
begin
342
  if(StateData[0])
343
    MTxD_d[3:0] = TxData[3:0];                                  // Lower nibble
344
  else
345
  if(StateData[1])
346
    MTxD_d[3:0] = TxData[7:4];                                  // Higher nibble
347
  else
348
  if(StateFCS)
349
    MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]};     // Crc
350
  else
351
  if(StateJam)
352
    MTxD_d[3:0] = 4'h9;                                         // Jam pattern
353
  else
354
  if(StatePreamble)
355
    if(NibCntEq15)
356
      MTxD_d[3:0] = 4'hd;                                       // SFD
357
    else
358
      MTxD_d[3:0] = 4'h5;                                       // Preamble
359
  else
360
    MTxD_d[3:0] = 4'h0;
361
end
362
 
363
 
364
// Transmit Enable
365
always @ (posedge MTxClk or posedge Reset)
366
begin
367
  if(Reset)
368
    MTxEn <= #Tp 1'b0;
369
  else
370 18 mohor
    MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
371 15 mohor
end
372
 
373
 
374
// Transmit nibble
375
always @ (posedge MTxClk or posedge Reset)
376
begin
377
  if(Reset)
378
    MTxD[3:0] <= #Tp 4'h0;
379
  else
380
    MTxD[3:0] <= #Tp MTxD_d[3:0];
381
end
382
 
383
 
384
// Transmit error
385
always @ (posedge MTxClk or posedge Reset)
386
begin
387
  if(Reset)
388
    MTxErr <= #Tp 1'b0;
389
  else
390
    MTxErr <= #Tp TooBig | UnderRun;
391
end
392
 
393
 
394
// WillTransmit
395
always @ (posedge MTxClk or posedge Reset)
396
begin
397
  if(Reset)
398
    WillTransmit <= #Tp  1'b0;
399
  else
400 18 mohor
    WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
401 15 mohor
end
402
 
403
 
404
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
405
 
406
 
407
// Packet finished
408
always @ (posedge MTxClk or posedge Reset)
409
begin
410
  if(Reset)
411
    begin
412
      PacketFinished <= #Tp 1'b0;
413
      PacketFinished_q  <= #Tp 1'b0;
414
    end
415
  else
416
    begin
417
      PacketFinished <= #Tp PacketFinished_d;
418
      PacketFinished_q  <= #Tp PacketFinished;
419
    end
420
end
421
 
422
 
423
// Connecting module Counters
424
eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
425
                            .StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
426
                            .StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
427
                            .StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
428
                            .Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
429
                            .PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
430
                            .StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
431
                            .NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
432
                            .DlyCrcCnt(DlyCrcCnt)
433
                           );
434
 
435
 
436
// Connecting module StateM
437
eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
438
                        .NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
439
                        .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
440
                        .UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
441
                        .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
442
                        .NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
443
                        .NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
444
                        .StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
445
                        .StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
446
                        .StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
447
                        .StartDefer(StartDefer), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
448
                       );
449
 
450
 
451
wire Enable_Crc;
452
wire [3:0] Data_Crc;
453
wire Initialize_Crc;
454
 
455
assign Enable_Crc = ~StateFCS;
456
 
457
assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
458
assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
459
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
460
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
461
 
462 18 mohor
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
463 15 mohor
 
464
 
465
// Connecting module Crc
466
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
467
               .Crc(Crc), .CrcError(CrcError)
468
              );
469
 
470
 
471
// Connecting module Random
472
eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
473
                    .NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
474
 
475
 
476
 
477
 
478
endmodule

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