OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_txstatem.v] - Blame information for rev 338

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_txstatem.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
11
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
12
////                                                              ////
13
////  All additional information is avaliable in the Readme.txt   ////
14
////  file.                                                       ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2001 Authors                                   ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
//
43
// CVS Revision History
44
//
45
// $Log: not supported by cvs2svn $
46 236 mohor
// Revision 1.4  2002/01/23 10:28:16  mohor
47
// Link in the header changed.
48
//
49 37 mohor
// Revision 1.3  2001/10/19 08:43:51  mohor
50
// eth_timescale.v changed to timescale.v This is done because of the
51
// simulation of the few cores in a one joined project.
52
//
53 22 mohor
// Revision 1.2  2001/09/11 14:17:00  mohor
54
// Few little NCSIM warnings fixed.
55
//
56 18 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
57
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
58
// Include files fixed to contain no path.
59
// File names and module names changed ta have a eth_ prologue in the name.
60
// File eth_timescale.v is used to define timescale
61
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
62
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
63
// and Mdo_OE. The bidirectional signal must be created on the top level. This
64
// is done due to the ASIC tools.
65
//
66 15 mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
67
// Directory structure changed. Files checked and joind together.
68
//
69
// Revision 1.3  2001/06/19 18:16:40  mohor
70
// TxClk changed to MTxClk (as discribed in the documentation).
71
// Crc changed so only one file can be used instead of two.
72
//
73
// Revision 1.2  2001/06/19 10:38:07  mohor
74
// Minor changes in header.
75
//
76
// Revision 1.1  2001/06/19 10:27:57  mohor
77
// TxEthMAC initial release.
78
//
79
//
80
//
81
//
82
 
83
 
84 22 mohor
`include "timescale.v"
85 15 mohor
 
86
 
87
module eth_txstatem  (MTxClk, Reset, ExcessiveDefer, CarrierSense, NibCnt, IPGT, IPGR1,
88
                      IPGR2, FullD, TxStartFrm, TxEndFrm, TxUnderRun, Collision, UnderRun,
89
                      StartTxDone, TooBig, NibCntEq7, NibCntEq15, MaxFrame, Pad, CrcEn,
90
                      NibbleMinFl, RandomEq0, ColWindow, RetryMax, NoBckof, RandomEqByteCnt,
91
                      StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS,
92
                      StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam,
93
                      StartBackoff, StartDefer, StartPreamble, StartData, StartIPG
94
                     );
95
 
96
parameter Tp = 1;
97
 
98
input MTxClk;
99
input Reset;
100
input ExcessiveDefer;
101
input CarrierSense;
102
input [6:0] NibCnt;
103
input [6:0] IPGT;
104
input [6:0] IPGR1;
105
input [6:0] IPGR2;
106
input FullD;
107
input TxStartFrm;
108
input TxEndFrm;
109
input TxUnderRun;
110
input Collision;
111
input UnderRun;
112
input StartTxDone;
113
input TooBig;
114
input NibCntEq7;
115
input NibCntEq15;
116
input MaxFrame;
117
input Pad;
118
input CrcEn;
119
input NibbleMinFl;
120
input RandomEq0;
121
input ColWindow;
122
input RetryMax;
123
input NoBckof;
124
input RandomEqByteCnt;
125
 
126
 
127
output StateIdle;         // Idle state
128
output StateIPG;          // IPG state
129
output StatePreamble;     // Preamble state
130
output [1:0] StateData;   // Data state
131
output StatePAD;          // PAD state
132
output StateFCS;          // FCS state
133
output StateJam;          // Jam state
134
output StateJam_q;        // Delayed Jam state
135
output StateBackOff;      // Backoff state
136
output StateDefer;        // Defer state
137
 
138
output StartFCS;          // FCS state will be activated in next clock
139
output StartJam;          // Jam state will be activated in next clock
140
output StartBackoff;      // Backoff state will be activated in next clock
141
output StartDefer;        // Defer state will be activated in next clock
142
output StartPreamble;     // Preamble state will be activated in next clock
143
output [1:0] StartData;   // Data state will be activated in next clock
144
output StartIPG;          // IPG state will be activated in next clock
145
 
146
wire StartIdle;           // Idle state will be activated in next clock
147
wire StartPAD;            // PAD state will be activated in next clock
148
 
149
 
150
reg StateIdle;
151
reg StateIPG;
152
reg StatePreamble;
153
reg [1:0] StateData;
154
reg StatePAD;
155
reg StateFCS;
156
reg StateJam;
157
reg StateJam_q;
158
reg StateBackOff;
159
reg StateDefer;
160
reg Rule1;
161
 
162
 
163
// Defining the next state
164
assign StartIPG = StateDefer & ~ExcessiveDefer & ~CarrierSense;
165
 
166
assign StartIdle = StateIPG & (Rule1 & NibCnt[6:0] >= IPGT | ~Rule1 & NibCnt[6:0] >= IPGR2);
167
 
168 236 mohor
assign StartPreamble = StateIdle & TxStartFrm & ~CarrierSense;
169 15 mohor
 
170
assign StartData[0] = ~Collision & (StatePreamble & NibCntEq15 | StateData[1] & ~TxEndFrm);
171
 
172
assign StartData[1] = ~Collision & StateData[0] & ~TxUnderRun & ~MaxFrame;
173
 
174
assign StartPAD = ~Collision & StateData[1] & TxEndFrm & Pad & ~NibbleMinFl;
175
 
176 236 mohor
assign StartFCS = ~Collision & StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & CrcEn
177
                | ~Collision & StatePAD & NibbleMinFl & CrcEn;
178 15 mohor
 
179 18 mohor
assign StartJam = (Collision | UnderRun) & ((StatePreamble & NibCntEq15) | (|StateData[1:0]) | StatePAD | StateFCS);
180 15 mohor
 
181
assign StartBackoff = StateJam & ~RandomEq0 & ColWindow & ~RetryMax & NibCntEq7 & ~NoBckof;
182
 
183
assign StartDefer = StateIPG & ~Rule1 & CarrierSense & NibCnt[6:0] <= IPGR1 & NibCnt[6:0] != IPGR2
184 236 mohor
                  | StateIdle & CarrierSense
185 15 mohor
                  | StateJam & NibCntEq7 & (NoBckof | RandomEq0 | ~ColWindow | RetryMax)
186
                  | StateBackOff & (TxUnderRun | RandomEqByteCnt)
187
                  | StartTxDone | TooBig;
188
 
189
 
190
 
191
// Tx State Machine
192
always @ (posedge MTxClk or posedge Reset)
193
begin
194
  if(Reset)
195
    begin
196
      StateIPG        <= #Tp 1'b0;
197
      StateIdle       <= #Tp 1'b0;
198
      StatePreamble   <= #Tp 1'b0;
199
      StateData[1:0]  <= #Tp 2'b0;
200
      StatePAD        <= #Tp 1'b0;
201
      StateFCS        <= #Tp 1'b0;
202
      StateJam        <= #Tp 1'b0;
203
      StateJam_q      <= #Tp 1'b0;
204
      StateBackOff    <= #Tp 1'b0;
205
      StateDefer      <= #Tp 1'b1;
206
    end
207
  else
208
    begin
209
      StateData[1:0] <= #Tp StartData[1:0];
210
      StateJam_q <= #Tp StateJam;
211
 
212
      if(StartDefer | StartIdle)
213
        StateIPG <= #Tp 1'b0;
214
      else
215
      if(StartIPG)
216
        StateIPG <= #Tp 1'b1;
217
 
218
      if(StartDefer | StartPreamble)
219
        StateIdle <= #Tp 1'b0;
220
      else
221
      if(StartIdle)
222
        StateIdle <= #Tp 1'b1;
223
 
224
      if(StartData[0] | StartJam)
225
        StatePreamble <= #Tp 1'b0;
226
      else
227
      if(StartPreamble)
228
        StatePreamble <= #Tp 1'b1;
229
 
230
      if(StartFCS | StartJam)
231
        StatePAD <= #Tp 1'b0;
232
      else
233
      if(StartPAD)
234
        StatePAD <= #Tp 1'b1;
235
 
236
      if(StartJam | StartDefer)
237
        StateFCS <= #Tp 1'b0;
238
      else
239
      if(StartFCS)
240
        StateFCS <= #Tp 1'b1;
241
 
242
      if(StartBackoff | StartDefer)
243
        StateJam <= #Tp 1'b0;
244
      else
245
      if(StartJam)
246
        StateJam <= #Tp 1'b1;
247
 
248
      if(StartDefer)
249
        StateBackOff <= #Tp 1'b0;
250
      else
251
      if(StartBackoff)
252
        StateBackOff <= #Tp 1'b1;
253
 
254
      if(StartIPG)
255
        StateDefer <= #Tp 1'b0;
256
      else
257
      if(StartDefer)
258
        StateDefer <= #Tp 1'b1;
259
    end
260
end
261
 
262
 
263
// This sections defines which interpack gap rule to use
264
always @ (posedge MTxClk or posedge Reset)
265
begin
266
  if(Reset)
267
    Rule1 <= #Tp 1'b0;
268
  else
269
    begin
270
      if(StateIdle | StateBackOff)
271
        Rule1 <= #Tp 1'b0;
272
      else
273
      if(StatePreamble | FullD)
274
        Rule1 <= #Tp 1'b1;
275
    end
276
end
277
 
278
 
279
 
280
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.