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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_wishbone.v                                              ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is available in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001, 2002 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.40  2002/10/14 16:07:02  mohor
// TxStatus is written after last access to the TX fifo is finished (in case of abort
// or retry). TxDone is fixed.
//
// Revision 1.39  2002/10/11 15:35:20  mohor
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
// TxDone and TxRetry are generated after the current WISHBONE access is
// finished.
//
// Revision 1.38  2002/10/10 16:29:30  mohor
// BIST added.
//
// Revision 1.37  2002/09/11 14:18:46  mohor
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
//
// Revision 1.36  2002/09/10 13:48:46  mohor
// Reception is possible after RxPointer is read and not after BD is read. For
// that reason RxBDReady is changed to RxReady.
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
// comes, interrupt is generated.
//
// Revision 1.35  2002/09/10 10:35:23  mohor
// Ethernet debug registers removed.
//
// Revision 1.34  2002/09/08 16:31:49  mohor
// Async reset for WB_ACK_O removed (when core was in reset, it was
// impossible to access BDs).
// RxPointers and TxPointers names changed to be more descriptive.
// TxUnderRun synchronized.
//
// Revision 1.33  2002/09/04 18:47:57  mohor
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
// was not used OK.
//
// Revision 1.32  2002/08/14 19:31:48  mohor
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
// need to multiply or devide any more.
//
// Revision 1.31  2002/07/25 18:29:01  mohor
// WriteRxDataToMemory signal changed so end of frame (when last word is
// written to fifo) is changed.
//
// Revision 1.30  2002/07/23 15:28:31  mohor
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
//
// Revision 1.29  2002/07/20 00:41:32  mohor
// ShiftEnded synchronization changed.
//
// Revision 1.28  2002/07/18 16:11:46  mohor
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
//
// Revision 1.27  2002/07/11 02:53:20  mohor
// RxPointer bug fixed.
//
// Revision 1.26  2002/07/10 13:12:38  mohor
// Previous bug wasn't succesfully removed. Now fixed.
//
// Revision 1.25  2002/07/09 23:53:24  mohor
// Master state machine had a bug when switching from master write to
// master read.
//
// Revision 1.24  2002/07/09 20:44:41  mohor
// m_wb_cyc_o signal released after every single transfer.
//
// Revision 1.23  2002/05/03 10:15:50  mohor
// Outputs registered. Reset changed for eth_wishbone module.
//
// Revision 1.22  2002/04/24 08:52:19  mohor
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
// bug fixed.
//
// Revision 1.21  2002/03/29 16:18:11  lampret
// Small typo fixed.
//
// Revision 1.20  2002/03/25 16:19:12  mohor
// Any address can be used for Tx and Rx BD pointers. Address does not need
// to be aligned.
//
// Revision 1.19  2002/03/19 12:51:50  mohor
// Comments in Slovene language removed.
//
// Revision 1.18  2002/03/19 12:46:52  mohor
// casex changed with case, fifo reset changed.
//
// Revision 1.17  2002/03/09 16:08:45  mohor
// rx_fifo was not always cleared ok. Fixed.
//
// Revision 1.16  2002/03/09 13:51:20  mohor
// Status was not latched correctly sometimes. Fixed.
//
// Revision 1.15  2002/03/08 06:56:46  mohor
// Big Endian problem when sending frames fixed.
//
// Revision 1.14  2002/03/02 19:12:40  mohor
// Byte ordering changed (Big Endian used). casex changed with case because
// Xilinx Foundation had problems. Tested in HW. It WORKS.
//
// Revision 1.13  2002/02/26 16:59:55  mohor
// Small fixes for external/internal DMA missmatches.
//
// Revision 1.12  2002/02/26 16:22:07  mohor
// Interrupts changed
//
// Revision 1.11  2002/02/15 17:07:39  mohor
// Status was not written correctly when frames were discarted because of
// address mismatch.
//
// Revision 1.10  2002/02/15 12:17:39  mohor
// RxStartFrm cleared when abort or retry comes.
//
// Revision 1.9  2002/02/15 11:59:10  mohor
// Changes that were lost when updating from 1.5 to 1.8 fixed.
//
// Revision 1.8  2002/02/14 20:54:33  billditt
// Addition  of new module eth_addrcheck.v
//
// Revision 1.7  2002/02/12 17:03:47  mohor
// RxOverRun added to statuses.
//
// Revision 1.6  2002/02/11 09:18:22  mohor
// Tx status is written back to the BD.
//
// Revision 1.5  2002/02/08 16:21:54  mohor
// Rx status is written back to the BD.
//
// Revision 1.4  2002/02/06 14:10:21  mohor
// non-DMA host interface added. Select the right configutation in eth_defines.
//
// Revision 1.3  2002/02/05 16:44:39  mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still  need
// to be fixed.
//
// Revision 1.2  2002/02/01 12:46:51  mohor
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
// added.
//
// Revision 1.1  2002/01/23 10:47:59  mohor
// Initial version. Equals to eth_wishbonedma.v at this moment.
//
//
//
 
`include "eth_defines.v"
`include "timescale.v"
 
 
module eth_wishbone
   (
 
    // WISHBONE common
    WB_CLK_I, WB_DAT_I, WB_DAT_O,
 
    // WISHBONE slave
                WB_ADR_I, WB_WE_I, WB_ACK_O,
    BDCs,
 
    Reset,
 
    // WISHBONE master
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
 
`ifdef ETH_WISHBONE_B3
    m_wb_cti_o, m_wb_bte_o,
`endif
 
    //TX
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
    PerPacketPad,
 
    //RX
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
 
    // Register
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr,
 
    // Interrupts
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
 
    // Rx Status
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
 
    // Tx Status
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
 
    // Bist
`ifdef ETH_BIST
   , trst, SO, SI, shift_DR, capture_DR, extest, tck
`endif
 
 
 
                );
 
 
parameter Tp = 1;
 
 
// WISHBONE common
input           WB_CLK_I;       // WISHBONE clock
input  [31:0]   WB_DAT_I;       // WISHBONE data input
output [31:0]   WB_DAT_O;       // WISHBONE data output
 
// WISHBONE slave
input   [9:2]   WB_ADR_I;       // WISHBONE address input
input           WB_WE_I;        // WISHBONE write enable input
input           BDCs;           // Buffer descriptors are selected
output          WB_ACK_O;       // WISHBONE acknowledge output
 
// WISHBONE master
output  [31:0]  m_wb_adr_o;     // 
output   [3:0]  m_wb_sel_o;     // 
output          m_wb_we_o;      // 
output  [31:0]  m_wb_dat_o;     // 
output          m_wb_cyc_o;     // 
output          m_wb_stb_o;     // 
input   [31:0]  m_wb_dat_i;     // 
input           m_wb_ack_i;     // 
input           m_wb_err_i;     // 
 
`ifdef ETH_WISHBONE_B3
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
`endif
 
input           Reset;       // Reset signal
 
// Rx Status signals
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
input           LatchedCrcError;  // CRC error
input           RxLateCollision;  // Late collision occured while receiving frame
input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
input           DribbleNibble;    // Extra nibble received
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
input    [15:0] RxLength;         // Length of the incoming frame
input           LoadRxStatus;     // Rx status was loaded
input           ReceivedPacketGood;// Received packet's length and CRC are good
 
// Tx Status signals
input     [3:0] RetryCntLatched;  // Latched Retry Counter
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
input           LateCollLatched;  // Late collision occured
input           DeferLatched;     // Defer indication (Frame was defered before sucessfully sent)
input           CarrierSenseLost; // Carrier Sense was lost during the frame transmission
 
// Tx
input           MTxClk;         // Transmit clock (from PHY)
input           TxUsedData;     // Transmit packet used data
input           TxRetry;        // Transmit packet retry
input           TxAbort;        // Transmit packet abort
input           TxDone;         // Transmission ended
output          TxStartFrm;     // Transmit packet start frame
output          TxEndFrm;       // Transmit packet end frame
output  [7:0]   TxData;         // Transmit packet data byte
output          TxUnderRun;     // Transmit packet under-run
output          PerPacketCrcEn; // Per packet crc enable
output          PerPacketPad;   // Per packet pading
 
// Rx
input           MRxClk;         // Receive clock (from PHY)
input   [7:0]   RxData;         // Received data byte (from PHY)
input           RxValid;        // 
input           RxStartFrm;     // 
input           RxEndFrm;       // 
input           RxAbort;        // This signal is set when address doesn't match.
 
//Register
input           r_TxEn;         // Transmit enable
input           r_RxEn;         // Receive enable
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
input           TX_BD_NUM_Wr;   // RxBDNumber written
 
// Interrupts
output TxB_IRQ;
output TxE_IRQ;
output RxB_IRQ;
output RxE_IRQ;
output Busy_IRQ;
 
 
// Bist
`ifdef ETH_BIST
input           trst;
input           shift_DR, capture_DR, tck, extest;
input           SI;
output          SO;
`endif
 
reg TxB_IRQ;
reg TxE_IRQ;
reg RxB_IRQ;
reg RxE_IRQ;
 
reg             TxStartFrm;
reg             TxEndFrm;
reg     [7:0]   TxData;
 
reg             TxUnderRun;
reg             TxUnderRun_wb;
 
reg             TxBDRead;
wire            TxStatusWrite;
 
reg     [1:0]   TxValidBytesLatched;
 
reg    [15:0]   TxLength;
reg    [15:0]   LatchedTxLength;
reg   [14:11]   TxStatus;
 
reg   [14:13]   RxStatus;
 
reg             TxStartFrm_wb;
reg             TxRetry_wb;
reg             TxAbort_wb;
reg             TxDone_wb;
 
reg             TxDone_wb_q;
reg             TxAbort_wb_q;
reg             TxRetry_wb_q;
reg             TxRetryPacket;
reg             TxRetryPacket_NotCleared;
reg             TxDonePacket;
reg             TxDonePacket_NotCleared;
reg             TxAbortPacket;
reg             TxAbortPacket_NotCleared;
reg             RxBDReady;
reg             RxReady;
reg             TxBDReady;
 
reg             RxBDRead;
wire            RxStatusWrite;
 
reg    [31:0]   TxDataLatched;
reg     [1:0]   TxByteCnt;
reg             LastWord;
reg             ReadTxDataFromFifo_tck;
 
reg             BlockingTxStatusWrite;
reg             BlockingTxBDRead;
 
reg             Flop;
 
reg     [7:0]   TxBDAddress;
reg     [7:0]   RxBDAddress;
 
reg             TxRetrySync1;
reg             TxAbortSync1;
reg             TxDoneSync1;
 
reg             TxAbort_q;
reg             TxRetry_q;
reg             TxUsedData_q;
 
reg    [31:0]   RxDataLatched2;
 
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
 
reg     [1:0]   RxValidBytes;
reg     [1:0]   RxByteCnt;
reg             LastByteIn;
reg             ShiftWillEnd;
 
reg             WriteRxDataToFifo;
reg    [15:0]   LatchedRxLength;
reg             RxAbortLatched;
 
reg             ShiftEnded;
reg             RxOverrun;
 
reg             BDWrite;                    // BD Write Enable for access from WISHBONE side
reg             BDRead;                     // BD Read access from WISHBONE side
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
 
reg             TxEndFrm_wb;
 
wire            TxRetryPulse;
wire            TxDonePulse;
wire            TxAbortPulse;
 
wire            StartRxBDRead;
 
wire            StartTxBDRead;
 
wire            TxIRQEn;
wire            WrapTxStatusBit;
 
wire            RxIRQEn;
wire            WrapRxStatusBit;
 
wire    [1:0]   TxValidBytes;
 
wire    [7:0]   TempTxBDAddress;
wire    [7:0]   TempRxBDAddress;
 
wire            SetGotData;
wire            GotDataEvaluate;
 
reg             WB_ACK_O;
 
wire    [6:0]   RxStatusIn;
reg     [6:0]   RxStatusInLatched;
 
reg WbEn, WbEn_q;
reg RxEn, RxEn_q;
reg TxEn, TxEn_q;
 
wire ram_ce;
wire ram_we;
wire ram_oe;
reg [7:0]   ram_addr;
reg [31:0]  ram_di;
wire [31:0] ram_do;
 
wire StartTxPointerRead;
reg  TxPointerRead;
reg TxEn_needed;
reg RxEn_needed;
 
wire StartRxPointerRead;
reg RxPointerRead;
 
`ifdef ETH_WISHBONE_B3
assign m_wb_bte_o = 2'b00;    // Linear burst
`endif
 
 
always @ (posedge WB_CLK_I)
begin
  WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
end
 
assign WB_DAT_O = ram_do;
 
// Generic synchronous single-port RAM interface
eth_spram_256x32 bd_ram (
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
`ifdef ETH_BIST
  , .trst(trst), .SO(SO), .SI(SI), .shift_DR(shift_DR), .capture_DR(capture_DR), .extest(extest), .tck(tck)
`endif
);
 
assign ram_ce = 1'b1;
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
 
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxEn_needed <=#Tp 1'b0;
  else
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
    TxEn_needed <=#Tp 1'b1;
  else
  if(TxPointerRead & TxEn & TxEn_q)
    TxEn_needed <=#Tp 1'b0;
end
 
// Enabling access to the RAM for three devices.
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    begin
      WbEn <=#Tp 1'b1;
      RxEn <=#Tp 1'b0;
      TxEn <=#Tp 1'b0;
      ram_addr <=#Tp 8'h0;
      ram_di <=#Tp 32'h0;
      BDRead <=#Tp 1'b0;
      BDWrite <=#Tp 1'b0;
    end
  else
    begin
      // Switching between three stages depends on enable signals
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
        5'b100_10, 5'b100_11 :
          begin
            WbEn <=#Tp 1'b0;
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
            TxEn <=#Tp 1'b0;
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
            ram_di <=#Tp RxBDDataIn;
          end
        5'b100_01 :
          begin
            WbEn <=#Tp 1'b0;
            RxEn <=#Tp 1'b0;
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
            ram_di <=#Tp TxBDDataIn;
          end
        5'b010_00, 5'b010_10 :
          begin
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
            RxEn <=#Tp 1'b0;
            TxEn <=#Tp 1'b0;
            ram_addr <=#Tp WB_ADR_I[9:2];
            ram_di <=#Tp WB_DAT_I;
            BDWrite <=#Tp BDCs & WB_WE_I;
            BDRead <=#Tp BDCs & ~WB_WE_I;
          end
        5'b010_01, 5'b010_11 :
          begin
            WbEn <=#Tp 1'b0;
            RxEn <=#Tp 1'b0;
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
            ram_di <=#Tp TxBDDataIn;
          end
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
          begin
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
            RxEn <=#Tp 1'b0;
            TxEn <=#Tp 1'b0;
            ram_addr <=#Tp WB_ADR_I[9:2];
            ram_di <=#Tp WB_DAT_I;
            BDWrite <=#Tp BDCs & WB_WE_I;
            BDRead <=#Tp BDCs & ~WB_WE_I;
          end
        5'b100_00 :
          begin
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
          end
        5'b000_00 :
          begin
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
            RxEn <=#Tp 1'b0;
            TxEn <=#Tp 1'b0;
            ram_addr <=#Tp WB_ADR_I[9:2];
            ram_di <=#Tp WB_DAT_I;
            BDWrite <=#Tp BDCs & WB_WE_I;
            BDRead <=#Tp BDCs & ~WB_WE_I;
          end
      endcase
    end
end
 
 
// Delayed stage signals
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    begin
      WbEn_q <=#Tp 1'b0;
      RxEn_q <=#Tp 1'b0;
      TxEn_q <=#Tp 1'b0;
    end
  else
    begin
      WbEn_q <=#Tp WbEn;
      RxEn_q <=#Tp RxEn;
      TxEn_q <=#Tp TxEn;
    end
end
 
// Changes for tx occur every second clock. Flop is used for this manner.
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    Flop <=#Tp 1'b0;
  else
  if(TxDone | TxAbort | TxRetry_q)
    Flop <=#Tp 1'b0;
  else
  if(TxUsedData)
    Flop <=#Tp ~Flop;
end
 
wire ResetTxBDReady;
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
 
// Latching READY status of the Tx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxBDReady <=#Tp 1'b0;
  else
  if(TxEn & TxEn_q & TxBDRead)
    TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
  else                                                // Only packets larger then 4 bytes are transmitted.
  if(ResetTxBDReady)
    TxBDReady <=#Tp 1'b0;
end
 
 
// Reading the Tx buffer descriptor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxBDRead <=#Tp 1'b1;
  else
  if(StartTxBDRead)
    TxBDRead <=#Tp 1'b1;
  else
  if(TxBDReady)
    TxBDRead <=#Tp 1'b0;
end
 
 
// Reading Tx BD pointer
assign StartTxPointerRead = TxBDRead & TxBDReady;
 
// Reading Tx BD Pointer
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxPointerRead <=#Tp 1'b0;
  else
  if(StartTxPointerRead)
    TxPointerRead <=#Tp 1'b1;
  else
  if(TxEn_q)
    TxPointerRead <=#Tp 1'b0;
end
 
 
// Writing status back to the Tx buffer descriptor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
 
 
 
// Status writing must occur only once. Meanwhile it is blocked.
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    BlockingTxStatusWrite <=#Tp 1'b0;
  else
  if(TxStatusWrite)
    BlockingTxStatusWrite <=#Tp 1'b1;
  else
  if(~TxDone_wb & ~TxAbort_wb)
    BlockingTxStatusWrite <=#Tp 1'b0;
end
 
 
reg BlockingTxStatusWrite_sync1;
reg BlockingTxStatusWrite_sync2;
 
// Synchronizing BlockingTxStatusWrite to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
  else
    BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
end
 
// Synchronizing BlockingTxStatusWrite to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
  else
    BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
end
 
 
// TxBDRead state is activated only once. 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    BlockingTxBDRead <=#Tp 1'b0;
  else
  if(StartTxBDRead)
    BlockingTxBDRead <=#Tp 1'b1;
  else
  if(~StartTxBDRead & ~TxBDReady)
    BlockingTxBDRead <=#Tp 1'b0;
end
 
 
// Latching status from the tx buffer descriptor
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxStatus <=#Tp 4'h0;
  else
  if(TxEn & TxEn_q & TxBDRead)
    TxStatus <=#Tp ram_do[14:11];
end
 
reg ReadTxDataFromMemory;
wire WriteRxDataToMemory;
 
reg MasterWbTX;
reg MasterWbRX;
 
reg [31:0] m_wb_adr_o;
reg        m_wb_cyc_o;
reg        m_wb_stb_o;
reg  [3:0] m_wb_sel_o;
reg        m_wb_we_o;
 
wire TxLengthEq0;
wire TxLengthLt4;
 
reg BlockingIncrementTxPointer;
reg [31:2] TxPointerMSB;
reg [1:0]  TxPointerLSB;
reg [1:0]  TxPointerLSB_rst;
reg [31:2] RxPointerMSB;
reg [1:0]  RxPointerLSB_rst;
 
wire RxBurstAcc;
wire RxWordAcc;
wire RxHalfAcc;
wire RxByteAcc;
 
//Latching length from the buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxLength <=#Tp 16'h0;
  else
  if(TxEn & TxEn_q & TxBDRead)
    TxLength <=#Tp ram_do[31:16];
  else
  if(MasterWbTX & m_wb_ack_i)
    begin
      if(TxLengthLt4)
        TxLength <=#Tp 16'h0;
      else
      if(TxPointerLSB_rst==2'h0)
        TxLength <=#Tp TxLength - 3'h4;    // Length is subtracted at the data request
      else
      if(TxPointerLSB_rst==2'h1)
        TxLength <=#Tp TxLength - 3'h3;    // Length is subtracted at the data request
      else
      if(TxPointerLSB_rst==2'h2)
        TxLength <=#Tp TxLength - 3'h2;    // Length is subtracted at the data request
      else
      if(TxPointerLSB_rst==2'h3)
        TxLength <=#Tp TxLength - 3'h1;    // Length is subtracted at the data request
    end
end
 
 
 
//Latching length from the buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    LatchedTxLength <=#Tp 16'h0;
  else
  if(TxEn & TxEn_q & TxBDRead)
    LatchedTxLength <=#Tp ram_do[31:16];
end
 
assign TxLengthEq0 = TxLength == 0;
assign TxLengthLt4 = TxLength < 4;
 
reg cyc_cleared;
reg IncrTxPointer;
 
 
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
// because TxPointerMSB is only used for word-aligned accesses.
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxPointerMSB <=#Tp 30'h0;
  else
  if(TxEn & TxEn_q & TxPointerRead)
    TxPointerMSB <=#Tp ram_do[31:2];
  else
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
    TxPointerMSB <=#Tp TxPointerMSB + 1'b1;     // TxPointer is word-aligned
end
 
 
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
// set by this two bits.
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxPointerLSB[1:0] <=#Tp 0;
  else
  if(TxEn & TxEn_q & TxPointerRead)
    TxPointerLSB[1:0] <=#Tp ram_do[1:0];
end
 
 
// Latching 2 MSB bits of the buffer descriptor. 
// After the read access, TxLength needs to be decremented for the number of the valid
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are 
// valid so this two bits are reset to zero. 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxPointerLSB_rst[1:0] <=#Tp 0;
  else
  if(TxEn & TxEn_q & TxPointerRead)
    TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
  else
  if(MasterWbTX & m_wb_ack_i)                 // After first access pointer is word alligned
    TxPointerLSB_rst[1:0] <=#Tp 0;
end
 
 
reg  [3:0] RxByteSel;
wire MasterAccessFinished;
 
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    BlockingIncrementTxPointer <=#Tp 0;
  else
  if(MasterAccessFinished)
    BlockingIncrementTxPointer <=#Tp 0;
  else
  if(IncrTxPointer)
    BlockingIncrementTxPointer <=#Tp 1'b1;
end
 
 
wire TxBufferAlmostFull;
wire TxBufferFull;
wire TxBufferEmpty;
wire TxBufferAlmostEmpty;
wire SetReadTxDataFromMemory;
 
reg BlockReadTxDataFromMemory;
 
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    ReadTxDataFromMemory <=#Tp 1'b0;
  else
  if(TxLengthEq0 | TxAbortPacket | TxRetryPacket)
    ReadTxDataFromMemory <=#Tp 1'b0;
  else
  if(SetReadTxDataFromMemory)
    ReadTxDataFromMemory <=#Tp 1'b1;
end
 
reg tx_burst_en;
reg rx_burst_en;
reg BlockingLastReadOn_Abort_Retry;
 
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory & ~BlockingLastReadOn_Abort_Retry;
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
 
wire [31:0] TxData_wb;
wire ReadTxDataFromFifo_wb;
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    BlockReadTxDataFromMemory <=#Tp 1'b0;
  else
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (!(TxAbortPacket | TxRetryPacket)))
    BlockReadTxDataFromMemory <=#Tp 1'b1;
  else
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
    BlockReadTxDataFromMemory <=#Tp 1'b0;
end
 
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
  else
  if(TxAbortPacket | TxRetryPacket)
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
  else
  if(((TxAbort_wb & !TxAbortPacket_NotCleared) | (TxRetry_wb & !TxRetryPacket_NotCleared)) & !TxBDReady)
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b1;
end
 
 
 
 
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
 
wire rx_burst;
wire enough_data_in_rxfifo_for_burst;
wire enough_data_in_rxfifo_for_burst_plus1;
reg [3:0] StateM;
// Enabling master wishbone access to the memory for two devices TX and RX.
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    begin
StateM<=#Tp 4'h0;
      MasterWbTX <=#Tp 1'b0;
      MasterWbRX <=#Tp 1'b0;
      m_wb_adr_o <=#Tp 32'h0;
      m_wb_cyc_o <=#Tp 1'b0;
      m_wb_stb_o <=#Tp 1'b0;
      m_wb_we_o  <=#Tp 1'b0;
      m_wb_sel_o <=#Tp 4'h0;
      cyc_cleared<=#Tp 1'b0;
      tx_burst_cnt<=#Tp 0;
      rx_burst_cnt<=#Tp 0;
      IncrTxPointer<=#Tp 1'b0;
      tx_burst_en<=#Tp 1'b1;
      rx_burst_en<=#Tp 1'b0;
      `ifdef ETH_WISHBONE_B3
        m_wb_cti_o <=#Tp 3'b0;
      `endif
    end
  else
    begin
      // Switching between two stages depends on enable signals
//      casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst})  // synopsys parallel_case
      case ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst})  // synopsys parallel_case
        8'b00_10_00_10,             // Idle and MRB needed
 
//        8'b10_1x_10_1x,             // MRB continues
        8'b10_10_10_10,             // MRB continues
        8'b10_10_10_11,             // MRB continues
        8'b10_11_10_10,             // MRB continues
        8'b10_11_10_11,             // MRB continues
 
        8'b10_10_01_10,             // Clear (previously MR) and MRB needed
 
//        8'b01_1x_01_1x :            // Clear (previously MW) and MRB needed
        8'b01_10_01_10 ,            // Clear (previously MW) and MRB needed
        8'b01_10_01_11 ,            // Clear (previously MW) and MRB needed
        8'b01_11_01_10 ,            // Clear (previously MW) and MRB needed
        8'b01_11_01_11 :            // Clear (previously MW) and MRB needed
          begin
StateM<=#Tp 4'h1;
            MasterWbTX <=#Tp 1'b1;  // tx burst
            MasterWbRX <=#Tp 1'b0;
            m_wb_cyc_o <=#Tp 1'b1;
            m_wb_stb_o <=#Tp 1'b1;
            m_wb_we_o  <=#Tp 1'b0;
            m_wb_sel_o <=#Tp 4'hf;
            cyc_cleared<=#Tp 1'b0;
            IncrTxPointer<=#Tp 1'b1;
            tx_burst_cnt <=#Tp tx_burst_cnt+1;
            if(tx_burst_cnt==0)
              m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
            else
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
 
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
              begin
                tx_burst_en<=#Tp 1'b0;
              `ifdef ETH_WISHBONE_B3
                m_wb_cti_o <=#Tp 3'b111;
              `endif
              end
            else
              begin
              `ifdef ETH_WISHBONE_B3
                m_wb_cti_o <=#Tp 3'b010;
              `endif
              end
          end
//        8'b00_x1_00_x1,             // Idle and MWB needed
        8'b00_01_00_01,             // Idle and MWB needed
        8'b00_01_00_11,             // Idle and MWB needed
        8'b00_11_00_01,             // Idle and MWB needed
        8'b00_11_00_11,             // Idle and MWB needed
 
//        8'b01_x1_10_x1,             // MWB continues
        8'b01_01_10_01,             // MWB continues
        8'b01_01_10_11,             // MWB continues
        8'b01_11_10_01,             // MWB continues
        8'b01_11_10_11,             // MWB continues
 
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
 
//        8'b10_x1_01_x1 :            // Clear (previously MR) and MWB needed
        8'b10_01_01_01 ,            // Clear (previously MR) and MWB needed
        8'b10_01_01_11 ,            // Clear (previously MR) and MWB needed
        8'b10_11_01_01 ,            // Clear (previously MR) and MWB needed
        8'b10_11_01_11 :            // Clear (previously MR) and MWB needed
          begin
StateM<=#Tp 4'h2;
            MasterWbTX <=#Tp 1'b0;  // rx burst
            MasterWbRX <=#Tp 1'b1;
            m_wb_cyc_o <=#Tp 1'b1;
            m_wb_stb_o <=#Tp 1'b1;
            m_wb_we_o  <=#Tp 1'b1;
            m_wb_sel_o <=#Tp RxByteSel;
            IncrTxPointer<=#Tp 1'b0;
            cyc_cleared<=#Tp 1'b0;
            rx_burst_cnt <=#Tp rx_burst_cnt+1;
 
            if(rx_burst_cnt==0)
              m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
            else
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
 
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
              begin
                rx_burst_en<=#Tp 1'b0;
              `ifdef ETH_WISHBONE_B3
                m_wb_cti_o <=#Tp 3'b111;
              `endif
              end
            else
              begin
              `ifdef ETH_WISHBONE_B3
                m_wb_cti_o <=#Tp 3'b010;
              `endif
              end
          end
//        8'b00_x1_00_x0 :            // idle and MW is needed (data write to rx buffer)
        8'b00_01_00_00 ,            // idle and MW is needed (data write to rx buffer)
        8'b00_01_00_10 ,            // idle and MW is needed (data write to rx buffer)
        8'b00_11_00_00 ,            // idle and MW is needed (data write to rx buffer)
        8'b00_11_00_10 :            // idle and MW is needed (data write to rx buffer)
          begin
StateM<=#Tp 4'h3;
            MasterWbTX <=#Tp 1'b0;
            MasterWbRX <=#Tp 1'b1;
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
            m_wb_cyc_o <=#Tp 1'b1;
            m_wb_stb_o <=#Tp 1'b1;
            m_wb_we_o  <=#Tp 1'b1;
            m_wb_sel_o <=#Tp RxByteSel;
            IncrTxPointer<=#Tp 1'b0;
          end
        8'b00_10_00_00 :            // idle and MR is needed (data read from tx buffer)
          begin
StateM<=#Tp 4'h4;
            MasterWbTX <=#Tp 1'b1;
            MasterWbRX <=#Tp 1'b0;
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
            m_wb_cyc_o <=#Tp 1'b1;
            m_wb_stb_o <=#Tp 1'b1;
            m_wb_we_o  <=#Tp 1'b0;
            m_wb_sel_o <=#Tp 4'hf;
            IncrTxPointer<=#Tp 1'b1;
          end
        8'b10_10_01_00,             // MR and MR is needed (data read from tx buffer)
 
//        8'b01_1x_01_0x  :           // MW and MR is needed (data read from tx buffer)
        8'b01_10_01_00  ,           // MW and MR is needed (data read from tx buffer)
        8'b01_10_01_01  ,           // MW and MR is needed (data read from tx buffer)
        8'b01_11_01_00  ,           // MW and MR is needed (data read from tx buffer)
        8'b01_11_01_01  :           // MW and MR is needed (data read from tx buffer)
          begin
StateM<=#Tp 4'h5;
            MasterWbTX <=#Tp 1'b1;
            MasterWbRX <=#Tp 1'b0;
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
            m_wb_cyc_o <=#Tp 1'b1;
            m_wb_stb_o <=#Tp 1'b1;
            m_wb_we_o  <=#Tp 1'b0;
            m_wb_sel_o <=#Tp 4'hf;
            cyc_cleared<=#Tp 1'b0;
            IncrTxPointer<=#Tp 1'b1;
          end
        8'b01_01_01_00,             // MW and MW needed (data write to rx buffer)
 
//        8'b10_x1_01_x0  :           // MR and MW is needed (data write to rx buffer)
        8'b10_01_01_00  ,           // MR and MW is needed (data write to rx buffer)
        8'b10_01_01_10  ,           // MR and MW is needed (data write to rx buffer)
        8'b10_11_01_00  ,           // MR and MW is needed (data write to rx buffer)
        8'b10_11_01_10  :           // MR and MW is needed (data write to rx buffer)
          begin
StateM<=#Tp 4'h6;
            MasterWbTX <=#Tp 1'b0;
            MasterWbRX <=#Tp 1'b1;
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
            m_wb_cyc_o <=#Tp 1'b1;
            m_wb_stb_o <=#Tp 1'b1;
            m_wb_we_o  <=#Tp 1'b1;
            m_wb_sel_o <=#Tp RxByteSel;
            cyc_cleared<=#Tp 1'b0;
            IncrTxPointer<=#Tp 1'b0;
          end
        8'b01_01_10_00,             // MW and MW needed (cycle is cleared between previous and next access)
 
//        8'b01_1x_10_x0,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
        8'b01_10_10_00,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
        8'b01_10_10_10,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
        8'b01_11_10_00,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
        8'b01_11_10_10,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
 
        8'b10_10_10_00,             // MR and MR needed (cycle is cleared between previous and next access)
 
//        8'b10_x1_10_0x :            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
        8'b10_01_10_00 ,            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
        8'b10_01_10_01 ,            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
        8'b10_11_10_00 ,            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
        8'b10_11_10_01 :            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
          begin
StateM<=#Tp 4'h7;
            m_wb_cyc_o <=#Tp 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
            m_wb_stb_o <=#Tp 1'b0;
            cyc_cleared<=#Tp 1'b1;
            IncrTxPointer<=#Tp 1'b0;
            tx_burst_cnt<=#Tp 0;
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
            rx_burst_cnt<=#Tp 0;
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
            `ifdef ETH_WISHBONE_B3
              m_wb_cti_o <=#Tp 3'b0;
            `endif
          end
//        8'bxx_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
        8'b00_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
        8'b01_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
        8'b10_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
        8'b11_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
 
//        8'bxx_00_01_00 :            // Between cyc_cleared request was cleared
        8'b00_00_01_00 ,            // Between cyc_cleared request was cleared
        8'b01_00_01_00 ,            // Between cyc_cleared request was cleared
        8'b10_00_01_00 ,            // Between cyc_cleared request was cleared
        8'b11_00_01_00 :            // Between cyc_cleared request was cleared
          begin
StateM<=#Tp 4'h8;
            MasterWbTX <=#Tp 1'b0;
            MasterWbRX <=#Tp 1'b0;
            m_wb_cyc_o <=#Tp 1'b0;
            m_wb_stb_o <=#Tp 1'b0;
            cyc_cleared<=#Tp 1'b0;
            IncrTxPointer<=#Tp 1'b0;
            rx_burst_cnt<=#Tp 0;
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
            `ifdef ETH_WISHBONE_B3
              m_wb_cti_o <=#Tp 3'b0;
            `endif
          end
        8'b00_00_00_00:             // whatever and no master read or write is needed (ack or err comes finishing previous access)
          begin
StateM<=#Tp 4'h9;
            tx_burst_cnt<=#Tp 0;
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
          end
        default:                    // Don't touch
          begin
            MasterWbTX <=#Tp MasterWbTX;
            MasterWbRX <=#Tp MasterWbRX;
            m_wb_cyc_o <=#Tp m_wb_cyc_o;
            m_wb_stb_o <=#Tp m_wb_stb_o;
            m_wb_sel_o <=#Tp m_wb_sel_o;
            IncrTxPointer<=#Tp IncrTxPointer;
          end
      endcase
    end
end
 
 
wire TxFifoClear;
 
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
 
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
          .clk(WB_CLK_I),                                   .reset(Reset),
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
          .clear(TxFifoClear),                              .full(TxBufferFull),
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
          .empty(TxBufferEmpty),                            .cnt(txfifo_cnt)
        );
 
 
reg StartOccured;
reg TxStartFrm_sync1;
reg TxStartFrm_sync2;
reg TxStartFrm_syncb1;
reg TxStartFrm_syncb2;
 
 
 
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxStartFrm_wb <=#Tp 1'b0;
  else
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
    TxStartFrm_wb <=#Tp 1'b1;
  else
  if(TxStartFrm_syncb2)
    TxStartFrm_wb <=#Tp 1'b0;
end
 
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    StartOccured <=#Tp 1'b0;
  else
  if(TxStartFrm_wb)
    StartOccured <=#Tp 1'b1;
  else
  if(ResetTxBDReady)
    StartOccured <=#Tp 1'b0;
end
 
// Synchronizing TxStartFrm_wb to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    TxStartFrm_sync1 <=#Tp 1'b0;
  else
    TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
end
 
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    TxStartFrm_sync2 <=#Tp 1'b0;
  else
    TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxStartFrm_syncb1 <=#Tp 1'b0;
  else
    TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxStartFrm_syncb2 <=#Tp 1'b0;
  else
    TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
end
 
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    TxStartFrm <=#Tp 1'b0;
  else
  if(TxStartFrm_sync2)
    TxStartFrm <=#Tp 1'b1;
  else
  if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry | TxAbort))
    TxStartFrm <=#Tp 1'b0;
end
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
 
 
// TxEndFrm_wb: indicator of the end of frame
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxEndFrm_wb <=#Tp 1'b0;
  else
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
    TxEndFrm_wb <=#Tp 1'b1;
  else
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
    TxEndFrm_wb <=#Tp 1'b0;
end
 
 
// Marks which bytes are valid within the word.
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
 
reg LatchValidBytes;
reg LatchValidBytes_q;
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    LatchValidBytes <=#Tp 1'b0;
  else
  if(TxLengthLt4 & TxBDReady)
    LatchValidBytes <=#Tp 1'b1;
  else
    LatchValidBytes <=#Tp 1'b0;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    LatchValidBytes_q <=#Tp 1'b0;
  else
    LatchValidBytes_q <=#Tp LatchValidBytes;
end
 
 
// Latching valid bytes
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxValidBytesLatched <=#Tp 2'h0;
  else
  if(LatchValidBytes & ~LatchValidBytes_q)
    TxValidBytesLatched <=#Tp TxValidBytes;
  else
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
    TxValidBytesLatched <=#Tp 2'h0;
end
 
 
assign TxIRQEn          = TxStatus[14];
assign WrapTxStatusBit  = TxStatus[13];
assign PerPacketPad     = TxStatus[12];
assign PerPacketCrcEn   = TxStatus[11];
 
 
assign RxIRQEn         = RxStatus[14];
assign WrapRxStatusBit = RxStatus[13];
 
 
// Temporary Tx and Rx buffer descriptor address 
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite     & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum<<1)     | // Using first Rx BD
                              {8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
 
 
// Latching Tx buffer descriptor address
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxBDAddress <=#Tp 8'h0;
  else
  if(TxStatusWrite)
    TxBDAddress <=#Tp TempTxBDAddress;
end
 
 
// Latching Rx buffer descriptor address
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF<<1;
  else
  if(TX_BD_NUM_Wr)                        // When r_TxBDNum is updated, RxBDAddress is also
    RxBDAddress <=#Tp WB_DAT_I[7:0]<<1;
  else
  if(RxStatusWrite)
    RxBDAddress <=#Tp TempRxBDAddress;
end
 
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
 
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 6'h0, RxStatusInLatched};
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
 
 
// Signals used for various purposes
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
 
 
 
// Generating delayed signals
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    begin
      TxAbort_q      <=#Tp 1'b0;
      TxRetry_q      <=#Tp 1'b0;
      TxUsedData_q   <=#Tp 1'b0;
    end
  else
    begin
      TxAbort_q      <=#Tp TxAbort;
      TxRetry_q      <=#Tp TxRetry;
      TxUsedData_q   <=#Tp TxUsedData;
    end
end
 
// Generating delayed signals
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    begin
      TxDone_wb_q   <=#Tp 1'b0;
      TxAbort_wb_q  <=#Tp 1'b0;
      TxRetry_wb_q  <=#Tp 1'b0;
    end
  else
    begin
      TxDone_wb_q   <=#Tp TxDone_wb;
      TxAbort_wb_q  <=#Tp TxAbort_wb;
      TxRetry_wb_q  <=#Tp TxRetry_wb;
    end
end
 
 
reg TxAbortPacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxAbortPacket <=#Tp 1'b0;
  else
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxAbortPacketBlocked |
     TxAbort_wb & !MasterWbTX & !TxAbortPacketBlocked)
    TxAbortPacket <=#Tp 1'b1;
  else
    TxAbortPacket <=#Tp 1'b0;
end
 
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxAbortPacket_NotCleared <=#Tp 1'b0;
  else
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
     TxAbort_wb & !MasterWbTX)
    TxAbortPacket_NotCleared <=#Tp 1'b1;
  else
    TxAbortPacket_NotCleared <=#Tp 1'b0;
end
 
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxAbortPacketBlocked <=#Tp 1'b0;
  else
  if(TxAbortPacket)
    TxAbortPacketBlocked <=#Tp 1'b1;
  else
  if(!TxAbort_wb & TxAbort_wb_q)
    TxAbortPacketBlocked <=#Tp 1'b0;
end
 
 
reg TxRetryPacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxRetryPacket <=#Tp 1'b0;
  else
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
     TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
    TxRetryPacket <=#Tp 1'b1;
  else
    TxRetryPacket <=#Tp 1'b0;
end
 
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxRetryPacket_NotCleared <=#Tp 1'b0;
  else
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
     TxRetry_wb & !MasterWbTX)
    TxRetryPacket_NotCleared <=#Tp 1'b1;
  else
    TxRetryPacket_NotCleared <=#Tp 1'b0;
end
 
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxRetryPacketBlocked <=#Tp 1'b0;
  else
  if(TxRetryPacket)
    TxRetryPacketBlocked <=#Tp 1'b1;
  else
  if(!TxRetry_wb & TxRetry_wb_q)
    TxRetryPacketBlocked <=#Tp 1'b0;
end
 
 
reg TxDonePacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxDonePacket <=#Tp 1'b0;
  else
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
     TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
    TxDonePacket <=#Tp 1'b1;
  else
    TxDonePacket <=#Tp 1'b0;
end
 
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxDonePacket_NotCleared <=#Tp 1'b0;
  else
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
     TxDone_wb & !MasterWbTX)
    TxDonePacket_NotCleared <=#Tp 1'b1;
  else
    TxDonePacket_NotCleared <=#Tp 1'b0;
end
 
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxDonePacketBlocked <=#Tp 1'b0;
  else
  if(TxDonePacket)
    TxDonePacketBlocked <=#Tp 1'b1;
  else
  if(!TxDone_wb & TxDone_wb_q)
    TxDonePacketBlocked <=#Tp 1'b0;
end
 
 
// Sinchronizing and evaluating tx data
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
assign SetGotData = (TxStartFrm_wb);
 
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
//assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
assign GotDataEvaluate = (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
 
 
// Indication of the last word
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    LastWord <=#Tp 1'b0;
  else
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
    LastWord <=#Tp 1'b0;
  else
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
    LastWord <=#Tp TxEndFrm_wb;
end
 
 
// Tx end frame generation
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    TxEndFrm <=#Tp 1'b0;
  else
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
    TxEndFrm <=#Tp 1'b0;
  else
  if(Flop & LastWord)
    begin
      case (TxValidBytesLatched)  // synopsys parallel_case
        1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
        2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
        3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
 
        default : TxEndFrm <=#Tp 1'b0;
      endcase
    end
end
 
 
// Tx data selection (latching)
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    TxData <=#Tp 0;
  else
  if(TxStartFrm_sync2 & ~TxStartFrm)
    case(TxPointerLSB)  // synopsys parallel_case
      2'h0 : TxData <=#Tp TxData_wb[31:24];                  // Big Endian Byte Ordering
      2'h1 : TxData <=#Tp TxData_wb[23:16];                  // Big Endian Byte Ordering
      2'h2 : TxData <=#Tp TxData_wb[15:08];                  // Big Endian Byte Ordering
      2'h3 : TxData <=#Tp TxData_wb[07:00];                  // Big Endian Byte Ordering
    endcase
  else
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
    TxData <=#Tp TxData_wb[31:24];                           // Big Endian Byte Ordering
  else
  if(TxUsedData & Flop)
    begin
      case(TxByteCnt)  // synopsys parallel_case
 
        1 : TxData <=#Tp TxDataLatched[23:16];
        2 : TxData <=#Tp TxDataLatched[15:8];
        3 : TxData <=#Tp TxDataLatched[7:0];
      endcase
    end
end
 
 
// Latching tx data
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    TxDataLatched[31:0] <=#Tp 32'h0;
  else
 if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
    TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
end
 
 
// Tx under run
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxUnderRun_wb <=#Tp 1'b0;
  else
  if(TxAbortPulse)
    TxUnderRun_wb <=#Tp 1'b0;
  else
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
    TxUnderRun_wb <=#Tp 1'b1;
end
 
 
reg TxUnderRun_sync1;
 
// Tx under run
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    TxUnderRun_sync1 <=#Tp 1'b0;
  else
  if(TxUnderRun_wb)
    TxUnderRun_sync1 <=#Tp 1'b1;
  else
  if(BlockingTxStatusWrite_sync2)
    TxUnderRun_sync1 <=#Tp 1'b0;
end
 
// Tx under run
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    TxUnderRun <=#Tp 1'b0;
  else
  if(BlockingTxStatusWrite_sync2)
    TxUnderRun <=#Tp 1'b0;
  else
  if(TxUnderRun_sync1)
    TxUnderRun <=#Tp 1'b1;
end
 
 
// Tx Byte counter
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    TxByteCnt <=#Tp 2'h0;
  else
  if(TxAbort_q | TxRetry_q)
    TxByteCnt <=#Tp 2'h0;
  else
  if(TxStartFrm & ~TxUsedData)
    case(TxPointerLSB)  // synopsys parallel_case
      2'h0 : TxByteCnt <=#Tp 2'h1;
      2'h1 : TxByteCnt <=#Tp 2'h2;
      2'h2 : TxByteCnt <=#Tp 2'h3;
      2'h3 : TxByteCnt <=#Tp 2'h0;
    endcase
  else
  if(TxUsedData & Flop)
    TxByteCnt <=#Tp TxByteCnt + 1'b1;
end
 
 
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
reg ReadTxDataFromFifo_sync1;
reg ReadTxDataFromFifo_sync2;
reg ReadTxDataFromFifo_sync3;
reg ReadTxDataFromFifo_syncb1;
reg ReadTxDataFromFifo_syncb2;
reg ReadTxDataFromFifo_syncb3;
 
 
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
  else
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
     ReadTxDataFromFifo_tck <=#Tp 1'b1;
  else
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
end
 
// Synchronizing TxStartFrm_wb to MTxClk
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
  else
    ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
  else
    ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
end
 
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
  else
    ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
end
 
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
  else
    ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
end
 
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
  else
    ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
  else
    ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
end
 
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
 
 
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxRetrySync1 <=#Tp 1'b0;
  else
    TxRetrySync1 <=#Tp TxRetry;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxRetry_wb <=#Tp 1'b0;
  else
    TxRetry_wb <=#Tp TxRetrySync1;
end
 
 
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxDoneSync1 <=#Tp 1'b0;
  else
    TxDoneSync1 <=#Tp TxDone;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxDone_wb <=#Tp 1'b0;
  else
    TxDone_wb <=#Tp TxDoneSync1;
end
 
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxAbortSync1 <=#Tp 1'b0;
  else
    TxAbortSync1 <=#Tp TxAbort;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxAbort_wb <=#Tp 1'b0;
  else
    TxAbort_wb <=#Tp TxAbortSync1;
end
 
 
reg RxAbortSync1;
reg RxAbortSync2;
reg RxAbortSync3;
reg RxAbortSync4;
reg RxAbortSyncb1;
reg RxAbortSyncb2;
 
//assign StartRxBDRead = RxStatusWrite | RxAbortLatched;
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
 
// Reading the Rx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxBDRead <=#Tp 1'b1;
  else
  if(StartRxBDRead & ~RxReady)
    RxBDRead <=#Tp 1'b1;
  else
  if(RxBDReady)
    RxBDRead <=#Tp 1'b0;
end
 
 
// Reading of the next receive buffer descriptor starts after reception status is
// written to the previous one.
 
// Latching READY status of the Rx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxBDReady <=#Tp 1'b0;
  else
  if(RxPointerRead)
    RxBDReady <=#Tp 1'b0;
  else
  if(RxEn & RxEn_q & RxBDRead)
    RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
end
 
// Latching Rx buffer descriptor status
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxStatus <=#Tp 2'h0;
  else
  if(RxEn & RxEn_q & RxBDRead)
    RxStatus <=#Tp ram_do[14:13];
end
 
 
// RxReady generation
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxReady <=#Tp 1'b0;
  else
  if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3)
    RxReady <=#Tp 1'b0;
  else
  if(RxEn & RxEn_q & RxPointerRead)
    RxReady <=#Tp 1'b1;
end
 
 
// Reading Rx BD pointer
 
 
assign StartRxPointerRead = RxBDRead & RxBDReady;
 
// Reading Tx BD Pointer
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxPointerRead <=#Tp 1'b0;
  else
  if(StartRxPointerRead)
    RxPointerRead <=#Tp 1'b1;
  else
  if(RxEn & RxEn_q)
    RxPointerRead <=#Tp 1'b0;
end
 
 
//Latching Rx buffer pointer from buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxPointerMSB <=#Tp 30'h0;
  else
  if(RxEn & RxEn_q & RxPointerRead)
    RxPointerMSB <=#Tp ram_do[31:2];
  else
  if(MasterWbRX & m_wb_ack_i)
      RxPointerMSB <=#Tp RxPointerMSB + 1; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
end
 
 
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxPointerLSB_rst[1:0] <=#Tp 0;
  else
  if(MasterWbRX & m_wb_ack_i)                 // After first write all RxByteSel are active
    RxPointerLSB_rst[1:0] <=#Tp 0;
  else
  if(RxEn & RxEn_q & RxPointerRead)
    RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
end
 
 
always @ (RxPointerLSB_rst)
begin
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
    2'h0 : RxByteSel[3:0] = 4'hf;
    2'h1 : RxByteSel[3:0] = 4'h7;
    2'h2 : RxByteSel[3:0] = 4'h3;
    2'h3 : RxByteSel[3:0] = 4'h1;
  endcase
end
 
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxEn_needed <=#Tp 1'b0;
  else
  if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
    RxEn_needed <=#Tp 1'b1;
  else
  if(RxPointerRead & RxEn & RxEn_q)
    RxEn_needed <=#Tp 1'b0;
end
 
 
// Reception status is written back to the buffer descriptor after the end of frame is detected.
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
 
reg RxStatusWriteLatched;
reg RxStatusWrite_rck;
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxStatusWriteLatched <=#Tp 1'b0;
  else
  if(RxStatusWrite & ~RxStatusWrite_rck)
    RxStatusWriteLatched <=#Tp 1'b1;
  else
  if(RxStatusWrite_rck)
    RxStatusWriteLatched <=#Tp 1'b0;
end
 
 
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxStatusWrite_rck <=#Tp 1'b0;
  else
  if(RxStatusWriteLatched)
    RxStatusWrite_rck <=#Tp 1'b1;
  else
    RxStatusWrite_rck <=#Tp 1'b0;
end
 
 
reg RxEnableWindow;
 
// Indicating that last byte is being reveived
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LastByteIn <=#Tp 1'b0;
  else
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
    LastByteIn <=#Tp 1'b0;
  else
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
    LastByteIn <=#Tp 1'b1;
end
 
reg ShiftEnded_rck;
reg ShiftEndedSync1;
reg ShiftEndedSync2;
reg ShiftEndedSync3;
reg ShiftEndedSync_c1;
reg ShiftEndedSync_c2;
 
wire StartShiftWillEnd;
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
 
// Indicating that data reception will end
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ShiftWillEnd <=#Tp 1'b0;
  else
  if(ShiftEnded_rck | RxAbort)
    ShiftWillEnd <=#Tp 1'b0;
  else
  if(StartShiftWillEnd)
    ShiftWillEnd <=#Tp 1'b1;
end
 
 
 
// Receive byte counter
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxByteCnt <=#Tp 2'h0;
  else
  if(ShiftEnded_rck | RxAbort)
    RxByteCnt <=#Tp 2'h0;
  else
  if(RxValid & RxStartFrm & RxReady)
    case(RxPointerLSB_rst)  // synopsys parallel_case
      2'h0 : RxByteCnt <=#Tp 2'h1;
      2'h1 : RxByteCnt <=#Tp 2'h2;
      2'h2 : RxByteCnt <=#Tp 2'h3;
      2'h3 : RxByteCnt <=#Tp 2'h0;
    endcase
  else
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
    RxByteCnt <=#Tp RxByteCnt + 1'b1;
end
 
 
// Indicates how many bytes are valid within the last word
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxValidBytes <=#Tp 2'h1;
  else
  if(RxValid & RxStartFrm)
    case(RxPointerLSB_rst)  // synopsys parallel_case
      2'h0 : RxValidBytes <=#Tp 2'h1;
      2'h1 : RxValidBytes <=#Tp 2'h2;
      2'h2 : RxValidBytes <=#Tp 2'h3;
      2'h3 : RxValidBytes <=#Tp 2'h0;
    endcase
  else
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
    RxValidBytes <=#Tp RxValidBytes + 1;
end
 
 
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxDataLatched1       <=#Tp 24'h0;
  else
  if(RxValid & RxReady & ~LastByteIn)
    if(RxStartFrm)
    begin
      case(RxPointerLSB_rst)     // synopsys parallel_case
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
      endcase
    end
    else if (RxEnableWindow)
    begin
      case(RxByteCnt)     // synopsys parallel_case
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
      endcase
    end
end
 
wire SetWriteRxDataToFifo;
 
// Assembling data that will be written to the rx_fifo
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxDataLatched2 <=#Tp 32'h0;
  else
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
    RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData};              // Big Endian Byte Ordering
  else
  if(SetWriteRxDataToFifo & ShiftWillEnd)
    case(RxValidBytes)  // synopsys parallel_case
 
      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};
    endcase
end
 
 
reg WriteRxDataToFifoSync1;
reg WriteRxDataToFifoSync2;
reg WriteRxDataToFifoSync3;
 
 
// Indicating start of the reception process
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
                              (RxValid & RxReady &  RxStartFrm & (&RxPointerLSB_rst))           |
                              (ShiftWillEnd & LastByteIn & (&RxByteCnt));
 
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    WriteRxDataToFifo <=#Tp 1'b0;
  else
  if(SetWriteRxDataToFifo & ~RxAbort)
    WriteRxDataToFifo <=#Tp 1'b1;
  else
  if(WriteRxDataToFifoSync2 | RxAbort)
    WriteRxDataToFifo <=#Tp 1'b0;
end
 
 
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
  else
  if(WriteRxDataToFifo)
    WriteRxDataToFifoSync1 <=#Tp 1'b1;
  else
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    WriteRxDataToFifoSync2 <=#Tp 1'b0;
  else
    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    WriteRxDataToFifoSync3 <=#Tp 1'b0;
  else
    WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
end
 
wire WriteRxDataToFifo_wb;
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
 
 
reg LatchedRxStartFrm;
reg SyncRxStartFrm;
reg SyncRxStartFrm_q;
reg SyncRxStartFrm_q2;
wire RxFifoReset;
 
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LatchedRxStartFrm <=#Tp 0;
  else
  if(RxStartFrm & ~SyncRxStartFrm_q)
    LatchedRxStartFrm <=#Tp 1;
  else
  if(SyncRxStartFrm_q)
    LatchedRxStartFrm <=#Tp 0;
end
 
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    SyncRxStartFrm <=#Tp 0;
  else
  if(LatchedRxStartFrm)
    SyncRxStartFrm <=#Tp 1;
  else
    SyncRxStartFrm <=#Tp 0;
end
 
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    SyncRxStartFrm_q <=#Tp 0;
  else
    SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    SyncRxStartFrm_q2 <=#Tp 0;
  else
    SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
end
 
 
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
 
 
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
         .clk(WB_CLK_I),                                .reset(Reset),
         .write(WriteRxDataToFifo_wb & ~RxBufferFull),  .read(MasterWbRX & m_wb_ack_i),
         .clear(RxFifoReset),                           .full(RxBufferFull),
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
         .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)
        );
 
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
assign WriteRxDataToMemory = ~RxBufferEmpty;
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
 
 
// Generation of the end-of-frame signal
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ShiftEnded_rck <=#Tp 1'b0;
  else
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
    ShiftEnded_rck <=#Tp 1'b1;
  else
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
    ShiftEnded_rck <=#Tp 1'b0;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    ShiftEndedSync1 <=#Tp 1'b0;
  else
    ShiftEndedSync1 <=#Tp ShiftEnded_rck;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    ShiftEndedSync2 <=#Tp 1'b0;
  else
    ShiftEndedSync2 <=#Tp ShiftEndedSync1;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    ShiftEndedSync3 <=#Tp 1'b0;
  else
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
    ShiftEndedSync3 <=#Tp 1'b1;
  else
  if(ShiftEnded)
    ShiftEndedSync3 <=#Tp 1'b0;
end
 
// Generation of the end-of-frame signal
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    ShiftEnded <=#Tp 1'b0;
  else
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
    ShiftEnded <=#Tp 1'b1;
  else
  if(RxStatusWrite)
    ShiftEnded <=#Tp 1'b0;
end
 
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ShiftEndedSync_c1 <=#Tp 1'b0;
  else
    ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
end
 
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ShiftEndedSync_c2 <=#Tp 1'b0;
  else
    ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
end
 
// Generation of the end-of-frame signal
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxEnableWindow <=#Tp 1'b0;
  else
  if(RxStartFrm)
    RxEnableWindow <=#Tp 1'b1;
  else
  if(RxEndFrm | RxAbort)
    RxEnableWindow <=#Tp 1'b0;
end
 
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxAbortSync1 <=#Tp 1'b0;
  else
    RxAbortSync1 <=#Tp RxAbortLatched;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxAbortSync2 <=#Tp 1'b0;
  else
    RxAbortSync2 <=#Tp RxAbortSync1;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxAbortSync3 <=#Tp 1'b0;
  else
    RxAbortSync3 <=#Tp RxAbortSync2;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxAbortSync4 <=#Tp 1'b0;
  else
    RxAbortSync4 <=#Tp RxAbortSync3;
end
 
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxAbortSyncb1 <=#Tp 1'b0;
  else
    RxAbortSyncb1 <=#Tp RxAbortSync2;
end
 
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxAbortSyncb2 <=#Tp 1'b0;
  else
    RxAbortSyncb2 <=#Tp RxAbortSyncb1;
end
 
 
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxAbortLatched <=#Tp 1'b0;
  else
  if(RxAbortSyncb2)
    RxAbortLatched <=#Tp 1'b0;
  else
  if(RxAbort)
    RxAbortLatched <=#Tp 1'b1;
end
 
 
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LatchedRxLength[15:0] <=#Tp 16'h0;
  else
  if(LoadRxStatus)
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
end
 
 
assign RxStatusIn = {RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
 
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxStatusInLatched <=#Tp 'h0;
  else
  if(LoadRxStatus)
    RxStatusInLatched <=#Tp RxStatusIn;
end
 
 
// Rx overrun
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxOverrun <=#Tp 1'b0;
  else
  if(RxStatusWrite)
    RxOverrun <=#Tp 1'b0;
  else
  if(RxBufferFull & WriteRxDataToFifo_wb)
    RxOverrun <=#Tp 1'b1;
end
 
 
 
wire TxError;
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
 
wire RxError;
assign RxError = |RxStatusInLatched[6:0];
 
// Tx Done Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxB_IRQ <=#Tp 1'b0;
  else
  if(TxStatusWrite & TxIRQEn)
    TxB_IRQ <=#Tp ~TxError;
  else
    TxB_IRQ <=#Tp 1'b0;
end
 
 
// Tx Error Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxE_IRQ <=#Tp 1'b0;
  else
  if(TxStatusWrite & TxIRQEn)
    TxE_IRQ <=#Tp TxError;
  else
    TxE_IRQ <=#Tp 1'b0;
end
 
 
// Rx Done Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxB_IRQ <=#Tp 1'b0;
  else
  if(RxStatusWrite & RxIRQEn)
    RxB_IRQ <=#Tp ReceivedPacketGood & ~RxError;
  else
    RxB_IRQ <=#Tp 1'b0;
end
 
 
// Rx Error Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxE_IRQ <=#Tp 1'b0;
  else
  if(RxStatusWrite & RxIRQEn)
    RxE_IRQ <=#Tp RxError;
  else
    RxE_IRQ <=#Tp 1'b0;
end
 
 
// Busy Interrupt
 
reg Busy_IRQ_rck;
reg Busy_IRQ_sync1;
reg Busy_IRQ_sync2;
reg Busy_IRQ_sync3;
reg Busy_IRQ_syncb1;
reg Busy_IRQ_syncb2;
 
 
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    Busy_IRQ_rck <=#Tp 1'b0;
  else
  if(RxValid & RxStartFrm & ~RxReady)
    Busy_IRQ_rck <=#Tp 1'b1;
  else
  if(Busy_IRQ_syncb2)
    Busy_IRQ_rck <=#Tp 1'b0;
end
 
always @ (posedge WB_CLK_I)
begin
    Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
    Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
    Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
end
 
always @ (posedge MRxClk)
begin
    Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
    Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
end
 
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
 
 
 
// TX
// bit 15 ready
// bit 14 interrupt
// bit 13 wrap
// bit 12 pad
// bit 11 crc
// bit 10 last
// bit 9  pause request (control frame)
// bit 8  TxUnderRun          
// bit 7-4 RetryCntLatched    
// bit 3  retransmittion limit
// bit 2  LateCollLatched        
// bit 1  DeferLatched        
// bit 0  CarrierSenseLost    
 
 
// RX
// bit 15 od rx je empty
// bit 14 od rx je interrupt
// bit 13 od rx je wrap
// bit 12 od rx je reserved
// bit 11 od rx je reserved
// bit 10 od rx je reserved
// bit 9  od rx je reserved
// bit 8  od rx je reserved
// bit 7  od rx je Miss
// bit 6  od rx je RxOverrun
// bit 5  od rx je InvalidSymbol
// bit 4  od rx je DribbleNibble
// bit 3  od rx je ReceivedPacketTooBig
// bit 2  od rx je ShortFrame
// bit 1  od rx je LatchedCrcError
// bit 0  od rx je RxLateCollision
 
 
endmodule
 

Line No.	Rev	Author	Line
1	38	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_wishbone.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects/ethmac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11	166	mohor	`//// All additional information is available in the Readme.txt ////`
12	38	mohor	`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16	118	mohor	`//// Copyright (C) 2001, 2002 Authors ////`
17	38	mohor	`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	226	tadejm	`// Revision 1.40 2002/10/14 16:07:02 mohor`
45			`// TxStatus is written after last access to the TX fifo is finished (in case of abort`
46			`// or retry). TxDone is fixed.`
47			`//`
48	221	mohor	`// Revision 1.39 2002/10/11 15:35:20 mohor`
49			`// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,`
50			`// TxDone and TxRetry are generated after the current WISHBONE access is`
51			`// finished.`
52			`//`
53	219	mohor	`// Revision 1.38 2002/10/10 16:29:30 mohor`
54			`// BIST added.`
55			`//`
56	210	mohor	`// Revision 1.37 2002/09/11 14:18:46 mohor`
57			`// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.`
58			`//`
59	167	mohor	`// Revision 1.36 2002/09/10 13:48:46 mohor`
60			`// Reception is possible after RxPointer is read and not after BD is read. For`
61			`// that reason RxBDReady is changed to RxReady.`
62			`// Busy_IRQ interrupt connected. When there is no RxBD ready and frame`
63			`// comes, interrupt is generated.`
64			`//`
65	166	mohor	`// Revision 1.35 2002/09/10 10:35:23 mohor`
66			`// Ethernet debug registers removed.`
67			`//`
68	164	mohor	`// Revision 1.34 2002/09/08 16:31:49 mohor`
69			`// Async reset for WB_ACK_O removed (when core was in reset, it was`
70			`// impossible to access BDs).`
71			`// RxPointers and TxPointers names changed to be more descriptive.`
72			`// TxUnderRun synchronized.`
73			`//`
74	159	mohor	`// Revision 1.33 2002/09/04 18:47:57 mohor`
75			`// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals`
76			`// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal`
77			`// was not used OK.`
78			`//`
79	150	mohor	`// Revision 1.32 2002/08/14 19:31:48 mohor`
80			`// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No`
81			`// need to multiply or devide any more.`
82			`//`
83	134	mohor	`// Revision 1.31 2002/07/25 18:29:01 mohor`
84			`// WriteRxDataToMemory signal changed so end of frame (when last word is`
85			`// written to fifo) is changed.`
86			`//`
87	127	mohor	`// Revision 1.30 2002/07/23 15:28:31 mohor`
88			`// Ram , used for BDs changed from generic_spram to eth_spram_256x32.`
89			`//`
90	119	mohor	`// Revision 1.29 2002/07/20 00:41:32 mohor`
91			`// ShiftEnded synchronization changed.`
92			`//`
93	118	mohor	`// Revision 1.28 2002/07/18 16:11:46 mohor`
94			// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
95			`//`
96	115	mohor	`// Revision 1.27 2002/07/11 02:53:20 mohor`
97			`// RxPointer bug fixed.`
98			`//`
99	113	mohor	`// Revision 1.26 2002/07/10 13:12:38 mohor`
100			`// Previous bug wasn't succesfully removed. Now fixed.`
101			`//`
102	112	mohor	`// Revision 1.25 2002/07/09 23:53:24 mohor`
103			`// Master state machine had a bug when switching from master write to`
104			`// master read.`
105			`//`
106	111	mohor	`// Revision 1.24 2002/07/09 20:44:41 mohor`
107			`// m_wb_cyc_o signal released after every single transfer.`
108			`//`
109	110	mohor	`// Revision 1.23 2002/05/03 10:15:50 mohor`
110			`// Outputs registered. Reset changed for eth_wishbone module.`
111			`//`
112	106	mohor	`// Revision 1.22 2002/04/24 08:52:19 mohor`
113			`// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"`
114			`// bug fixed.`
115			`//`
116	105	mohor	`// Revision 1.21 2002/03/29 16:18:11 lampret`
117			`// Small typo fixed.`
118			`//`
119	97	lampret	`// Revision 1.20 2002/03/25 16:19:12 mohor`
120			`// Any address can be used for Tx and Rx BD pointers. Address does not need`
121			`// to be aligned.`
122			`//`
123	96	mohor	`// Revision 1.19 2002/03/19 12:51:50 mohor`
124			`// Comments in Slovene language removed.`
125			`//`
126	91	mohor	`// Revision 1.18 2002/03/19 12:46:52 mohor`
127			`// casex changed with case, fifo reset changed.`
128			`//`
129	90	mohor	`// Revision 1.17 2002/03/09 16:08:45 mohor`
130			`// rx_fifo was not always cleared ok. Fixed.`
131			`//`
132	88	mohor	`// Revision 1.16 2002/03/09 13:51:20 mohor`
133			`// Status was not latched correctly sometimes. Fixed.`
134			`//`
135	87	mohor	`// Revision 1.15 2002/03/08 06:56:46 mohor`
136			`// Big Endian problem when sending frames fixed.`
137			`//`
138	86	mohor	`// Revision 1.14 2002/03/02 19:12:40 mohor`
139			`// Byte ordering changed (Big Endian used). casex changed with case because`
140			`// Xilinx Foundation had problems. Tested in HW. It WORKS.`
141			`//`
142	82	mohor	`// Revision 1.13 2002/02/26 16:59:55 mohor`
143			`// Small fixes for external/internal DMA missmatches.`
144			`//`
145	80	mohor	`// Revision 1.12 2002/02/26 16:22:07 mohor`
146			`// Interrupts changed`
147			`//`
148	77	mohor	`// Revision 1.11 2002/02/15 17:07:39 mohor`
149			`// Status was not written correctly when frames were discarted because of`
150			`// address mismatch.`
151			`//`
152	64	mohor	`// Revision 1.10 2002/02/15 12:17:39 mohor`
153			`// RxStartFrm cleared when abort or retry comes.`
154			`//`
155	61	mohor	`// Revision 1.9 2002/02/15 11:59:10 mohor`
156			`// Changes that were lost when updating from 1.5 to 1.8 fixed.`
157			`//`
158	60	mohor	`// Revision 1.8 2002/02/14 20:54:33 billditt`
159			`// Addition of new module eth_addrcheck.v`
160			`//`
161			`// Revision 1.7 2002/02/12 17:03:47 mohor`
162			`// RxOverRun added to statuses.`
163			`//`
164			`// Revision 1.6 2002/02/11 09:18:22 mohor`
165			`// Tx status is written back to the BD.`
166			`//`
167	43	mohor	`// Revision 1.5 2002/02/08 16:21:54 mohor`
168			`// Rx status is written back to the BD.`
169			`//`
170	42	mohor	`// Revision 1.4 2002/02/06 14:10:21 mohor`
171			`// non-DMA host interface added. Select the right configutation in eth_defines.`
172			`//`
173	41	mohor	`// Revision 1.3 2002/02/05 16:44:39 mohor`
174			`// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200`
175			`// MHz. Statuses, overrun, control frame transmission and reception still need`
176			`// to be fixed.`
177			`//`
178	40	mohor	`// Revision 1.2 2002/02/01 12:46:51 mohor`
179			`// Tx part finished. TxStatus needs to be fixed. Pause request needs to be`
180			`// added.`
181			`//`
182	39	mohor	`// Revision 1.1 2002/01/23 10:47:59 mohor`
183			`// Initial version. Equals to eth_wishbonedma.v at this moment.`
184	38	mohor	`//`
185			`//`
186			`//`
187
188			`include "eth_defines.v"
189			`include "timescale.v"
190
191
192			`module eth_wishbone`
193			`(`
194
195			`// WISHBONE common`
196	40	mohor	`WB_CLK_I, WB_DAT_I, WB_DAT_O,`
197	38	mohor
198			`// WISHBONE slave`
199	77	mohor	`WB_ADR_I, WB_WE_I, WB_ACK_O,`
200	40	mohor	`BDCs,`
201	38	mohor
202	40	mohor	`Reset,`
203
204	39	mohor	`// WISHBONE master`
205			`m_wb_adr_o, m_wb_sel_o, m_wb_we_o,`
206			`m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,`
207			`m_wb_stb_o, m_wb_ack_i, m_wb_err_i,`
208
209	219	mohor	`ifdef ETH_WISHBONE_B3
210			`m_wb_cti_o, m_wb_bte_o,`
211			`endif
212
213	38	mohor	`//TX`
214	60	mohor	`MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,`
215	150	mohor	`TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,`
216	38	mohor	`PerPacketPad,`
217
218			`//RX`
219	40	mohor	`MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,`
220	38	mohor
221			`// Register`
222	150	mohor	`r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr,`
223	38	mohor
224			`// Interrupts`
225	150	mohor	`TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,`
226	42	mohor
227	60	mohor	`// Rx Status`
228	42	mohor	`InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,`
229	77	mohor	`ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,`
230	60	mohor
231			`// Tx Status`
232	164	mohor	`RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost`
233
234	210	mohor	`// Bist`
235			`ifdef ETH_BIST
236			`, trst, SO, SI, shift_DR, capture_DR, extest, tck`
237			`endif
238
239
240
241	38	mohor	`);`
242
243
244			`parameter Tp = 1;`
245
246	150	mohor
247	38	mohor	`// WISHBONE common`
248			`input WB_CLK_I; // WISHBONE clock`
249			`input [31:0] WB_DAT_I; // WISHBONE data input`
250			`output [31:0] WB_DAT_O; // WISHBONE data output`
251
252			`// WISHBONE slave`
253			`input [9:2] WB_ADR_I; // WISHBONE address input`
254			`input WB_WE_I; // WISHBONE write enable input`
255			`input BDCs; // Buffer descriptors are selected`
256			`output WB_ACK_O; // WISHBONE acknowledge output`
257
258	39	mohor	`// WISHBONE master`
259			`output [31:0] m_wb_adr_o; //`
260			`output [3:0] m_wb_sel_o; //`
261			`output m_wb_we_o; //`
262			`output [31:0] m_wb_dat_o; //`
263			`output m_wb_cyc_o; //`
264			`output m_wb_stb_o; //`
265			`input [31:0] m_wb_dat_i; //`
266			`input m_wb_ack_i; //`
267			`input m_wb_err_i; //`
268
269	219	mohor	`ifdef ETH_WISHBONE_B3
270			`output [2:0] m_wb_cti_o; // Cycle Type Identifier`
271			`output [1:0] m_wb_bte_o; // Burst Type Extension`
272			`reg [2:0] m_wb_cti_o; // Cycle Type Identifier`
273			`endif
274
275	40	mohor	`input Reset; // Reset signal`
276	39	mohor
277	60	mohor	`// Rx Status signals`
278	42	mohor	`input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode`
279			`input LatchedCrcError; // CRC error`
280			`input RxLateCollision; // Late collision occured while receiving frame`
281			`input ShortFrame; // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)`
282			`input DribbleNibble; // Extra nibble received`
283			`input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL`
284			`input [15:0] RxLength; // Length of the incoming frame`
285			`input LoadRxStatus; // Rx status was loaded`
286	77	mohor	`input ReceivedPacketGood;// Received packet's length and CRC are good`
287	39	mohor
288	60	mohor	`// Tx Status signals`
289			`input [3:0] RetryCntLatched; // Latched Retry Counter`
290			`input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made)`
291			`input LateCollLatched; // Late collision occured`
292			`input DeferLatched; // Defer indication (Frame was defered before sucessfully sent)`
293			`input CarrierSenseLost; // Carrier Sense was lost during the frame transmission`
294
295	38	mohor	`// Tx`
296			`input MTxClk; // Transmit clock (from PHY)`
297			`input TxUsedData; // Transmit packet used data`
298			`input TxRetry; // Transmit packet retry`
299			`input TxAbort; // Transmit packet abort`
300			`input TxDone; // Transmission ended`
301			`output TxStartFrm; // Transmit packet start frame`
302			`output TxEndFrm; // Transmit packet end frame`
303			`output [7:0] TxData; // Transmit packet data byte`
304			`output TxUnderRun; // Transmit packet under-run`
305			`output PerPacketCrcEn; // Per packet crc enable`
306			`output PerPacketPad; // Per packet pading`
307
308			`// Rx`
309			`input MRxClk; // Receive clock (from PHY)`
310			`input [7:0] RxData; // Received data byte (from PHY)`
311			`input RxValid; //`
312			`input RxStartFrm; //`
313			`input RxEndFrm; //`
314	40	mohor	`input RxAbort; // This signal is set when address doesn't match.`
315	38	mohor
316			`//Register`
317			`input r_TxEn; // Transmit enable`
318			`input r_RxEn; // Receive enable`
319			`input [7:0] r_TxBDNum; // Receive buffer descriptor number`
320			`input TX_BD_NUM_Wr; // RxBDNumber written`
321
322			`// Interrupts`
323			`output TxB_IRQ;`
324			`output TxE_IRQ;`
325			`output RxB_IRQ;`
326	77	mohor	`output RxE_IRQ;`
327	38	mohor	`output Busy_IRQ;`
328
329	77	mohor
330	210	mohor	`// Bist`
331			`ifdef ETH_BIST
332			`input trst;`
333			`input shift_DR, capture_DR, tck, extest;`
334			`input SI;`
335			`output SO;`
336			`endif
337
338	77	mohor	`reg TxB_IRQ;`
339			`reg TxE_IRQ;`
340			`reg RxB_IRQ;`
341			`reg RxE_IRQ;`
342
343	38	mohor	`reg TxStartFrm;`
344			`reg TxEndFrm;`
345			`reg [7:0] TxData;`
346
347			`reg TxUnderRun;`
348	60	mohor	`reg TxUnderRun_wb;`
349	38	mohor
350			`reg TxBDRead;`
351	39	mohor	`wire TxStatusWrite;`
352	38	mohor
353			`reg [1:0] TxValidBytesLatched;`
354
355			`reg [15:0] TxLength;`
356	60	mohor	`reg [15:0] LatchedTxLength;`
357			`reg [14:11] TxStatus;`
358	38	mohor
359	60	mohor	`reg [14:13] RxStatus;`
360	38	mohor
361			`reg TxStartFrm_wb;`
362			`reg TxRetry_wb;`
363	39	mohor	`reg TxAbort_wb;`
364	38	mohor	`reg TxDone_wb;`
365
366			`reg TxDone_wb_q;`
367			`reg TxAbort_wb_q;`
368	39	mohor	`reg TxRetry_wb_q;`
369	219	mohor	`reg TxRetryPacket;`
370	221	mohor	`reg TxRetryPacket_NotCleared;`
371			`reg TxDonePacket;`
372			`reg TxDonePacket_NotCleared;`
373	219	mohor	`reg TxAbortPacket;`
374	221	mohor	`reg TxAbortPacket_NotCleared;`
375	38	mohor	`reg RxBDReady;`
376	166	mohor	`reg RxReady;`
377	38	mohor	`reg TxBDReady;`
378
379			`reg RxBDRead;`
380	40	mohor	`wire RxStatusWrite;`
381	38	mohor
382			`reg [31:0] TxDataLatched;`
383			`reg [1:0] TxByteCnt;`
384			`reg LastWord;`
385	39	mohor	`reg ReadTxDataFromFifo_tck;`
386	38	mohor
387			`reg BlockingTxStatusWrite;`
388			`reg BlockingTxBDRead;`
389
390	40	mohor	`reg Flop;`
391	38	mohor
392			`reg [7:0] TxBDAddress;`
393			`reg [7:0] RxBDAddress;`
394
395			`reg TxRetrySync1;`
396			`reg TxAbortSync1;`
397	39	mohor	`reg TxDoneSync1;`
398	38	mohor
399			`reg TxAbort_q;`
400			`reg TxRetry_q;`
401			`reg TxUsedData_q;`
402
403			`reg [31:0] RxDataLatched2;`
404	82	mohor
405			`reg [31:8] RxDataLatched1; // Big Endian Byte Ordering`
406
407	38	mohor	`reg [1:0] RxValidBytes;`
408			`reg [1:0] RxByteCnt;`
409			`reg LastByteIn;`
410			`reg ShiftWillEnd;`
411
412	40	mohor	`reg WriteRxDataToFifo;`
413	42	mohor	`reg [15:0] LatchedRxLength;`
414	64	mohor	`reg RxAbortLatched;`
415	38	mohor
416	40	mohor	`reg ShiftEnded;`
417	60	mohor	`reg RxOverrun;`
418	38	mohor
419	40	mohor	`reg BDWrite; // BD Write Enable for access from WISHBONE side`
420			`reg BDRead; // BD Read access from WISHBONE side`
421	39	mohor	`wire [31:0] RxBDDataIn; // Rx BD data in`
422			`wire [31:0] TxBDDataIn; // Tx BD data in`
423	38	mohor
424	39	mohor	`reg TxEndFrm_wb;`
425	38	mohor
426	39	mohor	`wire TxRetryPulse;`
427	38	mohor	`wire TxDonePulse;`
428			`wire TxAbortPulse;`
429
430			`wire StartRxBDRead;`
431
432			`wire StartTxBDRead;`
433
434			`wire TxIRQEn;`
435			`wire WrapTxStatusBit;`
436
437	77	mohor	`wire RxIRQEn;`
438	38	mohor	`wire WrapRxStatusBit;`
439
440			`wire [1:0] TxValidBytes;`
441
442			`wire [7:0] TempTxBDAddress;`
443			`wire [7:0] TempRxBDAddress;`
444
445			`wire SetGotData;`
446			`wire GotDataEvaluate;`
447
448	106	mohor	`reg WB_ACK_O;`
449	38	mohor
450	60	mohor	`wire [6:0] RxStatusIn;`
451			`reg [6:0] RxStatusInLatched;`
452	42	mohor
453	39	mohor	`reg WbEn, WbEn_q;`
454			`reg RxEn, RxEn_q;`
455			`reg TxEn, TxEn_q;`
456	38	mohor
457	39	mohor	`wire ram_ce;`
458			`wire ram_we;`
459			`wire ram_oe;`
460			`reg [7:0] ram_addr;`
461			`reg [31:0] ram_di;`
462			`wire [31:0] ram_do;`
463	38	mohor
464	39	mohor	`wire StartTxPointerRead;`
465			`reg TxPointerRead;`
466			`reg TxEn_needed;`
467	40	mohor	`reg RxEn_needed;`
468	38	mohor
469	40	mohor	`wire StartRxPointerRead;`
470			`reg RxPointerRead;`
471	38	mohor
472	219	mohor	`ifdef ETH_WISHBONE_B3
473			`assign m_wb_bte_o = 2'b00; // Linear burst`
474			`endif
475	39	mohor
476	219	mohor
477	159	mohor	`always @ (posedge WB_CLK_I)`
478	40	mohor	`begin`
479	159	mohor	`WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q \| BDRead & WbEn & ~WbEn_q;`
480	40	mohor	`end`
481	39	mohor
482	106	mohor	`assign WB_DAT_O = ram_do;`
483	39	mohor
484	41	mohor	`// Generic synchronous single-port RAM interface`
485	119	mohor	`eth_spram_256x32 bd_ram (`
486	226	tadejm	`.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)`
487	210	mohor	`ifdef ETH_BIST
488	219	mohor	`, .trst(trst), .SO(SO), .SI(SI), .shift_DR(shift_DR), .capture_DR(capture_DR), .extest(extest), .tck(tck)`
489	210	mohor	`endif
490	39	mohor	`);`
491	41	mohor
492	39	mohor	`assign ram_ce = 1'b1;`
493	40	mohor	`assign ram_we = BDWrite & WbEn & WbEn_q \| TxStatusWrite \| RxStatusWrite;`
494	61	mohor	`assign ram_oe = BDRead & WbEn & WbEn_q \| TxEn & TxEn_q & (TxBDRead \| TxPointerRead) \| RxEn & RxEn_q & (RxBDRead \| RxPointerRead);`
495	39	mohor
496
497	40	mohor	`always @ (posedge WB_CLK_I or posedge Reset)`
498	38	mohor	`begin`
499	40	mohor	`if(Reset)`
500	39	mohor	`TxEn_needed <=#Tp 1'b0;`

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