OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_rxethmac.v] - Blame information for rev 338

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_rxethmac.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
11
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
12
////                                                              ////
13
////  All additional information is avaliable in the Readme.txt   ////
14
////  file.                                                       ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2001 Authors                                   ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
//
43
// CVS Revision History
44
//
45
// $Log: not supported by cvs2svn $
46 261 mohor
// Revision 1.9  2002/11/19 17:35:35  mohor
47
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
48
// that a frame was received because of the promiscous mode.
49
//
50 250 mohor
// Revision 1.8  2002/02/16 07:15:27  mohor
51
// Testbench fixed, code simplified, unused signals removed.
52
//
53 65 mohor
// Revision 1.7  2002/02/15 13:44:28  mohor
54
// RxAbort is an output. No need to have is declared as wire.
55
//
56 62 mohor
// Revision 1.6  2002/02/15 11:17:48  mohor
57
// File format changed.
58
//
59 58 mohor
// Revision 1.5  2002/02/14 20:48:43  billditt
60
// Addition  of new module eth_addrcheck.v
61
//
62 53 billditt
// Revision 1.4  2002/01/23 10:28:16  mohor
63
// Link in the header changed.
64
//
65 37 mohor
// Revision 1.3  2001/10/19 08:43:51  mohor
66
// eth_timescale.v changed to timescale.v This is done because of the
67
// simulation of the few cores in a one joined project.
68
//
69 22 mohor
// Revision 1.2  2001/09/11 14:17:00  mohor
70
// Few little NCSIM warnings fixed.
71
//
72 18 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
73
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
74
// Include files fixed to contain no path.
75
// File names and module names changed ta have a eth_ prologue in the name.
76
// File eth_timescale.v is used to define timescale
77
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
78
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
79
// and Mdo_OE. The bidirectional signal must be created on the top level. This
80
// is done due to the ASIC tools.
81
//
82 15 mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
83
// Directory structure changed. Files checked and joind together.
84
//
85
// Revision 1.1  2001/06/27 21:26:19  mohor
86
// Initial release of the RxEthMAC module.
87
//
88
//
89
//
90
//
91
//
92
 
93 22 mohor
`include "timescale.v"
94 15 mohor
 
95
 
96
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
97 65 mohor
                     RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
98
                     ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
99 261 mohor
                     MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK
100 15 mohor
                    );
101
 
102
parameter Tp = 1;
103
 
104
 
105
 
106
input         MRxClk;
107
input         MRxDV;
108
input   [3:0] MRxD;
109
input         Transmitting;
110
input         HugEn;
111
input         DlyCrcEn;
112
input  [15:0] MaxFL;
113
input         r_IFG;
114
input         Reset;
115 53 billditt
input  [47:0] MAC;     //  Station Address  
116
input         r_Bro;   //  broadcast disable
117
input         r_Pro;   //  promiscuous enable 
118
input [31:0]  r_HASH0; //  lower 4 bytes Hash Table
119
input [31:0]  r_HASH1; //  upper 4 bytes Hash Table
120 261 mohor
input         PassAll;
121
input         ControlFrmAddressOK;
122
 
123 15 mohor
output  [7:0] RxData;
124
output        RxValid;
125
output        RxStartFrm;
126
output        RxEndFrm;
127
output [15:0] ByteCnt;
128
output        ByteCntEq0;
129
output        ByteCntGreat2;
130
output        ByteCntMaxFrame;
131
output        CrcError;
132
output        StateIdle;
133
output        StatePreamble;
134
output        StateSFD;
135
output  [1:0] StateData;
136 53 billditt
output        RxAbort;
137 250 mohor
output        AddressMiss;
138 15 mohor
 
139
reg     [7:0] RxData;
140
reg           RxValid;
141
reg           RxStartFrm;
142
reg           RxEndFrm;
143
reg           Broadcast;
144
reg           Multicast;
145
reg     [8:0] CrcHash;
146
reg           CrcHashGood;
147
reg           DelayData;
148
reg     [3:0] LatchedNibble;
149
reg     [7:0] LatchedByte;
150
reg     [7:0] RxData_d;
151
reg           RxValid_d;
152
reg           RxStartFrm_d;
153
reg           RxEndFrm_d;
154
 
155
wire          MRxDEqD;
156
wire          MRxDEq5;
157
wire          StateDrop;
158
wire          ByteCntEq1;
159 53 billditt
wire          ByteCntEq2;
160
wire          ByteCntEq3;
161
wire          ByteCntEq4;
162
wire          ByteCntEq5;
163 15 mohor
wire          ByteCntEq6;
164 53 billditt
wire          ByteCntEq7;
165 15 mohor
wire          ByteCntSmall7;
166
wire   [31:0] Crc;
167
wire          Enable_Crc;
168
wire          Initialize_Crc;
169
wire    [3:0] Data_Crc;
170
wire          GenerateRxValid;
171
wire          GenerateRxStartFrm;
172
wire          GenerateRxEndFrm;
173
wire          DribbleRxEndFrm;
174
wire    [3:0] DlyCrcCnt;
175
 
176
 
177
assign MRxDEqD = MRxD == 4'hd;
178
assign MRxDEq5 = MRxD == 4'h5;
179
 
180
 
181
// Rx State Machine module
182
eth_rxstatem rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0),
183
                        .ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5),
184
                        .MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame),
185
                        .StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble),
186
                        .StateSFD(StateSFD), .StateDrop(StateDrop)
187
                       );
188
 
189
 
190
// Rx Counters module
191
eth_rxcounters rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
192
                            .StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
193
                            .StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
194
                            .DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
195
                            .HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
196 58 mohor
                            .ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
197
                            .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6),
198
                            .ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2),
199 15 mohor
                            .ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
200
                            .ByteCnt(ByteCnt)
201
                           );
202
 
203 53 billditt
// Rx Address Check
204 15 mohor
 
205 58 mohor
eth_rxaddrcheck rxaddrcheck1
206 261 mohor
              (.MRxClk(MRxClk),         .Reset( Reset),             .RxData(RxData),
207
               .Broadcast (Broadcast),  .r_Bro (r_Bro),             .r_Pro(r_Pro),
208
               .ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7),    .ByteCntEq2(ByteCntEq2),
209
               .ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4),    .ByteCntEq5(ByteCntEq5),
210 58 mohor
               .HASH0(r_HASH0),         .HASH1(r_HASH1),
211 261 mohor
               .CrcHash(CrcHash[5:0]),  .CrcHashGood(CrcHashGood),  .StateData(StateData),
212
               .Multicast(Multicast),   .MAC(MAC),                  .RxAbort(RxAbort),
213
               .RxEndFrm(RxEndFrm),     .AddressMiss(AddressMiss),  .PassAll(PassAll),
214
               .ControlFrmAddressOK(ControlFrmAddressOK)
215 58 mohor
              );
216 15 mohor
 
217 53 billditt
 
218 15 mohor
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
219
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
220
 
221
assign Data_Crc[0] = MRxD[3];
222
assign Data_Crc[1] = MRxD[2];
223
assign Data_Crc[2] = MRxD[1];
224
assign Data_Crc[3] = MRxD[0];
225
 
226
 
227
// Connecting module Crc
228
eth_crc crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
229
               .Crc(Crc), .CrcError(CrcError)
230 58 mohor
              );
231 15 mohor
 
232
 
233
 
234
// Latching CRC for use in the hash table
235
 
236
always @ (posedge MRxClk)
237
begin
238
  CrcHashGood <= #Tp StateData[0] & ByteCntEq6;
239
end
240
 
241
always @ (posedge MRxClk)
242
begin
243
  if(Reset | StateIdle)
244
    CrcHash[8:0] <= #Tp 9'h0;
245
  else
246
  if(StateData[0] & ByteCntEq6)
247
    CrcHash[8:0] <= #Tp Crc[31:23];
248
end
249
 
250
 
251
// Output byte stream
252
always @ (posedge MRxClk or posedge Reset)
253
begin
254
  if(Reset)
255
    begin
256
      RxData_d[7:0]      <= #Tp 8'h0;
257
      DelayData          <= #Tp 1'b0;
258
      LatchedNibble[3:0] <= #Tp 4'h0;
259
      LatchedByte[7:0]   <= #Tp 8'h0;
260
      RxData[7:0]        <= #Tp 8'h0;
261
    end
262
  else
263
    begin
264
      LatchedNibble[3:0] <= #Tp MRxD[3:0];                        // Latched nibble
265
      LatchedByte[7:0]   <= #Tp {MRxD[3:0], LatchedNibble[3:0]};  // Latched byte
266
      DelayData          <= #Tp StateData[0];
267
 
268
      if(GenerateRxValid)
269
        RxData_d[7:0] <= #Tp LatchedByte[7:0] & {8{|StateData}};  // Data goes through only in data state 
270
      else
271
      if(~DelayData)
272
        RxData_d[7:0] <= #Tp 8'h0;                                // Delaying data to be valid for two cycles. Zero when not active.
273
 
274
      RxData[7:0] <= #Tp RxData_d[7:0];                           // Output data byte
275
    end
276
end
277
 
278
 
279
 
280
always @ (posedge MRxClk or posedge Reset)
281
begin
282
  if(Reset)
283
    Broadcast <= #Tp 1'b0;
284
  else
285
    begin
286
      if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
287
        Broadcast <= #Tp 1'b0;
288
      else
289 18 mohor
      if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
290 15 mohor
        Broadcast <= #Tp 1'b1;
291 58 mohor
      else
292
      if(RxAbort | RxEndFrm)
293
        Broadcast <= #Tp 1'b0;
294 15 mohor
    end
295
end
296
 
297
 
298
always @ (posedge MRxClk or posedge Reset)
299
begin
300
  if(Reset)
301
    Multicast <= #Tp 1'b0;
302
  else
303
    begin
304
      if(Reset)
305
        Multicast <= #Tp 1'b0;
306
      else
307 53 billditt
      if(StateData[0] & ByteCntEq1 & LatchedByte == 8'h01)
308
        Multicast <= #Tp 1'b1;
309 58 mohor
    else if(RxAbort | RxEndFrm)
310
      Multicast <= #Tp 1'b0;
311 15 mohor
    end
312
end
313
 
314
 
315
assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
316
 
317
always @ (posedge MRxClk or posedge Reset)
318
begin
319
  if(Reset)
320
    begin
321
      RxValid_d <= #Tp 1'b0;
322
      RxValid   <= #Tp 1'b0;
323
    end
324
  else
325
    begin
326
      RxValid_d <= #Tp GenerateRxValid;
327
      RxValid   <= #Tp RxValid_d;
328
    end
329
end
330
 
331
 
332
assign GenerateRxStartFrm = StateData[0] & (ByteCntEq1 & ~DlyCrcEn | DlyCrcCnt == 4'h3 & DlyCrcEn);
333
 
334
always @ (posedge MRxClk or posedge Reset)
335
begin
336
  if(Reset)
337
    begin
338
      RxStartFrm_d <= #Tp 1'b0;
339
      RxStartFrm   <= #Tp 1'b0;
340
    end
341
  else
342
    begin
343
      RxStartFrm_d <= #Tp GenerateRxStartFrm;
344
      RxStartFrm   <= #Tp RxStartFrm_d;
345
    end
346
end
347
 
348
 
349
assign GenerateRxEndFrm = StateData[0] & (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
350
assign DribbleRxEndFrm  = StateData[1] &  ~MRxDV & ByteCntGreat2;
351
 
352
 
353
always @ (posedge MRxClk or posedge Reset)
354
begin
355
  if(Reset)
356
    begin
357
      RxEndFrm_d <= #Tp 1'b0;
358
      RxEndFrm   <= #Tp 1'b0;
359
    end
360
  else
361
    begin
362
      RxEndFrm_d <= #Tp GenerateRxEndFrm;
363
      RxEndFrm   <= #Tp RxEndFrm_d | DribbleRxEndFrm;
364
    end
365
end
366
 
367
 
368
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.