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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_top.v] - Blame information for rev 338

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1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_top.v                                                   ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 202 mohor
////  All additional information is available in the Readme.txt   ////
12 15 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 202 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 15 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 276 tadejm
// Revision 1.45  2003/01/22 13:49:26  tadejm
45
// When control packets were received, they were ignored in some cases.
46
//
47 272 tadejm
// Revision 1.44  2003/01/21 12:09:40  mohor
48
// When receiving normal data frame and RxFlow control was switched on, RXB
49
// interrupt was not set.
50
//
51 270 mohor
// Revision 1.43  2002/11/22 01:57:06  mohor
52
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
53
// synchronized.
54
//
55 261 mohor
// Revision 1.42  2002/11/21 00:09:19  mohor
56
// TPauseRq synchronized to tx_clk.
57
//
58 255 mohor
// Revision 1.41  2002/11/19 18:13:49  mohor
59
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
60
//
61 253 mohor
// Revision 1.40  2002/11/19 17:34:25  mohor
62
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
63
// that a frame was received because of the promiscous mode.
64
//
65 250 mohor
// Revision 1.39  2002/11/18 17:31:55  mohor
66
// wb_rst_i is used for MIIM reset.
67
//
68 248 mohor
// Revision 1.38  2002/11/14 18:37:20  mohor
69
// r_Rst signal does not reset any module any more and is removed from the design.
70
//
71 244 mohor
// Revision 1.37  2002/11/13 22:25:36  tadejm
72
// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.
73
//
74 240 tadejm
// Revision 1.36  2002/10/18 17:04:20  tadejm
75
// Changed BIST scan signals.
76
//
77 227 tadejm
// Revision 1.35  2002/10/11 13:36:58  mohor
78
// Typo error fixed. (When using Bist)
79
//
80 218 mohor
// Revision 1.34  2002/10/10 16:49:50  mohor
81
// Signals for WISHBONE B3 compliant interface added.
82
//
83 214 mohor
// Revision 1.33  2002/10/10 16:29:30  mohor
84
// BIST added.
85
//
86 210 mohor
// Revision 1.32  2002/09/20 17:12:58  mohor
87
// CsMiss added. When address between 0x800 and 0xfff is accessed within
88
// Ethernet Core, error acknowledge is generated.
89
//
90 202 mohor
// Revision 1.31  2002/09/12 14:50:17  mohor
91
// CarrierSenseLost bug fixed when operating in full duplex mode.
92
//
93 168 mohor
// Revision 1.30  2002/09/10 10:35:23  mohor
94
// Ethernet debug registers removed.
95
//
96 164 mohor
// Revision 1.29  2002/09/09 13:03:13  mohor
97
// Error acknowledge is generated when accessing BDs and RST bit in the
98
// MODER register (r_Rst) is set.
99
//
100 161 mohor
// Revision 1.28  2002/09/04 18:44:10  mohor
101
// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
102
// connected.
103
//
104 149 mohor
// Revision 1.27  2002/07/25 18:15:37  mohor
105
// RxAbort changed. Packets received with MRxErr (from PHY) are also
106
// aborted.
107
//
108 125 mohor
// Revision 1.26  2002/07/17 18:51:50  mohor
109
// EXTERNAL_DMA removed. External DMA not supported.
110
//
111 114 mohor
// Revision 1.25  2002/05/03 10:15:50  mohor
112
// Outputs registered. Reset changed for eth_wishbone module.
113
//
114 106 mohor
// Revision 1.24  2002/04/22 14:15:42  mohor
115
// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
116
// selected in eth_defines.v
117
//
118 103 mohor
// Revision 1.23  2002/03/25 13:33:53  mohor
119
// md_padoen_o changed to md_padoe_o. Signal was always active high, just
120
// name was incorrect.
121
//
122 95 mohor
// Revision 1.22  2002/02/26 16:59:54  mohor
123
// Small fixes for external/internal DMA missmatches.
124
//
125 80 mohor
// Revision 1.21  2002/02/26 16:21:00  mohor
126
// Interrupts changed in the top file
127
//
128 76 mohor
// Revision 1.20  2002/02/18 10:40:17  mohor
129
// Small fixes.
130
//
131 70 mohor
// Revision 1.19  2002/02/16 14:03:44  mohor
132
// Registered trimmed. Unused registers removed.
133
//
134 68 mohor
// Revision 1.18  2002/02/16 13:06:33  mohor
135
// EXTERNAL_DMA used instead of WISHBONE_DMA.
136
//
137 67 mohor
// Revision 1.17  2002/02/16 07:15:27  mohor
138
// Testbench fixed, code simplified, unused signals removed.
139
//
140 65 mohor
// Revision 1.16  2002/02/15 13:49:39  mohor
141
// RxAbort is connected differently.
142
//
143 63 mohor
// Revision 1.15  2002/02/15 11:38:26  mohor
144
// Changes that were lost when updating from 1.11 to 1.14 fixed.
145
//
146 59 mohor
// Revision 1.14  2002/02/14 20:19:11  billditt
147
// Modified for Address Checking,
148
// addition of eth_addrcheck.v
149
//
150
// Revision 1.13  2002/02/12 17:03:03  mohor
151
// HASH0 and HASH1 registers added. Registers address width was
152
// changed to 8 bits.
153
//
154
// Revision 1.12  2002/02/11 09:18:22  mohor
155
// Tx status is written back to the BD.
156
//
157 43 mohor
// Revision 1.11  2002/02/08 16:21:54  mohor
158
// Rx status is written back to the BD.
159
//
160 42 mohor
// Revision 1.10  2002/02/06 14:10:21  mohor
161
// non-DMA host interface added. Select the right configutation in eth_defines.
162
//
163 41 mohor
// Revision 1.9  2002/01/23 10:28:16  mohor
164
// Link in the header changed.
165
//
166 37 mohor
// Revision 1.8  2001/12/05 15:00:16  mohor
167
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
168
// instead of the number of RX descriptors).
169
//
170 34 mohor
// Revision 1.7  2001/12/05 10:45:59  mohor
171
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
172
//
173 33 mohor
// Revision 1.6  2001/10/19 11:24:29  mohor
174
// Number of addresses (wb_adr_i) minimized.
175
//
176 23 mohor
// Revision 1.5  2001/10/19 08:43:51  mohor
177
// eth_timescale.v changed to timescale.v This is done because of the
178
// simulation of the few cores in a one joined project.
179
//
180 22 mohor
// Revision 1.4  2001/10/18 12:07:11  mohor
181
// Status signals changed, Adress decoding changed, interrupt controller
182
// added.
183
//
184 21 mohor
// Revision 1.3  2001/09/24 15:02:56  mohor
185
// Defines changed (All precede with ETH_). Small changes because some
186
// tools generate warnings when two operands are together. Synchronization
187
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
188
// demands).
189
//
190 20 mohor
// Revision 1.2  2001/08/15 14:03:59  mohor
191
// Signal names changed on the top level for easier pad insertion (ASIC).
192
//
193 17 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
194
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
195
// Include files fixed to contain no path.
196
// File names and module names changed ta have a eth_ prologue in the name.
197
// File eth_timescale.v is used to define timescale
198
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
199
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
200
// and Mdo_OE. The bidirectional signal must be created on the top level. This
201
// is done due to the ASIC tools.
202
//
203 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
204
// Unconnected signals are now connected.
205
//
206
// Revision 1.1  2001/07/30 21:23:42  mohor
207
// Directory structure changed. Files checked and joind together.
208
//
209
//
210
//
211 20 mohor
// 
212 15 mohor
 
213
 
214
`include "eth_defines.v"
215 22 mohor
`include "timescale.v"
216 15 mohor
 
217
 
218
module eth_top
219
(
220
  // WISHBONE common
221 17 mohor
  wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
222 15 mohor
 
223
  // WISHBONE slave
224 17 mohor
  wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
225 15 mohor
 
226 41 mohor
  // WISHBONE master
227
  m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
228
  m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
229
  m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
230
 
231 214 mohor
`ifdef ETH_WISHBONE_B3
232
  m_wb_cti_o, m_wb_bte_o,
233
`endif
234
 
235 15 mohor
  //TX
236 20 mohor
  mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
237 15 mohor
 
238
  //RX
239 20 mohor
  mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
240 15 mohor
 
241
  // MIIM
242 95 mohor
  mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
243 17 mohor
 
244 21 mohor
  int_o
245 17 mohor
 
246 210 mohor
  // Bist
247
`ifdef ETH_BIST
248 227 tadejm
  ,
249
  // debug chain signals
250
  scanb_rst,      // bist scan reset
251
  scanb_clk,      // bist scan clock
252
  scanb_si,       // bist scan serial in
253
  scanb_so,       // bist scan serial out
254
  scanb_en        // bist scan shift enable
255 210 mohor
`endif
256 21 mohor
 
257 15 mohor
);
258
 
259
 
260
parameter Tp = 1;
261
 
262
 
263
// WISHBONE common
264 17 mohor
input           wb_clk_i;     // WISHBONE clock
265
input           wb_rst_i;     // WISHBONE reset
266
input   [31:0]  wb_dat_i;     // WISHBONE data input
267
output  [31:0]  wb_dat_o;     // WISHBONE data output
268
output          wb_err_o;     // WISHBONE error output
269 15 mohor
 
270
// WISHBONE slave
271 23 mohor
input   [11:2]  wb_adr_i;     // WISHBONE address input
272 17 mohor
input    [3:0]  wb_sel_i;     // WISHBONE byte select input
273
input           wb_we_i;      // WISHBONE write enable input
274
input           wb_cyc_i;     // WISHBONE cycle input
275
input           wb_stb_i;     // WISHBONE strobe input
276
output          wb_ack_o;     // WISHBONE acknowledge output
277 15 mohor
 
278 41 mohor
// WISHBONE master
279
output  [31:0]  m_wb_adr_o;
280
output   [3:0]  m_wb_sel_o;
281
output          m_wb_we_o;
282
input   [31:0]  m_wb_dat_i;
283
output  [31:0]  m_wb_dat_o;
284
output          m_wb_cyc_o;
285
output          m_wb_stb_o;
286
input           m_wb_ack_i;
287
input           m_wb_err_i;
288 15 mohor
 
289 214 mohor
`ifdef ETH_WISHBONE_B3
290
output   [2:0]  m_wb_cti_o;   // Cycle Type Identifier
291
output   [1:0]  m_wb_bte_o;   // Burst Type Extension
292
`endif
293 41 mohor
 
294 15 mohor
// Tx
295 20 mohor
input           mtx_clk_pad_i; // Transmit clock (from PHY)
296 21 mohor
output   [3:0]  mtxd_pad_o;    // Transmit nibble (to PHY)
297
output          mtxen_pad_o;   // Transmit enable (to PHY)
298
output          mtxerr_pad_o;  // Transmit error (to PHY)
299 15 mohor
 
300
// Rx
301 20 mohor
input           mrx_clk_pad_i; // Receive clock (from PHY)
302 21 mohor
input    [3:0]  mrxd_pad_i;    // Receive nibble (from PHY)
303
input           mrxdv_pad_i;   // Receive data valid (from PHY)
304
input           mrxerr_pad_i;  // Receive data error (from PHY)
305 15 mohor
 
306
// Common Tx and Rx
307 21 mohor
input           mcoll_pad_i;   // Collision (from PHY)
308
input           mcrs_pad_i;    // Carrier sense (from PHY)
309 15 mohor
 
310
// MII Management interface
311 21 mohor
input           md_pad_i;      // MII data input (from I/O cell)
312
output          mdc_pad_o;     // MII Management data clock (to PHY)
313
output          md_pad_o;      // MII data output (to I/O cell)
314 95 mohor
output          md_padoe_o;    // MII data output enable (to I/O cell)
315 15 mohor
 
316 21 mohor
output          int_o;         // Interrupt output
317 15 mohor
 
318 210 mohor
// Bist
319
`ifdef ETH_BIST
320 227 tadejm
input   scanb_rst;      // bist scan reset
321
input   scanb_clk;      // bist scan clock
322
input   scanb_si;       // bist scan serial in
323
output  scanb_so;       // bist scan serial out
324
input   scanb_en;       // bist scan shift enable
325 210 mohor
`endif
326
 
327 15 mohor
wire     [7:0]  r_ClkDiv;
328
wire            r_MiiNoPre;
329
wire    [15:0]  r_CtrlData;
330
wire     [4:0]  r_FIAD;
331
wire     [4:0]  r_RGAD;
332
wire            r_WCtrlData;
333
wire            r_RStat;
334
wire            r_ScanStat;
335
wire            NValid_stat;
336
wire            Busy_stat;
337
wire            LinkFail;
338
wire    [15:0]  Prsd;             // Read Status Data (data read from the PHY)
339
wire            WCtrlDataStart;
340
wire            RStatStart;
341
wire            UpdateMIIRX_DATAReg;
342
 
343
wire            TxStartFrm;
344
wire            TxEndFrm;
345
wire            TxUsedData;
346
wire     [7:0]  TxData;
347
wire            TxRetry;
348
wire            TxAbort;
349
wire            TxUnderRun;
350
wire            TxDone;
351 42 mohor
wire     [5:0]  CollValid;
352 15 mohor
 
353
 
354 149 mohor
reg             WillSendControlFrame_sync1;
355
reg             WillSendControlFrame_sync2;
356
reg             WillSendControlFrame_sync3;
357
reg             RstTxPauseRq;
358 15 mohor
 
359 255 mohor
reg             TxPauseRq_sync1;
360
reg             TxPauseRq_sync2;
361
reg             TxPauseRq_sync3;
362
reg             TPauseRq;
363 15 mohor
 
364 255 mohor
 
365 15 mohor
// Connecting Miim module
366
eth_miim miim1
367
(
368 248 mohor
  .Clk(wb_clk_i),                         .Reset(wb_rst_i),                   .Divider(r_ClkDiv),
369 15 mohor
  .NoPre(r_MiiNoPre),                     .CtrlData(r_CtrlData),              .Rgad(r_RGAD),
370
  .Fiad(r_FIAD),                          .WCtrlData(r_WCtrlData),            .RStat(r_RStat),
371 17 mohor
  .ScanStat(r_ScanStat),                  .Mdi(md_pad_i),                     .Mdo(md_pad_o),
372 95 mohor
  .MdoEn(md_padoe_o),                     .Mdc(mdc_pad_o),                    .Busy(Busy_stat),
373 15 mohor
  .Prsd(Prsd),                            .LinkFail(LinkFail),                .Nvalid(NValid_stat),
374
  .WCtrlDataStart(WCtrlDataStart),        .RStatStart(RStatStart),            .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
375
);
376
 
377
 
378
 
379
 
380
wire        RegCs;          // Connected to registers
381 17 mohor
wire [31:0] RegDataOut;     // Multiplexed to wb_dat_o
382 42 mohor
wire        r_RecSmall;     // Receive small frames
383 15 mohor
wire        r_LoopBck;      // Loopback
384
wire        r_TxEn;         // Tx Enable
385
wire        r_RxEn;         // Rx Enable
386
 
387
wire        MRxDV_Lb;       // Muxed MII receive data valid
388
wire        MRxErr_Lb;      // Muxed MII Receive Error
389
wire  [3:0] MRxD_Lb;        // Muxed MII Receive Data
390
wire        Transmitting;   // Indication that TxEthMAC is transmitting
391
wire        r_HugEn;        // Huge packet enable
392
wire        r_DlyCrcEn;     // Delayed CRC enabled
393
wire [15:0] r_MaxFL;        // Maximum frame length
394
 
395
wire [15:0] r_MinFL;        // Minimum frame length
396 42 mohor
wire        ShortFrame;
397
wire        DribbleNibble;  // Extra nibble received
398
wire        ReceivedPacketTooBig; // Received packet is too big
399 15 mohor
wire [47:0] r_MAC;          // MAC address
400 42 mohor
wire        LoadRxStatus;   // Rx status was loaded
401 52 billditt
wire [31:0] r_HASH0;        // HASH table, lower 4 bytes
402
wire [31:0] r_HASH1;        // HASH table, upper 4 bytes
403 34 mohor
wire  [7:0] r_TxBDNum;      // Receive buffer descriptor number
404 15 mohor
wire  [6:0] r_IPGT;         // 
405
wire  [6:0] r_IPGR1;        // 
406
wire  [6:0] r_IPGR2;        // 
407
wire  [5:0] r_CollValid;    // 
408 149 mohor
wire [15:0] r_TxPauseTV;    // Transmit PAUSE value
409
wire        r_TxPauseRq;    // Transmit PAUSE request
410 15 mohor
 
411
wire  [3:0] r_MaxRet;       //
412
wire        r_NoBckof;      // 
413
wire        r_ExDfrEn;      // 
414 34 mohor
wire        TX_BD_NUM_Wr;   // Write enable that writes RX_BD_NUM to the registers.
415 15 mohor
wire        r_TxFlow;       // Tx flow control enable
416
wire        r_IFG;          // Minimum interframe gap for incoming packets
417
 
418 21 mohor
wire        TxB_IRQ;        // Interrupt Tx Buffer
419
wire        TxE_IRQ;        // Interrupt Tx Error
420
wire        RxB_IRQ;        // Interrupt Rx Buffer
421 76 mohor
wire        RxE_IRQ;        // Interrupt Rx Error
422 21 mohor
wire        Busy_IRQ;       // Interrupt Busy (lack of buffers)
423 15 mohor
 
424
wire        DWord;
425
wire        BDAck;
426 103 mohor
wire [31:0] BD_WB_DAT_O;    // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
427 21 mohor
wire        BDCs;           // Buffer descriptor CS
428 202 mohor
wire        CsMiss;         // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
429
                            // but data is not valid.
430 15 mohor
 
431 103 mohor
wire        temp_wb_ack_o;
432
wire [31:0] temp_wb_dat_o;
433
wire        temp_wb_err_o;
434 15 mohor
 
435 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
436
  reg         temp_wb_ack_o_reg;
437
  reg [31:0]  temp_wb_dat_o_reg;
438
  reg         temp_wb_err_o_reg;
439
`endif
440
 
441 17 mohor
assign DWord = &wb_sel_i;
442 103 mohor
assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10];   // 0x0   - 0x3FF
443 114 mohor
assign BDCs  = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] &  wb_adr_i[10];   // 0x400 - 0x7FF
444 202 mohor
assign CsMiss = wb_stb_i & wb_cyc_i & DWord & wb_adr_i[11];                   // 0x800 - 0xfFF
445 103 mohor
assign temp_wb_ack_o = RegCs | BDAck;
446
assign temp_wb_dat_o = (RegCs & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
447 240 tadejm
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~DWord | CsMiss);
448 15 mohor
 
449 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
450
  assign wb_ack_o = temp_wb_ack_o_reg;
451
  assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
452
  assign wb_err_o = temp_wb_err_o_reg;
453
`else
454
  assign wb_ack_o = temp_wb_ack_o;
455
  assign wb_dat_o[31:0] = temp_wb_dat_o;
456
  assign wb_err_o = temp_wb_err_o;
457
`endif
458 15 mohor
 
459
 
460
 
461 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
462
  always @ (posedge wb_clk_i or posedge wb_rst_i)
463
  begin
464
    if(wb_rst_i)
465
      begin
466
        temp_wb_ack_o_reg <=#Tp 1'b0;
467
        temp_wb_dat_o_reg <=#Tp 32'h0;
468
        temp_wb_err_o_reg <=#Tp 1'b0;
469
      end
470
    else
471
      begin
472 106 mohor
        temp_wb_ack_o_reg <=#Tp temp_wb_ack_o & ~temp_wb_ack_o_reg;
473 103 mohor
        temp_wb_dat_o_reg <=#Tp temp_wb_dat_o;
474 106 mohor
        temp_wb_err_o_reg <=#Tp temp_wb_err_o & ~temp_wb_err_o_reg;
475 103 mohor
      end
476
  end
477
`endif
478
 
479
 
480 15 mohor
// Connecting Ethernet registers
481
eth_registers ethreg1
482
(
483 47 mohor
  .DataIn(wb_dat_i),                      .Address(wb_adr_i[9:2]),                    .Rw(wb_we_i),
484 17 mohor
  .Cs(RegCs),                             .Clk(wb_clk_i),                             .Reset(wb_rst_i),
485 68 mohor
  .DataOut(RegDataOut),                   .r_RecSmall(r_RecSmall),
486 15 mohor
  .r_Pad(r_Pad),                          .r_HugEn(r_HugEn),                          .r_CrcEn(r_CrcEn),
487 244 mohor
  .r_DlyCrcEn(r_DlyCrcEn),                .r_FullD(r_FullD),
488 15 mohor
  .r_ExDfrEn(r_ExDfrEn),                  .r_NoBckof(r_NoBckof),                      .r_LoopBck(r_LoopBck),
489 52 billditt
  .r_IFG(r_IFG),                          .r_Pro(r_Pro),                              .r_Iam(),
490
  .r_Bro(r_Bro),                          .r_NoPre(r_NoPre),                          .r_TxEn(r_TxEn),
491 76 mohor
  .r_RxEn(r_RxEn),                        .Busy_IRQ(Busy_IRQ),                        .RxE_IRQ(RxE_IRQ),
492 21 mohor
  .RxB_IRQ(RxB_IRQ),                      .TxE_IRQ(TxE_IRQ),                          .TxB_IRQ(TxB_IRQ),
493 149 mohor
  .r_IPGT(r_IPGT),
494 15 mohor
  .r_IPGR1(r_IPGR1),                      .r_IPGR2(r_IPGR2),                          .r_MinFL(r_MinFL),
495
  .r_MaxFL(r_MaxFL),                      .r_MaxRet(r_MaxRet),                        .r_CollValid(r_CollValid),
496
  .r_TxFlow(r_TxFlow),                    .r_RxFlow(r_RxFlow),                        .r_PassAll(r_PassAll),
497 253 mohor
  .r_MiiNoPre(r_MiiNoPre),                .r_ClkDiv(r_ClkDiv),
498 15 mohor
  .r_WCtrlData(r_WCtrlData),              .r_RStat(r_RStat),                          .r_ScanStat(r_ScanStat),
499
  .r_RGAD(r_RGAD),                        .r_FIAD(r_FIAD),                            .r_CtrlData(r_CtrlData),
500
  .NValid_stat(NValid_stat),              .Busy_stat(Busy_stat),
501
  .LinkFail(LinkFail),                    .r_MAC(r_MAC),                              .WCtrlDataStart(WCtrlDataStart),
502
  .RStatStart(RStatStart),                .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg),  .Prsd(Prsd),
503 47 mohor
  .r_TxBDNum(r_TxBDNum),                  .TX_BD_NUM_Wr(TX_BD_NUM_Wr),                .int_o(int_o),
504 149 mohor
  .r_HASH0(r_HASH0),                      .r_HASH1(r_HASH1),                          .r_TxPauseRq(r_TxPauseRq),
505
  .r_TxPauseTV(r_TxPauseTV),              .RstTxPauseRq(RstTxPauseRq),                .TxCtrlEndFrm(TxCtrlEndFrm),
506
  .StartTxDone(StartTxDone),              .TxClk(mtx_clk_pad_i),                      .RxClk(mrx_clk_pad_i),
507 261 mohor
  .SetPauseTimer(SetPauseTimer)
508 149 mohor
 
509 15 mohor
);
510
 
511
 
512
 
513
wire  [7:0] RxData;
514
wire        RxValid;
515
wire        RxStartFrm;
516
wire        RxEndFrm;
517 41 mohor
wire        RxAbort;
518 15 mohor
 
519
wire        WillTransmit;            // Will transmit (to RxEthMAC)
520
wire        ResetCollision;          // Reset Collision (for synchronizing collision)
521
wire  [7:0] TxDataOut;               // Transmit Packet Data (to TxEthMAC)
522
wire        WillSendControlFrame;
523
wire        ReceiveEnd;
524
wire        ReceivedPacketGood;
525
wire        ReceivedLengthOK;
526 42 mohor
wire        InvalidSymbol;
527
wire        LatchedCrcError;
528
wire        RxLateCollision;
529 59 mohor
wire  [3:0] RetryCntLatched;
530
wire  [3:0] RetryCnt;
531
wire        StartTxAbort;
532
wire        MaxCollisionOccured;
533
wire        RetryLimit;
534
wire        StatePreamble;
535
wire  [1:0] StateData;
536 15 mohor
 
537
// Connecting MACControl
538
eth_maccontrol maccontrol1
539
(
540 255 mohor
  .MTxClk(mtx_clk_pad_i),                       .TPauseRq(TPauseRq),
541 149 mohor
  .TxPauseTV(r_TxPauseTV),                      .TxDataIn(TxData),
542 15 mohor
  .TxStartFrmIn(TxStartFrm),                    .TxEndFrmIn(TxEndFrm),
543
  .TxUsedDataIn(TxUsedDataIn),                  .TxDoneIn(TxDoneIn),
544 20 mohor
  .TxAbortIn(TxAbortIn),                        .MRxClk(mrx_clk_pad_i),
545 15 mohor
  .RxData(RxData),                              .RxValid(RxValid),
546
  .RxStartFrm(RxStartFrm),                      .RxEndFrm(RxEndFrm),
547
  .ReceiveEnd(ReceiveEnd),                      .ReceivedPacketGood(ReceivedPacketGood),
548 261 mohor
  .TxFlow(r_TxFlow),
549 15 mohor
  .RxFlow(r_RxFlow),                            .DlyCrcEn(r_DlyCrcEn),
550
  .MAC(r_MAC),                                  .PadIn(r_Pad | PerPacketPad),
551
  .PadOut(PadOut),                              .CrcEnIn(r_CrcEn | PerPacketCrcEn),
552 240 tadejm
  .CrcEnOut(CrcEnOut),                          .TxReset(wb_rst_i),
553
  .RxReset(wb_rst_i),                           .ReceivedLengthOK(ReceivedLengthOK),
554 15 mohor
  .TxDataOut(TxDataOut),                        .TxStartFrmOut(TxStartFrmOut),
555
  .TxEndFrmOut(TxEndFrmOut),                    .TxUsedDataOut(TxUsedData),
556
  .TxDoneOut(TxDone),                           .TxAbortOut(TxAbort),
557
  .WillSendControlFrame(WillSendControlFrame),  .TxCtrlEndFrm(TxCtrlEndFrm),
558 261 mohor
  .ReceivedPauseFrm(ReceivedPauseFrm),          .ControlFrmAddressOK(ControlFrmAddressOK),
559 272 tadejm
  .SetPauseTimer(SetPauseTimer),
560
  .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),                .r_PassAll(r_PassAll)
561 15 mohor
);
562
 
563
 
564
 
565
wire TxCarrierSense;          // Synchronized CarrierSense (to Tx clock)
566
wire Collision;               // Synchronized Collision
567
 
568
reg CarrierSense_Tx1;
569
reg CarrierSense_Tx2;
570
reg Collision_Tx1;
571
reg Collision_Tx2;
572
 
573
reg RxEnSync;                 // Synchronized Receive Enable
574
reg CarrierSense_Rx1;
575
reg RxCarrierSense;           // Synchronized CarrierSense (to Rx clock)
576
reg WillTransmit_q;
577
reg WillTransmit_q2;
578
 
579
 
580
 
581
// Muxed MII receive data valid
582 17 mohor
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
583 15 mohor
 
584
// Muxed MII Receive Error
585 17 mohor
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
586 15 mohor
 
587
// Muxed MII Receive Data
588 17 mohor
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
589 15 mohor
 
590
 
591
 
592
// Connecting TxEthMAC
593
eth_txethmac txethmac1
594
(
595 240 tadejm
  .MTxClk(mtx_clk_pad_i),             .Reset(wb_rst_i),                   .CarrierSense(TxCarrierSense),
596 15 mohor
  .Collision(Collision),              .TxData(TxDataOut),                 .TxStartFrm(TxStartFrmOut),
597
  .TxUnderRun(TxUnderRun),            .TxEndFrm(TxEndFrmOut),             .Pad(PadOut),
598
  .MinFL(r_MinFL),                    .CrcEn(CrcEnOut),                   .FullD(r_FullD),
599
  .HugEn(r_HugEn),                    .DlyCrcEn(r_DlyCrcEn),              .IPGT(r_IPGT),
600
  .IPGR1(r_IPGR1),                    .IPGR2(r_IPGR2),                    .CollValid(r_CollValid),
601
  .MaxRet(r_MaxRet),                  .NoBckof(r_NoBckof),                .ExDfrEn(r_ExDfrEn),
602 17 mohor
  .MaxFL(r_MaxFL),                    .MTxEn(mtxen_pad_o),                .MTxD(mtxd_pad_o),
603
  .MTxErr(mtxerr_pad_o),              .TxUsedData(TxUsedDataIn),          .TxDone(TxDoneIn),
604 15 mohor
  .TxRetry(TxRetry),                  .TxAbort(TxAbortIn),                .WillTransmit(WillTransmit),
605 59 mohor
  .ResetCollision(ResetCollision),    .RetryCnt(RetryCnt),                .StartTxDone(StartTxDone),
606
  .StartTxAbort(StartTxAbort),        .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
607 276 tadejm
  .DeferIndication(DeferIndication),  .StatePreamble(StatePreamble),      .StateData(StateData)
608 15 mohor
);
609
 
610
 
611
 
612
 
613
wire  [15:0]  RxByteCnt;
614
wire          RxByteCntEq0;
615
wire          RxByteCntGreat2;
616
wire          RxByteCntMaxFrame;
617
wire          RxCrcError;
618
wire          RxStateIdle;
619
wire          RxStatePreamble;
620
wire          RxStateSFD;
621
wire   [1:0]  RxStateData;
622 250 mohor
wire          AddressMiss;
623 15 mohor
 
624
 
625
 
626
// Connecting RxEthMAC
627
eth_rxethmac rxethmac1
628
(
629 21 mohor
  .MRxClk(mrx_clk_pad_i),               .MRxDV(MRxDV_Lb),                     .MRxD(MRxD_Lb),
630 15 mohor
  .Transmitting(Transmitting),          .HugEn(r_HugEn),                      .DlyCrcEn(r_DlyCrcEn),
631 240 tadejm
  .MaxFL(r_MaxFL),                      .r_IFG(r_IFG),                        .Reset(wb_rst_i),
632 15 mohor
  .RxData(RxData),                      .RxValid(RxValid),                    .RxStartFrm(RxStartFrm),
633 65 mohor
  .RxEndFrm(RxEndFrm),                  .ByteCnt(RxByteCnt),
634 15 mohor
  .ByteCntEq0(RxByteCntEq0),            .ByteCntGreat2(RxByteCntGreat2),      .ByteCntMaxFrame(RxByteCntMaxFrame),
635
  .CrcError(RxCrcError),                .StateIdle(RxStateIdle),              .StatePreamble(RxStatePreamble),
636 52 billditt
  .StateSFD(RxStateSFD),                .StateData(RxStateData),
637 63 mohor
  .MAC(r_MAC),                          .r_Pro(r_Pro),                        .r_Bro(r_Bro),
638 250 mohor
  .r_HASH0(r_HASH0),                    .r_HASH1(r_HASH1),                    .RxAbort(RxAbort),
639 261 mohor
  .AddressMiss(AddressMiss),            .PassAll(r_PassAll),                  .ControlFrmAddressOK(ControlFrmAddressOK)
640 15 mohor
);
641
 
642
 
643
// MII Carrier Sense Synchronization
644 240 tadejm
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
645 15 mohor
begin
646 240 tadejm
  if(wb_rst_i)
647 15 mohor
    begin
648
      CarrierSense_Tx1 <= #Tp 1'b0;
649
      CarrierSense_Tx2 <= #Tp 1'b0;
650
    end
651
  else
652
    begin
653 17 mohor
      CarrierSense_Tx1 <= #Tp mcrs_pad_i;
654 15 mohor
      CarrierSense_Tx2 <= #Tp CarrierSense_Tx1;
655
    end
656
end
657
 
658
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
659
 
660
 
661
// MII Collision Synchronization
662 240 tadejm
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
663 15 mohor
begin
664 240 tadejm
  if(wb_rst_i)
665 15 mohor
    begin
666
      Collision_Tx1 <= #Tp 1'b0;
667
      Collision_Tx2 <= #Tp 1'b0;
668
    end
669
  else
670
    begin
671 17 mohor
      Collision_Tx1 <= #Tp mcoll_pad_i;
672 15 mohor
      if(ResetCollision)
673
        Collision_Tx2 <= #Tp 1'b0;
674
      else
675
      if(Collision_Tx1)
676
        Collision_Tx2 <= #Tp 1'b1;
677
    end
678
end
679
 
680
 
681
// Synchronized Collision
682
assign Collision = ~r_FullD & Collision_Tx2;
683
 
684
 
685
 
686
// Carrier sense is synchronized to receive clock.
687 240 tadejm
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
688 15 mohor
begin
689 240 tadejm
  if(wb_rst_i)
690 15 mohor
    begin
691
      CarrierSense_Rx1 <= #Tp 1'h0;
692
      RxCarrierSense <= #Tp 1'h0;
693
    end
694
  else
695
    begin
696 17 mohor
      CarrierSense_Rx1 <= #Tp mcrs_pad_i;
697 15 mohor
      RxCarrierSense <= #Tp CarrierSense_Rx1;
698
    end
699
end
700
 
701
 
702
// Delayed WillTransmit
703 20 mohor
always @ (posedge mrx_clk_pad_i)
704 15 mohor
begin
705
  WillTransmit_q <= #Tp WillTransmit;
706
  WillTransmit_q2 <= #Tp WillTransmit_q;
707
end
708
 
709
 
710
assign Transmitting = ~r_FullD & WillTransmit_q2;
711
 
712
 
713
 
714
// Synchronized Receive Enable
715 240 tadejm
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
716 15 mohor
begin
717 240 tadejm
  if(wb_rst_i)
718 15 mohor
    RxEnSync <= #Tp 1'b0;
719
  else
720
  if(~RxCarrierSense | RxCarrierSense & Transmitting)
721
    RxEnSync <= #Tp r_RxEn;
722
end
723
 
724
 
725
 
726 149 mohor
// Synchronizing WillSendControlFrame to WB_CLK;
727
always @ (posedge wb_clk_i or posedge wb_rst_i)
728
begin
729
  if(wb_rst_i)
730
    WillSendControlFrame_sync1 <= 1'b0;
731
  else
732
    WillSendControlFrame_sync1 <=#Tp WillSendControlFrame;
733
end
734 15 mohor
 
735 149 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
736
begin
737
  if(wb_rst_i)
738
    WillSendControlFrame_sync2 <= 1'b0;
739
  else
740
    WillSendControlFrame_sync2 <=#Tp WillSendControlFrame_sync1;
741
end
742
 
743
always @ (posedge wb_clk_i or posedge wb_rst_i)
744
begin
745
  if(wb_rst_i)
746
    WillSendControlFrame_sync3 <= 1'b0;
747
  else
748
    WillSendControlFrame_sync3 <=#Tp WillSendControlFrame_sync2;
749
end
750
 
751
always @ (posedge wb_clk_i or posedge wb_rst_i)
752
begin
753
  if(wb_rst_i)
754
    RstTxPauseRq <= 1'b0;
755
  else
756
    RstTxPauseRq <=#Tp WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
757
end
758
 
759
 
760 255 mohor
 
761
 
762
// TX Pause request Synchronization
763
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
764
begin
765
  if(wb_rst_i)
766
    begin
767
      TxPauseRq_sync1 <= #Tp 1'b0;
768
      TxPauseRq_sync2 <= #Tp 1'b0;
769
      TxPauseRq_sync3 <= #Tp 1'b0;
770
    end
771
  else
772
    begin
773
      TxPauseRq_sync1 <= #Tp (r_TxPauseRq & r_TxFlow);
774
      TxPauseRq_sync2 <= #Tp TxPauseRq_sync1;
775
      TxPauseRq_sync3 <= #Tp TxPauseRq_sync2;
776
    end
777
end
778
 
779
 
780
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
781
begin
782
  if(wb_rst_i)
783
    TPauseRq <= #Tp 1'b0;
784
  else
785
    TPauseRq <= #Tp TxPauseRq_sync2 & (~TxPauseRq_sync3);
786
end
787
 
788
 
789 261 mohor
wire LatchedMRxErr;
790
reg RxAbort_latch;
791
reg RxAbort_sync1;
792
reg RxAbort_sync2;
793
reg RxAbort_wb;
794
reg RxAbortRst_sync1;
795
reg RxAbortRst;
796 255 mohor
 
797 261 mohor
// Synchronizing RxAbort to the WISHBONE clock
798
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
799
begin
800
  if(wb_rst_i)
801
    RxAbort_latch <= #Tp 1'b0;
802
  else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
803
    RxAbort_latch <= #Tp 1'b1;
804
  else if(RxAbortRst)
805
    RxAbort_latch <= #Tp 1'b0;
806
end
807 255 mohor
 
808 261 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
809
begin
810
  if(wb_rst_i)
811
    begin
812
      RxAbort_sync1 <= #Tp 1'b0;
813
      RxAbort_wb    <= #Tp 1'b0;
814
      RxAbort_wb    <= #Tp 1'b0;
815
    end
816
  else
817
    begin
818
      RxAbort_sync1 <= #Tp RxAbort_latch;
819
      RxAbort_wb    <= #Tp RxAbort_sync1;
820
    end
821
end
822
 
823
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
824
begin
825
  if(wb_rst_i)
826
    begin
827
      RxAbortRst_sync1 <= #Tp 1'b0;
828
      RxAbortRst       <= #Tp 1'b0;
829
    end
830
  else
831
    begin
832
      RxAbortRst_sync1 <= #Tp RxAbort_wb;
833
      RxAbortRst       <= #Tp RxAbortRst_sync1;
834
    end
835
end
836
 
837
 
838
 
839 114 mohor
// Connecting Wishbone module
840 41 mohor
eth_wishbone wishbone
841 15 mohor
(
842 41 mohor
  .WB_CLK_I(wb_clk_i),                .WB_DAT_I(wb_dat_i),
843 103 mohor
  .WB_DAT_O(BD_WB_DAT_O),
844 15 mohor
 
845
  // WISHBONE slave
846 76 mohor
  .WB_ADR_I(wb_adr_i[9:2]),           .WB_WE_I(wb_we_i),
847 21 mohor
  .BDCs(BDCs),                        .WB_ACK_O(BDAck),
848 15 mohor
 
849 240 tadejm
  .Reset(wb_rst_i),
850 41 mohor
 
851
  // WISHBONE master
852
  .m_wb_adr_o(m_wb_adr_o),            .m_wb_sel_o(m_wb_sel_o),                  .m_wb_we_o(m_wb_we_o),
853
  .m_wb_dat_i(m_wb_dat_i),            .m_wb_dat_o(m_wb_dat_o),                  .m_wb_cyc_o(m_wb_cyc_o),
854
  .m_wb_stb_o(m_wb_stb_o),            .m_wb_ack_i(m_wb_ack_i),                  .m_wb_err_i(m_wb_err_i),
855 214 mohor
 
856
`ifdef ETH_WISHBONE_B3
857
  .m_wb_cti_o(m_wb_cti_o),            .m_wb_bte_o(m_wb_bte_o),
858
`endif
859
 
860 41 mohor
 
861 15 mohor
    //TX
862 21 mohor
  .MTxClk(mtx_clk_pad_i),             .TxStartFrm(TxStartFrm),                  .TxEndFrm(TxEndFrm),
863 59 mohor
  .TxUsedData(TxUsedData),            .TxData(TxData),
864 15 mohor
  .TxRetry(TxRetry),                  .TxAbort(TxAbort),                        .TxUnderRun(TxUnderRun),
865 149 mohor
  .TxDone(TxDone),
866
  .PerPacketCrcEn(PerPacketCrcEn),    .PerPacketPad(PerPacketPad),
867 15 mohor
 
868
  // Register
869 34 mohor
  .r_TxEn(r_TxEn),                    .r_RxEn(r_RxEn),                          .r_TxBDNum(r_TxBDNum),
870 270 mohor
  .TX_BD_NUM_Wr(TX_BD_NUM_Wr),        .r_RxFlow(r_RxFlow),                      .r_PassAll(r_PassAll),
871 15 mohor
 
872
  //RX
873 21 mohor
  .MRxClk(mrx_clk_pad_i),             .RxData(RxData),                          .RxValid(RxValid),
874 41 mohor
  .RxStartFrm(RxStartFrm),            .RxEndFrm(RxEndFrm),
875 76 mohor
  .Busy_IRQ(Busy_IRQ),                .RxE_IRQ(RxE_IRQ),                        .RxB_IRQ(RxB_IRQ),
876 149 mohor
  .TxE_IRQ(TxE_IRQ),                  .TxB_IRQ(TxB_IRQ),
877 21 mohor
 
878 272 tadejm
  .RxAbort(RxAbort_wb),               .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
879 41 mohor
 
880 42 mohor
  .InvalidSymbol(InvalidSymbol),      .LatchedCrcError(LatchedCrcError),        .RxLength(RxByteCnt),
881
  .RxLateCollision(RxLateCollision),  .ShortFrame(ShortFrame),                  .DribbleNibble(DribbleNibble),
882 59 mohor
  .ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus),     .RetryCntLatched(RetryCntLatched),
883
  .RetryLimit(RetryLimit),            .LateCollLatched(LateCollLatched),        .DeferLatched(DeferLatched),
884 261 mohor
  .CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood),  .AddressMiss(AddressMiss),
885
  .ReceivedPauseFrm(ReceivedPauseFrm)
886 59 mohor
 
887 210 mohor
`ifdef ETH_BIST
888 218 mohor
  ,
889 227 tadejm
  .scanb_rst      (scanb_rst),
890
  .scanb_clk      (scanb_clk),
891
  .scanb_si       (scanb_si),
892
  .scanb_so       (scanb_so),
893
  .scanb_en       (scanb_en)
894 210 mohor
`endif
895 15 mohor
);
896
 
897
 
898
 
899
// Connecting MacStatus module
900
eth_macstatus macstatus1
901
(
902 240 tadejm
  .MRxClk(mrx_clk_pad_i),             .Reset(wb_rst_i),
903 42 mohor
  .ReceiveEnd(ReceiveEnd),            .ReceivedPacketGood(ReceivedPacketGood),     .ReceivedLengthOK(ReceivedLengthOK),
904
  .RxCrcError(RxCrcError),            .MRxErr(MRxErr_Lb),                          .MRxDV(MRxDV_Lb),
905
  .RxStateSFD(RxStateSFD),            .RxStateData(RxStateData),                   .RxStatePreamble(RxStatePreamble),
906
  .RxStateIdle(RxStateIdle),          .Transmitting(Transmitting),                 .RxByteCnt(RxByteCnt),
907
  .RxByteCntEq0(RxByteCntEq0),        .RxByteCntGreat2(RxByteCntGreat2),           .RxByteCntMaxFrame(RxByteCntMaxFrame),
908 261 mohor
  .InvalidSymbol(InvalidSymbol),
909 42 mohor
  .MRxD(MRxD_Lb),                     .LatchedCrcError(LatchedCrcError),           .Collision(mcoll_pad_i),
910
  .CollValid(r_CollValid),            .RxLateCollision(RxLateCollision),           .r_RecSmall(r_RecSmall),
911
  .r_MinFL(r_MinFL),                  .r_MaxFL(r_MaxFL),                           .ShortFrame(ShortFrame),
912
  .DribbleNibble(DribbleNibble),      .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
913 59 mohor
  .LoadRxStatus(LoadRxStatus),        .RetryCnt(RetryCnt),                         .StartTxDone(StartTxDone),
914
  .StartTxAbort(StartTxAbort),        .RetryCntLatched(RetryCntLatched),           .MTxClk(mtx_clk_pad_i),
915
  .MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit),              .LateCollision(LateCollision),
916 276 tadejm
  .LateCollLatched(LateCollLatched),  .DeferIndication(DeferIndication),           .DeferLatched(DeferLatched),
917 59 mohor
  .TxStartFrm(TxStartFrmOut),         .StatePreamble(StatePreamble),               .StateData(StateData),
918 125 mohor
  .CarrierSense(CarrierSense_Tx2),    .CarrierSenseLost(CarrierSenseLost),         .TxUsedData(TxUsedDataIn),
919 168 mohor
  .LatchedMRxErr(LatchedMRxErr),      .Loopback(r_LoopBck),                        .r_FullD(r_FullD)
920 15 mohor
);
921
 
922
 
923
endmodule

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