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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_top.v] - Blame information for rev 227

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1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_top.v                                                   ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 202 mohor
////  All additional information is available in the Readme.txt   ////
12 15 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 202 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 15 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 227 tadejm
// Revision 1.35  2002/10/11 13:36:58  mohor
45
// Typo error fixed. (When using Bist)
46
//
47 218 mohor
// Revision 1.34  2002/10/10 16:49:50  mohor
48
// Signals for WISHBONE B3 compliant interface added.
49
//
50 214 mohor
// Revision 1.33  2002/10/10 16:29:30  mohor
51
// BIST added.
52
//
53 210 mohor
// Revision 1.32  2002/09/20 17:12:58  mohor
54
// CsMiss added. When address between 0x800 and 0xfff is accessed within
55
// Ethernet Core, error acknowledge is generated.
56
//
57 202 mohor
// Revision 1.31  2002/09/12 14:50:17  mohor
58
// CarrierSenseLost bug fixed when operating in full duplex mode.
59
//
60 168 mohor
// Revision 1.30  2002/09/10 10:35:23  mohor
61
// Ethernet debug registers removed.
62
//
63 164 mohor
// Revision 1.29  2002/09/09 13:03:13  mohor
64
// Error acknowledge is generated when accessing BDs and RST bit in the
65
// MODER register (r_Rst) is set.
66
//
67 161 mohor
// Revision 1.28  2002/09/04 18:44:10  mohor
68
// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
69
// connected.
70
//
71 149 mohor
// Revision 1.27  2002/07/25 18:15:37  mohor
72
// RxAbort changed. Packets received with MRxErr (from PHY) are also
73
// aborted.
74
//
75 125 mohor
// Revision 1.26  2002/07/17 18:51:50  mohor
76
// EXTERNAL_DMA removed. External DMA not supported.
77
//
78 114 mohor
// Revision 1.25  2002/05/03 10:15:50  mohor
79
// Outputs registered. Reset changed for eth_wishbone module.
80
//
81 106 mohor
// Revision 1.24  2002/04/22 14:15:42  mohor
82
// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
83
// selected in eth_defines.v
84
//
85 103 mohor
// Revision 1.23  2002/03/25 13:33:53  mohor
86
// md_padoen_o changed to md_padoe_o. Signal was always active high, just
87
// name was incorrect.
88
//
89 95 mohor
// Revision 1.22  2002/02/26 16:59:54  mohor
90
// Small fixes for external/internal DMA missmatches.
91
//
92 80 mohor
// Revision 1.21  2002/02/26 16:21:00  mohor
93
// Interrupts changed in the top file
94
//
95 76 mohor
// Revision 1.20  2002/02/18 10:40:17  mohor
96
// Small fixes.
97
//
98 70 mohor
// Revision 1.19  2002/02/16 14:03:44  mohor
99
// Registered trimmed. Unused registers removed.
100
//
101 68 mohor
// Revision 1.18  2002/02/16 13:06:33  mohor
102
// EXTERNAL_DMA used instead of WISHBONE_DMA.
103
//
104 67 mohor
// Revision 1.17  2002/02/16 07:15:27  mohor
105
// Testbench fixed, code simplified, unused signals removed.
106
//
107 65 mohor
// Revision 1.16  2002/02/15 13:49:39  mohor
108
// RxAbort is connected differently.
109
//
110 63 mohor
// Revision 1.15  2002/02/15 11:38:26  mohor
111
// Changes that were lost when updating from 1.11 to 1.14 fixed.
112
//
113 59 mohor
// Revision 1.14  2002/02/14 20:19:11  billditt
114
// Modified for Address Checking,
115
// addition of eth_addrcheck.v
116
//
117
// Revision 1.13  2002/02/12 17:03:03  mohor
118
// HASH0 and HASH1 registers added. Registers address width was
119
// changed to 8 bits.
120
//
121
// Revision 1.12  2002/02/11 09:18:22  mohor
122
// Tx status is written back to the BD.
123
//
124 43 mohor
// Revision 1.11  2002/02/08 16:21:54  mohor
125
// Rx status is written back to the BD.
126
//
127 42 mohor
// Revision 1.10  2002/02/06 14:10:21  mohor
128
// non-DMA host interface added. Select the right configutation in eth_defines.
129
//
130 41 mohor
// Revision 1.9  2002/01/23 10:28:16  mohor
131
// Link in the header changed.
132
//
133 37 mohor
// Revision 1.8  2001/12/05 15:00:16  mohor
134
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
135
// instead of the number of RX descriptors).
136
//
137 34 mohor
// Revision 1.7  2001/12/05 10:45:59  mohor
138
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
139
//
140 33 mohor
// Revision 1.6  2001/10/19 11:24:29  mohor
141
// Number of addresses (wb_adr_i) minimized.
142
//
143 23 mohor
// Revision 1.5  2001/10/19 08:43:51  mohor
144
// eth_timescale.v changed to timescale.v This is done because of the
145
// simulation of the few cores in a one joined project.
146
//
147 22 mohor
// Revision 1.4  2001/10/18 12:07:11  mohor
148
// Status signals changed, Adress decoding changed, interrupt controller
149
// added.
150
//
151 21 mohor
// Revision 1.3  2001/09/24 15:02:56  mohor
152
// Defines changed (All precede with ETH_). Small changes because some
153
// tools generate warnings when two operands are together. Synchronization
154
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
155
// demands).
156
//
157 20 mohor
// Revision 1.2  2001/08/15 14:03:59  mohor
158
// Signal names changed on the top level for easier pad insertion (ASIC).
159
//
160 17 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
161
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
162
// Include files fixed to contain no path.
163
// File names and module names changed ta have a eth_ prologue in the name.
164
// File eth_timescale.v is used to define timescale
165
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
166
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
167
// and Mdo_OE. The bidirectional signal must be created on the top level. This
168
// is done due to the ASIC tools.
169
//
170 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
171
// Unconnected signals are now connected.
172
//
173
// Revision 1.1  2001/07/30 21:23:42  mohor
174
// Directory structure changed. Files checked and joind together.
175
//
176
//
177
//
178 20 mohor
// 
179 15 mohor
 
180
 
181
`include "eth_defines.v"
182 22 mohor
`include "timescale.v"
183 15 mohor
 
184
 
185
module eth_top
186
(
187
  // WISHBONE common
188 17 mohor
  wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
189 15 mohor
 
190
  // WISHBONE slave
191 17 mohor
  wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
192 15 mohor
 
193 41 mohor
  // WISHBONE master
194
  m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
195
  m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
196
  m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
197
 
198 214 mohor
`ifdef ETH_WISHBONE_B3
199
  m_wb_cti_o, m_wb_bte_o,
200
`endif
201
 
202 15 mohor
  //TX
203 20 mohor
  mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
204 15 mohor
 
205
  //RX
206 20 mohor
  mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
207 15 mohor
 
208
  // MIIM
209 95 mohor
  mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
210 17 mohor
 
211 21 mohor
  int_o
212 17 mohor
 
213 210 mohor
  // Bist
214
`ifdef ETH_BIST
215 227 tadejm
  ,
216
  // debug chain signals
217
  scanb_rst,      // bist scan reset
218
  scanb_clk,      // bist scan clock
219
  scanb_si,       // bist scan serial in
220
  scanb_so,       // bist scan serial out
221
  scanb_en        // bist scan shift enable
222 210 mohor
`endif
223 21 mohor
 
224 15 mohor
);
225
 
226
 
227
parameter Tp = 1;
228
 
229
 
230
// WISHBONE common
231 17 mohor
input           wb_clk_i;     // WISHBONE clock
232
input           wb_rst_i;     // WISHBONE reset
233
input   [31:0]  wb_dat_i;     // WISHBONE data input
234
output  [31:0]  wb_dat_o;     // WISHBONE data output
235
output          wb_err_o;     // WISHBONE error output
236 15 mohor
 
237
// WISHBONE slave
238 23 mohor
input   [11:2]  wb_adr_i;     // WISHBONE address input
239 17 mohor
input    [3:0]  wb_sel_i;     // WISHBONE byte select input
240
input           wb_we_i;      // WISHBONE write enable input
241
input           wb_cyc_i;     // WISHBONE cycle input
242
input           wb_stb_i;     // WISHBONE strobe input
243
output          wb_ack_o;     // WISHBONE acknowledge output
244 15 mohor
 
245 41 mohor
// WISHBONE master
246
output  [31:0]  m_wb_adr_o;
247
output   [3:0]  m_wb_sel_o;
248
output          m_wb_we_o;
249
input   [31:0]  m_wb_dat_i;
250
output  [31:0]  m_wb_dat_o;
251
output          m_wb_cyc_o;
252
output          m_wb_stb_o;
253
input           m_wb_ack_i;
254
input           m_wb_err_i;
255 15 mohor
 
256 214 mohor
`ifdef ETH_WISHBONE_B3
257
output   [2:0]  m_wb_cti_o;   // Cycle Type Identifier
258
output   [1:0]  m_wb_bte_o;   // Burst Type Extension
259
`endif
260 41 mohor
 
261 15 mohor
// Tx
262 20 mohor
input           mtx_clk_pad_i; // Transmit clock (from PHY)
263 21 mohor
output   [3:0]  mtxd_pad_o;    // Transmit nibble (to PHY)
264
output          mtxen_pad_o;   // Transmit enable (to PHY)
265
output          mtxerr_pad_o;  // Transmit error (to PHY)
266 15 mohor
 
267
// Rx
268 20 mohor
input           mrx_clk_pad_i; // Receive clock (from PHY)
269 21 mohor
input    [3:0]  mrxd_pad_i;    // Receive nibble (from PHY)
270
input           mrxdv_pad_i;   // Receive data valid (from PHY)
271
input           mrxerr_pad_i;  // Receive data error (from PHY)
272 15 mohor
 
273
// Common Tx and Rx
274 21 mohor
input           mcoll_pad_i;   // Collision (from PHY)
275
input           mcrs_pad_i;    // Carrier sense (from PHY)
276 15 mohor
 
277
// MII Management interface
278 21 mohor
input           md_pad_i;      // MII data input (from I/O cell)
279
output          mdc_pad_o;     // MII Management data clock (to PHY)
280
output          md_pad_o;      // MII data output (to I/O cell)
281 95 mohor
output          md_padoe_o;    // MII data output enable (to I/O cell)
282 15 mohor
 
283 21 mohor
output          int_o;         // Interrupt output
284 15 mohor
 
285 210 mohor
// Bist
286
`ifdef ETH_BIST
287 227 tadejm
input   scanb_rst;      // bist scan reset
288
input   scanb_clk;      // bist scan clock
289
input   scanb_si;       // bist scan serial in
290
output  scanb_so;       // bist scan serial out
291
input   scanb_en;       // bist scan shift enable
292 210 mohor
`endif
293
 
294 15 mohor
wire     [7:0]  r_ClkDiv;
295
wire            r_MiiNoPre;
296
wire    [15:0]  r_CtrlData;
297
wire     [4:0]  r_FIAD;
298
wire     [4:0]  r_RGAD;
299
wire            r_WCtrlData;
300
wire            r_RStat;
301
wire            r_ScanStat;
302
wire            NValid_stat;
303
wire            Busy_stat;
304
wire            LinkFail;
305
wire            r_MiiMRst;
306
wire    [15:0]  Prsd;             // Read Status Data (data read from the PHY)
307
wire            WCtrlDataStart;
308
wire            RStatStart;
309
wire            UpdateMIIRX_DATAReg;
310
 
311
wire            TxStartFrm;
312
wire            TxEndFrm;
313
wire            TxUsedData;
314
wire     [7:0]  TxData;
315
wire            TxRetry;
316
wire            TxAbort;
317
wire            TxUnderRun;
318
wire            TxDone;
319 42 mohor
wire     [5:0]  CollValid;
320 15 mohor
 
321
 
322 149 mohor
reg             WillSendControlFrame_sync1;
323
reg             WillSendControlFrame_sync2;
324
reg             WillSendControlFrame_sync3;
325
reg             RstTxPauseRq;
326 15 mohor
 
327
 
328
// Connecting Miim module
329
eth_miim miim1
330
(
331 17 mohor
  .Clk(wb_clk_i),                         .Reset(r_MiiMRst),                  .Divider(r_ClkDiv),
332 15 mohor
  .NoPre(r_MiiNoPre),                     .CtrlData(r_CtrlData),              .Rgad(r_RGAD),
333
  .Fiad(r_FIAD),                          .WCtrlData(r_WCtrlData),            .RStat(r_RStat),
334 17 mohor
  .ScanStat(r_ScanStat),                  .Mdi(md_pad_i),                     .Mdo(md_pad_o),
335 95 mohor
  .MdoEn(md_padoe_o),                     .Mdc(mdc_pad_o),                    .Busy(Busy_stat),
336 15 mohor
  .Prsd(Prsd),                            .LinkFail(LinkFail),                .Nvalid(NValid_stat),
337
  .WCtrlDataStart(WCtrlDataStart),        .RStatStart(RStatStart),            .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
338
);
339
 
340
 
341
 
342
 
343
wire        RegCs;          // Connected to registers
344 17 mohor
wire [31:0] RegDataOut;     // Multiplexed to wb_dat_o
345 42 mohor
wire        r_RecSmall;     // Receive small frames
346 15 mohor
wire        r_Rst;          // Reset
347
wire        r_LoopBck;      // Loopback
348
wire        r_TxEn;         // Tx Enable
349
wire        r_RxEn;         // Rx Enable
350
 
351
wire        MRxDV_Lb;       // Muxed MII receive data valid
352
wire        MRxErr_Lb;      // Muxed MII Receive Error
353
wire  [3:0] MRxD_Lb;        // Muxed MII Receive Data
354
wire        Transmitting;   // Indication that TxEthMAC is transmitting
355
wire        r_HugEn;        // Huge packet enable
356
wire        r_DlyCrcEn;     // Delayed CRC enabled
357
wire [15:0] r_MaxFL;        // Maximum frame length
358
 
359
wire [15:0] r_MinFL;        // Minimum frame length
360 42 mohor
wire        ShortFrame;
361
wire        DribbleNibble;  // Extra nibble received
362
wire        ReceivedPacketTooBig; // Received packet is too big
363 15 mohor
wire [47:0] r_MAC;          // MAC address
364 42 mohor
wire        LoadRxStatus;   // Rx status was loaded
365 52 billditt
wire [31:0] r_HASH0;        // HASH table, lower 4 bytes
366
wire [31:0] r_HASH1;        // HASH table, upper 4 bytes
367 34 mohor
wire  [7:0] r_TxBDNum;      // Receive buffer descriptor number
368 15 mohor
wire  [6:0] r_IPGT;         // 
369
wire  [6:0] r_IPGR1;        // 
370
wire  [6:0] r_IPGR2;        // 
371
wire  [5:0] r_CollValid;    // 
372 149 mohor
wire [15:0] r_TxPauseTV;    // Transmit PAUSE value
373
wire        r_TxPauseRq;    // Transmit PAUSE request
374 15 mohor
 
375
wire  [3:0] r_MaxRet;       //
376
wire        r_NoBckof;      // 
377
wire        r_ExDfrEn;      // 
378 34 mohor
wire        TX_BD_NUM_Wr;   // Write enable that writes RX_BD_NUM to the registers.
379 15 mohor
wire        r_TxFlow;       // Tx flow control enable
380
wire        r_IFG;          // Minimum interframe gap for incoming packets
381
 
382 21 mohor
wire        TxB_IRQ;        // Interrupt Tx Buffer
383
wire        TxE_IRQ;        // Interrupt Tx Error
384
wire        RxB_IRQ;        // Interrupt Rx Buffer
385 76 mohor
wire        RxE_IRQ;        // Interrupt Rx Error
386 21 mohor
wire        Busy_IRQ;       // Interrupt Busy (lack of buffers)
387 15 mohor
 
388
wire        DWord;
389
wire        BDAck;
390 103 mohor
wire [31:0] BD_WB_DAT_O;    // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
391 21 mohor
wire        BDCs;           // Buffer descriptor CS
392 202 mohor
wire        CsMiss;         // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
393
                            // but data is not valid.
394 15 mohor
 
395 103 mohor
wire        temp_wb_ack_o;
396
wire [31:0] temp_wb_dat_o;
397
wire        temp_wb_err_o;
398 15 mohor
 
399 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
400
  reg         temp_wb_ack_o_reg;
401
  reg [31:0]  temp_wb_dat_o_reg;
402
  reg         temp_wb_err_o_reg;
403
`endif
404
 
405 17 mohor
assign DWord = &wb_sel_i;
406 103 mohor
assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10];   // 0x0   - 0x3FF
407 114 mohor
assign BDCs  = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] &  wb_adr_i[10];   // 0x400 - 0x7FF
408 202 mohor
assign CsMiss = wb_stb_i & wb_cyc_i & DWord & wb_adr_i[11];                   // 0x800 - 0xfFF
409 103 mohor
assign temp_wb_ack_o = RegCs | BDAck;
410
assign temp_wb_dat_o = (RegCs & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
411 202 mohor
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~DWord | BDCs & r_Rst | CsMiss);
412 15 mohor
 
413 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
414
  assign wb_ack_o = temp_wb_ack_o_reg;
415
  assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
416
  assign wb_err_o = temp_wb_err_o_reg;
417
`else
418
  assign wb_ack_o = temp_wb_ack_o;
419
  assign wb_dat_o[31:0] = temp_wb_dat_o;
420
  assign wb_err_o = temp_wb_err_o;
421
`endif
422 15 mohor
 
423
 
424
 
425 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
426
  always @ (posedge wb_clk_i or posedge wb_rst_i)
427
  begin
428
    if(wb_rst_i)
429
      begin
430
        temp_wb_ack_o_reg <=#Tp 1'b0;
431
        temp_wb_dat_o_reg <=#Tp 32'h0;
432
        temp_wb_err_o_reg <=#Tp 1'b0;
433
      end
434
    else
435
      begin
436 106 mohor
        temp_wb_ack_o_reg <=#Tp temp_wb_ack_o & ~temp_wb_ack_o_reg;
437 103 mohor
        temp_wb_dat_o_reg <=#Tp temp_wb_dat_o;
438 106 mohor
        temp_wb_err_o_reg <=#Tp temp_wb_err_o & ~temp_wb_err_o_reg;
439 103 mohor
      end
440
  end
441
`endif
442
 
443
 
444 15 mohor
// Connecting Ethernet registers
445
eth_registers ethreg1
446
(
447 47 mohor
  .DataIn(wb_dat_i),                      .Address(wb_adr_i[9:2]),                    .Rw(wb_we_i),
448 17 mohor
  .Cs(RegCs),                             .Clk(wb_clk_i),                             .Reset(wb_rst_i),
449 68 mohor
  .DataOut(RegDataOut),                   .r_RecSmall(r_RecSmall),
450 15 mohor
  .r_Pad(r_Pad),                          .r_HugEn(r_HugEn),                          .r_CrcEn(r_CrcEn),
451
  .r_DlyCrcEn(r_DlyCrcEn),                .r_Rst(r_Rst),                              .r_FullD(r_FullD),
452
  .r_ExDfrEn(r_ExDfrEn),                  .r_NoBckof(r_NoBckof),                      .r_LoopBck(r_LoopBck),
453 52 billditt
  .r_IFG(r_IFG),                          .r_Pro(r_Pro),                              .r_Iam(),
454
  .r_Bro(r_Bro),                          .r_NoPre(r_NoPre),                          .r_TxEn(r_TxEn),
455 76 mohor
  .r_RxEn(r_RxEn),                        .Busy_IRQ(Busy_IRQ),                        .RxE_IRQ(RxE_IRQ),
456 21 mohor
  .RxB_IRQ(RxB_IRQ),                      .TxE_IRQ(TxE_IRQ),                          .TxB_IRQ(TxB_IRQ),
457 149 mohor
  .r_IPGT(r_IPGT),
458 15 mohor
  .r_IPGR1(r_IPGR1),                      .r_IPGR2(r_IPGR2),                          .r_MinFL(r_MinFL),
459
  .r_MaxFL(r_MaxFL),                      .r_MaxRet(r_MaxRet),                        .r_CollValid(r_CollValid),
460
  .r_TxFlow(r_TxFlow),                    .r_RxFlow(r_RxFlow),                        .r_PassAll(r_PassAll),
461
  .r_MiiMRst(r_MiiMRst),                  .r_MiiNoPre(r_MiiNoPre),                    .r_ClkDiv(r_ClkDiv),
462
  .r_WCtrlData(r_WCtrlData),              .r_RStat(r_RStat),                          .r_ScanStat(r_ScanStat),
463
  .r_RGAD(r_RGAD),                        .r_FIAD(r_FIAD),                            .r_CtrlData(r_CtrlData),
464
  .NValid_stat(NValid_stat),              .Busy_stat(Busy_stat),
465
  .LinkFail(LinkFail),                    .r_MAC(r_MAC),                              .WCtrlDataStart(WCtrlDataStart),
466
  .RStatStart(RStatStart),                .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg),  .Prsd(Prsd),
467 47 mohor
  .r_TxBDNum(r_TxBDNum),                  .TX_BD_NUM_Wr(TX_BD_NUM_Wr),                .int_o(int_o),
468 149 mohor
  .r_HASH0(r_HASH0),                      .r_HASH1(r_HASH1),                          .r_TxPauseRq(r_TxPauseRq),
469
  .r_TxPauseTV(r_TxPauseTV),              .RstTxPauseRq(RstTxPauseRq),                .TxCtrlEndFrm(TxCtrlEndFrm),
470
  .StartTxDone(StartTxDone),              .TxClk(mtx_clk_pad_i),                      .RxClk(mrx_clk_pad_i),
471 164 mohor
  .ReceivedPauseFrm(ReceivedPauseFrm)
472 149 mohor
 
473 15 mohor
);
474
 
475
 
476
 
477
wire  [7:0] RxData;
478
wire        RxValid;
479
wire        RxStartFrm;
480
wire        RxEndFrm;
481 41 mohor
wire        RxAbort;
482 15 mohor
 
483
wire        WillTransmit;            // Will transmit (to RxEthMAC)
484
wire        ResetCollision;          // Reset Collision (for synchronizing collision)
485
wire  [7:0] TxDataOut;               // Transmit Packet Data (to TxEthMAC)
486
wire        WillSendControlFrame;
487
wire        ReceiveEnd;
488
wire        ReceivedPacketGood;
489
wire        ReceivedLengthOK;
490 42 mohor
wire        InvalidSymbol;
491
wire        LatchedCrcError;
492
wire        RxLateCollision;
493 59 mohor
wire  [3:0] RetryCntLatched;
494
wire  [3:0] RetryCnt;
495
wire        StartTxAbort;
496
wire        MaxCollisionOccured;
497
wire        RetryLimit;
498
wire        StatePreamble;
499
wire  [1:0] StateData;
500 15 mohor
 
501
// Connecting MACControl
502
eth_maccontrol maccontrol1
503
(
504 149 mohor
  .MTxClk(mtx_clk_pad_i),                       .TPauseRq(r_TxPauseRq),
505
  .TxPauseTV(r_TxPauseTV),                      .TxDataIn(TxData),
506 15 mohor
  .TxStartFrmIn(TxStartFrm),                    .TxEndFrmIn(TxEndFrm),
507
  .TxUsedDataIn(TxUsedDataIn),                  .TxDoneIn(TxDoneIn),
508 20 mohor
  .TxAbortIn(TxAbortIn),                        .MRxClk(mrx_clk_pad_i),
509 15 mohor
  .RxData(RxData),                              .RxValid(RxValid),
510
  .RxStartFrm(RxStartFrm),                      .RxEndFrm(RxEndFrm),
511
  .ReceiveEnd(ReceiveEnd),                      .ReceivedPacketGood(ReceivedPacketGood),
512
  .PassAll(r_PassAll),                          .TxFlow(r_TxFlow),
513
  .RxFlow(r_RxFlow),                            .DlyCrcEn(r_DlyCrcEn),
514
  .MAC(r_MAC),                                  .PadIn(r_Pad | PerPacketPad),
515
  .PadOut(PadOut),                              .CrcEnIn(r_CrcEn | PerPacketCrcEn),
516
  .CrcEnOut(CrcEnOut),                          .TxReset(r_Rst),
517
  .RxReset(r_Rst),                              .ReceivedLengthOK(ReceivedLengthOK),
518
  .TxDataOut(TxDataOut),                        .TxStartFrmOut(TxStartFrmOut),
519
  .TxEndFrmOut(TxEndFrmOut),                    .TxUsedDataOut(TxUsedData),
520
  .TxDoneOut(TxDone),                           .TxAbortOut(TxAbort),
521
  .WillSendControlFrame(WillSendControlFrame),  .TxCtrlEndFrm(TxCtrlEndFrm),
522
  .ReceivedPauseFrm(ReceivedPauseFrm)
523
);
524
 
525
 
526
 
527
wire TxCarrierSense;          // Synchronized CarrierSense (to Tx clock)
528
wire Collision;               // Synchronized Collision
529
 
530
reg CarrierSense_Tx1;
531
reg CarrierSense_Tx2;
532
reg Collision_Tx1;
533
reg Collision_Tx2;
534
 
535
reg RxEnSync;                 // Synchronized Receive Enable
536
reg CarrierSense_Rx1;
537
reg RxCarrierSense;           // Synchronized CarrierSense (to Rx clock)
538
reg WillTransmit_q;
539
reg WillTransmit_q2;
540
 
541
 
542
 
543
// Muxed MII receive data valid
544 17 mohor
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
545 15 mohor
 
546
// Muxed MII Receive Error
547 17 mohor
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
548 15 mohor
 
549
// Muxed MII Receive Data
550 17 mohor
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
551 15 mohor
 
552
 
553
 
554
// Connecting TxEthMAC
555
eth_txethmac txethmac1
556
(
557 21 mohor
  .MTxClk(mtx_clk_pad_i),             .Reset(r_Rst),                      .CarrierSense(TxCarrierSense),
558 15 mohor
  .Collision(Collision),              .TxData(TxDataOut),                 .TxStartFrm(TxStartFrmOut),
559
  .TxUnderRun(TxUnderRun),            .TxEndFrm(TxEndFrmOut),             .Pad(PadOut),
560
  .MinFL(r_MinFL),                    .CrcEn(CrcEnOut),                   .FullD(r_FullD),
561
  .HugEn(r_HugEn),                    .DlyCrcEn(r_DlyCrcEn),              .IPGT(r_IPGT),
562
  .IPGR1(r_IPGR1),                    .IPGR2(r_IPGR2),                    .CollValid(r_CollValid),
563
  .MaxRet(r_MaxRet),                  .NoBckof(r_NoBckof),                .ExDfrEn(r_ExDfrEn),
564 17 mohor
  .MaxFL(r_MaxFL),                    .MTxEn(mtxen_pad_o),                .MTxD(mtxd_pad_o),
565
  .MTxErr(mtxerr_pad_o),              .TxUsedData(TxUsedDataIn),          .TxDone(TxDoneIn),
566 15 mohor
  .TxRetry(TxRetry),                  .TxAbort(TxAbortIn),                .WillTransmit(WillTransmit),
567 59 mohor
  .ResetCollision(ResetCollision),    .RetryCnt(RetryCnt),                .StartTxDone(StartTxDone),
568
  .StartTxAbort(StartTxAbort),        .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
569
  .StartDefer(StartDefer),            .StatePreamble(StatePreamble),      .StateData(StateData)
570 15 mohor
);
571
 
572
 
573
 
574
 
575
wire  [15:0]  RxByteCnt;
576
wire          RxByteCntEq0;
577
wire          RxByteCntGreat2;
578
wire          RxByteCntMaxFrame;
579
wire          RxCrcError;
580
wire          RxStateIdle;
581
wire          RxStatePreamble;
582
wire          RxStateSFD;
583
wire   [1:0]  RxStateData;
584
 
585
 
586
 
587
 
588
// Connecting RxEthMAC
589
eth_rxethmac rxethmac1
590
(
591 21 mohor
  .MRxClk(mrx_clk_pad_i),               .MRxDV(MRxDV_Lb),                     .MRxD(MRxD_Lb),
592 15 mohor
  .Transmitting(Transmitting),          .HugEn(r_HugEn),                      .DlyCrcEn(r_DlyCrcEn),
593
  .MaxFL(r_MaxFL),                      .r_IFG(r_IFG),                        .Reset(r_Rst),
594
  .RxData(RxData),                      .RxValid(RxValid),                    .RxStartFrm(RxStartFrm),
595 65 mohor
  .RxEndFrm(RxEndFrm),                  .ByteCnt(RxByteCnt),
596 15 mohor
  .ByteCntEq0(RxByteCntEq0),            .ByteCntGreat2(RxByteCntGreat2),      .ByteCntMaxFrame(RxByteCntMaxFrame),
597
  .CrcError(RxCrcError),                .StateIdle(RxStateIdle),              .StatePreamble(RxStatePreamble),
598 52 billditt
  .StateSFD(RxStateSFD),                .StateData(RxStateData),
599 63 mohor
  .MAC(r_MAC),                          .r_Pro(r_Pro),                        .r_Bro(r_Bro),
600
  .r_HASH0(r_HASH0),                    .r_HASH1(r_HASH1),                    .RxAbort(RxAbort)
601 15 mohor
);
602
 
603
 
604
// MII Carrier Sense Synchronization
605 20 mohor
always @ (posedge mtx_clk_pad_i or posedge r_Rst)
606 15 mohor
begin
607
  if(r_Rst)
608
    begin
609
      CarrierSense_Tx1 <= #Tp 1'b0;
610
      CarrierSense_Tx2 <= #Tp 1'b0;
611
    end
612
  else
613
    begin
614 17 mohor
      CarrierSense_Tx1 <= #Tp mcrs_pad_i;
615 15 mohor
      CarrierSense_Tx2 <= #Tp CarrierSense_Tx1;
616
    end
617
end
618
 
619
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
620
 
621
 
622
// MII Collision Synchronization
623 20 mohor
always @ (posedge mtx_clk_pad_i or posedge r_Rst)
624 15 mohor
begin
625
  if(r_Rst)
626
    begin
627
      Collision_Tx1 <= #Tp 1'b0;
628
      Collision_Tx2 <= #Tp 1'b0;
629
    end
630
  else
631
    begin
632 17 mohor
      Collision_Tx1 <= #Tp mcoll_pad_i;
633 15 mohor
      if(ResetCollision)
634
        Collision_Tx2 <= #Tp 1'b0;
635
      else
636
      if(Collision_Tx1)
637
        Collision_Tx2 <= #Tp 1'b1;
638
    end
639
end
640
 
641
 
642
// Synchronized Collision
643
assign Collision = ~r_FullD & Collision_Tx2;
644
 
645
 
646
 
647
// Carrier sense is synchronized to receive clock.
648 20 mohor
always @ (posedge mrx_clk_pad_i or posedge r_Rst)
649 15 mohor
begin
650
  if(r_Rst)
651
    begin
652
      CarrierSense_Rx1 <= #Tp 1'h0;
653
      RxCarrierSense <= #Tp 1'h0;
654
    end
655
  else
656
    begin
657 17 mohor
      CarrierSense_Rx1 <= #Tp mcrs_pad_i;
658 15 mohor
      RxCarrierSense <= #Tp CarrierSense_Rx1;
659
    end
660
end
661
 
662
 
663
// Delayed WillTransmit
664 20 mohor
always @ (posedge mrx_clk_pad_i)
665 15 mohor
begin
666
  WillTransmit_q <= #Tp WillTransmit;
667
  WillTransmit_q2 <= #Tp WillTransmit_q;
668
end
669
 
670
 
671
assign Transmitting = ~r_FullD & WillTransmit_q2;
672
 
673
 
674
 
675
// Synchronized Receive Enable
676 20 mohor
always @ (posedge mrx_clk_pad_i or posedge r_Rst)
677 15 mohor
begin
678
  if(r_Rst)
679
    RxEnSync <= #Tp 1'b0;
680
  else
681
  if(~RxCarrierSense | RxCarrierSense & Transmitting)
682
    RxEnSync <= #Tp r_RxEn;
683
end
684
 
685
 
686
 
687 149 mohor
// Synchronizing WillSendControlFrame to WB_CLK;
688
always @ (posedge wb_clk_i or posedge wb_rst_i)
689
begin
690
  if(wb_rst_i)
691
    WillSendControlFrame_sync1 <= 1'b0;
692
  else
693
    WillSendControlFrame_sync1 <=#Tp WillSendControlFrame;
694
end
695 15 mohor
 
696 149 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
697
begin
698
  if(wb_rst_i)
699
    WillSendControlFrame_sync2 <= 1'b0;
700
  else
701
    WillSendControlFrame_sync2 <=#Tp WillSendControlFrame_sync1;
702
end
703
 
704
always @ (posedge wb_clk_i or posedge wb_rst_i)
705
begin
706
  if(wb_rst_i)
707
    WillSendControlFrame_sync3 <= 1'b0;
708
  else
709
    WillSendControlFrame_sync3 <=#Tp WillSendControlFrame_sync2;
710
end
711
 
712
always @ (posedge wb_clk_i or posedge wb_rst_i)
713
begin
714
  if(wb_rst_i)
715
    RstTxPauseRq <= 1'b0;
716
  else
717
    RstTxPauseRq <=#Tp WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
718
end
719
 
720
 
721 114 mohor
// Connecting Wishbone module
722 41 mohor
eth_wishbone wishbone
723 15 mohor
(
724 41 mohor
  .WB_CLK_I(wb_clk_i),                .WB_DAT_I(wb_dat_i),
725 103 mohor
  .WB_DAT_O(BD_WB_DAT_O),
726 15 mohor
 
727
  // WISHBONE slave
728 76 mohor
  .WB_ADR_I(wb_adr_i[9:2]),           .WB_WE_I(wb_we_i),
729 21 mohor
  .BDCs(BDCs),                        .WB_ACK_O(BDAck),
730 15 mohor
 
731 106 mohor
  .Reset(r_Rst),
732 41 mohor
 
733
  // WISHBONE master
734
  .m_wb_adr_o(m_wb_adr_o),            .m_wb_sel_o(m_wb_sel_o),                  .m_wb_we_o(m_wb_we_o),
735
  .m_wb_dat_i(m_wb_dat_i),            .m_wb_dat_o(m_wb_dat_o),                  .m_wb_cyc_o(m_wb_cyc_o),
736
  .m_wb_stb_o(m_wb_stb_o),            .m_wb_ack_i(m_wb_ack_i),                  .m_wb_err_i(m_wb_err_i),
737 214 mohor
 
738
`ifdef ETH_WISHBONE_B3
739
  .m_wb_cti_o(m_wb_cti_o),            .m_wb_bte_o(m_wb_bte_o),
740
`endif
741
 
742 41 mohor
 
743 15 mohor
    //TX
744 21 mohor
  .MTxClk(mtx_clk_pad_i),             .TxStartFrm(TxStartFrm),                  .TxEndFrm(TxEndFrm),
745 59 mohor
  .TxUsedData(TxUsedData),            .TxData(TxData),
746 15 mohor
  .TxRetry(TxRetry),                  .TxAbort(TxAbort),                        .TxUnderRun(TxUnderRun),
747 149 mohor
  .TxDone(TxDone),
748
  .PerPacketCrcEn(PerPacketCrcEn),    .PerPacketPad(PerPacketPad),
749 15 mohor
 
750
  // Register
751 34 mohor
  .r_TxEn(r_TxEn),                    .r_RxEn(r_RxEn),                          .r_TxBDNum(r_TxBDNum),
752 149 mohor
  .TX_BD_NUM_Wr(TX_BD_NUM_Wr),
753 15 mohor
 
754
  //RX
755 21 mohor
  .MRxClk(mrx_clk_pad_i),             .RxData(RxData),                          .RxValid(RxValid),
756 41 mohor
  .RxStartFrm(RxStartFrm),            .RxEndFrm(RxEndFrm),
757 76 mohor
  .Busy_IRQ(Busy_IRQ),                .RxE_IRQ(RxE_IRQ),                        .RxB_IRQ(RxB_IRQ),
758 149 mohor
  .TxE_IRQ(TxE_IRQ),                  .TxB_IRQ(TxB_IRQ),
759 21 mohor
 
760 149 mohor
  .RxAbort(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | ReceivedPauseFrm & ~r_PassAll),
761 41 mohor
 
762 42 mohor
  .InvalidSymbol(InvalidSymbol),      .LatchedCrcError(LatchedCrcError),        .RxLength(RxByteCnt),
763
  .RxLateCollision(RxLateCollision),  .ShortFrame(ShortFrame),                  .DribbleNibble(DribbleNibble),
764 59 mohor
  .ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus),     .RetryCntLatched(RetryCntLatched),
765
  .RetryLimit(RetryLimit),            .LateCollLatched(LateCollLatched),        .DeferLatched(DeferLatched),
766 164 mohor
  .CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood)
767 59 mohor
 
768 210 mohor
`ifdef ETH_BIST
769 218 mohor
  ,
770 227 tadejm
  .scanb_rst      (scanb_rst),
771
  .scanb_clk      (scanb_clk),
772
  .scanb_si       (scanb_si),
773
  .scanb_so       (scanb_so),
774
  .scanb_en       (scanb_en)
775 210 mohor
`endif
776 15 mohor
);
777
 
778
 
779
 
780
// Connecting MacStatus module
781
eth_macstatus macstatus1
782
(
783 42 mohor
  .MRxClk(mrx_clk_pad_i),             .Reset(r_Rst),
784
  .ReceiveEnd(ReceiveEnd),            .ReceivedPacketGood(ReceivedPacketGood),     .ReceivedLengthOK(ReceivedLengthOK),
785
  .RxCrcError(RxCrcError),            .MRxErr(MRxErr_Lb),                          .MRxDV(MRxDV_Lb),
786
  .RxStateSFD(RxStateSFD),            .RxStateData(RxStateData),                   .RxStatePreamble(RxStatePreamble),
787
  .RxStateIdle(RxStateIdle),          .Transmitting(Transmitting),                 .RxByteCnt(RxByteCnt),
788
  .RxByteCntEq0(RxByteCntEq0),        .RxByteCntGreat2(RxByteCntGreat2),           .RxByteCntMaxFrame(RxByteCntMaxFrame),
789
  .ReceivedPauseFrm(ReceivedPauseFrm),.InvalidSymbol(InvalidSymbol),
790
  .MRxD(MRxD_Lb),                     .LatchedCrcError(LatchedCrcError),           .Collision(mcoll_pad_i),
791
  .CollValid(r_CollValid),            .RxLateCollision(RxLateCollision),           .r_RecSmall(r_RecSmall),
792
  .r_MinFL(r_MinFL),                  .r_MaxFL(r_MaxFL),                           .ShortFrame(ShortFrame),
793
  .DribbleNibble(DribbleNibble),      .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
794 59 mohor
  .LoadRxStatus(LoadRxStatus),        .RetryCnt(RetryCnt),                         .StartTxDone(StartTxDone),
795
  .StartTxAbort(StartTxAbort),        .RetryCntLatched(RetryCntLatched),           .MTxClk(mtx_clk_pad_i),
796
  .MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit),              .LateCollision(LateCollision),
797
  .LateCollLatched(LateCollLatched),  .StartDefer(StartDefer),                     .DeferLatched(DeferLatched),
798
  .TxStartFrm(TxStartFrmOut),         .StatePreamble(StatePreamble),               .StateData(StateData),
799 125 mohor
  .CarrierSense(CarrierSense_Tx2),    .CarrierSenseLost(CarrierSenseLost),         .TxUsedData(TxUsedDataIn),
800 168 mohor
  .LatchedMRxErr(LatchedMRxErr),      .Loopback(r_LoopBck),                        .r_FullD(r_FullD)
801 15 mohor
);
802
 
803
 
804
endmodule

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