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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_top.v] - Blame information for rev 250

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1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_top.v                                                   ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 202 mohor
////  All additional information is available in the Readme.txt   ////
12 15 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 202 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 15 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 250 mohor
// Revision 1.39  2002/11/18 17:31:55  mohor
45
// wb_rst_i is used for MIIM reset.
46
//
47 248 mohor
// Revision 1.38  2002/11/14 18:37:20  mohor
48
// r_Rst signal does not reset any module any more and is removed from the design.
49
//
50 244 mohor
// Revision 1.37  2002/11/13 22:25:36  tadejm
51
// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.
52
//
53 240 tadejm
// Revision 1.36  2002/10/18 17:04:20  tadejm
54
// Changed BIST scan signals.
55
//
56 227 tadejm
// Revision 1.35  2002/10/11 13:36:58  mohor
57
// Typo error fixed. (When using Bist)
58
//
59 218 mohor
// Revision 1.34  2002/10/10 16:49:50  mohor
60
// Signals for WISHBONE B3 compliant interface added.
61
//
62 214 mohor
// Revision 1.33  2002/10/10 16:29:30  mohor
63
// BIST added.
64
//
65 210 mohor
// Revision 1.32  2002/09/20 17:12:58  mohor
66
// CsMiss added. When address between 0x800 and 0xfff is accessed within
67
// Ethernet Core, error acknowledge is generated.
68
//
69 202 mohor
// Revision 1.31  2002/09/12 14:50:17  mohor
70
// CarrierSenseLost bug fixed when operating in full duplex mode.
71
//
72 168 mohor
// Revision 1.30  2002/09/10 10:35:23  mohor
73
// Ethernet debug registers removed.
74
//
75 164 mohor
// Revision 1.29  2002/09/09 13:03:13  mohor
76
// Error acknowledge is generated when accessing BDs and RST bit in the
77
// MODER register (r_Rst) is set.
78
//
79 161 mohor
// Revision 1.28  2002/09/04 18:44:10  mohor
80
// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
81
// connected.
82
//
83 149 mohor
// Revision 1.27  2002/07/25 18:15:37  mohor
84
// RxAbort changed. Packets received with MRxErr (from PHY) are also
85
// aborted.
86
//
87 125 mohor
// Revision 1.26  2002/07/17 18:51:50  mohor
88
// EXTERNAL_DMA removed. External DMA not supported.
89
//
90 114 mohor
// Revision 1.25  2002/05/03 10:15:50  mohor
91
// Outputs registered. Reset changed for eth_wishbone module.
92
//
93 106 mohor
// Revision 1.24  2002/04/22 14:15:42  mohor
94
// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
95
// selected in eth_defines.v
96
//
97 103 mohor
// Revision 1.23  2002/03/25 13:33:53  mohor
98
// md_padoen_o changed to md_padoe_o. Signal was always active high, just
99
// name was incorrect.
100
//
101 95 mohor
// Revision 1.22  2002/02/26 16:59:54  mohor
102
// Small fixes for external/internal DMA missmatches.
103
//
104 80 mohor
// Revision 1.21  2002/02/26 16:21:00  mohor
105
// Interrupts changed in the top file
106
//
107 76 mohor
// Revision 1.20  2002/02/18 10:40:17  mohor
108
// Small fixes.
109
//
110 70 mohor
// Revision 1.19  2002/02/16 14:03:44  mohor
111
// Registered trimmed. Unused registers removed.
112
//
113 68 mohor
// Revision 1.18  2002/02/16 13:06:33  mohor
114
// EXTERNAL_DMA used instead of WISHBONE_DMA.
115
//
116 67 mohor
// Revision 1.17  2002/02/16 07:15:27  mohor
117
// Testbench fixed, code simplified, unused signals removed.
118
//
119 65 mohor
// Revision 1.16  2002/02/15 13:49:39  mohor
120
// RxAbort is connected differently.
121
//
122 63 mohor
// Revision 1.15  2002/02/15 11:38:26  mohor
123
// Changes that were lost when updating from 1.11 to 1.14 fixed.
124
//
125 59 mohor
// Revision 1.14  2002/02/14 20:19:11  billditt
126
// Modified for Address Checking,
127
// addition of eth_addrcheck.v
128
//
129
// Revision 1.13  2002/02/12 17:03:03  mohor
130
// HASH0 and HASH1 registers added. Registers address width was
131
// changed to 8 bits.
132
//
133
// Revision 1.12  2002/02/11 09:18:22  mohor
134
// Tx status is written back to the BD.
135
//
136 43 mohor
// Revision 1.11  2002/02/08 16:21:54  mohor
137
// Rx status is written back to the BD.
138
//
139 42 mohor
// Revision 1.10  2002/02/06 14:10:21  mohor
140
// non-DMA host interface added. Select the right configutation in eth_defines.
141
//
142 41 mohor
// Revision 1.9  2002/01/23 10:28:16  mohor
143
// Link in the header changed.
144
//
145 37 mohor
// Revision 1.8  2001/12/05 15:00:16  mohor
146
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
147
// instead of the number of RX descriptors).
148
//
149 34 mohor
// Revision 1.7  2001/12/05 10:45:59  mohor
150
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
151
//
152 33 mohor
// Revision 1.6  2001/10/19 11:24:29  mohor
153
// Number of addresses (wb_adr_i) minimized.
154
//
155 23 mohor
// Revision 1.5  2001/10/19 08:43:51  mohor
156
// eth_timescale.v changed to timescale.v This is done because of the
157
// simulation of the few cores in a one joined project.
158
//
159 22 mohor
// Revision 1.4  2001/10/18 12:07:11  mohor
160
// Status signals changed, Adress decoding changed, interrupt controller
161
// added.
162
//
163 21 mohor
// Revision 1.3  2001/09/24 15:02:56  mohor
164
// Defines changed (All precede with ETH_). Small changes because some
165
// tools generate warnings when two operands are together. Synchronization
166
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
167
// demands).
168
//
169 20 mohor
// Revision 1.2  2001/08/15 14:03:59  mohor
170
// Signal names changed on the top level for easier pad insertion (ASIC).
171
//
172 17 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
173
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
174
// Include files fixed to contain no path.
175
// File names and module names changed ta have a eth_ prologue in the name.
176
// File eth_timescale.v is used to define timescale
177
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
178
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
179
// and Mdo_OE. The bidirectional signal must be created on the top level. This
180
// is done due to the ASIC tools.
181
//
182 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
183
// Unconnected signals are now connected.
184
//
185
// Revision 1.1  2001/07/30 21:23:42  mohor
186
// Directory structure changed. Files checked and joind together.
187
//
188
//
189
//
190 20 mohor
// 
191 15 mohor
 
192
 
193
`include "eth_defines.v"
194 22 mohor
`include "timescale.v"
195 15 mohor
 
196
 
197
module eth_top
198
(
199
  // WISHBONE common
200 17 mohor
  wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
201 15 mohor
 
202
  // WISHBONE slave
203 17 mohor
  wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
204 15 mohor
 
205 41 mohor
  // WISHBONE master
206
  m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
207
  m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
208
  m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
209
 
210 214 mohor
`ifdef ETH_WISHBONE_B3
211
  m_wb_cti_o, m_wb_bte_o,
212
`endif
213
 
214 15 mohor
  //TX
215 20 mohor
  mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
216 15 mohor
 
217
  //RX
218 20 mohor
  mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
219 15 mohor
 
220
  // MIIM
221 95 mohor
  mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
222 17 mohor
 
223 21 mohor
  int_o
224 17 mohor
 
225 210 mohor
  // Bist
226
`ifdef ETH_BIST
227 227 tadejm
  ,
228
  // debug chain signals
229
  scanb_rst,      // bist scan reset
230
  scanb_clk,      // bist scan clock
231
  scanb_si,       // bist scan serial in
232
  scanb_so,       // bist scan serial out
233
  scanb_en        // bist scan shift enable
234 210 mohor
`endif
235 21 mohor
 
236 15 mohor
);
237
 
238
 
239
parameter Tp = 1;
240
 
241
 
242
// WISHBONE common
243 17 mohor
input           wb_clk_i;     // WISHBONE clock
244
input           wb_rst_i;     // WISHBONE reset
245
input   [31:0]  wb_dat_i;     // WISHBONE data input
246
output  [31:0]  wb_dat_o;     // WISHBONE data output
247
output          wb_err_o;     // WISHBONE error output
248 15 mohor
 
249
// WISHBONE slave
250 23 mohor
input   [11:2]  wb_adr_i;     // WISHBONE address input
251 17 mohor
input    [3:0]  wb_sel_i;     // WISHBONE byte select input
252
input           wb_we_i;      // WISHBONE write enable input
253
input           wb_cyc_i;     // WISHBONE cycle input
254
input           wb_stb_i;     // WISHBONE strobe input
255
output          wb_ack_o;     // WISHBONE acknowledge output
256 15 mohor
 
257 41 mohor
// WISHBONE master
258
output  [31:0]  m_wb_adr_o;
259
output   [3:0]  m_wb_sel_o;
260
output          m_wb_we_o;
261
input   [31:0]  m_wb_dat_i;
262
output  [31:0]  m_wb_dat_o;
263
output          m_wb_cyc_o;
264
output          m_wb_stb_o;
265
input           m_wb_ack_i;
266
input           m_wb_err_i;
267 15 mohor
 
268 214 mohor
`ifdef ETH_WISHBONE_B3
269
output   [2:0]  m_wb_cti_o;   // Cycle Type Identifier
270
output   [1:0]  m_wb_bte_o;   // Burst Type Extension
271
`endif
272 41 mohor
 
273 15 mohor
// Tx
274 20 mohor
input           mtx_clk_pad_i; // Transmit clock (from PHY)
275 21 mohor
output   [3:0]  mtxd_pad_o;    // Transmit nibble (to PHY)
276
output          mtxen_pad_o;   // Transmit enable (to PHY)
277
output          mtxerr_pad_o;  // Transmit error (to PHY)
278 15 mohor
 
279
// Rx
280 20 mohor
input           mrx_clk_pad_i; // Receive clock (from PHY)
281 21 mohor
input    [3:0]  mrxd_pad_i;    // Receive nibble (from PHY)
282
input           mrxdv_pad_i;   // Receive data valid (from PHY)
283
input           mrxerr_pad_i;  // Receive data error (from PHY)
284 15 mohor
 
285
// Common Tx and Rx
286 21 mohor
input           mcoll_pad_i;   // Collision (from PHY)
287
input           mcrs_pad_i;    // Carrier sense (from PHY)
288 15 mohor
 
289
// MII Management interface
290 21 mohor
input           md_pad_i;      // MII data input (from I/O cell)
291
output          mdc_pad_o;     // MII Management data clock (to PHY)
292
output          md_pad_o;      // MII data output (to I/O cell)
293 95 mohor
output          md_padoe_o;    // MII data output enable (to I/O cell)
294 15 mohor
 
295 21 mohor
output          int_o;         // Interrupt output
296 15 mohor
 
297 210 mohor
// Bist
298
`ifdef ETH_BIST
299 227 tadejm
input   scanb_rst;      // bist scan reset
300
input   scanb_clk;      // bist scan clock
301
input   scanb_si;       // bist scan serial in
302
output  scanb_so;       // bist scan serial out
303
input   scanb_en;       // bist scan shift enable
304 210 mohor
`endif
305
 
306 15 mohor
wire     [7:0]  r_ClkDiv;
307
wire            r_MiiNoPre;
308
wire    [15:0]  r_CtrlData;
309
wire     [4:0]  r_FIAD;
310
wire     [4:0]  r_RGAD;
311
wire            r_WCtrlData;
312
wire            r_RStat;
313
wire            r_ScanStat;
314
wire            NValid_stat;
315
wire            Busy_stat;
316
wire            LinkFail;
317
wire            r_MiiMRst;
318
wire    [15:0]  Prsd;             // Read Status Data (data read from the PHY)
319
wire            WCtrlDataStart;
320
wire            RStatStart;
321
wire            UpdateMIIRX_DATAReg;
322
 
323
wire            TxStartFrm;
324
wire            TxEndFrm;
325
wire            TxUsedData;
326
wire     [7:0]  TxData;
327
wire            TxRetry;
328
wire            TxAbort;
329
wire            TxUnderRun;
330
wire            TxDone;
331 42 mohor
wire     [5:0]  CollValid;
332 15 mohor
 
333
 
334 149 mohor
reg             WillSendControlFrame_sync1;
335
reg             WillSendControlFrame_sync2;
336
reg             WillSendControlFrame_sync3;
337
reg             RstTxPauseRq;
338 15 mohor
 
339
 
340
// Connecting Miim module
341
eth_miim miim1
342
(
343 248 mohor
  .Clk(wb_clk_i),                         .Reset(wb_rst_i),                   .Divider(r_ClkDiv),
344 15 mohor
  .NoPre(r_MiiNoPre),                     .CtrlData(r_CtrlData),              .Rgad(r_RGAD),
345
  .Fiad(r_FIAD),                          .WCtrlData(r_WCtrlData),            .RStat(r_RStat),
346 17 mohor
  .ScanStat(r_ScanStat),                  .Mdi(md_pad_i),                     .Mdo(md_pad_o),
347 95 mohor
  .MdoEn(md_padoe_o),                     .Mdc(mdc_pad_o),                    .Busy(Busy_stat),
348 15 mohor
  .Prsd(Prsd),                            .LinkFail(LinkFail),                .Nvalid(NValid_stat),
349
  .WCtrlDataStart(WCtrlDataStart),        .RStatStart(RStatStart),            .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
350
);
351
 
352
 
353
 
354
 
355
wire        RegCs;          // Connected to registers
356 17 mohor
wire [31:0] RegDataOut;     // Multiplexed to wb_dat_o
357 42 mohor
wire        r_RecSmall;     // Receive small frames
358 15 mohor
wire        r_LoopBck;      // Loopback
359
wire        r_TxEn;         // Tx Enable
360
wire        r_RxEn;         // Rx Enable
361
 
362
wire        MRxDV_Lb;       // Muxed MII receive data valid
363
wire        MRxErr_Lb;      // Muxed MII Receive Error
364
wire  [3:0] MRxD_Lb;        // Muxed MII Receive Data
365
wire        Transmitting;   // Indication that TxEthMAC is transmitting
366
wire        r_HugEn;        // Huge packet enable
367
wire        r_DlyCrcEn;     // Delayed CRC enabled
368
wire [15:0] r_MaxFL;        // Maximum frame length
369
 
370
wire [15:0] r_MinFL;        // Minimum frame length
371 42 mohor
wire        ShortFrame;
372
wire        DribbleNibble;  // Extra nibble received
373
wire        ReceivedPacketTooBig; // Received packet is too big
374 15 mohor
wire [47:0] r_MAC;          // MAC address
375 42 mohor
wire        LoadRxStatus;   // Rx status was loaded
376 52 billditt
wire [31:0] r_HASH0;        // HASH table, lower 4 bytes
377
wire [31:0] r_HASH1;        // HASH table, upper 4 bytes
378 34 mohor
wire  [7:0] r_TxBDNum;      // Receive buffer descriptor number
379 15 mohor
wire  [6:0] r_IPGT;         // 
380
wire  [6:0] r_IPGR1;        // 
381
wire  [6:0] r_IPGR2;        // 
382
wire  [5:0] r_CollValid;    // 
383 149 mohor
wire [15:0] r_TxPauseTV;    // Transmit PAUSE value
384
wire        r_TxPauseRq;    // Transmit PAUSE request
385 15 mohor
 
386
wire  [3:0] r_MaxRet;       //
387
wire        r_NoBckof;      // 
388
wire        r_ExDfrEn;      // 
389 34 mohor
wire        TX_BD_NUM_Wr;   // Write enable that writes RX_BD_NUM to the registers.
390 15 mohor
wire        r_TxFlow;       // Tx flow control enable
391
wire        r_IFG;          // Minimum interframe gap for incoming packets
392
 
393 21 mohor
wire        TxB_IRQ;        // Interrupt Tx Buffer
394
wire        TxE_IRQ;        // Interrupt Tx Error
395
wire        RxB_IRQ;        // Interrupt Rx Buffer
396 76 mohor
wire        RxE_IRQ;        // Interrupt Rx Error
397 21 mohor
wire        Busy_IRQ;       // Interrupt Busy (lack of buffers)
398 15 mohor
 
399
wire        DWord;
400
wire        BDAck;
401 103 mohor
wire [31:0] BD_WB_DAT_O;    // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
402 21 mohor
wire        BDCs;           // Buffer descriptor CS
403 202 mohor
wire        CsMiss;         // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
404
                            // but data is not valid.
405 15 mohor
 
406 103 mohor
wire        temp_wb_ack_o;
407
wire [31:0] temp_wb_dat_o;
408
wire        temp_wb_err_o;
409 15 mohor
 
410 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
411
  reg         temp_wb_ack_o_reg;
412
  reg [31:0]  temp_wb_dat_o_reg;
413
  reg         temp_wb_err_o_reg;
414
`endif
415
 
416 17 mohor
assign DWord = &wb_sel_i;
417 103 mohor
assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10];   // 0x0   - 0x3FF
418 114 mohor
assign BDCs  = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] &  wb_adr_i[10];   // 0x400 - 0x7FF
419 202 mohor
assign CsMiss = wb_stb_i & wb_cyc_i & DWord & wb_adr_i[11];                   // 0x800 - 0xfFF
420 103 mohor
assign temp_wb_ack_o = RegCs | BDAck;
421
assign temp_wb_dat_o = (RegCs & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
422 240 tadejm
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~DWord | CsMiss);
423 15 mohor
 
424 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
425
  assign wb_ack_o = temp_wb_ack_o_reg;
426
  assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
427
  assign wb_err_o = temp_wb_err_o_reg;
428
`else
429
  assign wb_ack_o = temp_wb_ack_o;
430
  assign wb_dat_o[31:0] = temp_wb_dat_o;
431
  assign wb_err_o = temp_wb_err_o;
432
`endif
433 15 mohor
 
434
 
435
 
436 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
437
  always @ (posedge wb_clk_i or posedge wb_rst_i)
438
  begin
439
    if(wb_rst_i)
440
      begin
441
        temp_wb_ack_o_reg <=#Tp 1'b0;
442
        temp_wb_dat_o_reg <=#Tp 32'h0;
443
        temp_wb_err_o_reg <=#Tp 1'b0;
444
      end
445
    else
446
      begin
447 106 mohor
        temp_wb_ack_o_reg <=#Tp temp_wb_ack_o & ~temp_wb_ack_o_reg;
448 103 mohor
        temp_wb_dat_o_reg <=#Tp temp_wb_dat_o;
449 106 mohor
        temp_wb_err_o_reg <=#Tp temp_wb_err_o & ~temp_wb_err_o_reg;
450 103 mohor
      end
451
  end
452
`endif
453
 
454
 
455 15 mohor
// Connecting Ethernet registers
456
eth_registers ethreg1
457
(
458 47 mohor
  .DataIn(wb_dat_i),                      .Address(wb_adr_i[9:2]),                    .Rw(wb_we_i),
459 17 mohor
  .Cs(RegCs),                             .Clk(wb_clk_i),                             .Reset(wb_rst_i),
460 68 mohor
  .DataOut(RegDataOut),                   .r_RecSmall(r_RecSmall),
461 15 mohor
  .r_Pad(r_Pad),                          .r_HugEn(r_HugEn),                          .r_CrcEn(r_CrcEn),
462 244 mohor
  .r_DlyCrcEn(r_DlyCrcEn),                .r_FullD(r_FullD),
463 15 mohor
  .r_ExDfrEn(r_ExDfrEn),                  .r_NoBckof(r_NoBckof),                      .r_LoopBck(r_LoopBck),
464 52 billditt
  .r_IFG(r_IFG),                          .r_Pro(r_Pro),                              .r_Iam(),
465
  .r_Bro(r_Bro),                          .r_NoPre(r_NoPre),                          .r_TxEn(r_TxEn),
466 76 mohor
  .r_RxEn(r_RxEn),                        .Busy_IRQ(Busy_IRQ),                        .RxE_IRQ(RxE_IRQ),
467 21 mohor
  .RxB_IRQ(RxB_IRQ),                      .TxE_IRQ(TxE_IRQ),                          .TxB_IRQ(TxB_IRQ),
468 149 mohor
  .r_IPGT(r_IPGT),
469 15 mohor
  .r_IPGR1(r_IPGR1),                      .r_IPGR2(r_IPGR2),                          .r_MinFL(r_MinFL),
470
  .r_MaxFL(r_MaxFL),                      .r_MaxRet(r_MaxRet),                        .r_CollValid(r_CollValid),
471
  .r_TxFlow(r_TxFlow),                    .r_RxFlow(r_RxFlow),                        .r_PassAll(r_PassAll),
472
  .r_MiiMRst(r_MiiMRst),                  .r_MiiNoPre(r_MiiNoPre),                    .r_ClkDiv(r_ClkDiv),
473
  .r_WCtrlData(r_WCtrlData),              .r_RStat(r_RStat),                          .r_ScanStat(r_ScanStat),
474
  .r_RGAD(r_RGAD),                        .r_FIAD(r_FIAD),                            .r_CtrlData(r_CtrlData),
475
  .NValid_stat(NValid_stat),              .Busy_stat(Busy_stat),
476
  .LinkFail(LinkFail),                    .r_MAC(r_MAC),                              .WCtrlDataStart(WCtrlDataStart),
477
  .RStatStart(RStatStart),                .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg),  .Prsd(Prsd),
478 47 mohor
  .r_TxBDNum(r_TxBDNum),                  .TX_BD_NUM_Wr(TX_BD_NUM_Wr),                .int_o(int_o),
479 149 mohor
  .r_HASH0(r_HASH0),                      .r_HASH1(r_HASH1),                          .r_TxPauseRq(r_TxPauseRq),
480
  .r_TxPauseTV(r_TxPauseTV),              .RstTxPauseRq(RstTxPauseRq),                .TxCtrlEndFrm(TxCtrlEndFrm),
481
  .StartTxDone(StartTxDone),              .TxClk(mtx_clk_pad_i),                      .RxClk(mrx_clk_pad_i),
482 164 mohor
  .ReceivedPauseFrm(ReceivedPauseFrm)
483 149 mohor
 
484 15 mohor
);
485
 
486
 
487
 
488
wire  [7:0] RxData;
489
wire        RxValid;
490
wire        RxStartFrm;
491
wire        RxEndFrm;
492 41 mohor
wire        RxAbort;
493 15 mohor
 
494
wire        WillTransmit;            // Will transmit (to RxEthMAC)
495
wire        ResetCollision;          // Reset Collision (for synchronizing collision)
496
wire  [7:0] TxDataOut;               // Transmit Packet Data (to TxEthMAC)
497
wire        WillSendControlFrame;
498
wire        ReceiveEnd;
499
wire        ReceivedPacketGood;
500
wire        ReceivedLengthOK;
501 42 mohor
wire        InvalidSymbol;
502
wire        LatchedCrcError;
503
wire        RxLateCollision;
504 59 mohor
wire  [3:0] RetryCntLatched;
505
wire  [3:0] RetryCnt;
506
wire        StartTxAbort;
507
wire        MaxCollisionOccured;
508
wire        RetryLimit;
509
wire        StatePreamble;
510
wire  [1:0] StateData;
511 15 mohor
 
512
// Connecting MACControl
513
eth_maccontrol maccontrol1
514
(
515 149 mohor
  .MTxClk(mtx_clk_pad_i),                       .TPauseRq(r_TxPauseRq),
516
  .TxPauseTV(r_TxPauseTV),                      .TxDataIn(TxData),
517 15 mohor
  .TxStartFrmIn(TxStartFrm),                    .TxEndFrmIn(TxEndFrm),
518
  .TxUsedDataIn(TxUsedDataIn),                  .TxDoneIn(TxDoneIn),
519 20 mohor
  .TxAbortIn(TxAbortIn),                        .MRxClk(mrx_clk_pad_i),
520 15 mohor
  .RxData(RxData),                              .RxValid(RxValid),
521
  .RxStartFrm(RxStartFrm),                      .RxEndFrm(RxEndFrm),
522
  .ReceiveEnd(ReceiveEnd),                      .ReceivedPacketGood(ReceivedPacketGood),
523
  .PassAll(r_PassAll),                          .TxFlow(r_TxFlow),
524
  .RxFlow(r_RxFlow),                            .DlyCrcEn(r_DlyCrcEn),
525
  .MAC(r_MAC),                                  .PadIn(r_Pad | PerPacketPad),
526
  .PadOut(PadOut),                              .CrcEnIn(r_CrcEn | PerPacketCrcEn),
527 240 tadejm
  .CrcEnOut(CrcEnOut),                          .TxReset(wb_rst_i),
528
  .RxReset(wb_rst_i),                           .ReceivedLengthOK(ReceivedLengthOK),
529 15 mohor
  .TxDataOut(TxDataOut),                        .TxStartFrmOut(TxStartFrmOut),
530
  .TxEndFrmOut(TxEndFrmOut),                    .TxUsedDataOut(TxUsedData),
531
  .TxDoneOut(TxDone),                           .TxAbortOut(TxAbort),
532
  .WillSendControlFrame(WillSendControlFrame),  .TxCtrlEndFrm(TxCtrlEndFrm),
533
  .ReceivedPauseFrm(ReceivedPauseFrm)
534
);
535
 
536
 
537
 
538
wire TxCarrierSense;          // Synchronized CarrierSense (to Tx clock)
539
wire Collision;               // Synchronized Collision
540
 
541
reg CarrierSense_Tx1;
542
reg CarrierSense_Tx2;
543
reg Collision_Tx1;
544
reg Collision_Tx2;
545
 
546
reg RxEnSync;                 // Synchronized Receive Enable
547
reg CarrierSense_Rx1;
548
reg RxCarrierSense;           // Synchronized CarrierSense (to Rx clock)
549
reg WillTransmit_q;
550
reg WillTransmit_q2;
551
 
552
 
553
 
554
// Muxed MII receive data valid
555 17 mohor
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
556 15 mohor
 
557
// Muxed MII Receive Error
558 17 mohor
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
559 15 mohor
 
560
// Muxed MII Receive Data
561 17 mohor
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
562 15 mohor
 
563
 
564
 
565
// Connecting TxEthMAC
566
eth_txethmac txethmac1
567
(
568 240 tadejm
  .MTxClk(mtx_clk_pad_i),             .Reset(wb_rst_i),                   .CarrierSense(TxCarrierSense),
569 15 mohor
  .Collision(Collision),              .TxData(TxDataOut),                 .TxStartFrm(TxStartFrmOut),
570
  .TxUnderRun(TxUnderRun),            .TxEndFrm(TxEndFrmOut),             .Pad(PadOut),
571
  .MinFL(r_MinFL),                    .CrcEn(CrcEnOut),                   .FullD(r_FullD),
572
  .HugEn(r_HugEn),                    .DlyCrcEn(r_DlyCrcEn),              .IPGT(r_IPGT),
573
  .IPGR1(r_IPGR1),                    .IPGR2(r_IPGR2),                    .CollValid(r_CollValid),
574
  .MaxRet(r_MaxRet),                  .NoBckof(r_NoBckof),                .ExDfrEn(r_ExDfrEn),
575 17 mohor
  .MaxFL(r_MaxFL),                    .MTxEn(mtxen_pad_o),                .MTxD(mtxd_pad_o),
576
  .MTxErr(mtxerr_pad_o),              .TxUsedData(TxUsedDataIn),          .TxDone(TxDoneIn),
577 15 mohor
  .TxRetry(TxRetry),                  .TxAbort(TxAbortIn),                .WillTransmit(WillTransmit),
578 59 mohor
  .ResetCollision(ResetCollision),    .RetryCnt(RetryCnt),                .StartTxDone(StartTxDone),
579
  .StartTxAbort(StartTxAbort),        .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
580
  .StartDefer(StartDefer),            .StatePreamble(StatePreamble),      .StateData(StateData)
581 15 mohor
);
582
 
583
 
584
 
585
 
586
wire  [15:0]  RxByteCnt;
587
wire          RxByteCntEq0;
588
wire          RxByteCntGreat2;
589
wire          RxByteCntMaxFrame;
590
wire          RxCrcError;
591
wire          RxStateIdle;
592
wire          RxStatePreamble;
593
wire          RxStateSFD;
594
wire   [1:0]  RxStateData;
595 250 mohor
wire          AddressMiss;
596 15 mohor
 
597
 
598
 
599
// Connecting RxEthMAC
600
eth_rxethmac rxethmac1
601
(
602 21 mohor
  .MRxClk(mrx_clk_pad_i),               .MRxDV(MRxDV_Lb),                     .MRxD(MRxD_Lb),
603 15 mohor
  .Transmitting(Transmitting),          .HugEn(r_HugEn),                      .DlyCrcEn(r_DlyCrcEn),
604 240 tadejm
  .MaxFL(r_MaxFL),                      .r_IFG(r_IFG),                        .Reset(wb_rst_i),
605 15 mohor
  .RxData(RxData),                      .RxValid(RxValid),                    .RxStartFrm(RxStartFrm),
606 65 mohor
  .RxEndFrm(RxEndFrm),                  .ByteCnt(RxByteCnt),
607 15 mohor
  .ByteCntEq0(RxByteCntEq0),            .ByteCntGreat2(RxByteCntGreat2),      .ByteCntMaxFrame(RxByteCntMaxFrame),
608
  .CrcError(RxCrcError),                .StateIdle(RxStateIdle),              .StatePreamble(RxStatePreamble),
609 52 billditt
  .StateSFD(RxStateSFD),                .StateData(RxStateData),
610 63 mohor
  .MAC(r_MAC),                          .r_Pro(r_Pro),                        .r_Bro(r_Bro),
611 250 mohor
  .r_HASH0(r_HASH0),                    .r_HASH1(r_HASH1),                    .RxAbort(RxAbort),
612
  .AddressMiss(AddressMiss)
613 15 mohor
);
614
 
615
 
616
// MII Carrier Sense Synchronization
617 240 tadejm
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
618 15 mohor
begin
619 240 tadejm
  if(wb_rst_i)
620 15 mohor
    begin
621
      CarrierSense_Tx1 <= #Tp 1'b0;
622
      CarrierSense_Tx2 <= #Tp 1'b0;
623
    end
624
  else
625
    begin
626 17 mohor
      CarrierSense_Tx1 <= #Tp mcrs_pad_i;
627 15 mohor
      CarrierSense_Tx2 <= #Tp CarrierSense_Tx1;
628
    end
629
end
630
 
631
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
632
 
633
 
634
// MII Collision Synchronization
635 240 tadejm
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
636 15 mohor
begin
637 240 tadejm
  if(wb_rst_i)
638 15 mohor
    begin
639
      Collision_Tx1 <= #Tp 1'b0;
640
      Collision_Tx2 <= #Tp 1'b0;
641
    end
642
  else
643
    begin
644 17 mohor
      Collision_Tx1 <= #Tp mcoll_pad_i;
645 15 mohor
      if(ResetCollision)
646
        Collision_Tx2 <= #Tp 1'b0;
647
      else
648
      if(Collision_Tx1)
649
        Collision_Tx2 <= #Tp 1'b1;
650
    end
651
end
652
 
653
 
654
// Synchronized Collision
655
assign Collision = ~r_FullD & Collision_Tx2;
656
 
657
 
658
 
659
// Carrier sense is synchronized to receive clock.
660 240 tadejm
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
661 15 mohor
begin
662 240 tadejm
  if(wb_rst_i)
663 15 mohor
    begin
664
      CarrierSense_Rx1 <= #Tp 1'h0;
665
      RxCarrierSense <= #Tp 1'h0;
666
    end
667
  else
668
    begin
669 17 mohor
      CarrierSense_Rx1 <= #Tp mcrs_pad_i;
670 15 mohor
      RxCarrierSense <= #Tp CarrierSense_Rx1;
671
    end
672
end
673
 
674
 
675
// Delayed WillTransmit
676 20 mohor
always @ (posedge mrx_clk_pad_i)
677 15 mohor
begin
678
  WillTransmit_q <= #Tp WillTransmit;
679
  WillTransmit_q2 <= #Tp WillTransmit_q;
680
end
681
 
682
 
683
assign Transmitting = ~r_FullD & WillTransmit_q2;
684
 
685
 
686
 
687
// Synchronized Receive Enable
688 240 tadejm
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
689 15 mohor
begin
690 240 tadejm
  if(wb_rst_i)
691 15 mohor
    RxEnSync <= #Tp 1'b0;
692
  else
693
  if(~RxCarrierSense | RxCarrierSense & Transmitting)
694
    RxEnSync <= #Tp r_RxEn;
695
end
696
 
697
 
698
 
699 149 mohor
// Synchronizing WillSendControlFrame to WB_CLK;
700
always @ (posedge wb_clk_i or posedge wb_rst_i)
701
begin
702
  if(wb_rst_i)
703
    WillSendControlFrame_sync1 <= 1'b0;
704
  else
705
    WillSendControlFrame_sync1 <=#Tp WillSendControlFrame;
706
end
707 15 mohor
 
708 149 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
709
begin
710
  if(wb_rst_i)
711
    WillSendControlFrame_sync2 <= 1'b0;
712
  else
713
    WillSendControlFrame_sync2 <=#Tp WillSendControlFrame_sync1;
714
end
715
 
716
always @ (posedge wb_clk_i or posedge wb_rst_i)
717
begin
718
  if(wb_rst_i)
719
    WillSendControlFrame_sync3 <= 1'b0;
720
  else
721
    WillSendControlFrame_sync3 <=#Tp WillSendControlFrame_sync2;
722
end
723
 
724
always @ (posedge wb_clk_i or posedge wb_rst_i)
725
begin
726
  if(wb_rst_i)
727
    RstTxPauseRq <= 1'b0;
728
  else
729
    RstTxPauseRq <=#Tp WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
730
end
731
 
732
 
733 114 mohor
// Connecting Wishbone module
734 41 mohor
eth_wishbone wishbone
735 15 mohor
(
736 41 mohor
  .WB_CLK_I(wb_clk_i),                .WB_DAT_I(wb_dat_i),
737 103 mohor
  .WB_DAT_O(BD_WB_DAT_O),
738 15 mohor
 
739
  // WISHBONE slave
740 76 mohor
  .WB_ADR_I(wb_adr_i[9:2]),           .WB_WE_I(wb_we_i),
741 21 mohor
  .BDCs(BDCs),                        .WB_ACK_O(BDAck),
742 15 mohor
 
743 240 tadejm
  .Reset(wb_rst_i),
744 41 mohor
 
745
  // WISHBONE master
746
  .m_wb_adr_o(m_wb_adr_o),            .m_wb_sel_o(m_wb_sel_o),                  .m_wb_we_o(m_wb_we_o),
747
  .m_wb_dat_i(m_wb_dat_i),            .m_wb_dat_o(m_wb_dat_o),                  .m_wb_cyc_o(m_wb_cyc_o),
748
  .m_wb_stb_o(m_wb_stb_o),            .m_wb_ack_i(m_wb_ack_i),                  .m_wb_err_i(m_wb_err_i),
749 214 mohor
 
750
`ifdef ETH_WISHBONE_B3
751
  .m_wb_cti_o(m_wb_cti_o),            .m_wb_bte_o(m_wb_bte_o),
752
`endif
753
 
754 41 mohor
 
755 15 mohor
    //TX
756 21 mohor
  .MTxClk(mtx_clk_pad_i),             .TxStartFrm(TxStartFrm),                  .TxEndFrm(TxEndFrm),
757 59 mohor
  .TxUsedData(TxUsedData),            .TxData(TxData),
758 15 mohor
  .TxRetry(TxRetry),                  .TxAbort(TxAbort),                        .TxUnderRun(TxUnderRun),
759 149 mohor
  .TxDone(TxDone),
760
  .PerPacketCrcEn(PerPacketCrcEn),    .PerPacketPad(PerPacketPad),
761 15 mohor
 
762
  // Register
763 34 mohor
  .r_TxEn(r_TxEn),                    .r_RxEn(r_RxEn),                          .r_TxBDNum(r_TxBDNum),
764 149 mohor
  .TX_BD_NUM_Wr(TX_BD_NUM_Wr),
765 15 mohor
 
766
  //RX
767 21 mohor
  .MRxClk(mrx_clk_pad_i),             .RxData(RxData),                          .RxValid(RxValid),
768 41 mohor
  .RxStartFrm(RxStartFrm),            .RxEndFrm(RxEndFrm),
769 76 mohor
  .Busy_IRQ(Busy_IRQ),                .RxE_IRQ(RxE_IRQ),                        .RxB_IRQ(RxB_IRQ),
770 149 mohor
  .TxE_IRQ(TxE_IRQ),                  .TxB_IRQ(TxB_IRQ),
771 21 mohor
 
772 149 mohor
  .RxAbort(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | ReceivedPauseFrm & ~r_PassAll),
773 41 mohor
 
774 42 mohor
  .InvalidSymbol(InvalidSymbol),      .LatchedCrcError(LatchedCrcError),        .RxLength(RxByteCnt),
775
  .RxLateCollision(RxLateCollision),  .ShortFrame(ShortFrame),                  .DribbleNibble(DribbleNibble),
776 59 mohor
  .ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus),     .RetryCntLatched(RetryCntLatched),
777
  .RetryLimit(RetryLimit),            .LateCollLatched(LateCollLatched),        .DeferLatched(DeferLatched),
778 250 mohor
  .CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood),  .AddressMiss(AddressMiss)
779 59 mohor
 
780 210 mohor
`ifdef ETH_BIST
781 218 mohor
  ,
782 227 tadejm
  .scanb_rst      (scanb_rst),
783
  .scanb_clk      (scanb_clk),
784
  .scanb_si       (scanb_si),
785
  .scanb_so       (scanb_so),
786
  .scanb_en       (scanb_en)
787 210 mohor
`endif
788 15 mohor
);
789
 
790
 
791
 
792
// Connecting MacStatus module
793
eth_macstatus macstatus1
794
(
795 240 tadejm
  .MRxClk(mrx_clk_pad_i),             .Reset(wb_rst_i),
796 42 mohor
  .ReceiveEnd(ReceiveEnd),            .ReceivedPacketGood(ReceivedPacketGood),     .ReceivedLengthOK(ReceivedLengthOK),
797
  .RxCrcError(RxCrcError),            .MRxErr(MRxErr_Lb),                          .MRxDV(MRxDV_Lb),
798
  .RxStateSFD(RxStateSFD),            .RxStateData(RxStateData),                   .RxStatePreamble(RxStatePreamble),
799
  .RxStateIdle(RxStateIdle),          .Transmitting(Transmitting),                 .RxByteCnt(RxByteCnt),
800
  .RxByteCntEq0(RxByteCntEq0),        .RxByteCntGreat2(RxByteCntGreat2),           .RxByteCntMaxFrame(RxByteCntMaxFrame),
801
  .ReceivedPauseFrm(ReceivedPauseFrm),.InvalidSymbol(InvalidSymbol),
802
  .MRxD(MRxD_Lb),                     .LatchedCrcError(LatchedCrcError),           .Collision(mcoll_pad_i),
803
  .CollValid(r_CollValid),            .RxLateCollision(RxLateCollision),           .r_RecSmall(r_RecSmall),
804
  .r_MinFL(r_MinFL),                  .r_MaxFL(r_MaxFL),                           .ShortFrame(ShortFrame),
805
  .DribbleNibble(DribbleNibble),      .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
806 59 mohor
  .LoadRxStatus(LoadRxStatus),        .RetryCnt(RetryCnt),                         .StartTxDone(StartTxDone),
807
  .StartTxAbort(StartTxAbort),        .RetryCntLatched(RetryCntLatched),           .MTxClk(mtx_clk_pad_i),
808
  .MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit),              .LateCollision(LateCollision),
809
  .LateCollLatched(LateCollLatched),  .StartDefer(StartDefer),                     .DeferLatched(DeferLatched),
810
  .TxStartFrm(TxStartFrmOut),         .StatePreamble(StatePreamble),               .StateData(StateData),
811 125 mohor
  .CarrierSense(CarrierSense_Tx2),    .CarrierSenseLost(CarrierSenseLost),         .TxUsedData(TxUsedDataIn),
812 168 mohor
  .LatchedMRxErr(LatchedMRxErr),      .Loopback(r_LoopBck),                        .r_FullD(r_FullD)
813 15 mohor
);
814
 
815
 
816
endmodule

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