OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_7/] [rtl/] [verilog/] [eth_fifo.v] - Blame information for rev 40

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 40 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_fifo.v                                                  ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001 Authors                                   ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44
//
45
 
46
`include "timescale.v"
47
 
48
module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty);
49
 
50
parameter DATA_WIDTH    = 32;
51
parameter DEPTH         = 8;
52
parameter CNT_WIDTH     = 4;
53
 
54
parameter Tp            = 1;
55
 
56
input                     clk;
57
input                     reset;
58
input                     write;
59
input                     read;
60
input                     clear;
61
input   [DATA_WIDTH-1:0]  data_in;
62
 
63
output  [DATA_WIDTH-1:0]  data_out;
64
output                    almost_full;
65
output                    full;
66
output                    almost_empty;
67
output                    empty;
68
 
69
reg     [DATA_WIDTH-1:0]  fifo  [0:DEPTH-1];
70
reg     [CNT_WIDTH-1:0]   cnt;
71
reg     [CNT_WIDTH-2:0]   read_pointer;
72
reg     [CNT_WIDTH-2:0]   write_pointer;
73
 
74
 
75
always @ (posedge clk or posedge reset)
76
begin
77
  if(reset)
78
    cnt <=#Tp 0;
79
  else
80
  if(clear)
81
    cnt <=#Tp 0;
82
  else
83
  if(read ^ write)
84
    if(read)
85
      cnt <=#Tp cnt - 1'b1;
86
    else
87
      cnt <=#Tp cnt + 1'b1;
88
end
89
 
90
always @ (posedge clk or posedge reset)
91
begin
92
  if(reset)
93
    read_pointer <=#Tp 0;
94
  else
95
  if(clear)
96
    read_pointer <=#Tp 0;
97
  else
98
  if(read & ~empty)
99
    read_pointer <=#Tp read_pointer + 1'b1;
100
end
101
 
102
always @ (posedge clk or posedge reset)
103
begin
104
  if(reset)
105
    write_pointer <=#Tp 0;
106
  else
107
  if(clear)
108
    write_pointer <=#Tp 0;
109
  else
110
  if(write & ~full)
111
    write_pointer <=#Tp write_pointer + 1'b1;
112
end
113
 
114
assign empty = ~(|cnt);
115
assign almost_empty = cnt == 1;
116
assign full  = cnt == DEPTH;
117
assign almost_full  = &cnt[CNT_WIDTH-2:0];
118
 
119
always @ (posedge clk)
120
begin
121
  if(write & ~full)
122
    fifo[write_pointer] <=#Tp data_in;
123
end
124
 
125
assign data_out = fifo[read_pointer];
126
 
127
 
128
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2023 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.