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[/] [ethmac/] [tags/] [rel_7/] [rtl/] [verilog/] [eth_receivecontrol.v] - Blame information for rev 338

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_receivecontrol.v                                        ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/10/19 08:43:51  mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1  2001/08/06 14:44:29  mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1  2001/07/03 12:51:54  mohor
// Initial release of the MAC Control module.
//
//
//
//
//
 
 
`include "timescale.v"
 
 
module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
                           RxEndFrm, RxFlow, ReceiveEnd, MAC, PassAll, DlyCrcEn, TxDoneIn,
                           TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
                           TxUsedDataOutDetected, Pause, ReceivedPauseFrm
                          );
 
parameter Tp = 1;
 
 
input       MTxClk;
input       MRxClk;
input       TxReset;
input       RxReset;
input [7:0] RxData;
input       RxValid;
input       RxStartFrm;
input       RxEndFrm;
input       RxFlow;
input       ReceiveEnd;
input [47:0]MAC;
input       PassAll;
input       DlyCrcEn;
input       TxDoneIn;
input       TxAbortIn;
input       TxStartFrmOut;
input       ReceivedLengthOK;
input       ReceivedPacketGood;
input       TxUsedDataOutDetected;
 
output      Pause;
output      ReceivedPauseFrm;
 
reg         Pause;
reg         AddressOK;                // Multicast or unicast address detected
reg         TypeLengthOK;             // Type/Length field contains 0x8808
reg         DetectionWindow;          // Detection of the PAUSE frame is possible within this window
reg         OpCodeOK;                 // PAUSE opcode detected (0x0001)
reg  [2:0]  DlyCrcCnt;
reg  [4:0]  ByteCnt;
reg [15:0]  AssembledTimerValue;
reg [15:0]  LatchedTimerValue;
reg         ReceivedPauseFrm;
reg         ReceivedPauseFrmWAddr;
reg         PauseTimerEq0_sync1;
reg         PauseTimerEq0_sync2;
reg [15:0]  PauseTimer;
reg         Divider2;
reg  [5:0]  SlotTimer;
 
wire [47:0] ReservedMulticast;        // 0x0180C2000001
wire [15:0] TypeLength;               // 0x8808
wire        ResetByteCnt;             // 
wire        IncrementByteCnt;         // 
wire        ByteCntEq0;               // ByteCnt = 0
wire        ByteCntEq1;               // ByteCnt = 1
wire        ByteCntEq2;               // ByteCnt = 2
wire        ByteCntEq3;               // ByteCnt = 3
wire        ByteCntEq4;               // ByteCnt = 4
wire        ByteCntEq5;               // ByteCnt = 5
wire        ByteCntEq12;              // ByteCnt = 12
wire        ByteCntEq13;              // ByteCnt = 13
wire        ByteCntEq14;              // ByteCnt = 14
wire        ByteCntEq15;              // ByteCnt = 15
wire        ByteCntEq16;              // ByteCnt = 16
wire        ByteCntEq17;              // ByteCnt = 17
wire        ByteCntEq18;              // ByteCnt = 18
wire        SetPauseTimer;            // 
wire        DecrementPauseTimer;      // 
wire        PauseTimerEq0;            // 
wire        ResetSlotTimer;           // 
wire        IncrementSlotTimer;       // 
wire        SlotFinished;             // 
 
 
 
// Reserved multicast address and Type/Length for PAUSE control
assign ReservedMulticast = 48'h0180C2000001;
assign TypeLength = 16'h8808;
 
 
// Address Detection (Multicast or unicast)
always @ (posedge MRxClk or posedge RxReset)
begin
  if(RxReset)
    AddressOK <= #Tp 1'b0;
  else
  if(DetectionWindow & ByteCntEq0)
    AddressOK <= #Tp  RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40];
  else
  if(DetectionWindow & ByteCntEq1)
    AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK;
  else
  if(DetectionWindow & ByteCntEq2)
    AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK;
  else
  if(DetectionWindow & ByteCntEq3)
    AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK;
  else
  if(DetectionWindow & ByteCntEq4)
    AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[15:8]  | RxData[7:0] == MAC[15:8])  & AddressOK;
  else
  if(DetectionWindow & ByteCntEq5)
    AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[7:0]   | RxData[7:0] == MAC[7:0])   & AddressOK;
  else
  if(ReceiveEnd)
    AddressOK <= #Tp 1'b0;
end
 
 
 
// TypeLengthOK (Type/Length Control frame detected)
always @ (posedge MRxClk or posedge RxReset )
begin
  if(RxReset)
    TypeLengthOK <= #Tp 1'b0;
  else
  if(DetectionWindow & ByteCntEq12)
    TypeLengthOK <= #Tp ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]);
  else
  if(DetectionWindow & ByteCntEq13)
    TypeLengthOK <= #Tp ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK;
  else
  if(ReceiveEnd)
    TypeLengthOK <= #Tp 1'b0;
end
 
 
 
// Latch Control Frame Opcode
always @ (posedge MRxClk or posedge RxReset )
begin
  if(RxReset)
    OpCodeOK <= #Tp 1'b0;
  else
  if(RxStartFrm)
    OpCodeOK <= #Tp 1'b0;
  else
    begin
      if(DetectionWindow & ByteCntEq14)
        OpCodeOK <= #Tp ByteCntEq14 & RxData[7:0] == 8'h00;
 
      if(DetectionWindow & ByteCntEq15)
        OpCodeOK <= #Tp ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK;
    end
end
 
 
// ReceivedPauseFrmWAddr (+Address Check)
always @ (posedge MRxClk or posedge RxReset )
begin
  if(RxReset)
    ReceivedPauseFrmWAddr <= #Tp 1'b0;
  else
  if(ReceiveEnd)
    ReceivedPauseFrmWAddr <= #Tp 1'b0;
  else
  if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK)
    ReceivedPauseFrmWAddr <= #Tp 1'b1;
end
 
 
 
// Assembling 16-bit timer value from two 8-bit data
always @ (posedge MRxClk or posedge RxReset )
begin
  if(RxReset)
    AssembledTimerValue[15:0] <= #Tp 16'h0;
  else
  if(RxStartFrm)
    AssembledTimerValue[15:0] <= #Tp 16'h0;
  else
    begin
      if(DetectionWindow & ByteCntEq16)
        AssembledTimerValue[15:8] <= #Tp RxData[7:0];
      if(DetectionWindow & ByteCntEq17)
        AssembledTimerValue[7:0] <= #Tp RxData[7:0];
    end
end
 
 
// Detection window (while PAUSE detection is possible)
always @ (posedge MRxClk or posedge RxReset )
begin
  if(RxReset)
    DetectionWindow <= #Tp 1'b1;
  else
  if(ByteCntEq18)
    DetectionWindow <= #Tp 1'b0;
  else
  if(ReceiveEnd)
    DetectionWindow <= #Tp 1'b1;
end
 
 
 
// Latching Timer Value
always @ (posedge MRxClk or posedge RxReset )
begin
  if(RxReset)
    LatchedTimerValue[15:0] <= #Tp 16'h0;
  else
  if(~PassAll & DetectionWindow &  ReceivedPauseFrmWAddr &  ByteCntEq18)
    LatchedTimerValue[15:0] <= #Tp AssembledTimerValue[15:0];
  else
  if(ReceiveEnd)
    LatchedTimerValue[15:0] <= #Tp 16'h0;
end
 
 
 
// Delayed CEC counter
always @ (posedge MRxClk or posedge RxReset)
begin
  if(RxReset)
    DlyCrcCnt <= #Tp 3'h0;
  else
  if(RxValid & RxEndFrm)
    DlyCrcCnt <= #Tp 3'h0;
  else
  if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])
    DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
end
 
 
assign ResetByteCnt = RxEndFrm;
assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
 
 
// Byte counter
always @ (posedge MRxClk or posedge RxReset)
begin
  if(RxReset)
    ByteCnt[4:0] <= #Tp 5'h0;
  else
  if(ResetByteCnt)
    ByteCnt[4:0] <= #Tp 5'h0;
  else
  if(IncrementByteCnt)
    ByteCnt[4:0] <= #Tp ByteCnt[4:0] + 1'b1;
end
 
 
assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;
assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;
assign ByteCntEq2 = RxValid & ByteCnt[4:0] == 5'h2;
assign ByteCntEq3 = RxValid & ByteCnt[4:0] == 5'h3;
assign ByteCntEq4 = RxValid & ByteCnt[4:0] == 5'h4;
assign ByteCntEq5 = RxValid & ByteCnt[4:0] == 5'h5;
assign ByteCntEq12 = RxValid & ByteCnt[4:0] == 5'h0C;
assign ByteCntEq13 = RxValid & ByteCnt[4:0] == 5'h0D;
assign ByteCntEq14 = RxValid & ByteCnt[4:0] == 5'h0E;
assign ByteCntEq15 = RxValid & ByteCnt[4:0] == 5'h0F;
assign ByteCntEq16 = RxValid & ByteCnt[4:0] == 5'h10;
assign ByteCntEq17 = RxValid & ByteCnt[4:0] == 5'h11;
assign ByteCntEq18 = RxValid & ByteCnt[4:0] == 5'h12 & DetectionWindow;
 
 
assign SetPauseTimer = ReceiveEnd & ReceivedPauseFrmWAddr & ReceivedPacketGood & ReceivedLengthOK & RxFlow;
assign DecrementPauseTimer = SlotFinished & |PauseTimer;
 
 
// PauseTimer[15:0]
always @ (posedge MRxClk or posedge RxReset)
begin
  if(RxReset)
    PauseTimer[15:0] <= #Tp 16'h0;
  else
  if(SetPauseTimer)
    PauseTimer[15:0] <= #Tp LatchedTimerValue[15:0];
  else
  if(DecrementPauseTimer)
    PauseTimer[15:0] <= #Tp PauseTimer[15:0] - 1'b1;
end
 
assign PauseTimerEq0 = ~(|PauseTimer[15:0]);
 
 
 
// Synchronization of the pause timer
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    begin
      PauseTimerEq0_sync1 <= #Tp 1'b1;
      PauseTimerEq0_sync2 <= #Tp 1'b1;
    end
  else
    begin
      PauseTimerEq0_sync1 <= #Tp PauseTimerEq0;
      PauseTimerEq0_sync2 <= #Tp PauseTimerEq0_sync1;
    end
end
 
 
// Pause signal generation
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    Pause <= #Tp 1'b0;
  else
  if((TxDoneIn | TxAbortIn | ~TxUsedDataOutDetected) & ~TxStartFrmOut)
    Pause <= #Tp RxFlow & ~PauseTimerEq0_sync2;
end
 
 
// Divider2 is used for incrementing the Slot timer every other clock
always @ (posedge MRxClk or posedge RxReset)
begin
  if(RxReset)
    Divider2 <= #Tp 1'b0;
  else
  if(|PauseTimer[15:0] & RxFlow)
    Divider2 <= #Tp ~Divider2;
  else
    Divider2 <= #Tp 1'b0;
end
 
 
assign ResetSlotTimer = RxReset;
assign IncrementSlotTimer =  Pause & RxFlow & Divider2;
 
 
// SlotTimer
always @ (posedge MRxClk or posedge RxReset)
begin
  if(RxReset)
    SlotTimer[5:0] <= #Tp 6'h0;
  else
  if(ResetSlotTimer)
    SlotTimer[5:0] <= #Tp 6'h0;
  else
  if(IncrementSlotTimer)
    SlotTimer[5:0] <= #Tp SlotTimer[5:0] + 1'b1;
end
 
 
assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer;  // Slot is 512 bits (64 bytes)
 
 
 
// Pause Frame received
always @ (posedge MRxClk or posedge RxReset)
begin
  if(RxReset)
    ReceivedPauseFrm <=#Tp 1'b0;
  else
  if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
    ReceivedPauseFrm <=#Tp 1'b1;
  else
  if(ReceiveEnd)
    ReceivedPauseFrm <=#Tp 1'b0;
end
 
 
endmodule

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[/] [ethmac/] [tags/] [rel_7/] [rtl/] [verilog/] [eth_receivecontrol.v] - Blame information for rev 338

Line No.	Rev	Author	Line
1	15	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_receivecontrol.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6	37	mohor	`//// http://www.opencores.org/projects/ethmac/ ////`
7	15	mohor	`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	37	mohor	`// Revision 1.2 2001/10/19 08:43:51 mohor`
45			`// eth_timescale.v changed to timescale.v This is done because of the`
46			`// simulation of the few cores in a one joined project.`
47			`//`
48	22	mohor	`// Revision 1.1 2001/08/06 14:44:29 mohor`
49			`// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).`
50			`// Include files fixed to contain no path.`
51			`// File names and module names changed ta have a eth_ prologue in the name.`
52			`// File eth_timescale.v is used to define timescale`
53			`// All pin names on the top module are changed to contain _I, _O or _OE at the end.`
54			`// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O`
55			`// and Mdo_OE. The bidirectional signal must be created on the top level. This`
56			`// is done due to the ASIC tools.`
57			`//`
58	15	mohor	`// Revision 1.1 2001/07/30 21:23:42 mohor`
59			`// Directory structure changed. Files checked and joind together.`
60			`//`
61			`// Revision 1.1 2001/07/03 12:51:54 mohor`
62			`// Initial release of the MAC Control module.`
63			`//`
64			`//`
65			`//`
66			`//`
67			`//`
68
69
70	22	mohor	`include "timescale.v"
71	15	mohor
72
73			`module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,`
74			`RxEndFrm, RxFlow, ReceiveEnd, MAC, PassAll, DlyCrcEn, TxDoneIn,`
75			`TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,`
76			`TxUsedDataOutDetected, Pause, ReceivedPauseFrm`
77			`);`
78
79			`parameter Tp = 1;`
80
81
82			`input MTxClk;`
83			`input MRxClk;`
84			`input TxReset;`
85			`input RxReset;`
86			`input [7:0] RxData;`
87			`input RxValid;`
88			`input RxStartFrm;`
89			`input RxEndFrm;`
90			`input RxFlow;`
91			`input ReceiveEnd;`
92			`input [47:0]MAC;`
93			`input PassAll;`
94			`input DlyCrcEn;`
95			`input TxDoneIn;`
96			`input TxAbortIn;`
97			`input TxStartFrmOut;`
98			`input ReceivedLengthOK;`
99			`input ReceivedPacketGood;`
100			`input TxUsedDataOutDetected;`
101
102			`output Pause;`
103			`output ReceivedPauseFrm;`
104
105			`reg Pause;`
106			`reg AddressOK; // Multicast or unicast address detected`
107			`reg TypeLengthOK; // Type/Length field contains 0x8808`
108			`reg DetectionWindow; // Detection of the PAUSE frame is possible within this window`
109			`reg OpCodeOK; // PAUSE opcode detected (0x0001)`
110			`reg [2:0] DlyCrcCnt;`
111			`reg [4:0] ByteCnt;`
112			`reg [15:0] AssembledTimerValue;`
113			`reg [15:0] LatchedTimerValue;`
114			`reg ReceivedPauseFrm;`
115			`reg ReceivedPauseFrmWAddr;`
116			`reg PauseTimerEq0_sync1;`
117			`reg PauseTimerEq0_sync2;`
118			`reg [15:0] PauseTimer;`
119			`reg Divider2;`
120			`reg [5:0] SlotTimer;`
121
122			`wire [47:0] ReservedMulticast; // 0x0180C2000001`
123			`wire [15:0] TypeLength; // 0x8808`
124			`wire ResetByteCnt; //`
125			`wire IncrementByteCnt; //`
126			`wire ByteCntEq0; // ByteCnt = 0`
127			`wire ByteCntEq1; // ByteCnt = 1`
128			`wire ByteCntEq2; // ByteCnt = 2`
129			`wire ByteCntEq3; // ByteCnt = 3`
130			`wire ByteCntEq4; // ByteCnt = 4`
131			`wire ByteCntEq5; // ByteCnt = 5`
132			`wire ByteCntEq12; // ByteCnt = 12`
133			`wire ByteCntEq13; // ByteCnt = 13`
134			`wire ByteCntEq14; // ByteCnt = 14`
135			`wire ByteCntEq15; // ByteCnt = 15`
136			`wire ByteCntEq16; // ByteCnt = 16`
137			`wire ByteCntEq17; // ByteCnt = 17`
138			`wire ByteCntEq18; // ByteCnt = 18`
139			`wire SetPauseTimer; //`
140			`wire DecrementPauseTimer; //`
141			`wire PauseTimerEq0; //`
142			`wire ResetSlotTimer; //`
143			`wire IncrementSlotTimer; //`
144			`wire SlotFinished; //`
145
146
147
148			`// Reserved multicast address and Type/Length for PAUSE control`
149			`assign ReservedMulticast = 48'h0180C2000001;`
150			`assign TypeLength = 16'h8808;`
151
152
153			`// Address Detection (Multicast or unicast)`
154			`always @ (posedge MRxClk or posedge RxReset)`
155			`begin`
156			`if(RxReset)`
157			`AddressOK <= #Tp 1'b0;`
158			`else`
159			`if(DetectionWindow & ByteCntEq0)`
160			`AddressOK <= #Tp RxData[7:0] == ReservedMulticast[47:40] \| RxData[7:0] == MAC[47:40];`
161			`else`
162			`if(DetectionWindow & ByteCntEq1)`
163			`AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[39:32] \| RxData[7:0] == MAC[39:32]) & AddressOK;`
164			`else`
165			`if(DetectionWindow & ByteCntEq2)`
166			`AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[31:24] \| RxData[7:0] == MAC[31:24]) & AddressOK;`
167			`else`
168			`if(DetectionWindow & ByteCntEq3)`
169			`AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[23:16] \| RxData[7:0] == MAC[23:16]) & AddressOK;`
170			`else`
171			`if(DetectionWindow & ByteCntEq4)`
172			`AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[15:8] \| RxData[7:0] == MAC[15:8]) & AddressOK;`
173			`else`
174			`if(DetectionWindow & ByteCntEq5)`
175			`AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[7:0] \| RxData[7:0] == MAC[7:0]) & AddressOK;`
176			`else`
177			`if(ReceiveEnd)`
178			`AddressOK <= #Tp 1'b0;`
179			`end`
180
181
182
183			`// TypeLengthOK (Type/Length Control frame detected)`
184			`always @ (posedge MRxClk or posedge RxReset )`
185			`begin`
186			`if(RxReset)`
187			`TypeLengthOK <= #Tp 1'b0;`
188			`else`
189			`if(DetectionWindow & ByteCntEq12)`
190			`TypeLengthOK <= #Tp ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]);`
191			`else`
192			`if(DetectionWindow & ByteCntEq13)`
193			`TypeLengthOK <= #Tp ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK;`
194			`else`
195			`if(ReceiveEnd)`
196			`TypeLengthOK <= #Tp 1'b0;`
197			`end`
198
199
200
201			`// Latch Control Frame Opcode`
202			`always @ (posedge MRxClk or posedge RxReset )`
203			`begin`
204			`if(RxReset)`
205			`OpCodeOK <= #Tp 1'b0;`
206			`else`
207			`if(RxStartFrm)`
208			`OpCodeOK <= #Tp 1'b0;`
209			`else`
210			`begin`
211			`if(DetectionWindow & ByteCntEq14)`
212			`OpCodeOK <= #Tp ByteCntEq14 & RxData[7:0] == 8'h00;`
213
214			`if(DetectionWindow & ByteCntEq15)`
215			`OpCodeOK <= #Tp ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK;`
216			`end`
217			`end`
218
219
220			`// ReceivedPauseFrmWAddr (+Address Check)`
221			`always @ (posedge MRxClk or posedge RxReset )`
222			`begin`
223			`if(RxReset)`
224			`ReceivedPauseFrmWAddr <= #Tp 1'b0;`
225			`else`
226			`if(ReceiveEnd)`
227			`ReceivedPauseFrmWAddr <= #Tp 1'b0;`
228			`else`
229			`if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK)`
230			`ReceivedPauseFrmWAddr <= #Tp 1'b1;`
231			`end`
232
233
234
235			`// Assembling 16-bit timer value from two 8-bit data`
236			`always @ (posedge MRxClk or posedge RxReset )`
237			`begin`
238			`if(RxReset)`
239			`AssembledTimerValue[15:0] <= #Tp 16'h0;`
240			`else`
241			`if(RxStartFrm)`
242			`AssembledTimerValue[15:0] <= #Tp 16'h0;`
243			`else`
244			`begin`
245			`if(DetectionWindow & ByteCntEq16)`
246			`AssembledTimerValue[15:8] <= #Tp RxData[7:0];`
247			`if(DetectionWindow & ByteCntEq17)`
248			`AssembledTimerValue[7:0] <= #Tp RxData[7:0];`
249			`end`
250			`end`
251
252
253			`// Detection window (while PAUSE detection is possible)`
254			`always @ (posedge MRxClk or posedge RxReset )`
255			`begin`
256			`if(RxReset)`
257			`DetectionWindow <= #Tp 1'b1;`
258			`else`
259			`if(ByteCntEq18)`
260			`DetectionWindow <= #Tp 1'b0;`
261			`else`
262			`if(ReceiveEnd)`
263			`DetectionWindow <= #Tp 1'b1;`
264			`end`
265
266
267
268			`// Latching Timer Value`
269			`always @ (posedge MRxClk or posedge RxReset )`
270			`begin`
271			`if(RxReset)`
272			`LatchedTimerValue[15:0] <= #Tp 16'h0;`
273			`else`
274			`if(~PassAll & DetectionWindow & ReceivedPauseFrmWAddr & ByteCntEq18)`
275			`LatchedTimerValue[15:0] <= #Tp AssembledTimerValue[15:0];`
276			`else`
277			`if(ReceiveEnd)`
278			`LatchedTimerValue[15:0] <= #Tp 16'h0;`
279			`end`
280
281
282
283			`// Delayed CEC counter`
284			`always @ (posedge MRxClk or posedge RxReset)`
285			`begin`
286			`if(RxReset)`
287			`DlyCrcCnt <= #Tp 3'h0;`
288			`else`
289			`if(RxValid & RxEndFrm)`
290			`DlyCrcCnt <= #Tp 3'h0;`
291			`else`
292			`if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])`
293			`DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;`
294			`end`
295
296
297			`assign ResetByteCnt = RxEndFrm;`
298			`assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn \| DlyCrcEn & DlyCrcCnt[2]);`
299
300
301			`// Byte counter`
302			`always @ (posedge MRxClk or posedge RxReset)`
303			`begin`
304			`if(RxReset)`
305			`ByteCnt[4:0] <= #Tp 5'h0;`
306			`else`
307			`if(ResetByteCnt)`
308			`ByteCnt[4:0] <= #Tp 5'h0;`
309			`else`
310			`if(IncrementByteCnt)`
311			`ByteCnt[4:0] <= #Tp ByteCnt[4:0] + 1'b1;`
312			`end`
313
314
315			`assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;`
316			`assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;`
317			`assign ByteCntEq2 = RxValid & ByteCnt[4:0] == 5'h2;`
318			`assign ByteCntEq3 = RxValid & ByteCnt[4:0] == 5'h3;`
319			`assign ByteCntEq4 = RxValid & ByteCnt[4:0] == 5'h4;`
320			`assign ByteCntEq5 = RxValid & ByteCnt[4:0] == 5'h5;`
321			`assign ByteCntEq12 = RxValid & ByteCnt[4:0] == 5'h0C;`
322			`assign ByteCntEq13 = RxValid & ByteCnt[4:0] == 5'h0D;`
323			`assign ByteCntEq14 = RxValid & ByteCnt[4:0] == 5'h0E;`
324			`assign ByteCntEq15 = RxValid & ByteCnt[4:0] == 5'h0F;`
325			`assign ByteCntEq16 = RxValid & ByteCnt[4:0] == 5'h10;`
326			`assign ByteCntEq17 = RxValid & ByteCnt[4:0] == 5'h11;`
327			`assign ByteCntEq18 = RxValid & ByteCnt[4:0] == 5'h12 & DetectionWindow;`
328
329
330			`assign SetPauseTimer = ReceiveEnd & ReceivedPauseFrmWAddr & ReceivedPacketGood & ReceivedLengthOK & RxFlow;`
331			`assign DecrementPauseTimer = SlotFinished & \|PauseTimer;`
332
333
334			`// PauseTimer[15:0]`
335			`always @ (posedge MRxClk or posedge RxReset)`
336			`begin`
337			`if(RxReset)`
338			`PauseTimer[15:0] <= #Tp 16'h0;`
339			`else`
340			`if(SetPauseTimer)`
341			`PauseTimer[15:0] <= #Tp LatchedTimerValue[15:0];`
342			`else`
343			`if(DecrementPauseTimer)`
344			`PauseTimer[15:0] <= #Tp PauseTimer[15:0] - 1'b1;`
345			`end`
346
347			`assign PauseTimerEq0 = ~(\|PauseTimer[15:0]);`
348
349
350
351			`// Synchronization of the pause timer`
352			`always @ (posedge MTxClk or posedge TxReset)`
353			`begin`
354			`if(TxReset)`
355			`begin`
356			`PauseTimerEq0_sync1 <= #Tp 1'b1;`
357			`PauseTimerEq0_sync2 <= #Tp 1'b1;`
358			`end`
359			`else`
360			`begin`
361			`PauseTimerEq0_sync1 <= #Tp PauseTimerEq0;`
362			`PauseTimerEq0_sync2 <= #Tp PauseTimerEq0_sync1;`
363			`end`
364			`end`
365
366
367			`// Pause signal generation`
368			`always @ (posedge MTxClk or posedge TxReset)`
369			`begin`
370			`if(TxReset)`
371			`Pause <= #Tp 1'b0;`
372			`else`
373			`if((TxDoneIn \| TxAbortIn \| ~TxUsedDataOutDetected) & ~TxStartFrmOut)`
374			`Pause <= #Tp RxFlow & ~PauseTimerEq0_sync2;`
375			`end`
376
377
378			`// Divider2 is used for incrementing the Slot timer every other clock`
379			`always @ (posedge MRxClk or posedge RxReset)`
380			`begin`
381			`if(RxReset)`
382			`Divider2 <= #Tp 1'b0;`
383			`else`
384			`if(\|PauseTimer[15:0] & RxFlow)`
385			`Divider2 <= #Tp ~Divider2;`
386			`else`
387			`Divider2 <= #Tp 1'b0;`
388			`end`
389
390
391			`assign ResetSlotTimer = RxReset;`
392			`assign IncrementSlotTimer = Pause & RxFlow & Divider2;`
393
394
395			`// SlotTimer`
396			`always @ (posedge MRxClk or posedge RxReset)`
397			`begin`
398			`if(RxReset)`
399			`SlotTimer[5:0] <= #Tp 6'h0;`
400			`else`
401			`if(ResetSlotTimer)`
402			`SlotTimer[5:0] <= #Tp 6'h0;`
403			`else`
404			`if(IncrementSlotTimer)`
405			`SlotTimer[5:0] <= #Tp SlotTimer[5:0] + 1'b1;`
406			`end`
407
408
409			`assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer; // Slot is 512 bits (64 bytes)`
410
411
412
413			`// Pause Frame received`
414			`always @ (posedge MRxClk or posedge RxReset)`
415			`begin`
416			`if(RxReset)`
417			`ReceivedPauseFrm <=#Tp 1'b0;`
418			`else`
419			`if(ByteCntEq16 & TypeLengthOK & OpCodeOK)`
420			`ReceivedPauseFrm <=#Tp 1'b1;`
421			`else`
422			`if(ReceiveEnd)`
423			`ReceivedPauseFrm <=#Tp 1'b0;`
424			`end`
425
426
427			`endmodule`