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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  README.txt                                                  ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/project,ethmac                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////      - Olof Kindgren (olof@opencores.org)                    ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001, 2002 Authors                             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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//
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//
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RUNNING the simulation/Testbench in Icarus Verilog:
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Go to the scripts directory and write "make rtl-tests"
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All logs will be saved in the log directory
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To activate VCD dumps, run with "make rtl-tests VCD=1". The VCD is saved
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in build/sim/ethmac.vcd
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RUNNING the simulation/Testbench in ModelSIM:
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Open ModelSIM project: ethernet/sim/rtl_sim/modelsim_sim/bin/ethernet.mpf
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Run the macro do.do (write "do do.do" in the command window).
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Simulation will be automatically started. Logs are stored in the /log
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directory. tb_ethernet test is performed.
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RUNNING the simulation/Testbench in Ncsim:
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Go to the ethernet\sim\rtl_sim\ncsim_sim\run directory. Run the
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run_eth_sim_regr.scr script. Simulation is automatically started. Logs are
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stored in the /log directory. Before running the script for another time,
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run the clean script that deletes files from previous runs. tb_ethernet test
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is performed.
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Why are eth_cop.v, eth_host.v, eth_memory, tb_cop.v and tb_ethernet_with_cop.v
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files used for?
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Although the testbench does not include the traffic coprocessor, the
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coprocessor is part of the ethernet environment. eth_cop multiplexes
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two wishbone interface between 4 modules:
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- First wishbone master interface is connected to the HOST (eth_host)
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- Second wishbone master interface is connected to the Ethernet Core (for
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  accessing data in the memory (eth_memory)).
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- First wishbone slave interface is connected to the Ethernet Core (for
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  accessing registers and buffer descriptors).
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- Second wishbone slave interface is connected to the memory (eth_memory)
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  so host can write data to the memory (or read data from the memory.
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tb_cop.c is a testbench just for the traffic coprocessor (eth_cop).
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tb_ethernet_with_cop.v is a simple testbench where all above mentioned
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modules are connected into a single environment. Few packets are transmitted
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and received. The "main" testbench is tb_ethernet.v file. It performs several
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tests (eth_cop is not part of the simulation environment).
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