OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [README.txt] - Blame information for rev 350

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 190 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  README.txt                                                  ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 347 olof
////  http://www.opencores.org/project,ethmac                     ////
7 190 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10 347 olof
////      - Olof Kindgren (olof@opencores.org)                    ////
11 190 mohor
////                                                              ////
12
////                                                              ////
13
//////////////////////////////////////////////////////////////////////
14
////                                                              ////
15
//// Copyright (C) 2001, 2002 Authors                             ////
16
////                                                              ////
17
//// This source file may be used and distributed without         ////
18
//// restriction provided that this copyright statement is not    ////
19
//// removed from the file and that any derivative work contains  ////
20
//// the original copyright notice and the associated disclaimer. ////
21
////                                                              ////
22
//// This source file is free software; you can redistribute it   ////
23
//// and/or modify it under the terms of the GNU Lesser General   ////
24
//// Public License as published by the Free Software Foundation; ////
25
//// either version 2.1 of the License, or (at your option) any   ////
26
//// later version.                                               ////
27
////                                                              ////
28
//// This source is distributed in the hope that it will be       ////
29
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
30
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
31
//// PURPOSE.  See the GNU Lesser General Public License for more ////
32
//// details.                                                     ////
33
////                                                              ////
34
//// You should have received a copy of the GNU Lesser General    ////
35
//// Public License along with this source; if not, download it   ////
36
//// from http://www.opencores.org/lgpl.shtml                     ////
37
////                                                              ////
38
//////////////////////////////////////////////////////////////////////
39
//
40
// CVS Revision History
41
//
42
// $Log: not supported by cvs2svn $
43
//
44
//
45
//
46
 
47 347 olof
RUNNING the simulation/Testbench in Icarus Verilog:
48
 
49
Go to the scripts directory and write "make rtl-tests"
50
All logs will be saved in the log directory
51
 
52 348 olof
To activate VCD dumps, run with "make rtl-tests VCD=1". The VCD is saved
53
in build/sim/ethmac.vcd
54 347 olof
 
55 348 olof
 
56 190 mohor
RUNNING the simulation/Testbench in ModelSIM:
57
 
58
Open ModelSIM project: ethernet/sim/rtl_sim/modelsim_sim/bin/ethernet.mpf
59
Run the macro do.do (write "do do.do" in the command window).
60
Simulation will be automatically started. Logs are stored in the /log
61
directory. tb_ethernet test is performed.
62
 
63
 
64
 
65
RUNNING the simulation/Testbench in Ncsim:
66
 
67
Go to the ethernet\sim\rtl_sim\ncsim_sim\run directory. Run the
68
run_eth_sim_regr.scr script. Simulation is automatically started. Logs are
69
stored in the /log directory. Before running the script for another time,
70
run the clean script that deletes files from previous runs. tb_ethernet test
71
is performed.
72
 
73
 
74
 
75
 
76
 
77
 
78
Why are eth_cop.v, eth_host.v, eth_memory, tb_cop.v and tb_ethernet_with_cop.v
79
files used for?
80
 
81
Although the testbench does not include the traffic coprocessor, the
82
coprocessor is part of the ethernet environment. eth_cop multiplexes
83
two wishbone interface between 4 modules:
84
- First wishbone master interface is connected to the HOST (eth_host)
85
- Second wishbone master interface is connected to the Ethernet Core (for
86
  accessing data in the memory (eth_memory)).
87
- First wishbone slave interface is connected to the Ethernet Core (for
88
  accessing registers and buffer descriptors).
89
- Second wishbone slave interface is connected to the memory (eth_memory)
90
  so host can write data to the memory (or read data from the memory.
91
 
92
tb_cop.c is a testbench just for the traffic coprocessor (eth_cop).
93
tb_ethernet_with_cop.v is a simple testbench where all above mentioned
94
modules are connected into a single environment. Few packets are transmitted
95
and received. The "main" testbench is tb_ethernet.v file. It performs several
96
tests (eth_cop is not part of the simulation environment).
97
 
98
 
99
 
100
 
101
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.