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[/] [ethmac/] [trunk/] [bench/] [verilog/] [eth_host.v] - Blame information for rev 346

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1 116 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_host.v                                                  ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 116 mohor
////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001, 2002 Authors                             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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//
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//
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//
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`include "tb_eth_defines.v"
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`include "timescale.v"
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module eth_host
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(
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  // WISHBONE common
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  wb_clk_i, wb_rst_i,
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  // WISHBONE master
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  wb_adr_o, wb_sel_o, wb_we_o, wb_dat_i, wb_dat_o, wb_cyc_o, wb_stb_o, wb_ack_i, wb_err_i
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);
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parameter Tp=1;
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input         wb_clk_i, wb_rst_i;
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input  [31:0] wb_dat_i;
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input         wb_ack_i, wb_err_i;
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output [31:0] wb_adr_o, wb_dat_o;
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output  [3:0] wb_sel_o;
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output        wb_cyc_o, wb_stb_o, wb_we_o;
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reg    [31:0] wb_adr_o, wb_dat_o;
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reg     [3:0] wb_sel_o;
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reg           wb_cyc_o, wb_stb_o, wb_we_o;
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integer host_log;
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// Reset pulse
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initial
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begin
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  host_log = $fopen("eth_host.log");
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end
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task wb_write;
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  input  [31:0] addr;
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  input   [3:0] sel;
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  input  [31:0] data;
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  begin
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    @ (posedge wb_clk_i);   // Sync. with clock
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    #1;
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    wb_adr_o = addr;
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    wb_dat_o = data;
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    wb_sel_o = sel;
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    wb_cyc_o = 1;
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    wb_stb_o = 1;
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    wb_we_o  = 1;
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    wait(wb_ack_i | wb_err_i);
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    $fdisplay(host_log, "(%0t)(%m)wb_write (0x%0x) = 0x%0x", $time, wb_adr_o, wb_dat_o);
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    @ (posedge wb_clk_i);   // Sync. with clock
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    #1;
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    wb_adr_o = 'hx;
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    wb_dat_o = 'hx;
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    wb_sel_o = 'hx;
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    wb_cyc_o = 0;
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    wb_stb_o = 0;
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    wb_we_o  = 'hx;
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  end
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endtask
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task wb_read;
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  input  [31:0] addr;
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  input   [3:0] sel;
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  output [31:0] data;
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  begin
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    @ (posedge wb_clk_i);   // Sync. with clock
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    #1;
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    wb_adr_o = addr;
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    wb_sel_o = sel;
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    wb_cyc_o = 1;
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    wb_stb_o = 1;
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    wb_we_o  = 0;
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    wait(wb_ack_i | wb_err_i);
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    @ (posedge wb_clk_i);   // Sync. with clock
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    data = wb_dat_i;
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    $fdisplay(host_log, "(%0t)(%m)wb_read (0x%0x) = 0x%0x", $time, wb_adr_o, wb_dat_i);
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    #1;
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    wb_adr_o = 'hx;
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    wb_sel_o = 'hx;
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    wb_cyc_o = 0;
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    wb_stb_o = 0;
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    wb_we_o  = 'hx;
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  end
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endtask
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endmodule

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