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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_cop.v] - Blame information for rev 356

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1 116 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  tb_cop.v                                                    ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/projects/??????/                   ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001, 2002 Authors                             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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//
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//
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48
 
49
 
50
`include "timescale.v"
51
 
52
module tb_cop();
53
 
54
 
55
parameter Tp = 1;
56
 
57
 
58
reg         wb_clk_o;
59
reg         wb_rst_o;
60
 
61
 
62
// WISHBONE master 1 (input)
63
reg  [31:0] m1_wb_adr_o;
64
reg   [3:0] m1_wb_sel_o;
65
reg         m1_wb_we_o;
66
wire [31:0] m1_wb_dat_i;
67
reg  [31:0] m1_wb_dat_o;
68
reg         m1_wb_cyc_o;
69
reg         m1_wb_stb_o;
70
wire        m1_wb_ack_i;
71
wire        m1_wb_err_i;
72
 
73
// WISHBONE master 2 (input)
74
reg  [31:0] m2_wb_adr_o;
75
reg   [3:0] m2_wb_sel_o;
76
reg         m2_wb_we_o;
77
wire [31:0] m2_wb_dat_i;
78
reg  [31:0] m2_wb_dat_o;
79
reg         m2_wb_cyc_o;
80
reg         m2_wb_stb_o;
81
wire        m2_wb_ack_i;
82
wire        m2_wb_err_i;
83
 
84
// WISHBONE slave 1 (output)
85
wire [31:0] s1_wb_adr_i;
86
wire  [3:0] s1_wb_sel_i;
87
wire        s1_wb_we_i;
88
reg  [31:0] s1_wb_dat_o;
89
wire [31:0] s1_wb_dat_i;
90
wire        s1_wb_cyc_i;
91
wire        s1_wb_stb_i;
92
reg         s1_wb_ack_o;
93
reg         s1_wb_err_o;
94
 
95
// WISHBONE slave 2 (output)
96
wire [31:0] s2_wb_adr_i;
97
wire  [3:0] s2_wb_sel_i;
98
wire        s2_wb_we_i;
99
reg  [31:0] s2_wb_dat_o;
100
wire [31:0] s2_wb_dat_i;
101
wire        s2_wb_cyc_i;
102
wire        s2_wb_stb_i;
103
reg         s2_wb_ack_o;
104
reg         s2_wb_err_o;
105
 
106
 
107
reg         Wishbone1Busy;
108
reg         Wishbone2Busy;
109
 
110
reg         StartTB;
111
 
112
eth_cop i_eth_cop
113
(
114
  // WISHBONE common
115
  .wb_clk_i(wb_clk_o), .wb_rst_i(wb_rst_o),
116
 
117
  // WISHBONE MASTER 1
118
  .m1_wb_adr_i(m1_wb_adr_o), .m1_wb_sel_i(m1_wb_sel_o), .m1_wb_we_i (m1_wb_we_o),  .m1_wb_dat_o(m1_wb_dat_i),
119
  .m1_wb_dat_i(m1_wb_dat_o), .m1_wb_cyc_i(m1_wb_cyc_o), .m1_wb_stb_i(m1_wb_stb_o), .m1_wb_ack_o(m1_wb_ack_i),
120
  .m1_wb_err_o(m1_wb_err_i),
121
 
122
  // WISHBONE MASTER 2
123
  .m2_wb_adr_i(m2_wb_adr_o), .m2_wb_sel_i(m2_wb_sel_o), .m2_wb_we_i (m2_wb_we_o),  .m2_wb_dat_o(m2_wb_dat_i),
124
  .m2_wb_dat_i(m2_wb_dat_o), .m2_wb_cyc_i(m2_wb_cyc_o), .m2_wb_stb_i(m2_wb_stb_o), .m2_wb_ack_o(m2_wb_ack_i),
125
  .m2_wb_err_o(m2_wb_err_i),
126
 
127
  // WISHBONE slave 1
128
        .s1_wb_adr_o(s1_wb_adr_i), .s1_wb_sel_o(s1_wb_sel_i), .s1_wb_we_o (s1_wb_we_i),  .s1_wb_cyc_o(s1_wb_cyc_i),
129
        .s1_wb_stb_o(s1_wb_stb_i), .s1_wb_ack_i(s1_wb_ack_o), .s1_wb_err_i(s1_wb_err_o), .s1_wb_dat_i(s1_wb_dat_o),
130
        .s1_wb_dat_o(s1_wb_dat_i),
131
 
132
  // WISHBONE slave 2
133
        .s2_wb_adr_o(s2_wb_adr_i), .s2_wb_sel_o(s2_wb_sel_i), .s2_wb_we_o (s2_wb_we_i),  .s2_wb_cyc_o(s2_wb_cyc_i),
134
        .s2_wb_stb_o(s2_wb_stb_i), .s2_wb_ack_i(s2_wb_ack_o), .s2_wb_err_i(s2_wb_err_o), .s2_wb_dat_i(s2_wb_dat_o),
135
        .s2_wb_dat_o(s2_wb_dat_i)
136
);
137
 
138
/*
139
s1_wb_adr_i   m_wb_adr_i
140
s1_wb_sel_i   m_wb_sel_i
141
s1_wb_we_i    m_wb_we_i
142
s1_wb_dat_o   m_wb_dat_o
143
s1_wb_dat_i   m_wb_dat_i
144
s1_wb_cyc_i   m_wb_cyc_i
145
s1_wb_stb_i   m_wb_stb_i
146
s1_wb_ack_o   m_wb_ack_o
147
s1_wb_err_o   m_wb_err_o
148
*/
149
 
150
 
151
 
152
initial
153
begin
154
  s1_wb_ack_o = 0;
155
  s1_wb_err_o = 0;
156
  s1_wb_dat_o = 0;
157
  s2_wb_ack_o = 0;
158
  s2_wb_err_o = 0;
159
  s2_wb_dat_o = 0;
160
 
161
// WISHBONE master 1 (input)
162
  m1_wb_adr_o = 0;
163
  m1_wb_sel_o = 0;
164
  m1_wb_we_o  = 0;
165
  m1_wb_dat_o = 0;
166
  m1_wb_cyc_o = 0;
167
  m1_wb_stb_o = 0;
168
 
169
  // WISHBONE master 2 (input)
170
  m2_wb_adr_o = 0;
171
  m2_wb_sel_o = 0;
172
  m2_wb_we_o  = 0;
173
  m2_wb_dat_o = 0;
174
  m2_wb_cyc_o = 0;
175
  m2_wb_stb_o = 0;
176
 
177
  Wishbone1Busy = 1'b0;
178
  Wishbone2Busy = 1'b0;
179
end
180
 
181
 
182
// Reset pulse
183
initial
184
begin
185
  wb_rst_o =  1'b1;
186
  #100 wb_rst_o =  1'b0;
187
  #100 StartTB  =  1'b1;
188
end
189
 
190
 
191
 
192
// Generating WB_CLK_I clock
193
always
194
begin
195
  wb_clk_o = 0;
196
  forever #15 wb_clk_o = ~wb_clk_o;  // 2*15 ns -> 33.3 MHz    
197
end
198
 
199
 
200
integer seed_wb1, seed_wb2;
201
integer jj, kk;
202
initial
203
begin
204
  seed_wb1 = 0;
205
  seed_wb2 = 5;
206
end
207
 
208
 
209
 
210
 
211
initial
212
begin
213
  wait(StartTB);  // Start of testbench
214
 
215
  fork
216
 
217
  begin
218
    for(jj=0; jj<100; jj=jj+1)
219
    begin
220
      if(seed_wb1[3:0]<4)
221
        begin
222
          $display("(%0t) m1 write to eth start  (Data = Addr = 0x%0x)", $time, {21'h1a0000, seed_wb1[10:0]}); //0xd0000xxx
223
          Wishbone1Write({21'h1a0000, seed_wb1[10:0]}, {21'h1a0000, seed_wb1[10:0]});
224
        end
225
      else
226
      if(seed_wb1[3:0]<=7 && seed_wb1[3:0]>=4)
227
        begin
228
          $display("(%0t) m1 read to eth start  (Addr = 0x%0x)", $time, {21'h1a0000, seed_wb1[10:0]});
229
          Wishbone1Read({21'h1a0000, seed_wb1[10:0]});
230
        end
231
      else
232
      if(seed_wb1[3:0]<=11 && seed_wb1[3:0]>=8)
233
        begin
234
          $display("(%0t) m1 write to memory start  (Data = Addr = 0x%0x)", $time, {21'h000040, seed_wb1[10:0]}); //0x00020xxx
235
          Wishbone1Write({21'h1a0000, seed_wb1[10:0]}, {21'h000040, seed_wb1[10:0]});
236
        end
237
      else
238
      if(seed_wb1[3:0]>=12)
239
        begin
240
          $display("(%0t) m1 read to memory start  (Addr = 0x%0x)", $time, {21'h000040, seed_wb1[10:0]});
241
          Wishbone1Read({21'h000040, seed_wb1[10:0]});
242
        end
243
 
244
      #1 seed_wb1 = $random(seed_wb1);
245
      $display("seed_wb1[4:0] = 0x%0x", seed_wb1[4:0]);
246
      repeat(seed_wb1[4:0])   @ (posedge wb_clk_o);
247
    end
248
  end
249
 
250
 
251
  begin
252
    for(kk=0; kk<100; kk=kk+1)
253
    begin
254
      if(seed_wb2[3:0]<4)
255
        begin
256
          $display("(%0t) m2 write to eth start  (Data = Addr = 0x%0x)", $time, {21'h1a0000, seed_wb2[10:0]}); //0xd0000xxx
257
          Wishbone2Write({21'h1a0000, seed_wb2[10:0]}, {21'h1a0000, seed_wb2[10:0]});
258
        end
259
      else
260
      if(seed_wb2[3:0]<=7 && seed_wb2[3:0]>=4)
261
        begin
262
          $display("(%0t) m2 read to eth start  (Addr = 0x%0x)", $time, {21'h1a0000, seed_wb2[10:0]});
263
          Wishbone2Read({21'h1a0000, seed_wb2[10:0]});
264
        end
265
      else
266
      if(seed_wb2[3:0]<=11 && seed_wb2[3:0]>=8)
267
        begin
268
          $display("(%0t) m2 write to memory start  (Data = Addr = 0x%0x)", $time, {21'h000040, seed_wb2[10:0]}); //0x00020xxx
269
          Wishbone2Write({21'h1a0000, seed_wb2[10:0]}, {21'h000040, seed_wb2[10:0]});
270
        end
271
      else
272
      if(seed_wb2[3:0]>=12)
273
        begin
274
          $display("(%0t) m2 read to memory start  (Addr = 0x%0x)", $time, {21'h000040, seed_wb2[10:0]});
275
          Wishbone2Read({21'h000040, seed_wb2[10:0]});
276
        end
277
 
278
      #1 seed_wb2 = $random(seed_wb2);
279
      $display("seed_wb2[4:0] = 0x%0x", seed_wb2[4:0]);
280
      repeat(seed_wb2[4:0])   @ (posedge wb_clk_o);
281
    end
282
  end
283
 
284
 
285
 
286
 
287
  join
288
 
289
  #10000 $stop;
290
end
291
 
292
 
293
 
294
 
295
 
296
 
297
 
298
task Wishbone1Write;
299
  input [31:0] Data;
300
  input [31:0] Address;
301
  integer ii;
302
 
303
  begin
304
    wait (~Wishbone1Busy);
305
    Wishbone1Busy = 1;
306
    @ (posedge wb_clk_o);
307
    #1;
308
    m1_wb_adr_o = Address;
309
    m1_wb_dat_o = Data;
310
    m1_wb_we_o  = 1'b1;
311
    m1_wb_cyc_o = 1'b1;
312
    m1_wb_stb_o = 1'b1;
313
    m1_wb_sel_o = 4'hf;
314
 
315
    wait(m1_wb_ack_i | m1_wb_err_i);   // waiting for acknowledge response
316
 
317
    // Writing information about the access to the screen
318
    @ (posedge wb_clk_o);
319
    if(m1_wb_ack_i)
320
      $display("(%0t) Master1 write cycle finished ok(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
321
    else
322
      $display("(%0t) Master1 write cycle finished with error(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
323
 
324
    #1;
325
    m1_wb_adr_o = 32'hx;
326
    m1_wb_dat_o = 32'hx;
327
    m1_wb_we_o  = 1'bx;
328
    m1_wb_cyc_o = 1'b0;
329
    m1_wb_stb_o = 1'b0;
330
    m1_wb_sel_o = 4'hx;
331
    #5 Wishbone1Busy = 0;
332
  end
333
endtask
334
 
335
 
336
task Wishbone1Read;
337
  input [31:0] Address;
338
  reg   [31:0] Data;
339
  integer ii;
340
 
341
  begin
342
    wait (~Wishbone1Busy);
343
    Wishbone1Busy = 1;
344
    @ (posedge wb_clk_o);
345
    #1;
346
    m1_wb_adr_o = Address;
347
    m1_wb_we_o  = 1'b0;
348
    m1_wb_cyc_o = 1'b1;
349
    m1_wb_stb_o = 1'b1;
350
    m1_wb_sel_o = 4'hf;
351
 
352
    wait(m1_wb_ack_i | m1_wb_err_i);   // waiting for acknowledge response
353
    Data = m1_wb_dat_i;
354
 
355
    // Writing information about the access to the screen
356
    @ (posedge wb_clk_o);
357
    if(m1_wb_ack_i)
358
      $display("(%0t) Master1 read cycle finished ok(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
359
    else
360
      $display("(%0t) Master1 read cycle finished with error(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
361
 
362
    #1;
363
    m1_wb_adr_o = 32'hx;
364
    m1_wb_dat_o = 32'hx;
365
    m1_wb_we_o  = 1'bx;
366
    m1_wb_cyc_o = 1'b0;
367
    m1_wb_stb_o = 1'b0;
368
    m1_wb_sel_o = 4'hx;
369
    #5 Wishbone1Busy = 0;
370
  end
371
endtask
372
 
373
 
374
 
375
task Wishbone2Write;
376
  input [31:0] Data;
377
  input [31:0] Address;
378
  integer ii;
379
 
380
  begin
381
    wait (~Wishbone2Busy);
382
    Wishbone2Busy = 1;
383
    @ (posedge wb_clk_o);
384
    #1;
385
    m2_wb_adr_o = Address;
386
    m2_wb_dat_o = Data;
387
    m2_wb_we_o  = 1'b1;
388
    m2_wb_cyc_o = 1'b1;
389
    m2_wb_stb_o = 1'b1;
390
    m2_wb_sel_o = 4'hf;
391
 
392
    wait(m2_wb_ack_i | m2_wb_err_i);   // waiting for acknowledge response
393
 
394
    // Writing information about the access to the screen
395
    @ (posedge wb_clk_o);
396
    if(m2_wb_ack_i)
397
      $display("(%0t) Master2 write cycle finished ok(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
398
    else
399
      $display("(%0t) Master2 write cycle finished with error(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
400
 
401
    #1;
402
    m2_wb_adr_o = 32'hx;
403
    m2_wb_dat_o = 32'hx;
404
    m2_wb_we_o  = 1'bx;
405
    m2_wb_cyc_o = 1'b0;
406
    m2_wb_stb_o = 1'b0;
407
    m2_wb_sel_o = 4'hx;
408
    #5 Wishbone2Busy = 0;
409
  end
410
endtask
411
 
412
 
413
task Wishbone2Read;
414
  input [31:0] Address;
415
  reg   [31:0] Data;
416
  integer ii;
417
 
418
  begin
419
    wait (~Wishbone2Busy);
420
    Wishbone2Busy = 1;
421
    @ (posedge wb_clk_o);
422
    #1;
423
    m2_wb_adr_o = Address;
424
    m2_wb_we_o  = 1'b0;
425
    m2_wb_cyc_o = 1'b1;
426
    m2_wb_stb_o = 1'b1;
427
    m2_wb_sel_o = 4'hf;
428
 
429
    wait(m2_wb_ack_i | m2_wb_err_i);   // waiting for acknowledge response
430
    Data = m2_wb_dat_i;
431
 
432
    // Writing information about the access to the screen
433
    @ (posedge wb_clk_o);
434
    if(m2_wb_ack_i)
435
      $display("(%0t) Master2 read cycle finished ok(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
436
    else
437
      $display("(%0t) Master2 read cycle finished with error(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
438
 
439
    #1;
440
    m2_wb_adr_o = 32'hx;
441
    m2_wb_dat_o = 32'hx;
442
    m2_wb_we_o  = 1'bx;
443
    m2_wb_cyc_o = 1'b0;
444
    m2_wb_stb_o = 1'b0;
445
    m2_wb_sel_o = 4'hx;
446
    #5 Wishbone2Busy = 0;
447
  end
448
endtask
449
 
450
 
451
 
452
 
453
 
454
 
455
 
456
 
457
integer seed_ack_s1, seed_ack_s2;
458
integer cnt_s1, cnt_s2;
459
initial
460
begin
461
  seed_ack_s1 = 1;
462
  cnt_s1      = 1;
463
  seed_ack_s2 = 2;
464
  cnt_s2      = 32'h88888888;
465
end
466
 
467
// Response from slave 1
468
always @ (posedge wb_clk_o or posedge wb_rst_o)
469
begin
470
  #1 seed_ack_s1 = $random(seed_ack_s1);
471
 
472
  wait(s1_wb_cyc_i & s1_wb_stb_i);
473
 
474
  s1_wb_dat_o = cnt_s1;
475
  repeat(seed_ack_s1[3:0])   @ (posedge wb_clk_o);
476
 
477
  #Tp s1_wb_ack_o = 1'b1;
478
 
479
  if(~s1_wb_we_i)
480
    cnt_s1=cnt_s1+1;
481
 
482
  @ (posedge wb_clk_o);
483
  #Tp s1_wb_ack_o = 1'b0;
484
end
485
 
486
// Response from slave 2
487
always @ (posedge wb_clk_o or posedge wb_rst_o)
488
begin
489
  #1 seed_ack_s2 = $random(seed_ack_s2);
490
 
491
  wait(s2_wb_cyc_i & s2_wb_stb_i);
492
 
493
  s2_wb_dat_o = cnt_s2;
494
  repeat(seed_ack_s2[3:0])   @ (posedge wb_clk_o);
495
 
496
  #Tp s2_wb_ack_o = 1'b1;
497
 
498
  if(~s1_wb_we_i)
499
    cnt_s2=cnt_s2+1;
500
 
501
  @ (posedge wb_clk_o);
502
  #Tp s2_wb_ack_o = 1'b0;
503
end
504
 
505
endmodule
506
 

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