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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  tb_eth_defines.v                                            ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001, 2002 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2002/07/25 17:19:06  mohor
// Define ETH_MIIMODER_RST corrected to 0x00000400.
//
// Revision 1.3  2002/07/19 13:57:53  mohor
// Testing environment also includes traffic cop, memory interface and host
// interface.
//
// Revision 1.2  2002/05/03 10:22:17  mohor
// TX_BUF_BASE changed.
//
// Revision 1.1  2002/03/19 12:53:54  mohor
// Some defines that are used in testbench only were moved to tb_eth_defines.v
// file.
//
//
//
//
 
 
//`define EXTERNAL_DMA                  // Using DMA
 
`define MULTICAST_XFR          0
`define UNICAST_XFR            1
`define BROADCAST_XFR          2
`define UNICAST_WRONG_XFR      3
 
`define ETH_BASE              32'hd0000000
`define ETH_WIDTH             32'h800
`define MEMORY_BASE           32'h2000
`define MEMORY_WIDTH          32'h10000
`define TX_BUF_BASE           `MEMORY_BASE
`define RX_BUF_BASE           `MEMORY_BASE + 32'h8000
`define TX_BD_BASE            `ETH_BASE + 32'h00000400
`define RX_BD_BASE            `ETH_BASE + 32'h00000600
 
`define M1_ADDRESSED_S1 ( (m1_wb_adr_i >= `ETH_BASE)    & (m1_wb_adr_i < (`ETH_BASE    + `ETH_WIDTH   )) )
`define M1_ADDRESSED_S2 ( (m1_wb_adr_i >= `MEMORY_BASE) & (m1_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) )
`define M2_ADDRESSED_S1 ( (m2_wb_adr_i >= `ETH_BASE)    & (m2_wb_adr_i < (`ETH_BASE    + `ETH_WIDTH   )) )
`define M2_ADDRESSED_S2 ( (m2_wb_adr_i >= `MEMORY_BASE) & (m2_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) )
 
 
 
/* Tx BD */
`define ETH_TX_BD_READY    32'h8000 /* Tx BD Ready */
`define ETH_TX_BD_IRQ      32'h4000 /* Tx BD IRQ Enable */
`define ETH_TX_BD_WRAP     32'h2000 /* Tx BD Wrap (last BD) */
`define ETH_TX_BD_PAD      32'h1000 /* Tx BD Pad Enable */
`define ETH_TX_BD_CRC      32'h0800 /* Tx BD CRC Enable */
 
`define ETH_TX_BD_UNDERRUN 32'h0100 /* Tx BD Underrun Status */
`define ETH_TX_BD_RETRY    32'h00F0 /* Tx BD Retry Status */
`define ETH_TX_BD_RETLIM   32'h0008 /* Tx BD Retransmission Limit Status */
`define ETH_TX_BD_LATECOL  32'h0004 /* Tx BD Late Collision Status */
`define ETH_TX_BD_DEFER    32'h0002 /* Tx BD Defer Status */
`define ETH_TX_BD_CARRIER  32'h0001 /* Tx BD Carrier Sense Lost Status */
 
/* Rx BD */
`define ETH_RX_BD_EMPTY    32'h8000 /* Rx BD Empty */
`define ETH_RX_BD_IRQ      32'h4000 /* Rx BD IRQ Enable */
`define ETH_RX_BD_WRAP     32'h2000 /* Rx BD Wrap (last BD) */
 
`define ETH_RX_BD_MISS     32'h0080 /* Rx BD Miss Status */
`define ETH_RX_BD_OVERRUN  32'h0040 /* Rx BD Overrun Status */
`define ETH_RX_BD_INVSIMB  32'h0020 /* Rx BD Invalid Symbol Status */
`define ETH_RX_BD_DRIBBLE  32'h0010 /* Rx BD Dribble Nibble Status */
`define ETH_RX_BD_TOOLONG  32'h0008 /* Rx BD Too Long Status */
`define ETH_RX_BD_SHORT    32'h0004 /* Rx BD Too Short Frame Status */
`define ETH_RX_BD_CRCERR   32'h0002 /* Rx BD CRC Error Status */
`define ETH_RX_BD_LATECOL  32'h0001 /* Rx BD Late Collision Status */
 
 
 
/* Register space */
`define ETH_MODER      `ETH_BASE + 32'h00       /* Mode Register */
`define ETH_INT        `ETH_BASE + 32'h04       /* Interrupt Source Register */
`define ETH_INT_MASK   `ETH_BASE + 32'h08 /* Interrupt Mask Register */
`define ETH_IPGT       `ETH_BASE + 32'h0C /* Back to Bak Inter Packet Gap Register */
`define ETH_IPGR1      `ETH_BASE + 32'h10 /* Non Back to Back Inter Packet Gap Register 1 */
`define ETH_IPGR2      `ETH_BASE + 32'h14 /* Non Back to Back Inter Packet Gap Register 2 */
`define ETH_PACKETLEN  `ETH_BASE + 32'h18 /* Packet Length Register (min. and max.) */
`define ETH_COLLCONF   `ETH_BASE + 32'h1C /* Collision and Retry Configuration Register */
`define ETH_RX_BD_NUM  `ETH_BASE + 32'h20 /* Receive Buffer Descriptor Number Register */
`define ETH_CTRLMODER  `ETH_BASE + 32'h24 /* Control Module Mode Register */
`define ETH_MIIMODER   `ETH_BASE + 32'h28 /* MII Mode Register */
`define ETH_MIICOMMAND `ETH_BASE + 32'h2C /* MII Command Register */
`define ETH_MIIADDRESS `ETH_BASE + 32'h30 /* MII Address Register */
`define ETH_MIITX_DATA `ETH_BASE + 32'h34 /* MII Transmit Data Register */
`define ETH_MIIRX_DATA `ETH_BASE + 32'h38 /* MII Receive Data Register */
`define ETH_MIISTATUS  `ETH_BASE + 32'h3C /* MII Status Register */
`define ETH_MAC_ADDR0  `ETH_BASE + 32'h40 /* MAC Individual Address Register 0 */
`define ETH_MAC_ADDR1  `ETH_BASE + 32'h44 /* MAC Individual Address Register 1 */
`define ETH_HASH_ADDR0 `ETH_BASE + 32'h48 /* Hash Register 0 */
`define ETH_HASH_ADDR1 `ETH_BASE + 32'h4C /* Hash Register 1 */
`define ETH_TX_CTRL    `ETH_BASE + 32'h50 /* Tx Control Register */
`define ETH_RX_CTRL    `ETH_BASE + 32'h54 /* Rx Control Register */
 
/* MODER Register */
`define ETH_MODER_RXEN     32'h00000001 /* Receive Enable  */
`define ETH_MODER_TXEN     32'h00000002 /* Transmit Enable */
`define ETH_MODER_NOPRE    32'h00000004 /* No Preamble  */
`define ETH_MODER_BRO      32'h00000008 /* Reject Broadcast */
`define ETH_MODER_IAM      32'h00000010 /* Use Individual Hash */
`define ETH_MODER_PRO      32'h00000020 /* Promiscuous (receive all) */
`define ETH_MODER_IFG      32'h00000040 /* Min. IFG not required */
`define ETH_MODER_LOOPBCK  32'h00000080 /* Loop Back */
`define ETH_MODER_NOBCKOF  32'h00000100 /* No Backoff */
`define ETH_MODER_EXDFREN  32'h00000200 /* Excess Defer */
`define ETH_MODER_FULLD    32'h00000400 /* Full Duplex */
`define ETH_MODER_RST      32'h00000800 /* Reset MAC */
`define ETH_MODER_DLYCRCEN 32'h00001000 /* Delayed CRC Enable */
`define ETH_MODER_CRCEN    32'h00002000 /* CRC Enable */
`define ETH_MODER_HUGEN    32'h00004000 /* Huge Enable */
`define ETH_MODER_PAD      32'h00008000 /* Pad Enable */
`define ETH_MODER_RECSMALL 32'h00010000 /* Receive Small */
 
/* Interrupt Source Register */
`define ETH_INT_TXB        32'h00000001 /* Transmit Buffer IRQ */
`define ETH_INT_TXE        32'h00000002 /* Transmit Error IRQ */
`define ETH_INT_RXF        32'h00000004 /* Receive Frame IRQ */
`define ETH_INT_RXE        32'h00000008 /* Receive Error IRQ */
`define ETH_INT_BUSY       32'h00000010 /* Busy IRQ */
`define ETH_INT_TXC        32'h00000020 /* Transmit Control Frame IRQ */
`define ETH_INT_RXC        32'h00000040 /* Received Control Frame IRQ */
 
/* Interrupt Mask Register */
`define ETH_INT_MASK_TXB   32'h00000001 /* Transmit Buffer IRQ Mask */
`define ETH_INT_MASK_TXE   32'h00000002 /* Transmit Error IRQ Mask */
`define ETH_INT_MASK_RXF   32'h00000004 /* Receive Frame IRQ Mask */
`define ETH_INT_MASK_RXE   32'h00000008 /* Receive Error IRQ Mask */
`define ETH_INT_MASK_BUSY  32'h00000010 /* Busy IRQ Mask */
`define ETH_INT_MASK_TXC   32'h00000020 /* Transmit Control Frame IRQ Mask */
`define ETH_INT_MASK_RXC   32'h00000040 /* Received Control Frame IRQ Mask */
 
/* Control Module Mode Register */
`define ETH_CTRLMODER_PASSALL 32'h00000001 /* Pass Control Frames */
`define ETH_CTRLMODER_RXFLOW  32'h00000002 /* Receive Control Flow Enable */
`define ETH_CTRLMODER_TXFLOW  32'h00000004 /* Transmit Control Flow Enable */
 
/* MII Mode Register */
`define ETH_MIIMODER_CLKDIV   32'h000000FF /* Clock Divider */
`define ETH_MIIMODER_NOPRE    32'h00000100 /* No Preamble */
`define ETH_MIIMODER_RST      32'h00000400 /* MIIM Reset */
 
/* MII Command Register */
`define ETH_MIICOMMAND_SCANSTAT  32'h00000001 /* Scan Status */
`define ETH_MIICOMMAND_RSTAT     32'h00000002 /* Read Status */
`define ETH_MIICOMMAND_WCTRLDATA 32'h00000004 /* Write Control Data */
 
/* MII Address Register */
`define ETH_MIIADDRESS_FIAD 32'h0000001F /* PHY Address */
`define ETH_MIIADDRESS_RGAD 32'h00001F00 /* RGAD Address */
 
/* MII Status Register */
`define ETH_MIISTATUS_LINKFAIL 32'h00000001 /* Link Fail */
`define ETH_MIISTATUS_BUSY     32'h00000002 /* MII Busy */
`define ETH_MIISTATUS_NVALID   32'h00000004 /* Data in MII Status Register is invalid */

Line No.	Rev	Author	Line
1	92	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// tb_eth_defines.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects/ethmac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16	116	mohor	`//// Copyright (C) 2001, 2002 Authors ////`
17	92	mohor	`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	155	mohor	`// Revision 1.4 2002/07/25 17:19:06 mohor`
45			`// Define ETH_MIIMODER_RST corrected to 0x00000400.`
46			`//`
47	124	mohor	`// Revision 1.3 2002/07/19 13:57:53 mohor`
48			`// Testing environment also includes traffic cop, memory interface and host`
49			`// interface.`
50			`//`
51	116	mohor	`// Revision 1.2 2002/05/03 10:22:17 mohor`
52			`// TX_BUF_BASE changed.`
53			`//`
54	107	mohor	`// Revision 1.1 2002/03/19 12:53:54 mohor`
55			`// Some defines that are used in testbench only were moved to tb_eth_defines.v`
56			`// file.`
57	92	mohor	`//`
58			`//`
59			`//`
60	107	mohor	`//`
61	92	mohor
62
63			//`define EXTERNAL_DMA // Using DMA
64
65			`define MULTICAST_XFR 0
66			`define UNICAST_XFR 1
67			`define BROADCAST_XFR 2
68	107	mohor	`define UNICAST_WRONG_XFR 3
69	92	mohor
70	116	mohor	`define ETH_BASE 32'hd0000000
71			`define ETH_WIDTH 32'h800
72			`define MEMORY_BASE 32'h2000
73			`define MEMORY_WIDTH 32'h10000
74	107	mohor	`define TX_BUF_BASE `MEMORY_BASE
75	92	mohor	`define RX_BUF_BASE `MEMORY_BASE + 32'h8000
76	116	mohor	`define TX_BD_BASE `ETH_BASE + 32'h00000400
77			`define RX_BD_BASE `ETH_BASE + 32'h00000600
78
79			`define M1_ADDRESSED_S1 ( (m1_wb_adr_i >= `ETH_BASE) & (m1_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) )
80			`define M1_ADDRESSED_S2 ( (m1_wb_adr_i >= `MEMORY_BASE) & (m1_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) )
81			`define M2_ADDRESSED_S1 ( (m2_wb_adr_i >= `ETH_BASE) & (m2_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) )
82			`define M2_ADDRESSED_S2 ( (m2_wb_adr_i >= `MEMORY_BASE) & (m2_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) )
83
84
85
86			`/* Tx BD */`
87			`define ETH_TX_BD_READY 32'h8000 /* Tx BD Ready */
88			`define ETH_TX_BD_IRQ 32'h4000 /* Tx BD IRQ Enable */
89			`define ETH_TX_BD_WRAP 32'h2000 /* Tx BD Wrap (last BD) */
90			`define ETH_TX_BD_PAD 32'h1000 /* Tx BD Pad Enable */
91			`define ETH_TX_BD_CRC 32'h0800 /* Tx BD CRC Enable */
92
93			`define ETH_TX_BD_UNDERRUN 32'h0100 /* Tx BD Underrun Status */
94			`define ETH_TX_BD_RETRY 32'h00F0 /* Tx BD Retry Status */
95			`define ETH_TX_BD_RETLIM 32'h0008 /* Tx BD Retransmission Limit Status */
96			`define ETH_TX_BD_LATECOL 32'h0004 /* Tx BD Late Collision Status */
97			`define ETH_TX_BD_DEFER 32'h0002 /* Tx BD Defer Status */
98			`define ETH_TX_BD_CARRIER 32'h0001 /* Tx BD Carrier Sense Lost Status */
99
100			`/* Rx BD */`
101			`define ETH_RX_BD_EMPTY 32'h8000 /* Rx BD Empty */
102			`define ETH_RX_BD_IRQ 32'h4000 /* Rx BD IRQ Enable */
103			`define ETH_RX_BD_WRAP 32'h2000 /* Rx BD Wrap (last BD) */
104
105			`define ETH_RX_BD_MISS 32'h0080 /* Rx BD Miss Status */
106			`define ETH_RX_BD_OVERRUN 32'h0040 /* Rx BD Overrun Status */
107			`define ETH_RX_BD_INVSIMB 32'h0020 /* Rx BD Invalid Symbol Status */
108			`define ETH_RX_BD_DRIBBLE 32'h0010 /* Rx BD Dribble Nibble Status */
109			`define ETH_RX_BD_TOOLONG 32'h0008 /* Rx BD Too Long Status */
110			`define ETH_RX_BD_SHORT 32'h0004 /* Rx BD Too Short Frame Status */
111			`define ETH_RX_BD_CRCERR 32'h0002 /* Rx BD CRC Error Status */
112			`define ETH_RX_BD_LATECOL 32'h0001 /* Rx BD Late Collision Status */
113
114
115
116			`/* Register space */`
117			`define ETH_MODER `ETH_BASE + 32'h00 /* Mode Register */
118			`define ETH_INT `ETH_BASE + 32'h04 /* Interrupt Source Register */
119			`define ETH_INT_MASK `ETH_BASE + 32'h08 /* Interrupt Mask Register */
120			`define ETH_IPGT `ETH_BASE + 32'h0C /* Back to Bak Inter Packet Gap Register */
121			`define ETH_IPGR1 `ETH_BASE + 32'h10 /* Non Back to Back Inter Packet Gap Register 1 */
122			`define ETH_IPGR2 `ETH_BASE + 32'h14 /* Non Back to Back Inter Packet Gap Register 2 */
123			`define ETH_PACKETLEN `ETH_BASE + 32'h18 /* Packet Length Register (min. and max.) */
124			`define ETH_COLLCONF `ETH_BASE + 32'h1C /* Collision and Retry Configuration Register */
125			`define ETH_RX_BD_NUM `ETH_BASE + 32'h20 /* Receive Buffer Descriptor Number Register */
126			`define ETH_CTRLMODER `ETH_BASE + 32'h24 /* Control Module Mode Register */
127			`define ETH_MIIMODER `ETH_BASE + 32'h28 /* MII Mode Register */
128			`define ETH_MIICOMMAND `ETH_BASE + 32'h2C /* MII Command Register */
129			`define ETH_MIIADDRESS `ETH_BASE + 32'h30 /* MII Address Register */
130			`define ETH_MIITX_DATA `ETH_BASE + 32'h34 /* MII Transmit Data Register */
131			`define ETH_MIIRX_DATA `ETH_BASE + 32'h38 /* MII Receive Data Register */
132			`define ETH_MIISTATUS `ETH_BASE + 32'h3C /* MII Status Register */
133			`define ETH_MAC_ADDR0 `ETH_BASE + 32'h40 /* MAC Individual Address Register 0 */
134			`define ETH_MAC_ADDR1 `ETH_BASE + 32'h44 /* MAC Individual Address Register 1 */
135			`define ETH_HASH_ADDR0 `ETH_BASE + 32'h48 /* Hash Register 0 */
136			`define ETH_HASH_ADDR1 `ETH_BASE + 32'h4C /* Hash Register 1 */
137	155	mohor	`define ETH_TX_CTRL `ETH_BASE + 32'h50 /* Tx Control Register */
138			`define ETH_RX_CTRL `ETH_BASE + 32'h54 /* Rx Control Register */
139	116	mohor
140			`/* MODER Register */`
141			`define ETH_MODER_RXEN 32'h00000001 /* Receive Enable */
142			`define ETH_MODER_TXEN 32'h00000002 /* Transmit Enable */
143			`define ETH_MODER_NOPRE 32'h00000004 /* No Preamble */
144			`define ETH_MODER_BRO 32'h00000008 /* Reject Broadcast */
145			`define ETH_MODER_IAM 32'h00000010 /* Use Individual Hash */
146			`define ETH_MODER_PRO 32'h00000020 /* Promiscuous (receive all) */
147			`define ETH_MODER_IFG 32'h00000040 /* Min. IFG not required */
148			`define ETH_MODER_LOOPBCK 32'h00000080 /* Loop Back */
149			`define ETH_MODER_NOBCKOF 32'h00000100 /* No Backoff */
150			`define ETH_MODER_EXDFREN 32'h00000200 /* Excess Defer */
151			`define ETH_MODER_FULLD 32'h00000400 /* Full Duplex */
152			`define ETH_MODER_RST 32'h00000800 /* Reset MAC */
153			`define ETH_MODER_DLYCRCEN 32'h00001000 /* Delayed CRC Enable */
154			`define ETH_MODER_CRCEN 32'h00002000 /* CRC Enable */
155			`define ETH_MODER_HUGEN 32'h00004000 /* Huge Enable */
156			`define ETH_MODER_PAD 32'h00008000 /* Pad Enable */
157			`define ETH_MODER_RECSMALL 32'h00010000 /* Receive Small */
158
159			`/* Interrupt Source Register */`
160			`define ETH_INT_TXB 32'h00000001 /* Transmit Buffer IRQ */
161			`define ETH_INT_TXE 32'h00000002 /* Transmit Error IRQ */
162			`define ETH_INT_RXF 32'h00000004 /* Receive Frame IRQ */
163			`define ETH_INT_RXE 32'h00000008 /* Receive Error IRQ */
164			`define ETH_INT_BUSY 32'h00000010 /* Busy IRQ */
165			`define ETH_INT_TXC 32'h00000020 /* Transmit Control Frame IRQ */
166			`define ETH_INT_RXC 32'h00000040 /* Received Control Frame IRQ */
167
168			`/* Interrupt Mask Register */`
169			`define ETH_INT_MASK_TXB 32'h00000001 /* Transmit Buffer IRQ Mask */
170			`define ETH_INT_MASK_TXE 32'h00000002 /* Transmit Error IRQ Mask */
171			`define ETH_INT_MASK_RXF 32'h00000004 /* Receive Frame IRQ Mask */
172			`define ETH_INT_MASK_RXE 32'h00000008 /* Receive Error IRQ Mask */
173			`define ETH_INT_MASK_BUSY 32'h00000010 /* Busy IRQ Mask */
174			`define ETH_INT_MASK_TXC 32'h00000020 /* Transmit Control Frame IRQ Mask */
175			`define ETH_INT_MASK_RXC 32'h00000040 /* Received Control Frame IRQ Mask */
176
177			`/* Control Module Mode Register */`
178			`define ETH_CTRLMODER_PASSALL 32'h00000001 /* Pass Control Frames */
179			`define ETH_CTRLMODER_RXFLOW 32'h00000002 /* Receive Control Flow Enable */
180			`define ETH_CTRLMODER_TXFLOW 32'h00000004 /* Transmit Control Flow Enable */
181
182			`/* MII Mode Register */`
183			`define ETH_MIIMODER_CLKDIV 32'h000000FF /* Clock Divider */
184			`define ETH_MIIMODER_NOPRE 32'h00000100 /* No Preamble */
185	124	mohor	`define ETH_MIIMODER_RST 32'h00000400 /* MIIM Reset */
186	116	mohor
187			`/* MII Command Register */`
188			`define ETH_MIICOMMAND_SCANSTAT 32'h00000001 /* Scan Status */
189			`define ETH_MIICOMMAND_RSTAT 32'h00000002 /* Read Status */
190			`define ETH_MIICOMMAND_WCTRLDATA 32'h00000004 /* Write Control Data */
191
192			`/* MII Address Register */`
193			`define ETH_MIIADDRESS_FIAD 32'h0000001F /* PHY Address */
194			`define ETH_MIIADDRESS_RGAD 32'h00001F00 /* RGAD Address */
195
196			`/* MII Status Register */`
197			`define ETH_MIISTATUS_LINKFAIL 32'h00000001 /* Link Fail */
198			`define ETH_MIISTATUS_BUSY 32'h00000002 /* MII Busy */
199			`define ETH_MIISTATUS_NVALID 32'h00000004 /* Data in MII Status Register is invalid */

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