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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_eth_top.v] - Blame information for rev 17

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1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  tb_eth_top.v                                                ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/cores/ethmac/                      ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001 Authors                                   ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 17 mohor
// Revision 1.1  2001/08/06 14:41:09  mohor
45
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
46
// Include files fixed to contain no path.
47
// File names and module names changed ta have a eth_ prologue in the name.
48
// File eth_timescale.v is used to define timescale
49
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
50
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
51
// and Mdo_OE. The bidirectional signal must be created on the top level. This
52
// is done due to the ASIC tools.
53
//
54 15 mohor
// Revision 1.1  2001/07/30 21:46:09  mohor
55
// Directory structure changed. Files checked and joind together.
56
//
57
//
58
//
59
//
60
//
61
 
62
 
63
 
64
`include "eth_defines.v"
65
`include "eth_timescale.v"
66
 
67
module tb_eth_top();
68
 
69
 
70
parameter Tp = 1;
71
 
72
 
73
reg           WB_CLK_I;
74
reg           WB_RST_I;
75
reg   [31:0]  WB_DAT_I;
76
 
77
reg   [31:0]  WB_ADR_I;
78
reg    [3:0]  WB_SEL_I;
79
reg           WB_WE_I;
80
reg           WB_CYC_I;
81
reg           WB_STB_I;
82
reg    [1:0]  WB_ACK_I;
83
 
84
wire  [31:0]  WB_DAT_O;
85
wire          WB_ACK_O;
86
wire          WB_ERR_O;
87
wire   [1:0]  WB_REQ_O;
88
wire   [1:0]  WB_ND_O;
89
wire          WB_RD_O;
90
 
91
reg           MTxClk;
92
wire   [3:0]  MTxD;
93
wire          MTxEn;
94
wire          MTxErr;
95
 
96
reg           MRxClk;
97
reg    [3:0]  MRxD;
98
reg           MRxDV;
99
reg           MRxErr;
100
reg           MColl;
101
reg           MCrs;
102
 
103
reg           Mdi_I;
104
wire          Mdo_O;
105
wire          Mdo_OE;
106
wire          Mdc_O;
107
 
108
 
109
 
110
reg GSR;
111
 
112
reg WishboneBusy;
113
reg StartTB;
114
reg [9:0] TxBDIndex;
115
reg [9:0] RxBDIndex;
116
 
117
 
118
 
119
// Connecting Ethernet top module
120
 
121
eth_top ethtop
122
(
123
  // WISHBONE common
124 17 mohor
  .wb_clk_i(WB_CLK_I), .wb_rst_i(WB_RST_I), .wb_dat_i(WB_DAT_I), .wb_dat_o(WB_DAT_O),
125 15 mohor
 
126
  // WISHBONE slave
127 17 mohor
        .wb_adr_i(WB_ADR_I), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I),   .wb_cyc_i(WB_CYC_I),
128
        .wb_stb_i(WB_STB_I), .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O), .wb_req_o(WB_REQ_O),
129
        .wb_ack_i(WB_ACK_I), .wb_nd_o(WB_ND_O),   .wb_rd_o(WB_RD_O),
130 15 mohor
 
131
  //TX
132 17 mohor
  .mtxclk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
133 15 mohor
 
134
  //RX
135 17 mohor
  .mrxclk_pad_i(MRxClk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
136
  .mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),
137 15 mohor
 
138
  // MIIM
139 17 mohor
  .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_pad_oe(Mdo_OE)
140 15 mohor
);
141
 
142
 
143
 
144
 
145
 
146
 
147
 
148
initial
149
begin
150
  WB_CLK_I  =  1'b0;
151
  WB_DAT_I  = 32'hx;
152
  WB_ADR_I  = 32'hx;
153
  WB_SEL_I  =  4'hx;
154
  WB_WE_I   =  1'bx;
155
  WB_CYC_I  =  1'b0;
156
  WB_STB_I  =  1'b0;
157
  WB_ACK_I  =  2'h0;
158
  MTxClk    =  1'b0;
159
  MRxClk    =  1'b0;
160
  MRxD      =  4'h0;
161
  MRxDV     =  1'b0;
162
  MRxErr    =  1'b0;
163
  MColl     =  1'b0;
164
  MCrs      =  1'b0;
165
  Mdi_I     =  1'b0;
166
 
167
  WishboneBusy = 1'b0;
168
  TxBDIndex = 10'h0;
169
  RxBDIndex = 10'h0;
170
end
171
 
172
 
173
// Reset pulse
174
initial
175
begin
176
  GSR           =  1'b0;
177
  WB_RST_I      =  1'b0;
178
  #100 WB_RST_I =  1'b1;
179
  GSR           =  1'b1;
180
  #100 WB_RST_I =  1'b0;
181
  GSR           =  1'b0;
182
  #100 StartTB  =  1'b1;
183
end
184
 
185
 
186
assign glbl.GSR = GSR;
187
 
188
 
189
 
190
// Generating WB_CLK_I clock
191
always
192
begin
193
//  forever #10 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 50.0 MHz    
194
  forever #15 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 33.3 MHz    
195
//  forever #18 WB_CLK_I = ~WB_CLK_I;  // 2*18 ns -> 27.7 MHz    
196
//  forever #100 WB_CLK_I = ~WB_CLK_I;
197
end
198
 
199
// Generating MTxClk clock
200
always
201
begin
202
  #3 forever #20 MTxClk = ~MTxClk;   // 2*20 ns -> 25 MHz
203
//  #3 forever #200 MTxClk = ~MTxClk;
204
end
205
 
206
// Generating MRxClk clock
207
always
208
begin
209
  #16 forever #20 MRxClk = ~MRxClk;   // 2*20 ns -> 25 MHz
210
//  #16 forever #250 MRxClk = ~MRxClk;
211
end
212
 
213
 
214
 
215
initial
216
begin
217
  wait(StartTB);  // Start of testbench
218
 
219
  WishboneWrite(32'h00000800, {`ETHERNET_SPACE, `REG_SPACE, 6'h0, `MODER_ADR<<2});    // r_Rst = 1
220
  WishboneWrite(32'h00000000, {`ETHERNET_SPACE, `REG_SPACE, 6'h0, `MODER_ADR<<2});    // r_Rst = 0
221
  WishboneWrite(32'h00000080, {`ETHERNET_SPACE, `REG_SPACE, 6'h0, `RX_BD_ADR_ADR<<2});// r_RxBDAddress = 0x80
222
  WishboneWrite(32'h0002A443, {`ETHERNET_SPACE, `REG_SPACE, 6'h0, `MODER_ADR<<2});    // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
223
  WishboneWrite(32'h00000004, {`ETHERNET_SPACE, `REG_SPACE, 6'h0, `CTRLMODER_ADR<<2});//r_TxFlow = 1
224
 
225
 
226
 
227
 
228
  SendPacket(16'h0015, 1'b0);
229
  SendPacket(16'h0043, 1'b1);   // Control frame
230
  SendPacket(16'h0025, 1'b0);
231
  SendPacket(16'h0045, 1'b0);
232
  SendPacket(16'h0025, 1'b0);
233
 
234
 
235
  ReceivePacket(16'h0012, 1'b1);    // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
236
  ReceivePacket(16'h0011, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
237
  ReceivePacket(16'h0016, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
238
  ReceivePacket(16'h0017, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
239
  ReceivePacket(16'h0018, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
240
 
241
 
242
  WishboneRead({`ETHERNET_SPACE, `REG_SPACE, 6'h0, `MODER_ADR<<2});   // Read from MODER register
243
 
244
  WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h0<<2)});       // Read from TxBD register
245
  WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h1<<2)});       // Read from TxBD register
246
  WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h2<<2)});       // Read from TxBD register
247
  WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h3<<2)});       // Read from TxBD register
248
  WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h4<<2)});       // Read from TxBD register
249
 
250
  WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h80<<2)});       // Read from RxBD register
251
  WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h81<<2)});       // Read from RxBD register
252
  WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h82<<2)});       // Read from RxBD register
253
  WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h83<<2)});       // Read from RxBD register
254
  WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h84<<2)});       // Read from RxBD register
255
 
256
  #10000 $stop;
257
end
258
 
259
 
260
 
261
 
262
 
263
 
264
 
265
task WishboneWrite;
266
  input [31:0] Data;
267
  input [31:0] Address;
268
  integer ii;
269
 
270
  begin
271
    wait (~WishboneBusy);
272
    WishboneBusy = 1;
273
    @ (posedge WB_CLK_I);
274
    #1;
275
    WB_ADR_I = Address;
276
    WB_DAT_I = Data;
277
    WB_WE_I  = 1'b1;
278
    WB_CYC_I = 1'b1;
279
    WB_STB_I = 1'b1;
280
    WB_SEL_I = 4'hf;
281
 
282
    for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1)   // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
283
    begin
284
      @ (posedge WB_CLK_I);
285
    end
286
 
287
    if(ii==20)
288
      begin
289
        $display("\nERROR: Task WishboneWrite(Data=0x%0h, Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)",
290
          Data, Address, $time);
291
        #50 $stop;
292
      end
293
 
294
    @ (posedge WB_CLK_I);
295
    if(Address[31:16] == `ETHERNET_SPACE)
296
      if(Address[15:12] == `REG_SPACE)
297
        $write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address[9:2]);
298
      else
299
      if(Address[15:12] == `BD_SPACE)
300
        if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
301
          begin
302
            $write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address[9:2]);
303
            if(Data[13])
304
              $write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);
305
          end
306
        else
307
          $write("\nWrite to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address[9:2]);
308
      else
309
        $write("\nWB write      Data: 0x%x      Addr: 0x%0x", Data, Address);
310
    else
311
      $write("\nWARNING !!! WB write to non-ethernet space (Data: 0x%x, Addr: 0x%0x)", Data, Address);
312
    #1;
313
    WB_ADR_I = 32'hx;
314
    WB_DAT_I = 32'hx;
315
    WB_WE_I  = 1'bx;
316
    WB_CYC_I = 1'b0;
317
    WB_STB_I = 1'b0;
318
    WB_SEL_I = 4'hx;
319
    #5 WishboneBusy = 0;
320
  end
321
endtask
322
 
323
 
324
task WishboneRead;
325
  input [31:0] Address;
326
  reg   [31:0] Data;
327
  integer ii;
328
 
329
  begin
330
    wait (~WishboneBusy);
331
    WishboneBusy = 1;
332
    @ (posedge WB_CLK_I);
333
    #1;
334
    WB_ADR_I = Address;
335
    WB_WE_I  = 1'b0;
336
    WB_CYC_I = 1'b1;
337
    WB_STB_I = 1'b1;
338
    WB_SEL_I = 4'hf;
339
 
340
    for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1)   // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
341
    begin
342
      @ (posedge WB_CLK_I);
343
      Data = WB_DAT_O;
344
    end
345
 
346
    if(ii==20)
347
      begin
348
        $display("\nERROR: Task WishboneRead(Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)",
349
          Address, $time);
350
        #50 $stop;
351
      end
352
 
353
    @ (posedge WB_CLK_I);
354
    if(Address[31:16] == `ETHERNET_SPACE)
355
      if(Address[15:12] == `REG_SPACE)
356
        $write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address[9:2]);
357
      else
358
      if(Address[15:12] == `BD_SPACE)
359
        if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
360
          begin
361
            $write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address[9:2]);
362
          end
363
        else
364
          $write("\nRead from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address[9:2]);
365
      else
366
        $write("\nWB read      Data: 0x%x      Addr: 0x%0x", Data, Address);
367
    else
368
      $write("\nWARNING !!! WB read to non-ethernet space (Data: 0x%x, Addr: 0x%0x)", Data, Address);
369
    #1;
370
    WB_ADR_I = 32'hx;
371
    WB_WE_I  = 1'bx;
372
    WB_CYC_I = 1'b0;
373
    WB_STB_I = 1'b0;
374
    WB_SEL_I = 4'hx;
375
    #5 WishboneBusy = 0;
376
  end
377
endtask
378
 
379
 
380
 
381
 
382
task SendPacket;
383
  input [15:0]  Length;
384
  input         ControlFrame;
385
  reg           Wrap;
386
  reg [31:0]    TempAddr;
387
  reg [31:0]    TempData;
388
 
389
  begin
390
    if(TxBDIndex == 3)    // Only 4 buffer descriptors are used
391
      Wrap = 1'b1;
392
    else
393
      Wrap = 1'b0;
394
 
395
    TempAddr = {`ETHERNET_SPACE, `BD_SPACE, 2'h0, (TxBDIndex<<2)};
396
    TempData = {Length[15:0], 1'b1, Wrap, ControlFrame, 5'h0, TxBDIndex[7:0]};  // Ready and Wrap = 1
397
 
398
    #1;
399
    if(TxBDIndex == 3)    // Only 4 buffer descriptors are used
400
      TxBDIndex = 0;
401
    else
402
      TxBDIndex = TxBDIndex + 1;
403
 
404
    fork
405
      begin
406
        WishboneWrite(TempData, TempAddr); // Writing status to TxBD
407
      end
408
 
409
      begin
410
        if(~ControlFrame)
411
        WaitingForTxDMARequest(4'h1, Length); // Delay, DMALength
412
      end
413
    join
414
  end
415
endtask
416
 
417
 
418
 
419
task ReceivePacket;    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
420
  input [15:0] LengthRx;
421
  input        RxControlFrame;
422
  reg        WrapRx;
423
  reg [31:0] TempRxAddr;
424
  reg [31:0] TempRxData;
425
  reg abc;
426
  begin
427
    if(RxBDIndex == 3)    // Only 4 buffer descriptors are used
428
      WrapRx = 1'b1;
429
    else
430
      WrapRx = 1'b0;
431
 
432
    TempRxAddr = {`ETHERNET_SPACE, `BD_SPACE, 2'h0, ((tb_eth_top.ethtop.r_RxBDAddress + RxBDIndex)<<2)};
433
 
434
    TempRxData = {LengthRx[15:0], 1'b1, WrapRx, 6'h0, RxBDIndex[7:0]};  // Ready and WrapRx = 1 or 0
435
 
436
    #1;
437
    if(RxBDIndex == 3)    // Only 4 buffer descriptors are used
438
      RxBDIndex = 0;
439
    else
440
      RxBDIndex = RxBDIndex + 1;
441
 
442
    abc=1;
443
    WishboneWrite(TempRxData, TempRxAddr); // Writing status to RxBD
444
    abc=0;
445
    fork
446
      begin
447
        #200;
448
        if(RxControlFrame)
449
          GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.
450
        else
451
          GetDataOnMRxD(LengthRx); // LengthRx bytes is comming on MRxD[3:0] signals
452
      end
453
 
454
      begin
455
        if(RxControlFrame)
456
          WaitingForRxDMARequest(4'h1, 16'h40); // Delay, DMALength = 64 bytes.
457
        else
458
          WaitingForRxDMARequest(4'h1, LengthRx); // Delay, DMALength
459
      end
460
    join
461
  end
462
endtask
463
 
464
 
465
 
466
task WaitingForTxDMARequest;
467
  input [3:0] Delay;
468
  input [15:0] DMALength;
469
  integer pp;
470
  reg [7:0]a, b, c, d;
471
 
472
  for(pp=0; pp*4<DMALength; pp=pp+1)
473
  begin
474
    a = 4*pp[7:0]+3;
475
    b = 4*pp[7:0]+2;
476
    c = 4*pp[7:0]+1;
477
    d = 4*pp[7:0]  ;
478
    @ (posedge WB_REQ_O[0]);
479
    repeat(Delay) @(posedge WB_CLK_I);
480
 
481
    wait (~WishboneBusy);
482
    WishboneBusy = 1;
483
    #1;
484
    WB_DAT_I = {a, b, c, d};
485
    WB_ADR_I = {`ETHERNET_SPACE, `TX_DATA, pp[11:0]};
486
    $display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);
487
 
488
    WB_WE_I  = 1'b1;
489
    WB_CYC_I = 1'b1;
490
    WB_STB_I = 1'b1;
491
    WB_SEL_I = 4'hf;
492
    WB_ACK_I[0] = 1'b1;
493
 
494
    @ (posedge WB_CLK_I);
495
    #1;
496
    WB_ADR_I = 32'hx;
497
    WB_DAT_I = 32'hx;
498
    WB_WE_I  = 1'bx;
499
    WB_CYC_I = 1'b0;
500
    WB_STB_I = 1'b0;
501
    WB_SEL_I = 4'hx;
502
    WB_ACK_I[0] = 1'b0;
503
    #5 WishboneBusy = 0;
504
  end
505
endtask
506
 
507
 
508
task WaitingForRxDMARequest;
509
  input [3:0] Delay;
510
  input [15:0] DMALengthRx;
511
  integer rr;
512
 
513
  for(rr=0; rr*4<DMALengthRx; rr=rr+1)
514
  begin
515
    @ (posedge WB_REQ_O[1]);
516
    repeat(Delay) @(posedge WB_CLK_I);
517
 
518
    wait (~WishboneBusy);
519
    WishboneBusy = 1;
520
    #1;
521
    WB_ADR_I = {`ETHERNET_SPACE, `RX_DATA, rr[11:0]};
522
    $display("task WaitingForRxDMARequest: rr=%0d, WB_ADR_I=0x%0h, WB_DAT_O=0x%0h", rr, WB_ADR_I, WB_DAT_O);
523
 
524
    WB_WE_I  = 1'b1;
525
    WB_CYC_I = 1'b1;
526
    WB_STB_I = 1'b1;
527
    WB_SEL_I = 4'hf;
528
    WB_ACK_I[1] = 1'b1;
529
 
530
    @ (posedge WB_CLK_I);
531
    #1;
532
    WB_ADR_I = 32'hx;
533
    WB_WE_I  = 1'bx;
534
    WB_CYC_I = 1'b0;
535
    WB_STB_I = 1'b0;
536
    WB_SEL_I = 4'hx;
537
    WB_ACK_I[1] = 1'b0;
538
    #5 WishboneBusy = 0;
539
  end
540
endtask
541
 
542
 
543
 
544
task GetDataOnMRxD;
545
  input [15:0] Len;
546
  integer tt;
547
 
548
  begin
549
    @ (posedge MRxClk);
550
    MRxDV=1'b1;
551
 
552
    for(tt=0; tt<15; tt=tt+1)
553
    begin
554
      MRxD=4'h5;              // preamble
555
      @ (posedge MRxClk);
556
    end
557
    MRxD=4'hd;                // SFD
558
 
559
    for(tt=0; tt<Len; tt=tt+1)
560
    begin
561
      @ (posedge MRxClk);
562
      MRxD=tt[3:0];
563
      @ (posedge MRxClk);
564
      MRxD=tt[7:4];
565
    end
566
    @ (posedge MRxClk);
567
    MRxDV=1'b0;
568
  end
569
endtask
570
 
571
 
572
task GetControlDataOnMRxD;
573
  input [15:0] Timer;
574
  reg [127:0] Packet;
575
  reg [127:0] Data;
576
  reg [31:0] Crc;
577
  integer tt;
578
 
579
  begin
580
  Packet = 128'h10082C000010_deadbeef0013_8880_0010; // 0180c2000001 + 8808 + 0001
581
  Crc = 32'h6014fe08; // not a correct value
582
 
583
    @ (posedge MRxClk);
584
    MRxDV=1'b1;
585
 
586
    for(tt=0; tt<15; tt=tt+1)
587
    begin
588
      MRxD=4'h5;              // preamble
589
      @ (posedge MRxClk);
590
    end
591
    MRxD=4'hd;                // SFD
592
 
593
    for(tt=0; tt<32; tt=tt+1)
594
    begin
595
      Data = Packet << (tt*4);
596
      @ (posedge MRxClk);
597
      MRxD=Data[127:124];
598
    end
599
 
600
    for(tt=0; tt<2; tt=tt+1)    // timer
601
    begin
602
      Data[15:0] = Timer << (tt*8);
603
      @ (posedge MRxClk);
604
      MRxD=Data[11:8];
605
      @ (posedge MRxClk);
606
      MRxD=Data[15:12];
607
    end
608
 
609
    for(tt=0; tt<42; tt=tt+1)   // padding
610
    begin
611
      Data[7:0] = 8'h0;
612
      @ (posedge MRxClk);
613
      MRxD=Data[3:0];
614
      @ (posedge MRxClk);
615
      MRxD=Data[3:0];
616
    end
617
 
618
    for(tt=0; tt<4; tt=tt+1)    // crc
619
    begin
620
      Data[31:0] = Crc << (tt*8);
621
      @ (posedge MRxClk);
622
      MRxD=Data[27:24];
623
      @ (posedge MRxClk);
624
      MRxD=Data[31:28];
625
    end
626
 
627
 
628
 
629
    @ (posedge MRxClk);
630
    MRxDV=1'b0;
631
  end
632
endtask
633
 
634
 
635
 
636
endmodule

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