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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_eth_top.v] - Blame information for rev 19

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1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  tb_eth_top.v                                                ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/cores/ethmac/                      ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001 Authors                                   ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
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////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 19 mohor
// Revision 1.2  2001/08/15 14:04:30  mohor
45
// Signal names changed on the top level for easier pad insertion (ASIC).
46
//
47 17 mohor
// Revision 1.1  2001/08/06 14:41:09  mohor
48
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
49
// Include files fixed to contain no path.
50
// File names and module names changed ta have a eth_ prologue in the name.
51
// File eth_timescale.v is used to define timescale
52
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
53
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
54
// and Mdo_OE. The bidirectional signal must be created on the top level. This
55
// is done due to the ASIC tools.
56
//
57 15 mohor
// Revision 1.1  2001/07/30 21:46:09  mohor
58
// Directory structure changed. Files checked and joind together.
59
//
60
//
61
//
62
//
63
//
64
 
65
 
66
 
67
`include "eth_defines.v"
68
`include "eth_timescale.v"
69
 
70
module tb_eth_top();
71
 
72
 
73
parameter Tp = 1;
74
 
75
 
76
reg           WB_CLK_I;
77
reg           WB_RST_I;
78
reg   [31:0]  WB_DAT_I;
79
 
80
reg   [31:0]  WB_ADR_I;
81
reg    [3:0]  WB_SEL_I;
82
reg           WB_WE_I;
83
reg           WB_CYC_I;
84
reg           WB_STB_I;
85
reg    [1:0]  WB_ACK_I;
86
 
87
wire  [31:0]  WB_DAT_O;
88
wire          WB_ACK_O;
89
wire          WB_ERR_O;
90
wire   [1:0]  WB_REQ_O;
91
wire   [1:0]  WB_ND_O;
92
wire          WB_RD_O;
93
 
94
reg           MTxClk;
95
wire   [3:0]  MTxD;
96
wire          MTxEn;
97
wire          MTxErr;
98
 
99
reg           MRxClk;
100
reg    [3:0]  MRxD;
101
reg           MRxDV;
102
reg           MRxErr;
103
reg           MColl;
104
reg           MCrs;
105
 
106
reg           Mdi_I;
107
wire          Mdo_O;
108
wire          Mdo_OE;
109
wire          Mdc_O;
110
 
111
 
112
 
113
reg GSR;
114
 
115
reg WishboneBusy;
116
reg StartTB;
117
reg [9:0] TxBDIndex;
118
reg [9:0] RxBDIndex;
119
 
120
 
121
 
122
// Connecting Ethernet top module
123
 
124
eth_top ethtop
125
(
126
  // WISHBONE common
127 17 mohor
  .wb_clk_i(WB_CLK_I), .wb_rst_i(WB_RST_I), .wb_dat_i(WB_DAT_I), .wb_dat_o(WB_DAT_O),
128 15 mohor
 
129
  // WISHBONE slave
130 17 mohor
        .wb_adr_i(WB_ADR_I), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I),   .wb_cyc_i(WB_CYC_I),
131
        .wb_stb_i(WB_STB_I), .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O), .wb_req_o(WB_REQ_O),
132
        .wb_ack_i(WB_ACK_I), .wb_nd_o(WB_ND_O),   .wb_rd_o(WB_RD_O),
133 15 mohor
 
134
  //TX
135 19 mohor
  .mtx_clk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
136 15 mohor
 
137
  //RX
138 19 mohor
  .mrx_clk_pad_i(MRxClk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
139 17 mohor
  .mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),
140 15 mohor
 
141
  // MIIM
142 19 mohor
  .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoen_o(Mdo_OE)
143 15 mohor
);
144
 
145
 
146
 
147
 
148
 
149
 
150
 
151
initial
152
begin
153
  WB_CLK_I  =  1'b0;
154 19 mohor
  WB_DAT_I  = 32'h0;
155
  WB_ADR_I  = 32'h0;
156
  WB_SEL_I  =  4'h0;
157
  WB_WE_I   =  1'b0;
158 15 mohor
  WB_CYC_I  =  1'b0;
159
  WB_STB_I  =  1'b0;
160
  WB_ACK_I  =  2'h0;
161
  MTxClk    =  1'b0;
162
  MRxClk    =  1'b0;
163
  MRxD      =  4'h0;
164
  MRxDV     =  1'b0;
165
  MRxErr    =  1'b0;
166
  MColl     =  1'b0;
167
  MCrs      =  1'b0;
168
  Mdi_I     =  1'b0;
169
 
170
  WishboneBusy = 1'b0;
171
  TxBDIndex = 10'h0;
172
  RxBDIndex = 10'h0;
173
end
174
 
175
 
176
// Reset pulse
177
initial
178
begin
179 19 mohor
  GSR           =  1'b1;
180
  WB_RST_I      =  1'b1;
181 15 mohor
  #100 WB_RST_I =  1'b1;
182
  GSR           =  1'b1;
183
  #100 WB_RST_I =  1'b0;
184
  GSR           =  1'b0;
185
  #100 StartTB  =  1'b1;
186
end
187
 
188
 
189
assign glbl.GSR = GSR;
190
 
191
 
192
 
193
// Generating WB_CLK_I clock
194
always
195
begin
196 19 mohor
//  forever #5 WB_CLK_I = ~WB_CLK_I;  // 2*5 ns -> 100.0 MHz    
197 15 mohor
//  forever #10 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 50.0 MHz    
198
  forever #15 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 33.3 MHz    
199
//  forever #18 WB_CLK_I = ~WB_CLK_I;  // 2*18 ns -> 27.7 MHz    
200
//  forever #100 WB_CLK_I = ~WB_CLK_I;
201
end
202
 
203
// Generating MTxClk clock
204
always
205
begin
206
  #3 forever #20 MTxClk = ~MTxClk;   // 2*20 ns -> 25 MHz
207
//  #3 forever #200 MTxClk = ~MTxClk;
208
end
209
 
210
// Generating MRxClk clock
211
always
212
begin
213
  #16 forever #20 MRxClk = ~MRxClk;   // 2*20 ns -> 25 MHz
214
//  #16 forever #250 MRxClk = ~MRxClk;
215
end
216
 
217
 
218
 
219
initial
220
begin
221
  wait(StartTB);  // Start of testbench
222
 
223 19 mohor
  WishboneWrite(32'h00000800, {`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_MODER_ADR<<2});    // r_Rst = 1
224
  WishboneWrite(32'h00000000, {`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_MODER_ADR<<2});    // r_Rst = 0
225
  WishboneWrite(32'h00000080, {`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_RX_BD_ADR_ADR<<2});// r_RxBDAddress = 0x80
226
  WishboneWrite(32'h0002A443, {`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_MODER_ADR<<2});    // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
227
  WishboneWrite(32'h00000004, {`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_CTRLMODER_ADR<<2});//r_TxFlow = 1
228 15 mohor
 
229
 
230
 
231
 
232
  SendPacket(16'h0015, 1'b0);
233
  SendPacket(16'h0043, 1'b1);   // Control frame
234
  SendPacket(16'h0025, 1'b0);
235
  SendPacket(16'h0045, 1'b0);
236
  SendPacket(16'h0025, 1'b0);
237
 
238
 
239
  ReceivePacket(16'h0012, 1'b1);    // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
240
  ReceivePacket(16'h0011, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
241
  ReceivePacket(16'h0016, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
242
  ReceivePacket(16'h0017, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
243
  ReceivePacket(16'h0018, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
244
 
245
 
246 19 mohor
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_REG_SPACE, 6'h0, `ETH_MODER_ADR<<2});   // Read from MODER register
247 15 mohor
 
248 19 mohor
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h0<<2)});       // Read from TxBD register
249
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h1<<2)});       // Read from TxBD register
250
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h2<<2)});       // Read from TxBD register
251
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h3<<2)});       // Read from TxBD register
252
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h4<<2)});       // Read from TxBD register
253 15 mohor
 
254 19 mohor
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h80<<2)});       // Read from RxBD register
255
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h81<<2)});       // Read from RxBD register
256
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h82<<2)});       // Read from RxBD register
257
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h83<<2)});       // Read from RxBD register
258
  WishboneRead({`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (10'h84<<2)});       // Read from RxBD register
259 15 mohor
 
260
  #10000 $stop;
261
end
262
 
263
 
264
 
265
 
266
 
267
 
268
 
269
task WishboneWrite;
270
  input [31:0] Data;
271
  input [31:0] Address;
272
  integer ii;
273
 
274
  begin
275
    wait (~WishboneBusy);
276
    WishboneBusy = 1;
277
    @ (posedge WB_CLK_I);
278
    #1;
279
    WB_ADR_I = Address;
280
    WB_DAT_I = Data;
281
    WB_WE_I  = 1'b1;
282
    WB_CYC_I = 1'b1;
283
    WB_STB_I = 1'b1;
284
    WB_SEL_I = 4'hf;
285
 
286 19 mohor
//    for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1)   // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
287
//    begin
288
//      @ (posedge WB_CLK_I);
289
//    end
290 15 mohor
 
291 19 mohor
//    if(ii==20)
292
//      begin
293
//        $display("\nERROR: Task WishboneWrite(Data=0x%0h, Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)", 
294
//          Data, Address, $time);
295
//        #50 $stop;
296
//      end
297 15 mohor
 
298 19 mohor
    wait(WB_ACK_O);   // waiting for acknowledge response
299
 
300
    // Writing information about the access to the screen
301 15 mohor
    @ (posedge WB_CLK_I);
302 19 mohor
    if(Address[31:16] == `ETH_ETHERNET_SPACE)
303
      if(Address[15:12] == `ETH_REG_SPACE)
304 15 mohor
        $write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address[9:2]);
305
      else
306 19 mohor
      if(Address[15:12] == `ETH_BD_SPACE)
307 15 mohor
        if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
308
          begin
309
            $write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address[9:2]);
310
            if(Data[13])
311
              $write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);
312
          end
313
        else
314
          $write("\nWrite to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address[9:2]);
315
      else
316
        $write("\nWB write      Data: 0x%x      Addr: 0x%0x", Data, Address);
317
    else
318
      $write("\nWARNING !!! WB write to non-ethernet space (Data: 0x%x, Addr: 0x%0x)", Data, Address);
319
    #1;
320
    WB_ADR_I = 32'hx;
321
    WB_DAT_I = 32'hx;
322
    WB_WE_I  = 1'bx;
323
    WB_CYC_I = 1'b0;
324
    WB_STB_I = 1'b0;
325
    WB_SEL_I = 4'hx;
326
    #5 WishboneBusy = 0;
327
  end
328
endtask
329
 
330
 
331
task WishboneRead;
332
  input [31:0] Address;
333
  reg   [31:0] Data;
334
  integer ii;
335
 
336
  begin
337
    wait (~WishboneBusy);
338
    WishboneBusy = 1;
339
    @ (posedge WB_CLK_I);
340
    #1;
341
    WB_ADR_I = Address;
342
    WB_WE_I  = 1'b0;
343
    WB_CYC_I = 1'b1;
344
    WB_STB_I = 1'b1;
345
    WB_SEL_I = 4'hf;
346
 
347
    for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1)   // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
348
    begin
349
      @ (posedge WB_CLK_I);
350
      Data = WB_DAT_O;
351
    end
352
 
353
    if(ii==20)
354
      begin
355
        $display("\nERROR: Task WishboneRead(Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)",
356
          Address, $time);
357
        #50 $stop;
358
      end
359
 
360
    @ (posedge WB_CLK_I);
361 19 mohor
    if(Address[31:16] == `ETH_ETHERNET_SPACE)
362
      if(Address[15:12] == `ETH_REG_SPACE)
363 15 mohor
        $write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address[9:2]);
364
      else
365 19 mohor
      if(Address[15:12] == `ETH_BD_SPACE)
366 15 mohor
        if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
367
          begin
368
            $write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address[9:2]);
369
          end
370
        else
371
          $write("\nRead from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address[9:2]);
372
      else
373
        $write("\nWB read      Data: 0x%x      Addr: 0x%0x", Data, Address);
374
    else
375
      $write("\nWARNING !!! WB read to non-ethernet space (Data: 0x%x, Addr: 0x%0x)", Data, Address);
376
    #1;
377
    WB_ADR_I = 32'hx;
378
    WB_WE_I  = 1'bx;
379
    WB_CYC_I = 1'b0;
380
    WB_STB_I = 1'b0;
381
    WB_SEL_I = 4'hx;
382
    #5 WishboneBusy = 0;
383
  end
384
endtask
385
 
386
 
387
 
388
 
389
task SendPacket;
390
  input [15:0]  Length;
391
  input         ControlFrame;
392
  reg           Wrap;
393
  reg [31:0]    TempAddr;
394
  reg [31:0]    TempData;
395
 
396
  begin
397
    if(TxBDIndex == 3)    // Only 4 buffer descriptors are used
398
      Wrap = 1'b1;
399
    else
400
      Wrap = 1'b0;
401
 
402 19 mohor
    TempAddr = {`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, (TxBDIndex<<2)};
403 15 mohor
    TempData = {Length[15:0], 1'b1, Wrap, ControlFrame, 5'h0, TxBDIndex[7:0]};  // Ready and Wrap = 1
404
 
405
    #1;
406
    if(TxBDIndex == 3)    // Only 4 buffer descriptors are used
407
      TxBDIndex = 0;
408
    else
409
      TxBDIndex = TxBDIndex + 1;
410
 
411
    fork
412
      begin
413
        WishboneWrite(TempData, TempAddr); // Writing status to TxBD
414
      end
415
 
416
      begin
417
        if(~ControlFrame)
418
        WaitingForTxDMARequest(4'h1, Length); // Delay, DMALength
419
      end
420
    join
421
  end
422
endtask
423
 
424
 
425
 
426
task ReceivePacket;    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
427
  input [15:0] LengthRx;
428
  input        RxControlFrame;
429
  reg        WrapRx;
430
  reg [31:0] TempRxAddr;
431
  reg [31:0] TempRxData;
432
  reg abc;
433
  begin
434
    if(RxBDIndex == 3)    // Only 4 buffer descriptors are used
435
      WrapRx = 1'b1;
436
    else
437
      WrapRx = 1'b0;
438
 
439 19 mohor
    TempRxAddr = {`ETH_ETHERNET_SPACE, `ETH_BD_SPACE, 2'h0, ((tb_eth_top.ethtop.r_RxBDAddress + RxBDIndex)<<2)};
440 15 mohor
 
441
    TempRxData = {LengthRx[15:0], 1'b1, WrapRx, 6'h0, RxBDIndex[7:0]};  // Ready and WrapRx = 1 or 0
442
 
443
    #1;
444
    if(RxBDIndex == 3)    // Only 4 buffer descriptors are used
445
      RxBDIndex = 0;
446
    else
447
      RxBDIndex = RxBDIndex + 1;
448
 
449
    abc=1;
450
    WishboneWrite(TempRxData, TempRxAddr); // Writing status to RxBD
451
    abc=0;
452
    fork
453
      begin
454
        #200;
455
        if(RxControlFrame)
456
          GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.
457
        else
458
          GetDataOnMRxD(LengthRx); // LengthRx bytes is comming on MRxD[3:0] signals
459
      end
460
 
461
      begin
462
        if(RxControlFrame)
463
          WaitingForRxDMARequest(4'h1, 16'h40); // Delay, DMALength = 64 bytes.
464
        else
465
          WaitingForRxDMARequest(4'h1, LengthRx); // Delay, DMALength
466
      end
467
    join
468
  end
469
endtask
470
 
471
 
472
 
473
task WaitingForTxDMARequest;
474
  input [3:0] Delay;
475
  input [15:0] DMALength;
476
  integer pp;
477
  reg [7:0]a, b, c, d;
478
 
479
  for(pp=0; pp*4<DMALength; pp=pp+1)
480
  begin
481
    a = 4*pp[7:0]+3;
482
    b = 4*pp[7:0]+2;
483
    c = 4*pp[7:0]+1;
484
    d = 4*pp[7:0]  ;
485
    @ (posedge WB_REQ_O[0]);
486
    repeat(Delay) @(posedge WB_CLK_I);
487
 
488
    wait (~WishboneBusy);
489
    WishboneBusy = 1;
490
    #1;
491
    WB_DAT_I = {a, b, c, d};
492 19 mohor
    WB_ADR_I = {`ETH_ETHERNET_SPACE, `ETH_TX_DATA, pp[11:0]};
493 15 mohor
    $display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);
494
 
495
    WB_WE_I  = 1'b1;
496
    WB_CYC_I = 1'b1;
497
    WB_STB_I = 1'b1;
498
    WB_SEL_I = 4'hf;
499
    WB_ACK_I[0] = 1'b1;
500
 
501
    @ (posedge WB_CLK_I);
502
    #1;
503
    WB_ADR_I = 32'hx;
504
    WB_DAT_I = 32'hx;
505
    WB_WE_I  = 1'bx;
506
    WB_CYC_I = 1'b0;
507
    WB_STB_I = 1'b0;
508
    WB_SEL_I = 4'hx;
509
    WB_ACK_I[0] = 1'b0;
510
    #5 WishboneBusy = 0;
511
  end
512
endtask
513
 
514
 
515
task WaitingForRxDMARequest;
516
  input [3:0] Delay;
517
  input [15:0] DMALengthRx;
518
  integer rr;
519
 
520
  for(rr=0; rr*4<DMALengthRx; rr=rr+1)
521
  begin
522
    @ (posedge WB_REQ_O[1]);
523
    repeat(Delay) @(posedge WB_CLK_I);
524
 
525
    wait (~WishboneBusy);
526
    WishboneBusy = 1;
527
    #1;
528 19 mohor
    WB_ADR_I = {`ETH_ETHERNET_SPACE, `ETH_RX_DATA, rr[11:0]};
529 15 mohor
    $display("task WaitingForRxDMARequest: rr=%0d, WB_ADR_I=0x%0h, WB_DAT_O=0x%0h", rr, WB_ADR_I, WB_DAT_O);
530
 
531
    WB_WE_I  = 1'b1;
532
    WB_CYC_I = 1'b1;
533
    WB_STB_I = 1'b1;
534
    WB_SEL_I = 4'hf;
535
    WB_ACK_I[1] = 1'b1;
536
 
537
    @ (posedge WB_CLK_I);
538
    #1;
539
    WB_ADR_I = 32'hx;
540
    WB_WE_I  = 1'bx;
541
    WB_CYC_I = 1'b0;
542
    WB_STB_I = 1'b0;
543
    WB_SEL_I = 4'hx;
544
    WB_ACK_I[1] = 1'b0;
545
    #5 WishboneBusy = 0;
546
  end
547
endtask
548
 
549
 
550
 
551
task GetDataOnMRxD;
552
  input [15:0] Len;
553
  integer tt;
554
 
555
  begin
556
    @ (posedge MRxClk);
557
    MRxDV=1'b1;
558
 
559
    for(tt=0; tt<15; tt=tt+1)
560
    begin
561
      MRxD=4'h5;              // preamble
562
      @ (posedge MRxClk);
563
    end
564
    MRxD=4'hd;                // SFD
565
 
566
    for(tt=0; tt<Len; tt=tt+1)
567
    begin
568
      @ (posedge MRxClk);
569
      MRxD=tt[3:0];
570
      @ (posedge MRxClk);
571
      MRxD=tt[7:4];
572
    end
573
    @ (posedge MRxClk);
574
    MRxDV=1'b0;
575
  end
576
endtask
577
 
578
 
579
task GetControlDataOnMRxD;
580
  input [15:0] Timer;
581
  reg [127:0] Packet;
582
  reg [127:0] Data;
583
  reg [31:0] Crc;
584
  integer tt;
585
 
586
  begin
587
  Packet = 128'h10082C000010_deadbeef0013_8880_0010; // 0180c2000001 + 8808 + 0001
588
  Crc = 32'h6014fe08; // not a correct value
589
 
590
    @ (posedge MRxClk);
591
    MRxDV=1'b1;
592
 
593
    for(tt=0; tt<15; tt=tt+1)
594
    begin
595
      MRxD=4'h5;              // preamble
596
      @ (posedge MRxClk);
597
    end
598
    MRxD=4'hd;                // SFD
599
 
600
    for(tt=0; tt<32; tt=tt+1)
601
    begin
602
      Data = Packet << (tt*4);
603
      @ (posedge MRxClk);
604
      MRxD=Data[127:124];
605
    end
606
 
607
    for(tt=0; tt<2; tt=tt+1)    // timer
608
    begin
609
      Data[15:0] = Timer << (tt*8);
610
      @ (posedge MRxClk);
611
      MRxD=Data[11:8];
612
      @ (posedge MRxClk);
613
      MRxD=Data[15:12];
614
    end
615
 
616
    for(tt=0; tt<42; tt=tt+1)   // padding
617
    begin
618
      Data[7:0] = 8'h0;
619
      @ (posedge MRxClk);
620
      MRxD=Data[3:0];
621
      @ (posedge MRxClk);
622
      MRxD=Data[3:0];
623
    end
624
 
625
    for(tt=0; tt<4; tt=tt+1)    // crc
626
    begin
627
      Data[31:0] = Crc << (tt*8);
628
      @ (posedge MRxClk);
629
      MRxD=Data[27:24];
630
      @ (posedge MRxClk);
631
      MRxD=Data[31:28];
632
    end
633
 
634
 
635
 
636
    @ (posedge MRxClk);
637
    MRxDV=1'b0;
638
  end
639
endtask
640
 
641
 
642
 
643
endmodule

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