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///////////3///////////////////////////////////////////////////////////
////                                                              ////
////  tb_eth_top.v                                                ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/cores/ethmac/                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2001/09/24 14:55:49  mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
// Revision 1.2  2001/08/15 14:04:30  mohor
// Signal names changed on the top level for easier pad insertion (ASIC).
//
// Revision 1.1  2001/08/06 14:41:09  mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1  2001/07/30 21:46:09  mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
 
 
 
`include "eth_defines.v"
`include "timescale.v"
 
module tb_eth_top();
 
 
parameter Tp = 1;
 
 
reg           WB_CLK_I;
reg           WB_RST_I;
reg   [31:0]  WB_DAT_I;
 
reg   [31:0]  WB_ADR_I;
reg    [3:0]  WB_SEL_I;
reg           WB_WE_I;
reg           WB_CYC_I;
reg           WB_STB_I;
reg    [1:0]  WB_ACK_I;
 
wire  [31:0]  WB_DAT_O;
wire          WB_ACK_O;
wire          WB_ERR_O;
wire   [1:0]  WB_REQ_O;
wire   [1:0]  WB_ND_O;
wire          WB_RD_O;
 
reg           MTxClk;
wire   [3:0]  MTxD;
wire          MTxEn;
wire          MTxErr;
 
reg           MRxClk;
reg    [3:0]  MRxD;
reg           MRxDV;
reg           MRxErr;
reg           MColl;
reg           MCrs;
 
reg           Mdi_I;
wire          Mdo_O;
wire          Mdo_OE;
wire          Mdc_O;
 
 
 
reg GSR;
 
reg WishboneBusy;
reg StartTB;
reg [9:0] TxBDIndex;
reg [9:0] RxBDIndex;
 
 
 
// Connecting Ethernet top module
 
eth_top ethtop
(
  // WISHBONE common
  .wb_clk_i(WB_CLK_I), .wb_rst_i(WB_RST_I), .wb_dat_i(WB_DAT_I), .wb_dat_o(WB_DAT_O),
 
  // WISHBONE slave
        .wb_adr_i(WB_ADR_I), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I),   .wb_cyc_i(WB_CYC_I),
        .wb_stb_i(WB_STB_I), .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O), .wb_req_o(WB_REQ_O),
        .wb_ack_i(WB_ACK_I), .wb_nd_o(WB_ND_O),   .wb_rd_o(WB_RD_O),
 
  //TX
  .mtx_clk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
 
  //RX
  .mrx_clk_pad_i(MRxClk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
  .mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),
 
  // MIIM
  .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoen_o(Mdo_OE),
 
  .int_o()
);
 
 
 
 
 
 
 
initial
begin
  WB_CLK_I  =  1'b0;
  WB_DAT_I  = 32'h0;
  WB_ADR_I  = 32'h0;
  WB_SEL_I  =  4'h0;
  WB_WE_I   =  1'b0;
  WB_CYC_I  =  1'b0;
  WB_STB_I  =  1'b0;
  WB_ACK_I  =  2'h0;
  MTxClk    =  1'b0;
  MRxClk    =  1'b0;
  MRxD      =  4'h0;
  MRxDV     =  1'b0;
  MRxErr    =  1'b0;
  MColl     =  1'b0;
  MCrs      =  1'b0;
  Mdi_I     =  1'b0;
 
  WishboneBusy = 1'b0;
  TxBDIndex = 10'h0;
  RxBDIndex = 10'h0;
end
 
 
// Reset pulse
initial
begin
  GSR           =  1'b1;
  WB_RST_I      =  1'b1;
  #100 WB_RST_I =  1'b1;
  GSR           =  1'b1;
  #100 WB_RST_I =  1'b0;
  GSR           =  1'b0;
  #100 StartTB  =  1'b1;
end
 
 
assign glbl.GSR = GSR;
 
 
 
// Generating WB_CLK_I clock
always
begin
//  forever #5 WB_CLK_I = ~WB_CLK_I;  // 2*5 ns -> 100.0 MHz    
//  forever #10 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 50.0 MHz    
  forever #15 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 33.3 MHz    
//  forever #18 WB_CLK_I = ~WB_CLK_I;  // 2*18 ns -> 27.7 MHz    
//  forever #100 WB_CLK_I = ~WB_CLK_I;
end
 
// Generating MTxClk clock
always
begin
  #3 forever #20 MTxClk = ~MTxClk;   // 2*20 ns -> 25 MHz
//  #3 forever #200 MTxClk = ~MTxClk;
end
 
// Generating MRxClk clock
always
begin
  #16 forever #20 MRxClk = ~MRxClk;   // 2*20 ns -> 25 MHz
//  #16 forever #250 MRxClk = ~MRxClk;
end
 
 
 
initial
begin
  wait(StartTB);  // Start of testbench
 
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 1
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 0
  WishboneWrite(32'h00000080, {26'h0, `ETH_RX_BD_ADR_ADR<<2}); // r_RxBDAddress = 0x80
  WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR<<2});     // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
 
 
 
 
  SendPacket(16'h0015, 1'b0);
  SendPacket(16'h0043, 1'b1);   // Control frame
  SendPacket(16'h0025, 1'b0);
  SendPacket(16'h0045, 1'b0);
  SendPacket(16'h0025, 1'b0);
 
 
  ReceivePacket(16'h0012, 1'b1);    // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
  ReceivePacket(16'h0011, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
  ReceivePacket(16'h0016, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
  ReceivePacket(16'h0017, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
  ReceivePacket(16'h0018, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
 
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
 
  WishboneRead({24'h100, (8'h0<<2)});       // Read from TxBD register
  WishboneRead({24'h100, (8'h1<<2)});       // Read from TxBD register
  WishboneRead({24'h100, (8'h2<<2)});       // Read from TxBD register
  WishboneRead({24'h100, (8'h3<<2)});       // Read from TxBD register
  WishboneRead({24'h100, (8'h4<<2)});       // Read from TxBD register
 
  WishboneRead({22'h40, (10'h80<<2)});       // Read from RxBD register
  WishboneRead({22'h40, (10'h81<<2)});       // Read from RxBD register
  WishboneRead({22'h40, (10'h82<<2)});       // Read from RxBD register
  WishboneRead({22'h40, (10'h83<<2)});       // Read from RxBD register
  WishboneRead({22'h40, (10'h84<<2)});       // Read from RxBD register
 
  #10000 $stop;
end
 
 
 
 
 
 
 
task WishboneWrite;
  input [31:0] Data;
  input [31:0] Address;
  integer ii;
 
  begin
    wait (~WishboneBusy);
    WishboneBusy = 1;
    @ (posedge WB_CLK_I);
    #1;
    WB_ADR_I = Address;
    WB_DAT_I = Data;
    WB_WE_I  = 1'b1;
    WB_CYC_I = 1'b1;
    WB_STB_I = 1'b1;
    WB_SEL_I = 4'hf;
 
//    for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1)   // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
//    begin
//      @ (posedge WB_CLK_I);
//    end
 
//    if(ii==20)
//      begin
//        $display("\nERROR: Task WishboneWrite(Data=0x%0h, Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)", 
//          Data, Address, $time);
//        #50 $stop;
//      end
 
    wait(WB_ACK_O);   // waiting for acknowledge response
 
    // Writing information about the access to the screen
    @ (posedge WB_CLK_I);
      if(~Address[17] & ~Address[16])
        $write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
      else
      if(~Address[17] & Address[16])
        if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
          begin
            $write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address);
            if(Data[13])
              $write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);
          end
        else
          $write("\nWrite to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
      else
        $write("\nWB write ??????????????     Data: 0x%x      Addr: 0x%0x", Data, Address);
    #1;
    WB_ADR_I = 32'hx;
    WB_DAT_I = 32'hx;
    WB_WE_I  = 1'bx;
    WB_CYC_I = 1'b0;
    WB_STB_I = 1'b0;
    WB_SEL_I = 4'hx;
    #5 WishboneBusy = 0;
  end
endtask
 
 
task WishboneRead;
  input [31:0] Address;
  reg   [31:0] Data;
  integer ii;
 
  begin
    wait (~WishboneBusy);
    WishboneBusy = 1;
    @ (posedge WB_CLK_I);
    #1;
    WB_ADR_I = Address;
    WB_WE_I  = 1'b0;
    WB_CYC_I = 1'b1;
    WB_STB_I = 1'b1;
    WB_SEL_I = 4'hf;
 
    for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1)   // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
    begin
      @ (posedge WB_CLK_I);
      Data = WB_DAT_O;
    end
 
    if(ii==20)
      begin
        $display("\nERROR: Task WishboneRead(Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)",
          Address, $time);
        #50 $stop;
      end
 
    @ (posedge WB_CLK_I);
      if(~Address[17] & ~Address[16])
        $write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
      else
      if(~Address[17] & Address[16])
        if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
          begin
            $write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address);
          end
        else
          $write("\nRead from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
      else
        $write("\nWB read  ?????????    Data: 0x%x      Addr: 0x%0x", Data, Address);
    #1;
    WB_ADR_I = 32'hx;
    WB_WE_I  = 1'bx;
    WB_CYC_I = 1'b0;
    WB_STB_I = 1'b0;
    WB_SEL_I = 4'hx;
    #5 WishboneBusy = 0;
  end
endtask
 
 
 
 
task SendPacket;
  input [15:0]  Length;
  input         ControlFrame;
  reg           Wrap;
  reg [31:0]    TempAddr;
  reg [31:0]    TempData;
 
  begin
    if(TxBDIndex == 3)    // Only 4 buffer descriptors are used
      Wrap = 1'b1;
    else
      Wrap = 1'b0;
 
    TempAddr = {22'h40, (TxBDIndex<<2)};
    TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]};  // Ready and Wrap = 1
 
    #1;
    if(TxBDIndex == 3)    // Only 4 buffer descriptors are used
      TxBDIndex = 0;
    else
      TxBDIndex = TxBDIndex + 1;
 
    fork
      begin
        WishboneWrite(TempData, TempAddr); // Writing status to TxBD
      end
 
      begin
        if(~ControlFrame)
        WaitingForTxDMARequest(4'h1, Length); // Delay, DMALength
      end
    join
  end
endtask
 
 
 
task ReceivePacket;    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
  input [15:0] LengthRx;
  input        RxControlFrame;
  reg        WrapRx;
  reg [31:0] TempRxAddr;
  reg [31:0] TempRxData;
  reg abc;
  begin
    if(RxBDIndex == 3)    // Only 4 buffer descriptors are used
      WrapRx = 1'b1;
    else
      WrapRx = 1'b0;
 
    TempRxAddr = {22'h40, ((tb_eth_top.ethtop.r_RxBDAddress + RxBDIndex)<<2)};
 
    TempRxData = {LengthRx[15:0], 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]};  // Ready and WrapRx = 1 or 0
 
    #1;
    if(RxBDIndex == 3)    // Only 4 buffer descriptors are used
      RxBDIndex = 0;
    else
      RxBDIndex = RxBDIndex + 1;
 
    abc=1;
    WishboneWrite(TempRxData, TempRxAddr); // Writing status to RxBD
    abc=0;
    fork
      begin
        #200;
        if(RxControlFrame)
          GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.
        else
          GetDataOnMRxD(LengthRx); // LengthRx bytes is comming on MRxD[3:0] signals
      end
 
      begin
        if(RxControlFrame)
          WaitingForRxDMARequest(4'h1, 16'h40); // Delay, DMALength = 64 bytes.
        else
          WaitingForRxDMARequest(4'h1, LengthRx); // Delay, DMALength
      end
    join
  end
endtask
 
 
 
task WaitingForTxDMARequest;
  input [3:0] Delay;
  input [15:0] DMALength;
  integer pp;
  reg [7:0]a, b, c, d;
 
  for(pp=0; pp*4<DMALength; pp=pp+1)
  begin
    a = 4*pp[7:0]+3;
    b = 4*pp[7:0]+2;
    c = 4*pp[7:0]+1;
    d = 4*pp[7:0]  ;
    @ (posedge WB_REQ_O[0]);
    repeat(Delay) @(posedge WB_CLK_I);
 
    wait (~WishboneBusy);
    WishboneBusy = 1;
    #1;
    WB_DAT_I = {a, b, c, d};
    WB_ADR_I = {20'h20, pp[11:0]};
    $display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);
 
    WB_WE_I  = 1'b1;
    WB_CYC_I = 1'b1;
    WB_STB_I = 1'b1;
    WB_SEL_I = 4'hf;
    WB_ACK_I[0] = 1'b1;
 
    @ (posedge WB_CLK_I);
    #1;
    WB_ADR_I = 32'hx;
    WB_DAT_I = 32'hx;
    WB_WE_I  = 1'bx;
    WB_CYC_I = 1'b0;
    WB_STB_I = 1'b0;
    WB_SEL_I = 4'hx;
    WB_ACK_I[0] = 1'b0;
    #5 WishboneBusy = 0;
  end
endtask
 
 
task WaitingForRxDMARequest;
  input [3:0] Delay;
  input [15:0] DMALengthRx;
  integer rr;
 
  for(rr=0; rr*4<DMALengthRx; rr=rr+1)
  begin
    @ (posedge WB_REQ_O[1]);
    repeat(Delay) @(posedge WB_CLK_I);
 
    wait (~WishboneBusy);
    WishboneBusy = 1;
    #1;
    WB_ADR_I = {20'h20, rr[11:0]};
    $display("task WaitingForRxDMARequest: rr=%0d, WB_ADR_I=0x%0h, WB_DAT_O=0x%0h", rr, WB_ADR_I, WB_DAT_O);
 
    WB_WE_I  = 1'b1;
    WB_CYC_I = 1'b1;
    WB_STB_I = 1'b1;
    WB_SEL_I = 4'hf;
    WB_ACK_I[1] = 1'b1;
 
    @ (posedge WB_CLK_I);
    #1;
    WB_ADR_I = 32'hx;
    WB_WE_I  = 1'bx;
    WB_CYC_I = 1'b0;
    WB_STB_I = 1'b0;
    WB_SEL_I = 4'hx;
    WB_ACK_I[1] = 1'b0;
    #5 WishboneBusy = 0;
  end
endtask
 
 
 
task GetDataOnMRxD;
  input [15:0] Len;
  integer tt;
 
  begin
    @ (posedge MRxClk);
    MRxDV=1'b1;
 
    for(tt=0; tt<15; tt=tt+1)
    begin
      MRxD=4'h5;              // preamble
      @ (posedge MRxClk);
    end
    MRxD=4'hd;                // SFD
 
    for(tt=0; tt<Len; tt=tt+1)
    begin
      @ (posedge MRxClk);
      MRxD=tt[3:0];
      @ (posedge MRxClk);
      MRxD=tt[7:4];
    end
    @ (posedge MRxClk);
    MRxDV=1'b0;
  end
endtask
 
 
task GetControlDataOnMRxD;
  input [15:0] Timer;
  reg [127:0] Packet;
  reg [127:0] Data;
  reg [31:0] Crc;
  integer tt;
 
  begin
  Packet = 128'h10082C000010_deadbeef0013_8880_0010; // 0180c2000001 + 8808 + 0001
  Crc = 32'h6014fe08; // not a correct value
 
    @ (posedge MRxClk);
    MRxDV=1'b1;
 
    for(tt=0; tt<15; tt=tt+1)
    begin
      MRxD=4'h5;              // preamble
      @ (posedge MRxClk);
    end
    MRxD=4'hd;                // SFD
 
    for(tt=0; tt<32; tt=tt+1)
    begin
      Data = Packet << (tt*4);
      @ (posedge MRxClk);
      MRxD=Data[127:124];
    end
 
    for(tt=0; tt<2; tt=tt+1)    // timer
    begin
      Data[15:0] = Timer << (tt*8);
      @ (posedge MRxClk);
      MRxD=Data[11:8];
      @ (posedge MRxClk);
      MRxD=Data[15:12];
    end
 
    for(tt=0; tt<42; tt=tt+1)   // padding
    begin
      Data[7:0] = 8'h0;
      @ (posedge MRxClk);
      MRxD=Data[3:0];
      @ (posedge MRxClk);
      MRxD=Data[3:0];
    end
 
    for(tt=0; tt<4; tt=tt+1)    // crc
    begin
      Data[31:0] = Crc << (tt*8);
      @ (posedge MRxClk);
      MRxD=Data[27:24];
      @ (posedge MRxClk);
      MRxD=Data[31:28];
    end
 
 
 
    @ (posedge MRxClk);
    MRxDV=1'b0;
  end
endtask
 
 
 
endmodule

Line No.	Rev	Author	Line
1	22	mohor	`///////////3///////////////////////////////////////////////////////////`
2	15	mohor	`//// ////`
3			`//// tb_eth_top.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/cores/ethmac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	22	mohor	`// Revision 1.3 2001/09/24 14:55:49 mohor`
45			`// Defines changed (All precede with ETH_). Small changes because some`
46			`// tools generate warnings when two operands are together. Synchronization`
47			`// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC`
48			`// demands).`
49			`//`
50	19	mohor	`// Revision 1.2 2001/08/15 14:04:30 mohor`
51			`// Signal names changed on the top level for easier pad insertion (ASIC).`
52			`//`
53	17	mohor	`// Revision 1.1 2001/08/06 14:41:09 mohor`
54			`// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).`
55			`// Include files fixed to contain no path.`
56			`// File names and module names changed ta have a eth_ prologue in the name.`
57			`// File eth_timescale.v is used to define timescale`
58			`// All pin names on the top module are changed to contain _I, _O or _OE at the end.`
59			`// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O`
60			`// and Mdo_OE. The bidirectional signal must be created on the top level. This`
61			`// is done due to the ASIC tools.`
62			`//`
63	15	mohor	`// Revision 1.1 2001/07/30 21:46:09 mohor`
64			`// Directory structure changed. Files checked and joind together.`
65			`//`
66			`//`
67			`//`
68			`//`
69			`//`
70
71
72
73			`include "eth_defines.v"
74	22	mohor	`include "timescale.v"
75	15	mohor
76			`module tb_eth_top();`
77
78
79			`parameter Tp = 1;`
80
81
82			`reg WB_CLK_I;`
83			`reg WB_RST_I;`
84			`reg [31:0] WB_DAT_I;`
85
86			`reg [31:0] WB_ADR_I;`
87			`reg [3:0] WB_SEL_I;`
88			`reg WB_WE_I;`
89			`reg WB_CYC_I;`
90			`reg WB_STB_I;`
91			`reg [1:0] WB_ACK_I;`
92
93			`wire [31:0] WB_DAT_O;`
94			`wire WB_ACK_O;`
95			`wire WB_ERR_O;`
96			`wire [1:0] WB_REQ_O;`
97			`wire [1:0] WB_ND_O;`
98			`wire WB_RD_O;`
99
100			`reg MTxClk;`
101			`wire [3:0] MTxD;`
102			`wire MTxEn;`
103			`wire MTxErr;`
104
105			`reg MRxClk;`
106			`reg [3:0] MRxD;`
107			`reg MRxDV;`
108			`reg MRxErr;`
109			`reg MColl;`
110			`reg MCrs;`
111
112			`reg Mdi_I;`
113			`wire Mdo_O;`
114			`wire Mdo_OE;`
115			`wire Mdc_O;`
116
117
118
119			`reg GSR;`
120
121			`reg WishboneBusy;`
122			`reg StartTB;`
123			`reg [9:0] TxBDIndex;`
124			`reg [9:0] RxBDIndex;`
125
126
127
128			`// Connecting Ethernet top module`
129
130			`eth_top ethtop`
131			`(`
132			`// WISHBONE common`
133	17	mohor	`.wb_clk_i(WB_CLK_I), .wb_rst_i(WB_RST_I), .wb_dat_i(WB_DAT_I), .wb_dat_o(WB_DAT_O),`
134	15	mohor
135			`// WISHBONE slave`
136	17	mohor	`.wb_adr_i(WB_ADR_I), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I), .wb_cyc_i(WB_CYC_I),`
137			`.wb_stb_i(WB_STB_I), .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O), .wb_req_o(WB_REQ_O),`
138			`.wb_ack_i(WB_ACK_I), .wb_nd_o(WB_ND_O), .wb_rd_o(WB_RD_O),`
139	15	mohor
140			`//TX`
141	19	mohor	`.mtx_clk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),`
142	15	mohor
143			`//RX`
144	19	mohor	`.mrx_clk_pad_i(MRxClk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),`
145	17	mohor	`.mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),`
146	15	mohor
147			`// MIIM`
148	22	mohor	`.mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoen_o(Mdo_OE),`
149
150			`.int_o()`
151	15	mohor	`);`
152
153
154
155
156
157
158
159			`initial`
160			`begin`
161			`WB_CLK_I = 1'b0;`
162	19	mohor	`WB_DAT_I = 32'h0;`
163			`WB_ADR_I = 32'h0;`
164			`WB_SEL_I = 4'h0;`
165			`WB_WE_I = 1'b0;`
166	15	mohor	`WB_CYC_I = 1'b0;`
167			`WB_STB_I = 1'b0;`
168			`WB_ACK_I = 2'h0;`
169			`MTxClk = 1'b0;`
170			`MRxClk = 1'b0;`
171			`MRxD = 4'h0;`
172			`MRxDV = 1'b0;`
173			`MRxErr = 1'b0;`
174			`MColl = 1'b0;`
175			`MCrs = 1'b0;`
176			`Mdi_I = 1'b0;`
177
178			`WishboneBusy = 1'b0;`
179			`TxBDIndex = 10'h0;`
180			`RxBDIndex = 10'h0;`
181			`end`
182
183
184			`// Reset pulse`
185			`initial`
186			`begin`
187	19	mohor	`GSR = 1'b1;`
188			`WB_RST_I = 1'b1;`
189	15	mohor	`#100 WB_RST_I = 1'b1;`
190			`GSR = 1'b1;`
191			`#100 WB_RST_I = 1'b0;`
192			`GSR = 1'b0;`
193			`#100 StartTB = 1'b1;`
194			`end`
195
196
197			`assign glbl.GSR = GSR;`
198
199
200
201			`// Generating WB_CLK_I clock`
202			`always`
203			`begin`
204	19	mohor	`// forever #5 WB_CLK_I = ~WB_CLK_I; // 2*5 ns -> 100.0 MHz`
205	15	mohor	`// forever #10 WB_CLK_I = ~WB_CLK_I; // 2*10 ns -> 50.0 MHz`
206			`forever #15 WB_CLK_I = ~WB_CLK_I; // 2*10 ns -> 33.3 MHz`
207			`// forever #18 WB_CLK_I = ~WB_CLK_I; // 2*18 ns -> 27.7 MHz`
208			`// forever #100 WB_CLK_I = ~WB_CLK_I;`
209			`end`
210
211			`// Generating MTxClk clock`
212			`always`
213			`begin`
214			`#3 forever #20 MTxClk = ~MTxClk; // 2*20 ns -> 25 MHz`
215			`// #3 forever #200 MTxClk = ~MTxClk;`
216			`end`
217
218			`// Generating MRxClk clock`
219			`always`
220			`begin`
221			`#16 forever #20 MRxClk = ~MRxClk; // 2*20 ns -> 25 MHz`
222			`// #16 forever #250 MRxClk = ~MRxClk;`
223			`end`
224
225
226
227			`initial`
228			`begin`
229			`wait(StartTB); // Start of testbench`
230
231	22	mohor	WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 1
232			WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 0
233			WishboneWrite(32'h00000080, {26'h0, `ETH_RX_BD_ADR_ADR<<2}); // r_RxBDAddress = 0x80
234			WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR<<2}); // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
235			WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
236	15	mohor
237
238
239
240			`SendPacket(16'h0015, 1'b0);`
241			`SendPacket(16'h0043, 1'b1); // Control frame`
242			`SendPacket(16'h0025, 1'b0);`
243			`SendPacket(16'h0045, 1'b0);`
244			`SendPacket(16'h0025, 1'b0);`
245
246
247			`ReceivePacket(16'h0012, 1'b1); // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.`
248			`ReceivePacket(16'h0011, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.`
249			`ReceivePacket(16'h0016, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.`
250			`ReceivePacket(16'h0017, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.`
251			`ReceivePacket(16'h0018, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.`
252
253
254	22	mohor	WishboneRead({26'h0, `ETH_MODER_ADR}); // Read from MODER register
255	15	mohor
256	22	mohor	`WishboneRead({24'h100, (8'h0<<2)}); // Read from TxBD register`
257			`WishboneRead({24'h100, (8'h1<<2)}); // Read from TxBD register`
258			`WishboneRead({24'h100, (8'h2<<2)}); // Read from TxBD register`
259			`WishboneRead({24'h100, (8'h3<<2)}); // Read from TxBD register`
260			`WishboneRead({24'h100, (8'h4<<2)}); // Read from TxBD register`
261	15	mohor
262	22	mohor	`WishboneRead({22'h40, (10'h80<<2)}); // Read from RxBD register`
263			`WishboneRead({22'h40, (10'h81<<2)}); // Read from RxBD register`
264			`WishboneRead({22'h40, (10'h82<<2)}); // Read from RxBD register`
265			`WishboneRead({22'h40, (10'h83<<2)}); // Read from RxBD register`
266			`WishboneRead({22'h40, (10'h84<<2)}); // Read from RxBD register`
267	15	mohor
268			`#10000 $stop;`
269			`end`
270
271
272
273
274
275
276
277			`task WishboneWrite;`
278			`input [31:0] Data;`
279			`input [31:0] Address;`
280			`integer ii;`
281
282			`begin`
283			`wait (~WishboneBusy);`
284			`WishboneBusy = 1;`
285			`@ (posedge WB_CLK_I);`
286			`#1;`
287			`WB_ADR_I = Address;`
288			`WB_DAT_I = Data;`
289			`WB_WE_I = 1'b1;`
290			`WB_CYC_I = 1'b1;`
291			`WB_STB_I = 1'b1;`
292			`WB_SEL_I = 4'hf;`
293
294	19	mohor	`// for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1) // Response on the WISHBONE is limited to 20 WB_CLK_I cycles`
295			`// begin`
296			`// @ (posedge WB_CLK_I);`
297			`// end`
298	15	mohor
299	19	mohor	`// if(ii==20)`
300			`// begin`
301			`// $display("\nERROR: Task WishboneWrite(Data=0x%0h, Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)",`
302			`// Data, Address, $time);`
303			`// #50 $stop;`
304			`// end`
305	15	mohor
306	19	mohor	`wait(WB_ACK_O); // waiting for acknowledge response`
307
308			`// Writing information about the access to the screen`
309	15	mohor	`@ (posedge WB_CLK_I);`
310	22	mohor	`if(~Address[17] & ~Address[16])`
311			`$write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);`
312	15	mohor	`else`
313	22	mohor	`if(~Address[17] & Address[16])`
314	15	mohor	`if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)`
315			`begin`
316	22	mohor	`$write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address);`
317	15	mohor	`if(Data[13])`
318			`$write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);`
319			`end`
320			`else`
321	22	mohor	`$write("\nWrite to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);`
322	15	mohor	`else`
323	22	mohor	`$write("\nWB write ?????????????? Data: 0x%x Addr: 0x%0x", Data, Address);`
324	15	mohor	`#1;`
325			`WB_ADR_I = 32'hx;`
326			`WB_DAT_I = 32'hx;`
327			`WB_WE_I = 1'bx;`
328			`WB_CYC_I = 1'b0;`
329			`WB_STB_I = 1'b0;`
330			`WB_SEL_I = 4'hx;`
331			`#5 WishboneBusy = 0;`
332			`end`
333			`endtask`
334
335
336			`task WishboneRead;`
337			`input [31:0] Address;`
338			`reg [31:0] Data;`
339			`integer ii;`
340
341			`begin`
342			`wait (~WishboneBusy);`
343			`WishboneBusy = 1;`
344			`@ (posedge WB_CLK_I);`
345			`#1;`
346			`WB_ADR_I = Address;`
347			`WB_WE_I = 1'b0;`
348			`WB_CYC_I = 1'b1;`
349			`WB_STB_I = 1'b1;`
350			`WB_SEL_I = 4'hf;`
351
352			`for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1) // Response on the WISHBONE is limited to 20 WB_CLK_I cycles`
353			`begin`
354			`@ (posedge WB_CLK_I);`
355			`Data = WB_DAT_O;`
356			`end`
357
358			`if(ii==20)`
359			`begin`
360			`$display("\nERROR: Task WishboneRead(Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)",`
361			`Address, $time);`
362			`#50 $stop;`
363			`end`
364
365			`@ (posedge WB_CLK_I);`
366	22	mohor	`if(~Address[17] & ~Address[16])`
367			`$write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);`
368	15	mohor	`else`
369	22	mohor	`if(~Address[17] & Address[16])`
370	15	mohor	`if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)`
371			`begin`
372	22	mohor	`$write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address);`
373	15	mohor	`end`
374			`else`
375	22	mohor	`$write("\nRead from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);`
376	15	mohor	`else`
377	22	mohor	`$write("\nWB read ????????? Data: 0x%x Addr: 0x%0x", Data, Address);`
378	15	mohor	`#1;`
379			`WB_ADR_I = 32'hx;`
380			`WB_WE_I = 1'bx;`
381			`WB_CYC_I = 1'b0;`
382			`WB_STB_I = 1'b0;`
383			`WB_SEL_I = 4'hx;`
384			`#5 WishboneBusy = 0;`
385			`end`
386			`endtask`
387
388
389
390
391			`task SendPacket;`
392			`input [15:0] Length;`
393			`input ControlFrame;`
394			`reg Wrap;`
395			`reg [31:0] TempAddr;`
396			`reg [31:0] TempData;`
397
398			`begin`
399			`if(TxBDIndex == 3) // Only 4 buffer descriptors are used`
400			`Wrap = 1'b1;`
401			`else`
402			`Wrap = 1'b0;`
403
404	22	mohor	`TempAddr = {22'h40, (TxBDIndex<<2)};`
405			`TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]}; // Ready and Wrap = 1`
406	15	mohor
407			`#1;`
408			`if(TxBDIndex == 3) // Only 4 buffer descriptors are used`
409			`TxBDIndex = 0;`
410			`else`
411			`TxBDIndex = TxBDIndex + 1;`
412
413			`fork`
414			`begin`
415			`WishboneWrite(TempData, TempAddr); // Writing status to TxBD`
416			`end`
417
418			`begin`
419			`if(~ControlFrame)`
420			`WaitingForTxDMARequest(4'h1, Length); // Delay, DMALength`
421			`end`
422			`join`
423			`end`
424			`endtask`
425
426
427
428			`task ReceivePacket; // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.`
429			`input [15:0] LengthRx;`
430			`input RxControlFrame;`
431			`reg WrapRx;`
432			`reg [31:0] TempRxAddr;`
433			`reg [31:0] TempRxData;`
434			`reg abc;`
435			`begin`
436			`if(RxBDIndex == 3) // Only 4 buffer descriptors are used`
437			`WrapRx = 1'b1;`
438			`else`
439			`WrapRx = 1'b0;`
440
441	22	mohor	`TempRxAddr = {22'h40, ((tb_eth_top.ethtop.r_RxBDAddress + RxBDIndex)<<2)};`
442	15	mohor
443	22	mohor	`TempRxData = {LengthRx[15:0], 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]}; // Ready and WrapRx = 1 or 0`
444	15	mohor
445			`#1;`
446			`if(RxBDIndex == 3) // Only 4 buffer descriptors are used`
447			`RxBDIndex = 0;`
448			`else`
449			`RxBDIndex = RxBDIndex + 1;`
450
451			`abc=1;`
452			`WishboneWrite(TempRxData, TempRxAddr); // Writing status to RxBD`
453			`abc=0;`
454			`fork`
455			`begin`
456			`#200;`
457			`if(RxControlFrame)`
458			`GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.`
459			`else`
460			`GetDataOnMRxD(LengthRx); // LengthRx bytes is comming on MRxD[3:0] signals`
461			`end`
462
463			`begin`
464			`if(RxControlFrame)`
465			`WaitingForRxDMARequest(4'h1, 16'h40); // Delay, DMALength = 64 bytes.`
466			`else`
467			`WaitingForRxDMARequest(4'h1, LengthRx); // Delay, DMALength`
468			`end`
469			`join`
470			`end`
471			`endtask`
472
473
474
475			`task WaitingForTxDMARequest;`
476			`input [3:0] Delay;`
477			`input [15:0] DMALength;`
478			`integer pp;`
479			`reg [7:0]a, b, c, d;`
480
481			`for(pp=0; pp*4<DMALength; pp=pp+1)`
482			`begin`
483			`a = 4*pp[7:0]+3;`
484			`b = 4*pp[7:0]+2;`
485			`c = 4*pp[7:0]+1;`
486			`d = 4*pp[7:0] ;`
487			`@ (posedge WB_REQ_O[0]);`
488			`repeat(Delay) @(posedge WB_CLK_I);`
489
490			`wait (~WishboneBusy);`
491			`WishboneBusy = 1;`
492			`#1;`
493			`WB_DAT_I = {a, b, c, d};`
494	22	mohor	`WB_ADR_I = {20'h20, pp[11:0]};`
495	15	mohor	`$display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);`
496
497			`WB_WE_I = 1'b1;`
498			`WB_CYC_I = 1'b1;`
499			`WB_STB_I = 1'b1;`
500			`WB_SEL_I = 4'hf;`

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