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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_eth_top.v] - Blame information for rev 36

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1 22 mohor
///////////3///////////////////////////////////////////////////////////
2 15 mohor
////                                                              ////
3
////  tb_eth_top.v                                                ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/cores/ethmac/                      ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001 Authors                                   ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 36 mohor
// Revision 1.5  2001/10/19 11:24:04  mohor
45
// Number of addresses (wb_adr_i) minimized.
46
//
47 23 mohor
// Revision 1.4  2001/10/19 08:46:53  mohor
48
// eth_timescale.v changed to timescale.v This is done because of the
49
// simulation of the few cores in a one joined project.
50
//
51 22 mohor
// Revision 1.3  2001/09/24 14:55:49  mohor
52
// Defines changed (All precede with ETH_). Small changes because some
53
// tools generate warnings when two operands are together. Synchronization
54
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
55
// demands).
56
//
57 19 mohor
// Revision 1.2  2001/08/15 14:04:30  mohor
58
// Signal names changed on the top level for easier pad insertion (ASIC).
59
//
60 17 mohor
// Revision 1.1  2001/08/06 14:41:09  mohor
61
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
62
// Include files fixed to contain no path.
63
// File names and module names changed ta have a eth_ prologue in the name.
64
// File eth_timescale.v is used to define timescale
65
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
66
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
67
// and Mdo_OE. The bidirectional signal must be created on the top level. This
68
// is done due to the ASIC tools.
69
//
70 15 mohor
// Revision 1.1  2001/07/30 21:46:09  mohor
71
// Directory structure changed. Files checked and joind together.
72
//
73
//
74
//
75
//
76
//
77
 
78
 
79
 
80
`include "eth_defines.v"
81 22 mohor
`include "timescale.v"
82 15 mohor
 
83
module tb_eth_top();
84
 
85
 
86
parameter Tp = 1;
87
 
88
 
89
reg           WB_CLK_I;
90
reg           WB_RST_I;
91
reg   [31:0]  WB_DAT_I;
92
 
93
reg   [31:0]  WB_ADR_I;
94
reg    [3:0]  WB_SEL_I;
95
reg           WB_WE_I;
96
reg           WB_CYC_I;
97
reg           WB_STB_I;
98
reg    [1:0]  WB_ACK_I;
99
 
100
wire  [31:0]  WB_DAT_O;
101
wire          WB_ACK_O;
102
wire          WB_ERR_O;
103
wire   [1:0]  WB_REQ_O;
104
wire   [1:0]  WB_ND_O;
105
wire          WB_RD_O;
106
 
107
reg           MTxClk;
108
wire   [3:0]  MTxD;
109
wire          MTxEn;
110
wire          MTxErr;
111
 
112
reg           MRxClk;
113
reg    [3:0]  MRxD;
114
reg           MRxDV;
115
reg           MRxErr;
116
reg           MColl;
117
reg           MCrs;
118
 
119
reg           Mdi_I;
120
wire          Mdo_O;
121
wire          Mdo_OE;
122
wire          Mdc_O;
123
 
124
 
125
 
126
reg GSR;
127
 
128
reg WishboneBusy;
129
reg StartTB;
130
reg [9:0] TxBDIndex;
131
reg [9:0] RxBDIndex;
132
 
133
 
134
 
135
// Connecting Ethernet top module
136
 
137
eth_top ethtop
138
(
139
  // WISHBONE common
140 17 mohor
  .wb_clk_i(WB_CLK_I), .wb_rst_i(WB_RST_I), .wb_dat_i(WB_DAT_I), .wb_dat_o(WB_DAT_O),
141 15 mohor
 
142
  // WISHBONE slave
143 23 mohor
        .wb_adr_i(WB_ADR_I[11:2]), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I),   .wb_cyc_i(WB_CYC_I),
144 17 mohor
        .wb_stb_i(WB_STB_I), .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O), .wb_req_o(WB_REQ_O),
145
        .wb_ack_i(WB_ACK_I), .wb_nd_o(WB_ND_O),   .wb_rd_o(WB_RD_O),
146 15 mohor
 
147
  //TX
148 19 mohor
  .mtx_clk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
149 15 mohor
 
150
  //RX
151 19 mohor
  .mrx_clk_pad_i(MRxClk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
152 17 mohor
  .mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),
153 15 mohor
 
154
  // MIIM
155 22 mohor
  .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoen_o(Mdo_OE),
156
 
157
  .int_o()
158 15 mohor
);
159
 
160
 
161
 
162
 
163
 
164
 
165
 
166
initial
167
begin
168
  WB_CLK_I  =  1'b0;
169 19 mohor
  WB_DAT_I  = 32'h0;
170
  WB_ADR_I  = 32'h0;
171
  WB_SEL_I  =  4'h0;
172
  WB_WE_I   =  1'b0;
173 15 mohor
  WB_CYC_I  =  1'b0;
174
  WB_STB_I  =  1'b0;
175
  WB_ACK_I  =  2'h0;
176
  MTxClk    =  1'b0;
177
  MRxClk    =  1'b0;
178
  MRxD      =  4'h0;
179
  MRxDV     =  1'b0;
180
  MRxErr    =  1'b0;
181
  MColl     =  1'b0;
182
  MCrs      =  1'b0;
183
  Mdi_I     =  1'b0;
184
 
185
  WishboneBusy = 1'b0;
186
  TxBDIndex = 10'h0;
187
  RxBDIndex = 10'h0;
188
end
189
 
190
 
191
// Reset pulse
192
initial
193
begin
194 19 mohor
  GSR           =  1'b1;
195
  WB_RST_I      =  1'b1;
196 15 mohor
  #100 WB_RST_I =  1'b1;
197
  GSR           =  1'b1;
198
  #100 WB_RST_I =  1'b0;
199
  GSR           =  1'b0;
200
  #100 StartTB  =  1'b1;
201
end
202
 
203
 
204
assign glbl.GSR = GSR;
205
 
206
 
207
 
208
// Generating WB_CLK_I clock
209
always
210
begin
211 19 mohor
//  forever #5 WB_CLK_I = ~WB_CLK_I;  // 2*5 ns -> 100.0 MHz    
212 15 mohor
//  forever #10 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 50.0 MHz    
213
  forever #15 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 33.3 MHz    
214
//  forever #18 WB_CLK_I = ~WB_CLK_I;  // 2*18 ns -> 27.7 MHz    
215
//  forever #100 WB_CLK_I = ~WB_CLK_I;
216
end
217
 
218
// Generating MTxClk clock
219
always
220
begin
221
  #3 forever #20 MTxClk = ~MTxClk;   // 2*20 ns -> 25 MHz
222
//  #3 forever #200 MTxClk = ~MTxClk;
223
end
224
 
225
// Generating MRxClk clock
226
always
227
begin
228
  #16 forever #20 MRxClk = ~MRxClk;   // 2*20 ns -> 25 MHz
229
//  #16 forever #250 MRxClk = ~MRxClk;
230
end
231
 
232
 
233
 
234
initial
235
begin
236
  wait(StartTB);  // Start of testbench
237
 
238 22 mohor
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 1
239
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 0
240 36 mohor
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
241 22 mohor
  WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR<<2});     // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
242
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
243 15 mohor
 
244
 
245
 
246
 
247
  SendPacket(16'h0015, 1'b0);
248
  SendPacket(16'h0043, 1'b1);   // Control frame
249
  SendPacket(16'h0025, 1'b0);
250
  SendPacket(16'h0045, 1'b0);
251
  SendPacket(16'h0025, 1'b0);
252
 
253
 
254
  ReceivePacket(16'h0012, 1'b1);    // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
255
  ReceivePacket(16'h0011, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
256
  ReceivePacket(16'h0016, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
257
  ReceivePacket(16'h0017, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
258
  ReceivePacket(16'h0018, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
259
 
260
 
261 22 mohor
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
262 15 mohor
 
263 23 mohor
  WishboneRead({24'h04, (8'h0<<2)});       // Read from TxBD register
264
  WishboneRead({24'h04, (8'h1<<2)});       // Read from TxBD register
265
  WishboneRead({24'h04, (8'h2<<2)});       // Read from TxBD register
266
  WishboneRead({24'h04, (8'h3<<2)});       // Read from TxBD register
267
  WishboneRead({24'h04, (8'h4<<2)});       // Read from TxBD register
268 15 mohor
 
269 23 mohor
  WishboneRead({22'h01, (10'h80<<2)});       // Read from RxBD register
270
  WishboneRead({22'h01, (10'h81<<2)});       // Read from RxBD register
271
  WishboneRead({22'h01, (10'h82<<2)});       // Read from RxBD register
272
  WishboneRead({22'h01, (10'h83<<2)});       // Read from RxBD register
273
  WishboneRead({22'h01, (10'h84<<2)});       // Read from RxBD register
274 15 mohor
 
275
  #10000 $stop;
276
end
277
 
278
 
279
 
280
 
281
 
282
 
283
 
284
task WishboneWrite;
285
  input [31:0] Data;
286
  input [31:0] Address;
287
  integer ii;
288
 
289
  begin
290
    wait (~WishboneBusy);
291
    WishboneBusy = 1;
292
    @ (posedge WB_CLK_I);
293
    #1;
294
    WB_ADR_I = Address;
295
    WB_DAT_I = Data;
296
    WB_WE_I  = 1'b1;
297
    WB_CYC_I = 1'b1;
298
    WB_STB_I = 1'b1;
299
    WB_SEL_I = 4'hf;
300
 
301 19 mohor
//    for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1)   // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
302
//    begin
303
//      @ (posedge WB_CLK_I);
304
//    end
305 15 mohor
 
306 19 mohor
//    if(ii==20)
307
//      begin
308
//        $display("\nERROR: Task WishboneWrite(Data=0x%0h, Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)", 
309
//          Data, Address, $time);
310
//        #50 $stop;
311
//      end
312 15 mohor
 
313 19 mohor
    wait(WB_ACK_O);   // waiting for acknowledge response
314
 
315
    // Writing information about the access to the screen
316 15 mohor
    @ (posedge WB_CLK_I);
317 23 mohor
      if(~Address[11] & ~Address[10])
318 22 mohor
        $write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
319 15 mohor
      else
320 23 mohor
      if(~Address[11] & Address[10])
321 36 mohor
        if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
322 15 mohor
          begin
323 22 mohor
            $write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address);
324 23 mohor
            if(Data[9])
325 15 mohor
              $write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);
326
          end
327
        else
328 22 mohor
          $write("\nWrite to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
329 15 mohor
      else
330 22 mohor
        $write("\nWB write ??????????????     Data: 0x%x      Addr: 0x%0x", Data, Address);
331 15 mohor
    #1;
332
    WB_ADR_I = 32'hx;
333
    WB_DAT_I = 32'hx;
334
    WB_WE_I  = 1'bx;
335
    WB_CYC_I = 1'b0;
336
    WB_STB_I = 1'b0;
337
    WB_SEL_I = 4'hx;
338
    #5 WishboneBusy = 0;
339
  end
340
endtask
341
 
342
 
343
task WishboneRead;
344
  input [31:0] Address;
345
  reg   [31:0] Data;
346
  integer ii;
347
 
348
  begin
349
    wait (~WishboneBusy);
350
    WishboneBusy = 1;
351
    @ (posedge WB_CLK_I);
352
    #1;
353
    WB_ADR_I = Address;
354
    WB_WE_I  = 1'b0;
355
    WB_CYC_I = 1'b1;
356
    WB_STB_I = 1'b1;
357
    WB_SEL_I = 4'hf;
358
 
359
    for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1)   // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
360
    begin
361
      @ (posedge WB_CLK_I);
362
      Data = WB_DAT_O;
363
    end
364
 
365
    if(ii==20)
366
      begin
367
        $display("\nERROR: Task WishboneRead(Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)",
368
          Address, $time);
369
        #50 $stop;
370
      end
371
 
372
    @ (posedge WB_CLK_I);
373 23 mohor
      if(~Address[11] & ~Address[10])
374 22 mohor
        $write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
375 15 mohor
      else
376 23 mohor
      if(~Address[11] & Address[10])
377 36 mohor
        if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
378 15 mohor
          begin
379 22 mohor
            $write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address);
380 15 mohor
          end
381
        else
382 22 mohor
          $write("\nRead from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
383 15 mohor
      else
384 22 mohor
        $write("\nWB read  ?????????    Data: 0x%x      Addr: 0x%0x", Data, Address);
385 15 mohor
    #1;
386
    WB_ADR_I = 32'hx;
387
    WB_WE_I  = 1'bx;
388
    WB_CYC_I = 1'b0;
389
    WB_STB_I = 1'b0;
390
    WB_SEL_I = 4'hx;
391
    #5 WishboneBusy = 0;
392
  end
393
endtask
394
 
395
 
396
 
397
 
398
task SendPacket;
399
  input [15:0]  Length;
400
  input         ControlFrame;
401
  reg           Wrap;
402
  reg [31:0]    TempAddr;
403
  reg [31:0]    TempData;
404
 
405
  begin
406
    if(TxBDIndex == 3)    // Only 4 buffer descriptors are used
407
      Wrap = 1'b1;
408
    else
409
      Wrap = 1'b0;
410
 
411 23 mohor
    TempAddr = {22'h01, (TxBDIndex<<2)};
412 22 mohor
    TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]};  // Ready and Wrap = 1
413 15 mohor
 
414
    #1;
415
    if(TxBDIndex == 3)    // Only 4 buffer descriptors are used
416
      TxBDIndex = 0;
417
    else
418
      TxBDIndex = TxBDIndex + 1;
419
 
420
    fork
421
      begin
422
        WishboneWrite(TempData, TempAddr); // Writing status to TxBD
423
      end
424
 
425
      begin
426
        if(~ControlFrame)
427
        WaitingForTxDMARequest(4'h1, Length); // Delay, DMALength
428
      end
429
    join
430
  end
431
endtask
432
 
433
 
434
 
435
task ReceivePacket;    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
436
  input [15:0] LengthRx;
437
  input        RxControlFrame;
438
  reg        WrapRx;
439
  reg [31:0] TempRxAddr;
440
  reg [31:0] TempRxData;
441
  reg abc;
442
  begin
443
    if(RxBDIndex == 3)    // Only 4 buffer descriptors are used
444
      WrapRx = 1'b1;
445
    else
446
      WrapRx = 1'b0;
447
 
448 36 mohor
    TempRxAddr = {22'h01, ((tb_eth_top.ethtop.r_TxBDNum + RxBDIndex)<<2)};
449 15 mohor
 
450 22 mohor
    TempRxData = {LengthRx[15:0], 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]};  // Ready and WrapRx = 1 or 0
451 15 mohor
 
452
    #1;
453
    if(RxBDIndex == 3)    // Only 4 buffer descriptors are used
454
      RxBDIndex = 0;
455
    else
456
      RxBDIndex = RxBDIndex + 1;
457
 
458
    abc=1;
459
    WishboneWrite(TempRxData, TempRxAddr); // Writing status to RxBD
460
    abc=0;
461
    fork
462
      begin
463
        #200;
464
        if(RxControlFrame)
465
          GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.
466
        else
467
          GetDataOnMRxD(LengthRx); // LengthRx bytes is comming on MRxD[3:0] signals
468
      end
469
 
470
      begin
471
        if(RxControlFrame)
472
          WaitingForRxDMARequest(4'h1, 16'h40); // Delay, DMALength = 64 bytes.
473
        else
474
          WaitingForRxDMARequest(4'h1, LengthRx); // Delay, DMALength
475
      end
476
    join
477
  end
478
endtask
479
 
480
 
481
 
482
task WaitingForTxDMARequest;
483
  input [3:0] Delay;
484
  input [15:0] DMALength;
485
  integer pp;
486
  reg [7:0]a, b, c, d;
487
 
488
  for(pp=0; pp*4<DMALength; pp=pp+1)
489
  begin
490
    a = 4*pp[7:0]+3;
491
    b = 4*pp[7:0]+2;
492
    c = 4*pp[7:0]+1;
493
    d = 4*pp[7:0]  ;
494
    @ (posedge WB_REQ_O[0]);
495
    repeat(Delay) @(posedge WB_CLK_I);
496
 
497
    wait (~WishboneBusy);
498
    WishboneBusy = 1;
499
    #1;
500
    WB_DAT_I = {a, b, c, d};
501 23 mohor
//    WB_ADR_I = {20'h20, pp[11:0]};
502
    WB_ADR_I = {22'h02, pp[9:0]};
503 15 mohor
    $display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);
504
 
505
    WB_WE_I  = 1'b1;
506
    WB_CYC_I = 1'b1;
507
    WB_STB_I = 1'b1;
508
    WB_SEL_I = 4'hf;
509
    WB_ACK_I[0] = 1'b1;
510
 
511
    @ (posedge WB_CLK_I);
512
    #1;
513
    WB_ADR_I = 32'hx;
514
    WB_DAT_I = 32'hx;
515
    WB_WE_I  = 1'bx;
516
    WB_CYC_I = 1'b0;
517
    WB_STB_I = 1'b0;
518
    WB_SEL_I = 4'hx;
519
    WB_ACK_I[0] = 1'b0;
520
    #5 WishboneBusy = 0;
521
  end
522
endtask
523
 
524
 
525
task WaitingForRxDMARequest;
526
  input [3:0] Delay;
527
  input [15:0] DMALengthRx;
528
  integer rr;
529
 
530
  for(rr=0; rr*4<DMALengthRx; rr=rr+1)
531
  begin
532
    @ (posedge WB_REQ_O[1]);
533
    repeat(Delay) @(posedge WB_CLK_I);
534
 
535
    wait (~WishboneBusy);
536
    WishboneBusy = 1;
537
    #1;
538 23 mohor
//    WB_ADR_I = {20'h20, rr[11:0]};
539
    WB_ADR_I = {22'h02, rr[9:0]};
540 15 mohor
    $display("task WaitingForRxDMARequest: rr=%0d, WB_ADR_I=0x%0h, WB_DAT_O=0x%0h", rr, WB_ADR_I, WB_DAT_O);
541
 
542
    WB_WE_I  = 1'b1;
543
    WB_CYC_I = 1'b1;
544
    WB_STB_I = 1'b1;
545
    WB_SEL_I = 4'hf;
546
    WB_ACK_I[1] = 1'b1;
547
 
548
    @ (posedge WB_CLK_I);
549
    #1;
550
    WB_ADR_I = 32'hx;
551
    WB_WE_I  = 1'bx;
552
    WB_CYC_I = 1'b0;
553
    WB_STB_I = 1'b0;
554
    WB_SEL_I = 4'hx;
555
    WB_ACK_I[1] = 1'b0;
556
    #5 WishboneBusy = 0;
557
  end
558
endtask
559
 
560
 
561
 
562
task GetDataOnMRxD;
563
  input [15:0] Len;
564
  integer tt;
565
 
566
  begin
567
    @ (posedge MRxClk);
568
    MRxDV=1'b1;
569
 
570
    for(tt=0; tt<15; tt=tt+1)
571
    begin
572
      MRxD=4'h5;              // preamble
573
      @ (posedge MRxClk);
574
    end
575
    MRxD=4'hd;                // SFD
576
 
577
    for(tt=0; tt<Len; tt=tt+1)
578
    begin
579
      @ (posedge MRxClk);
580
      MRxD=tt[3:0];
581
      @ (posedge MRxClk);
582
      MRxD=tt[7:4];
583
    end
584
    @ (posedge MRxClk);
585
    MRxDV=1'b0;
586
  end
587
endtask
588
 
589
 
590
task GetControlDataOnMRxD;
591
  input [15:0] Timer;
592
  reg [127:0] Packet;
593
  reg [127:0] Data;
594
  reg [31:0] Crc;
595
  integer tt;
596
 
597
  begin
598
  Packet = 128'h10082C000010_deadbeef0013_8880_0010; // 0180c2000001 + 8808 + 0001
599
  Crc = 32'h6014fe08; // not a correct value
600
 
601
    @ (posedge MRxClk);
602
    MRxDV=1'b1;
603
 
604
    for(tt=0; tt<15; tt=tt+1)
605
    begin
606
      MRxD=4'h5;              // preamble
607
      @ (posedge MRxClk);
608
    end
609
    MRxD=4'hd;                // SFD
610
 
611
    for(tt=0; tt<32; tt=tt+1)
612
    begin
613
      Data = Packet << (tt*4);
614
      @ (posedge MRxClk);
615
      MRxD=Data[127:124];
616
    end
617
 
618
    for(tt=0; tt<2; tt=tt+1)    // timer
619
    begin
620
      Data[15:0] = Timer << (tt*8);
621
      @ (posedge MRxClk);
622
      MRxD=Data[11:8];
623
      @ (posedge MRxClk);
624
      MRxD=Data[15:12];
625
    end
626
 
627
    for(tt=0; tt<42; tt=tt+1)   // padding
628
    begin
629
      Data[7:0] = 8'h0;
630
      @ (posedge MRxClk);
631
      MRxD=Data[3:0];
632
      @ (posedge MRxClk);
633
      MRxD=Data[3:0];
634
    end
635
 
636
    for(tt=0; tt<4; tt=tt+1)    // crc
637
    begin
638
      Data[31:0] = Crc << (tt*8);
639
      @ (posedge MRxClk);
640
      MRxD=Data[27:24];
641
      @ (posedge MRxClk);
642
      MRxD=Data[31:28];
643
    end
644
 
645
 
646
 
647
    @ (posedge MRxClk);
648
    MRxDV=1'b0;
649
  end
650
endtask
651
 
652
 
653
 
654
endmodule

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