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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_eth_top.v] - Blame information for rev 51

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Line No. Rev Author Line
1 22 mohor
///////////3///////////////////////////////////////////////////////////
2 15 mohor
////                                                              ////
3
////  tb_eth_top.v                                                ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 41 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001 Authors                                   ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 49 mohor
// Revision 1.7  2002/02/06 14:11:35  mohor
45
// non-DMA host interface added. Select the right configutation in eth_defines.
46
//
47 41 mohor
// Revision 1.6  2001/12/08 12:36:00  mohor
48
// TX_BD_NUM register added instead of the RB_BD_ADDR.
49
//
50 36 mohor
// Revision 1.5  2001/10/19 11:24:04  mohor
51
// Number of addresses (wb_adr_i) minimized.
52
//
53 23 mohor
// Revision 1.4  2001/10/19 08:46:53  mohor
54
// eth_timescale.v changed to timescale.v This is done because of the
55
// simulation of the few cores in a one joined project.
56
//
57 22 mohor
// Revision 1.3  2001/09/24 14:55:49  mohor
58
// Defines changed (All precede with ETH_). Small changes because some
59
// tools generate warnings when two operands are together. Synchronization
60
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
61
// demands).
62
//
63 19 mohor
// Revision 1.2  2001/08/15 14:04:30  mohor
64
// Signal names changed on the top level for easier pad insertion (ASIC).
65
//
66 17 mohor
// Revision 1.1  2001/08/06 14:41:09  mohor
67
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
68
// Include files fixed to contain no path.
69
// File names and module names changed ta have a eth_ prologue in the name.
70
// File eth_timescale.v is used to define timescale
71
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
72
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
73
// and Mdo_OE. The bidirectional signal must be created on the top level. This
74
// is done due to the ASIC tools.
75
//
76 15 mohor
// Revision 1.1  2001/07/30 21:46:09  mohor
77
// Directory structure changed. Files checked and joind together.
78
//
79
//
80
//
81
//
82
//
83
 
84
 
85
 
86
`include "eth_defines.v"
87 22 mohor
`include "timescale.v"
88 15 mohor
 
89
module tb_eth_top();
90
 
91
 
92
parameter Tp = 1;
93
 
94
 
95
reg           WB_CLK_I;
96
reg           WB_RST_I;
97
reg   [31:0]  WB_DAT_I;
98
 
99
reg   [31:0]  WB_ADR_I;
100
reg    [3:0]  WB_SEL_I;
101
reg           WB_WE_I;
102
reg           WB_CYC_I;
103
reg           WB_STB_I;
104
 
105
wire  [31:0]  WB_DAT_O;
106
wire          WB_ACK_O;
107
wire          WB_ERR_O;
108 41 mohor
reg    [1:0]  WB_ACK_I;
109
 
110
`ifdef WISHBONE_DMA
111 15 mohor
wire   [1:0]  WB_REQ_O;
112
wire   [1:0]  WB_ND_O;
113
wire          WB_RD_O;
114 41 mohor
`else
115
// WISHBONE master
116
wire    [31:0]    m_wb_adr_o;
117
wire     [3:0]    m_wb_sel_o;
118
wire              m_wb_we_o;
119
reg     [31:0]    m_wb_dat_i;
120
wire    [31:0]    m_wb_dat_o;
121
wire              m_wb_cyc_o;
122
wire              m_wb_stb_o;
123
reg               m_wb_ack_i;
124
reg               m_wb_err_i;
125
`endif
126 15 mohor
 
127
reg           MTxClk;
128
wire   [3:0]  MTxD;
129
wire          MTxEn;
130
wire          MTxErr;
131
 
132
reg           MRxClk;
133
reg    [3:0]  MRxD;
134
reg           MRxDV;
135
reg           MRxErr;
136
reg           MColl;
137
reg           MCrs;
138 41 mohor
reg           RxAbort;
139 15 mohor
 
140
reg           Mdi_I;
141
wire          Mdo_O;
142
wire          Mdo_OE;
143
wire          Mdc_O;
144
 
145
 
146
 
147
reg GSR;
148
 
149
reg WishboneBusy;
150
reg StartTB;
151
reg [9:0] TxBDIndex;
152
reg [9:0] RxBDIndex;
153
 
154 41 mohor
`ifdef WISHBONE_DMA
155
`else
156
  integer mcd1;
157
  integer mcd2;
158
`endif
159 15 mohor
 
160
// Connecting Ethernet top module
161
 
162
eth_top ethtop
163
(
164
  // WISHBONE common
165 17 mohor
  .wb_clk_i(WB_CLK_I), .wb_rst_i(WB_RST_I), .wb_dat_i(WB_DAT_I), .wb_dat_o(WB_DAT_O),
166 15 mohor
 
167
  // WISHBONE slave
168 23 mohor
        .wb_adr_i(WB_ADR_I[11:2]), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I),   .wb_cyc_i(WB_CYC_I),
169 41 mohor
        .wb_stb_i(WB_STB_I),       .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O), .wb_ack_i(WB_ACK_I),
170
 
171
`ifdef WISHBONE_DMA
172
        .wb_req_o(WB_REQ_O), .wb_nd_o(WB_ND_O),   .wb_rd_o(WB_RD_O),
173
`else
174
// WISHBONE master
175
  .m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o), .m_wb_dat_i(m_wb_dat_i),
176
  .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o), .m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i),
177
  .m_wb_err_i(m_wb_err_i),
178
`endif
179 15 mohor
 
180
  //TX
181 19 mohor
  .mtx_clk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
182 15 mohor
 
183
  //RX
184 19 mohor
  .mrx_clk_pad_i(MRxClk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
185 17 mohor
  .mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),
186 41 mohor
  .RxAbort(RxAbort), // igor !!! Ta se mora preseliti da bo prisel iz enega izmed modulov. Tu je le zaradi
187
                     // testiranja. Pove, kdaj adresa ni ustrezala in se paketi sklirajo, stevci pa resetirajo.
188 15 mohor
 
189
  // MIIM
190 22 mohor
  .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoen_o(Mdo_OE),
191
 
192
  .int_o()
193 15 mohor
);
194
 
195
 
196
 
197
 
198
 
199
 
200
 
201
initial
202
begin
203
  WB_CLK_I  =  1'b0;
204 19 mohor
  WB_DAT_I  = 32'h0;
205
  WB_ADR_I  = 32'h0;
206
  WB_SEL_I  =  4'h0;
207
  WB_WE_I   =  1'b0;
208 15 mohor
  WB_CYC_I  =  1'b0;
209
  WB_STB_I  =  1'b0;
210 41 mohor
 
211
`ifdef WISHBONE_DMA
212 15 mohor
  WB_ACK_I  =  2'h0;
213 41 mohor
`else
214
  m_wb_ack_i = 0;
215
  m_wb_err_i = 0;
216
`endif
217 15 mohor
  MTxClk    =  1'b0;
218
  MRxClk    =  1'b0;
219
  MRxD      =  4'h0;
220
  MRxDV     =  1'b0;
221
  MRxErr    =  1'b0;
222
  MColl     =  1'b0;
223
  MCrs      =  1'b0;
224 41 mohor
  RxAbort   =  1'b0;
225 15 mohor
  Mdi_I     =  1'b0;
226
 
227
  WishboneBusy = 1'b0;
228
  TxBDIndex = 10'h0;
229
  RxBDIndex = 10'h0;
230
end
231
 
232
 
233
// Reset pulse
234
initial
235
begin
236 41 mohor
`ifdef WISHBONE_DMA
237
`else
238
  mcd1 = $fopen("ethernet_tx.log");
239
  mcd2 = $fopen("ethernet_rx.log");
240
`endif
241
  WB_RST_I =  1'b1;
242 19 mohor
  GSR           =  1'b1;
243 15 mohor
  #100 WB_RST_I =  1'b0;
244
  GSR           =  1'b0;
245
  #100 StartTB  =  1'b1;
246
end
247
 
248
 
249 51 billditt
//assign glbl.GSR = GSR;
250 15 mohor
 
251
 
252
 
253
// Generating WB_CLK_I clock
254
always
255
begin
256 41 mohor
//  forever #2.5 WB_CLK_I = ~WB_CLK_I;  // 2*2.5 ns -> 200.0 MHz    
257 19 mohor
//  forever #5 WB_CLK_I = ~WB_CLK_I;  // 2*5 ns -> 100.0 MHz    
258 15 mohor
//  forever #10 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 50.0 MHz    
259
  forever #15 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 33.3 MHz    
260
//  forever #18 WB_CLK_I = ~WB_CLK_I;  // 2*18 ns -> 27.7 MHz    
261 41 mohor
//  forever #25 WB_CLK_I = ~WB_CLK_I;  // 2*25 ns -> 20.0 MHz
262
//  forever #50 WB_CLK_I = ~WB_CLK_I;  // 2*50 ns -> 10.0 MHz
263
//  forever #55 WB_CLK_I = ~WB_CLK_I;  // 2*55 ns ->  9.1 MHz    
264 15 mohor
end
265
 
266
// Generating MTxClk clock
267
always
268
begin
269
  #3 forever #20 MTxClk = ~MTxClk;   // 2*20 ns -> 25 MHz
270
//  #3 forever #200 MTxClk = ~MTxClk;
271
end
272
 
273
// Generating MRxClk clock
274
always
275
begin
276
  #16 forever #20 MRxClk = ~MRxClk;   // 2*20 ns -> 25 MHz
277
//  #16 forever #250 MRxClk = ~MRxClk;
278
end
279
 
280 41 mohor
`ifdef WISHBONE_DMA
281 15 mohor
initial
282
begin
283
  wait(StartTB);  // Start of testbench
284
 
285 22 mohor
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 1
286
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 0
287 36 mohor
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
288 22 mohor
  WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR<<2});     // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
289
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
290 51 billditt
  WishboneWrite(32'h0040000, {26'h0, `ETH_HASH1_ADR,2'h0}); // set bit 16, multicast hash 36
291 15 mohor
 
292
 
293
 
294
  SendPacket(16'h0015, 1'b0);
295
  SendPacket(16'h0043, 1'b1);   // Control frame
296
  SendPacket(16'h0025, 1'b0);
297
  SendPacket(16'h0045, 1'b0);
298
  SendPacket(16'h0025, 1'b0);
299
 
300
 
301
  ReceivePacket(16'h0012, 1'b1);    // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
302
  ReceivePacket(16'h0011, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
303
  ReceivePacket(16'h0016, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
304
  ReceivePacket(16'h0017, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
305
  ReceivePacket(16'h0018, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
306
 
307
 
308 22 mohor
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
309 15 mohor
 
310 23 mohor
  WishboneRead({24'h04, (8'h0<<2)});       // Read from TxBD register
311
  WishboneRead({24'h04, (8'h1<<2)});       // Read from TxBD register
312
  WishboneRead({24'h04, (8'h2<<2)});       // Read from TxBD register
313
  WishboneRead({24'h04, (8'h3<<2)});       // Read from TxBD register
314
  WishboneRead({24'h04, (8'h4<<2)});       // Read from TxBD register
315 15 mohor
 
316 23 mohor
  WishboneRead({22'h01, (10'h80<<2)});       // Read from RxBD register
317
  WishboneRead({22'h01, (10'h81<<2)});       // Read from RxBD register
318
  WishboneRead({22'h01, (10'h82<<2)});       // Read from RxBD register
319
  WishboneRead({22'h01, (10'h83<<2)});       // Read from RxBD register
320
  WishboneRead({22'h01, (10'h84<<2)});       // Read from RxBD register
321 15 mohor
 
322
  #10000 $stop;
323
end
324
 
325
 
326
 
327
 
328
 
329
 
330
 
331
task WishboneWrite;
332
  input [31:0] Data;
333
  input [31:0] Address;
334
  integer ii;
335
 
336
  begin
337
    wait (~WishboneBusy);
338
    WishboneBusy = 1;
339
    @ (posedge WB_CLK_I);
340
    #1;
341
    WB_ADR_I = Address;
342
    WB_DAT_I = Data;
343
    WB_WE_I  = 1'b1;
344
    WB_CYC_I = 1'b1;
345
    WB_STB_I = 1'b1;
346
    WB_SEL_I = 4'hf;
347
 
348 19 mohor
//    for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1)   // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
349
//    begin
350
//      @ (posedge WB_CLK_I);
351
//    end
352 15 mohor
 
353 19 mohor
//    if(ii==20)
354
//      begin
355
//        $display("\nERROR: Task WishboneWrite(Data=0x%0h, Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)", 
356
//          Data, Address, $time);
357
//        #50 $stop;
358
//      end
359 15 mohor
 
360 19 mohor
    wait(WB_ACK_O);   // waiting for acknowledge response
361
 
362
    // Writing information about the access to the screen
363 15 mohor
    @ (posedge WB_CLK_I);
364 23 mohor
      if(~Address[11] & ~Address[10])
365 22 mohor
        $write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
366 15 mohor
      else
367 23 mohor
      if(~Address[11] & Address[10])
368 36 mohor
        if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
369 15 mohor
          begin
370 22 mohor
            $write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address);
371 23 mohor
            if(Data[9])
372 15 mohor
              $write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);
373
          end
374
        else
375 22 mohor
          $write("\nWrite to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
376 15 mohor
      else
377 22 mohor
        $write("\nWB write ??????????????     Data: 0x%x      Addr: 0x%0x", Data, Address);
378 15 mohor
    #1;
379
    WB_ADR_I = 32'hx;
380
    WB_DAT_I = 32'hx;
381
    WB_WE_I  = 1'bx;
382
    WB_CYC_I = 1'b0;
383
    WB_STB_I = 1'b0;
384
    WB_SEL_I = 4'hx;
385
    #5 WishboneBusy = 0;
386
  end
387
endtask
388
 
389
 
390
task WishboneRead;
391
  input [31:0] Address;
392
  reg   [31:0] Data;
393
  integer ii;
394
 
395
  begin
396
    wait (~WishboneBusy);
397
    WishboneBusy = 1;
398
    @ (posedge WB_CLK_I);
399
    #1;
400
    WB_ADR_I = Address;
401
    WB_WE_I  = 1'b0;
402
    WB_CYC_I = 1'b1;
403
    WB_STB_I = 1'b1;
404
    WB_SEL_I = 4'hf;
405
 
406
    for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1)   // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
407
    begin
408
      @ (posedge WB_CLK_I);
409
      Data = WB_DAT_O;
410
    end
411
 
412
    if(ii==20)
413
      begin
414
        $display("\nERROR: Task WishboneRead(Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)",
415
          Address, $time);
416
        #50 $stop;
417
      end
418
 
419
    @ (posedge WB_CLK_I);
420 23 mohor
      if(~Address[11] & ~Address[10])
421 22 mohor
        $write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
422 15 mohor
      else
423 23 mohor
      if(~Address[11] & Address[10])
424 36 mohor
        if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
425 15 mohor
          begin
426 22 mohor
            $write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address);
427 15 mohor
          end
428
        else
429 22 mohor
          $write("\nRead from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
430 15 mohor
      else
431 22 mohor
        $write("\nWB read  ?????????    Data: 0x%x      Addr: 0x%0x", Data, Address);
432 15 mohor
    #1;
433
    WB_ADR_I = 32'hx;
434
    WB_WE_I  = 1'bx;
435
    WB_CYC_I = 1'b0;
436
    WB_STB_I = 1'b0;
437
    WB_SEL_I = 4'hx;
438
    #5 WishboneBusy = 0;
439
  end
440
endtask
441
 
442
 
443
 
444
 
445
task SendPacket;
446
  input [15:0]  Length;
447
  input         ControlFrame;
448
  reg           Wrap;
449
  reg [31:0]    TempAddr;
450
  reg [31:0]    TempData;
451
 
452
  begin
453
    if(TxBDIndex == 3)    // Only 4 buffer descriptors are used
454
      Wrap = 1'b1;
455
    else
456
      Wrap = 1'b0;
457
 
458 23 mohor
    TempAddr = {22'h01, (TxBDIndex<<2)};
459 22 mohor
    TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]};  // Ready and Wrap = 1
460 15 mohor
 
461
    #1;
462
    if(TxBDIndex == 3)    // Only 4 buffer descriptors are used
463
      TxBDIndex = 0;
464
    else
465
      TxBDIndex = TxBDIndex + 1;
466
 
467
    fork
468
      begin
469
        WishboneWrite(TempData, TempAddr); // Writing status to TxBD
470
      end
471
 
472
      begin
473
        if(~ControlFrame)
474
        WaitingForTxDMARequest(4'h1, Length); // Delay, DMALength
475
      end
476
    join
477
  end
478
endtask
479
 
480
 
481
 
482
task ReceivePacket;    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
483
  input [15:0] LengthRx;
484
  input        RxControlFrame;
485
  reg        WrapRx;
486
  reg [31:0] TempRxAddr;
487
  reg [31:0] TempRxData;
488
  reg abc;
489
  begin
490
    if(RxBDIndex == 3)    // Only 4 buffer descriptors are used
491
      WrapRx = 1'b1;
492
    else
493
      WrapRx = 1'b0;
494
 
495 36 mohor
    TempRxAddr = {22'h01, ((tb_eth_top.ethtop.r_TxBDNum + RxBDIndex)<<2)};
496 15 mohor
 
497 22 mohor
    TempRxData = {LengthRx[15:0], 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]};  // Ready and WrapRx = 1 or 0
498 15 mohor
 
499
    #1;
500
    if(RxBDIndex == 3)    // Only 4 buffer descriptors are used
501
      RxBDIndex = 0;
502
    else
503
      RxBDIndex = RxBDIndex + 1;
504
 
505
    abc=1;
506
    WishboneWrite(TempRxData, TempRxAddr); // Writing status to RxBD
507
    abc=0;
508
    fork
509
      begin
510
        #200;
511
        if(RxControlFrame)
512
          GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.
513
        else
514
          GetDataOnMRxD(LengthRx); // LengthRx bytes is comming on MRxD[3:0] signals
515
      end
516
 
517
      begin
518
        if(RxControlFrame)
519
          WaitingForRxDMARequest(4'h1, 16'h40); // Delay, DMALength = 64 bytes.
520
        else
521
          WaitingForRxDMARequest(4'h1, LengthRx); // Delay, DMALength
522
      end
523
    join
524
  end
525
endtask
526
 
527
 
528
 
529
task WaitingForTxDMARequest;
530
  input [3:0] Delay;
531
  input [15:0] DMALength;
532
  integer pp;
533
  reg [7:0]a, b, c, d;
534
 
535
  for(pp=0; pp*4<DMALength; pp=pp+1)
536
  begin
537
    a = 4*pp[7:0]+3;
538
    b = 4*pp[7:0]+2;
539
    c = 4*pp[7:0]+1;
540
    d = 4*pp[7:0]  ;
541
    @ (posedge WB_REQ_O[0]);
542
    repeat(Delay) @(posedge WB_CLK_I);
543
 
544
    wait (~WishboneBusy);
545
    WishboneBusy = 1;
546
    #1;
547
    WB_DAT_I = {a, b, c, d};
548 23 mohor
//    WB_ADR_I = {20'h20, pp[11:0]};
549
    WB_ADR_I = {22'h02, pp[9:0]};
550 15 mohor
    $display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);
551
 
552
    WB_WE_I  = 1'b1;
553
    WB_CYC_I = 1'b1;
554
    WB_STB_I = 1'b1;
555
    WB_SEL_I = 4'hf;
556
    WB_ACK_I[0] = 1'b1;
557
 
558
    @ (posedge WB_CLK_I);
559
    #1;
560
    WB_ADR_I = 32'hx;
561
    WB_DAT_I = 32'hx;
562
    WB_WE_I  = 1'bx;
563
    WB_CYC_I = 1'b0;
564
    WB_STB_I = 1'b0;
565
    WB_SEL_I = 4'hx;
566
    WB_ACK_I[0] = 1'b0;
567
    #5 WishboneBusy = 0;
568
  end
569
endtask
570
 
571
 
572
task WaitingForRxDMARequest;
573
  input [3:0] Delay;
574
  input [15:0] DMALengthRx;
575
  integer rr;
576
 
577
  for(rr=0; rr*4<DMALengthRx; rr=rr+1)
578
  begin
579
    @ (posedge WB_REQ_O[1]);
580
    repeat(Delay) @(posedge WB_CLK_I);
581
 
582
    wait (~WishboneBusy);
583
    WishboneBusy = 1;
584
    #1;
585 23 mohor
//    WB_ADR_I = {20'h20, rr[11:0]};
586
    WB_ADR_I = {22'h02, rr[9:0]};
587 15 mohor
    $display("task WaitingForRxDMARequest: rr=%0d, WB_ADR_I=0x%0h, WB_DAT_O=0x%0h", rr, WB_ADR_I, WB_DAT_O);
588
 
589
    WB_WE_I  = 1'b1;
590
    WB_CYC_I = 1'b1;
591
    WB_STB_I = 1'b1;
592
    WB_SEL_I = 4'hf;
593
    WB_ACK_I[1] = 1'b1;
594
 
595
    @ (posedge WB_CLK_I);
596
    #1;
597
    WB_ADR_I = 32'hx;
598
    WB_WE_I  = 1'bx;
599
    WB_CYC_I = 1'b0;
600
    WB_STB_I = 1'b0;
601
    WB_SEL_I = 4'hx;
602
    WB_ACK_I[1] = 1'b0;
603
    #5 WishboneBusy = 0;
604
  end
605
endtask
606
 
607
 
608
 
609
task GetDataOnMRxD;
610
  input [15:0] Len;
611
  integer tt;
612
 
613
  begin
614
    @ (posedge MRxClk);
615
    MRxDV=1'b1;
616
 
617
    for(tt=0; tt<15; tt=tt+1)
618
    begin
619
      MRxD=4'h5;              // preamble
620
      @ (posedge MRxClk);
621
    end
622
    MRxD=4'hd;                // SFD
623
 
624
    for(tt=0; tt<Len; tt=tt+1)
625
    begin
626
      @ (posedge MRxClk);
627
      MRxD=tt[3:0];
628
      @ (posedge MRxClk);
629
      MRxD=tt[7:4];
630
    end
631
    @ (posedge MRxClk);
632
    MRxDV=1'b0;
633
  end
634
endtask
635
 
636
 
637
task GetControlDataOnMRxD;
638
  input [15:0] Timer;
639
  reg [127:0] Packet;
640
  reg [127:0] Data;
641
  reg [31:0] Crc;
642
  integer tt;
643
 
644
  begin
645
  Packet = 128'h10082C000010_deadbeef0013_8880_0010; // 0180c2000001 + 8808 + 0001
646
  Crc = 32'h6014fe08; // not a correct value
647
 
648
    @ (posedge MRxClk);
649
    MRxDV=1'b1;
650
 
651
    for(tt=0; tt<15; tt=tt+1)
652
    begin
653
      MRxD=4'h5;              // preamble
654
      @ (posedge MRxClk);
655
    end
656
    MRxD=4'hd;                // SFD
657
 
658
    for(tt=0; tt<32; tt=tt+1)
659
    begin
660
      Data = Packet << (tt*4);
661
      @ (posedge MRxClk);
662
      MRxD=Data[127:124];
663
    end
664
 
665
    for(tt=0; tt<2; tt=tt+1)    // timer
666
    begin
667
      Data[15:0] = Timer << (tt*8);
668
      @ (posedge MRxClk);
669
      MRxD=Data[11:8];
670
      @ (posedge MRxClk);
671
      MRxD=Data[15:12];
672
    end
673
 
674
    for(tt=0; tt<42; tt=tt+1)   // padding
675
    begin
676
      Data[7:0] = 8'h0;
677
      @ (posedge MRxClk);
678
      MRxD=Data[3:0];
679
      @ (posedge MRxClk);
680
      MRxD=Data[3:0];
681
    end
682
 
683
    for(tt=0; tt<4; tt=tt+1)    // crc
684
    begin
685
      Data[31:0] = Crc << (tt*8);
686
      @ (posedge MRxClk);
687
      MRxD=Data[27:24];
688
      @ (posedge MRxClk);
689
      MRxD=Data[31:28];
690
    end
691
 
692
 
693
 
694
    @ (posedge MRxClk);
695
    MRxDV=1'b0;
696
  end
697
endtask
698
 
699 41 mohor
`else // No WISHBONE_DMA
700 15 mohor
 
701 41 mohor
initial
702
begin
703
  wait(StartTB);  // Start of testbench
704 51 billditt
  //IGORS_BOILER_PLATE;
705
  // TestUnicast;
706
  // TestBroadcast;
707
   TestMulticast;
708
end
709
 
710
task IGORS_BOILER_PLATE;
711
 begin
712
  $display("\nBegin IGORS_BOILER_PLATE \n");
713
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 1
714
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 0
715
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
716
 
717
  WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR, 2'h0});     // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
718
 
719
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); //r_TxFlow = 1
720
 
721
 
722 41 mohor
 
723 51 billditt
  SendPacket(16'h0010, 1'b0);
724
  SendPacket(16'h0011, 1'b0);
725
  SendPacket(16'h0012, 1'b0);
726
  SendPacket(16'h0013, 1'b0);
727
  SendPacket(16'h0014, 1'b0);
728 15 mohor
 
729 51 billditt
  SendPacket(16'h0030, 1'b0);
730
  SendPacket(16'h0031, 1'b0);
731
  SendPacket(16'h0032, 1'b0);
732
  SendPacket(16'h0033, 1'b0);
733
  SendPacket(16'h0025, 1'b0);
734
  SendPacket(16'h0045, 1'b0);
735
  SendPacket(16'h0025, 1'b0);
736
  SendPacket(16'h0017, 1'b0);
737 41 mohor
 
738 51 billditt
//  ReceivePacket(16'h0012, 1'b1, 1'b0);    
739
// Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
740 41 mohor
 
741 51 billditt
 
742
 
743
  WishboneWrite(32'h00400000, {26'h0, `ETH_HASH1_ADR,2'h0}); // set bit 16, multicast hash 36
744
  WishboneRead({26'h0, `ETH_HASH1_ADR});  // read back
745
 
746
  $display("\n Set Hash Filter to accept this Multicast packet, send packets\n");
747
 
748
  ReceivePacket(16'h0015, 1'b0, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
749
  ReceivePacket(16'h0016, 1'b0, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
750
  ReceivePacket(16'h0017, 1'b0, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
751
  ReceivePacket(16'h0018, 1'b0, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
752 41 mohor
 
753 51 billditt
  repeat(5000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
754 49 mohor
 
755 51 billditt
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
756
 
757
  WishboneRead({24'h04, (8'h0<<2)});       // Read from TxBD register
758
  WishboneRead({24'h04, (8'h1<<2)});       // Read from TxBD register
759
  WishboneRead({24'h04, (8'h2<<2)});       // Read from TxBD register
760
  WishboneRead({24'h04, (8'h3<<2)});       // Read from TxBD register
761
  WishboneRead({24'h04, (8'h4<<2)});       // Read from TxBD register
762
 
763
 
764
  WishboneRead({22'h01, (10'h80<<2)});       // Read from RxBD register
765
  WishboneRead({22'h01, (10'h81<<2)});       // Read from RxBD register
766
  WishboneRead({22'h01, (10'h82<<2)});       // Read from RxBD register
767
  WishboneRead({22'h01, (10'h83<<2)});       // Read from RxBD register
768
  WishboneRead({22'h01, (10'h84<<2)});       // Read from RxBD register
769
  WishboneRead({22'h01, (10'h85<<2)});       // Read from RxBD register
770
  WishboneRead({22'h01, (10'h86<<2)});       // Read from RxBD register
771
  WishboneRead({22'h01, (10'h87<<2)});       // Read from RxBD register
772
 
773
  #100000 $stop;
774
  $display("\nEnd IGORS_BOILER_PLATE \n");
775
  end
776
  endtask //IGORS_BOILER_PLATE
777
 
778
task TestUnicast;
779
 begin
780
  $display("\nBegin TestUnicast \n");
781
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 1
782
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 0
783
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
784
 
785
  WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR, 2'h0});     // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
786
 
787
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); //r_TxFlow = 1
788
 
789
 
790
 
791
  SendPacket(16'h0010, 1'b0);
792 41 mohor
  SendPacket(16'h0011, 1'b0);
793
  SendPacket(16'h0012, 1'b0);
794
  SendPacket(16'h0013, 1'b0);
795
  SendPacket(16'h0014, 1'b0);
796
 
797
  SendPacket(16'h0030, 1'b0);
798
  SendPacket(16'h0031, 1'b0);
799
  SendPacket(16'h0032, 1'b0);
800
  SendPacket(16'h0033, 1'b0);
801
  SendPacket(16'h0025, 1'b0);
802
  SendPacket(16'h0045, 1'b0);
803
  SendPacket(16'h0025, 1'b0);
804
  SendPacket(16'h0017, 1'b0);
805
 
806
//  ReceivePacket(16'h0012, 1'b1, 1'b0);    // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
807 51 billditt
 $display("\n This Uniicast packet will be rejected, wrong address in MAC Address Regs\n");
808
 
809
  ReceivePacket(16'h0015, 1'b0, 1'b0,`UNICAST_XFR);
810
 
811
  WishboneWrite(32'h04030200, {26'h0,`ETH_MAC_ADDR0_ADR ,2'h0}); // Mac Address 
812
  WishboneWrite(32'h00000605, {26'h0,`ETH_MAC_ADDR1_ADR ,2'h0}); // Mac Address
813
 
814
 
815
  $display("\n Set Proper Unicast Address in MAC_ADDRESS regs, resend packet\n");
816
 
817
  ReceivePacket(16'h0015, 1'b0, 1'b0,`UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
818
  ReceivePacket(16'h0016, 1'b0, 1'b0,`UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
819
  ReceivePacket(16'h0017, 1'b0, 1'b0,`UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
820
  ReceivePacket(16'h0018, 1'b0, 1'b0,`UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
821 41 mohor
 
822
  repeat(5000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
823
 
824
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
825
 
826
  WishboneRead({24'h04, (8'h0<<2)});       // Read from TxBD register
827
  WishboneRead({24'h04, (8'h1<<2)});       // Read from TxBD register
828
  WishboneRead({24'h04, (8'h2<<2)});       // Read from TxBD register
829
  WishboneRead({24'h04, (8'h3<<2)});       // Read from TxBD register
830
  WishboneRead({24'h04, (8'h4<<2)});       // Read from TxBD register
831
 
832
 
833
  WishboneRead({22'h01, (10'h80<<2)});       // Read from RxBD register
834
  WishboneRead({22'h01, (10'h81<<2)});       // Read from RxBD register
835
  WishboneRead({22'h01, (10'h82<<2)});       // Read from RxBD register
836
  WishboneRead({22'h01, (10'h83<<2)});       // Read from RxBD register
837
  WishboneRead({22'h01, (10'h84<<2)});       // Read from RxBD register
838
  WishboneRead({22'h01, (10'h85<<2)});       // Read from RxBD register
839
  WishboneRead({22'h01, (10'h86<<2)});       // Read from RxBD register
840
  WishboneRead({22'h01, (10'h87<<2)});       // Read from RxBD register
841 51 billditt
 
842
  #100000 $stop;
843
  $display("\nEnd TestUnicast \n");
844
end
845
endtask //TestUnicast
846 41 mohor
 
847 51 billditt
task TestMulticast;
848
 begin
849
  $display("\nBegin TestMulticast \n");
850
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 1
851
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 0
852
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
853
 
854
  WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR, 2'h0});     // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
855
 
856
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); //r_TxFlow = 1
857
 
858
 
859
 
860
  SendPacket(16'h0010, 1'b0);
861
  SendPacket(16'h0011, 1'b0);
862
  SendPacket(16'h0012, 1'b0);
863
  SendPacket(16'h0013, 1'b0);
864
  SendPacket(16'h0014, 1'b0);
865
 
866
  SendPacket(16'h0030, 1'b0);
867
  SendPacket(16'h0031, 1'b0);
868
  SendPacket(16'h0032, 1'b0);
869
  SendPacket(16'h0033, 1'b0);
870
  SendPacket(16'h0025, 1'b0);
871
  SendPacket(16'h0045, 1'b0);
872
  SendPacket(16'h0025, 1'b0);
873
  SendPacket(16'h0017, 1'b0);
874
 
875
//  ReceivePacket(16'h0012, 1'b1, 1'b0);    
876
// Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
877
 
878
 $display("\n This Multicast packet will be rejected by Hash Filter\n");
879
 
880
  ReceivePacket(16'h0015, 1'b0, 1'b0,`MULTICAST_XFR);
881
 
882
  WishboneWrite(32'h00400000, {26'h0, `ETH_HASH1_ADR,2'h0}); // set bit 16, multicast hash 36
883
  WishboneRead({26'h0, `ETH_HASH1_ADR});  // read back
884
 
885
  $display("\n Set Hash Filter to accept this Multicast packet, resend packet\n");
886
 
887
  ReceivePacket(16'h0015, 1'b0, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
888
  ReceivePacket(16'h0016, 1'b0, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
889
  ReceivePacket(16'h0017, 1'b0, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
890
  ReceivePacket(16'h0018, 1'b0, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
891
 
892
  repeat(5000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
893
 
894
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
895
 
896
  WishboneRead({24'h04, (8'h0<<2)});       // Read from TxBD register
897
  WishboneRead({24'h04, (8'h1<<2)});       // Read from TxBD register
898
  WishboneRead({24'h04, (8'h2<<2)});       // Read from TxBD register
899
  WishboneRead({24'h04, (8'h3<<2)});       // Read from TxBD register
900
  WishboneRead({24'h04, (8'h4<<2)});       // Read from TxBD register
901
 
902
 
903
  WishboneRead({22'h01, (10'h80<<2)});       // Read from RxBD register
904
  WishboneRead({22'h01, (10'h81<<2)});       // Read from RxBD register
905
  WishboneRead({22'h01, (10'h82<<2)});       // Read from RxBD register
906
  WishboneRead({22'h01, (10'h83<<2)});       // Read from RxBD register
907
  WishboneRead({22'h01, (10'h84<<2)});       // Read from RxBD register
908
  WishboneRead({22'h01, (10'h85<<2)});       // Read from RxBD register
909
  WishboneRead({22'h01, (10'h86<<2)});       // Read from RxBD register
910
  WishboneRead({22'h01, (10'h87<<2)});       // Read from RxBD register
911
 
912 41 mohor
  #100000 $stop;
913 51 billditt
  $display("\nEnd TestMulticast \n");
914 41 mohor
end
915 51 billditt
endtask //TestMulticast
916 41 mohor
 
917
 
918 51 billditt
task TestBroadcast;
919
 begin
920
  $display("\nBegin TestBroadcast \n");
921
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 1
922
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 0
923
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
924 41 mohor
 
925 51 billditt
  WishboneWrite(32'h0002A44b, {26'h0, `ETH_MODER_ADR, 2'h0});
926
  // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG, r_Bro = 1 (disabled)
927
 
928
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); //r_TxFlow = 1
929
 
930
 
931
 
932
  SendPacket(16'h0010, 1'b0);
933
  SendPacket(16'h0011, 1'b0);
934
  SendPacket(16'h0012, 1'b0);
935
  SendPacket(16'h0013, 1'b0);
936
  SendPacket(16'h0014, 1'b0);
937
 
938
  SendPacket(16'h0030, 1'b0);
939
  SendPacket(16'h0031, 1'b0);
940
  SendPacket(16'h0032, 1'b0);
941
  SendPacket(16'h0033, 1'b0);
942
  SendPacket(16'h0025, 1'b0);
943
  SendPacket(16'h0045, 1'b0);
944
  SendPacket(16'h0025, 1'b0);
945
  SendPacket(16'h0017, 1'b0);
946
 
947
//  ReceivePacket(16'h0012, 1'b1, 1'b0);    
948
// Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
949
 
950
 $display("\n This Broadcast packet will be rejected ,r_BRO  set\n");
951
 
952
  ReceivePacket(16'h0015, 1'b0, 1'b0,`BROADCAST_XFR);
953
 
954
 
955
  WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR, 2'h0});
956
 
957
  // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG, r_Bro
958
  $display("\n Set r_Bro, resend packet\n");
959
 
960
  ReceivePacket(16'h0015, 1'b0, 1'b0,`BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
961
  ReceivePacket(16'h0016, 1'b0, 1'b0,`BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
962
  ReceivePacket(16'h0017, 1'b0, 1'b0,`BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
963
  ReceivePacket(16'h0018, 1'b0, 1'b0,`BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
964
 
965
  repeat(5000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
966
 
967
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
968
 
969
  WishboneRead({24'h04, (8'h0<<2)});       // Read from TxBD register
970
  WishboneRead({24'h04, (8'h1<<2)});       // Read from TxBD register
971
  WishboneRead({24'h04, (8'h2<<2)});       // Read from TxBD register
972
  WishboneRead({24'h04, (8'h3<<2)});       // Read from TxBD register
973
  WishboneRead({24'h04, (8'h4<<2)});       // Read from TxBD register
974
 
975
 
976
  WishboneRead({22'h01, (10'h80<<2)});       // Read from RxBD register
977
  WishboneRead({22'h01, (10'h81<<2)});       // Read from RxBD register
978
  WishboneRead({22'h01, (10'h82<<2)});       // Read from RxBD register
979
  WishboneRead({22'h01, (10'h83<<2)});       // Read from RxBD register
980
  WishboneRead({22'h01, (10'h84<<2)});       // Read from RxBD register
981
  WishboneRead({22'h01, (10'h85<<2)});       // Read from RxBD register
982
  WishboneRead({22'h01, (10'h86<<2)});       // Read from RxBD register
983
  WishboneRead({22'h01, (10'h87<<2)});       // Read from RxBD register
984
 
985
  #100000 $stop;
986
  $display("\nEnd TestBroadcast \n");
987
end
988
endtask //TestBroadcast
989
 
990
//integer ijk;
991
 
992
//initial
993
//ijk = 0;    // for stoping generation of the m_wb_ack_i signal at the right moment so we get underrun
994
 
995 41 mohor
// Answering to master Wishbone requests
996
always @ (posedge WB_CLK_I)
997
begin
998
  if(m_wb_cyc_o & m_wb_stb_o) // Add valid address range
999
    begin
1000
      repeat(3) @ (posedge WB_CLK_I);
1001
        begin
1002 51 billditt
//          if(ijk==41)
1003 41 mohor
//            begin
1004
//              repeat(1000) @ (posedge WB_CLK_I);
1005
//            end
1006
//          else
1007
            m_wb_ack_i <=#Tp 1'b1;
1008
          if(~m_wb_we_o)
1009
            begin
1010
              #Tp m_wb_dat_i = m_wb_adr_o + 1'b1; // For easier following of the data
1011
              $fdisplay(mcd1, "(%0t) master read (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_i);
1012 51 billditt
//              ijk = ijk + 1;
1013 41 mohor
            end
1014
          else
1015
            $fdisplay(mcd2, "(%0t) master write (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_o);
1016
        end
1017
      @ (posedge WB_CLK_I);
1018
      m_wb_ack_i <=#Tp 1'b0;
1019
    end
1020
end
1021
 
1022
// Generating error
1023
always @ (posedge WB_CLK_I)
1024
begin
1025
  if(m_wb_cyc_o & m_wb_stb_o & ~(&m_wb_sel_o))  // Add false address range
1026
    m_wb_err_i <=#Tp 1'b1;
1027
end
1028
 
1029
always @ (posedge WB_CLK_I)
1030
  if(tb_eth_top.ethtop.wishbone.RxStatusWrite)
1031
    $fdisplay(mcd2, "");  // newline added
1032
 
1033
task WishboneWrite;
1034
  input [31:0] Data;
1035
  input [31:0] Address;
1036
  integer ii;
1037
 
1038
  begin
1039
    wait (~WishboneBusy);
1040
    WishboneBusy = 1;
1041
    @ (posedge WB_CLK_I);
1042
    #1;
1043
    WB_ADR_I = Address;
1044
    WB_DAT_I = Data;
1045
    WB_WE_I  = 1'b1;
1046
    WB_CYC_I = 1'b1;
1047
    WB_STB_I = 1'b1;
1048
    WB_SEL_I = 4'hf;
1049
 
1050
 
1051
    wait(WB_ACK_O);   // waiting for acknowledge response
1052
 
1053
    // Writing information about the access to the screen
1054
    @ (posedge WB_CLK_I);
1055
      if(~Address[11] & ~Address[10])
1056
        $write("\n(%0t) Write to register (Data: 0x%x, Reg. Addr: 0x%0x)", $time, Data, Address);
1057
      else
1058
      if(~Address[11] & Address[10])
1059
        if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
1060
          begin
1061
            $write("\n(%0t) Write to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", $time, Data, Address);
1062
            if(Data[9])
1063
              $write("(%0t) Send Control packet (PAUSE = 0x%0h)\n", $time, Data[31:16]);
1064
          end
1065
        else
1066
          $write("\n(%0t) Write to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", $time, Data, Address);
1067
      else
1068
        $write("\n(%0t) WB write ??????????????     Data: 0x%x      Addr: 0x%0x", $time, Data, Address);
1069
    #1;
1070
    WB_ADR_I = 32'hx;
1071
    WB_DAT_I = 32'hx;
1072
    WB_WE_I  = 1'bx;
1073
    WB_CYC_I = 1'b0;
1074
    WB_STB_I = 1'b0;
1075
    WB_SEL_I = 4'hx;
1076
    #5 WishboneBusy = 0;
1077
  end
1078
endtask
1079
 
1080
 
1081
task WishboneRead;
1082
  input [31:0] Address;
1083
 
1084
  begin
1085
    wait (~WishboneBusy);
1086
    WishboneBusy = 1;
1087
    @ (posedge WB_CLK_I);
1088
    #1;
1089
    WB_ADR_I = Address;
1090
    WB_WE_I  = 1'b0;
1091
    WB_CYC_I = 1'b1;
1092
    WB_STB_I = 1'b1;
1093
    WB_SEL_I = 4'hf;
1094
 
1095
    wait(WB_ACK_O);   // waiting for acknowledge response
1096
    @ (posedge WB_CLK_I);
1097
 
1098
      if(~Address[11] & ~Address[10])
1099
        $write("\n(%0t) Read from register (Data: 0x%x, Reg. Addr: 0x%0x)", $time, WB_DAT_O, Address);
1100
      else
1101
      if(~Address[11] & Address[10])
1102
        if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
1103
          begin
1104
            $write("\n(%0t) Read from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", $time, WB_DAT_O, Address);
1105
          end
1106
        else
1107
          $write("\n(%0t) Read from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", $time, WB_DAT_O, Address);
1108
      else
1109
        $write("\n(%0t) WB read  ?????????    Data: 0x%x      Addr: 0x%0x", $time, WB_DAT_O, Address);
1110
    #1;
1111
    WB_ADR_I = 32'hx;
1112
    WB_WE_I  = 1'bx;
1113
    WB_CYC_I = 1'b0;
1114
    WB_STB_I = 1'b0;
1115
    WB_SEL_I = 4'hx;
1116
    #5 WishboneBusy = 0;
1117
  end
1118
endtask
1119
 
1120
 
1121
 
1122
 
1123
task SendPacket;
1124
  input [15:0]  Length;
1125
  input         ControlFrame;
1126
  reg           Wrap;
1127
  reg [31:0]    TempAddr;
1128
  reg [31:0]    TempData;
1129
 
1130
  begin
1131
//    if(TxBDIndex == 6)    // Only 3 buffer descriptors are used 
1132
//      Wrap = 1'b1;
1133
//    else
1134
      Wrap = 1'b0;    // At the moment no wrap bit is set
1135
 
1136
    // Writing buffer pointer
1137
    TempAddr = {22'h01, ((TxBDIndex + 1'b1)<<2)};
1138
    TempData = 32'h78563411;
1139
    WishboneWrite(TempData, TempAddr); // buffer pointer
1140
 
1141
 
1142 51 billditt
    TempAddr = {22'h01, (TxBDIndex<<2)};  // igor !!! zbrisi spodnjo vrstico
1143
//    TempAddr = {22'h01, 10'b1010010100};
1144 41 mohor
 
1145
    TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]};  // Ready and Wrap = 1
1146
 
1147
    #1;
1148
//    if(TxBDIndex == 6)    // Only 4 buffer descriptors are used
1149
//      TxBDIndex = 0;
1150
//    else
1151
      TxBDIndex = TxBDIndex + 2;
1152
 
1153
    WishboneWrite(TempData, TempAddr); // Writing status to TxBD
1154
  end
1155
endtask
1156
 
1157
 
1158
 
1159
task ReceivePacket;    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
1160
  input [15:0] LengthRx;
1161
  input        RxControlFrame;
1162
  input        Abort;
1163 51 billditt
  input [31:0] TransferType;  //Broadcast,Unicast,Multicast
1164 41 mohor
  reg        WrapRx;
1165
  reg [31:0] TempRxAddr;
1166
  reg [31:0] TempRxData;
1167
  reg abc;
1168
  begin
1169
//    if(RxBDIndex == 6)    // Only 3 buffer descriptors are used
1170
//      WrapRx = 1'b1;
1171
//    else
1172
      WrapRx = 1'b0;
1173
 
1174
    TempRxAddr = {22'h01, ((tb_eth_top.ethtop.r_TxBDNum + RxBDIndex + 1'b1)<<2)};
1175
    TempRxData = 32'h73507350 + RxBDIndex;
1176
    WishboneWrite(TempRxData, TempRxAddr); // Writing Rx pointer
1177
 
1178
 
1179
    TempRxAddr = {22'h01, ((tb_eth_top.ethtop.r_TxBDNum + RxBDIndex)<<2)};
1180
//    TempRxData = {LengthRx[15:0], 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]};  // Ready and WrapRx = 1 or 0
1181
    TempRxData = {16'h0, 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]};  // Ready and WrapRx = 1 or 0
1182
 
1183
    #1;
1184
//    if(RxBDIndex == 6)    // Only 4 buffer descriptors are used
1185
//      RxBDIndex = 0;
1186
//    else
1187
      RxBDIndex = RxBDIndex + 2;
1188
 
1189
    abc=1;
1190
    WishboneWrite(TempRxData, TempRxAddr); // Writing status to RxBD
1191
    abc=0;
1192
 
1193
      begin
1194
        #200;
1195
        if(RxControlFrame)
1196
          GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.
1197
        else
1198 51 billditt
          GetDataOnMRxD(LengthRx, Abort, TransferType); // LengthRx bytes is comming on MRxD[3:0] signals
1199 41 mohor
      end
1200
 
1201
  end
1202
endtask
1203
 
1204
 
1205
task GetDataOnMRxD;
1206
  input [15:0] Len;
1207
  input abort;
1208 51 billditt
  input [31:0] TransferType;
1209 41 mohor
  integer tt;
1210
 
1211
  begin
1212
    @ (posedge MRxClk);
1213
    MRxDV=1'b1;
1214
 
1215
    for(tt=0; tt<15; tt=tt+1)
1216
    begin
1217
      MRxD=4'h5;              // preamble
1218
      @ (posedge MRxClk);
1219
    end
1220
    MRxD=4'hd;                // SFD
1221 51 billditt
 
1222
  for(tt=1; tt<(Len+1); tt=tt+1)
1223
 
1224 41 mohor
    begin
1225 51 billditt
 
1226 41 mohor
      @ (posedge MRxClk);
1227 51 billditt
          if(TransferType == `UNICAST_XFR && tt == 1)
1228
           MRxD= 4'h0;   // Unicast transfer
1229
          else if(TransferType == `BROADCAST_XFR && tt < 7)
1230
           MRxD = 4'hf;
1231
          else
1232
       MRxD=tt[3:0]; // Multicast transfer
1233
 
1234 41 mohor
      if(tt==9)
1235
        RxAbort<=#1 abort;
1236
      @ (posedge MRxClk);
1237 51 billditt
 
1238
           if(TransferType == `BROADCAST_XFR && tt < 7)
1239
            MRxD = 4'hf;
1240
          else
1241
        MRxD=tt[7:4];
1242 41 mohor
      RxAbort<=#1 0;
1243
    end
1244 51 billditt
 
1245 41 mohor
    @ (posedge MRxClk);
1246
    MRxDV=1'b0;
1247
  end
1248
endtask
1249
 
1250
 
1251
task GetControlDataOnMRxD;
1252
  input [15:0] Timer;
1253
  reg [127:0] Packet;
1254
  reg [127:0] Data;
1255
  reg [31:0] Crc;
1256
  integer tt;
1257
 
1258
  begin
1259 51 billditt
   //Packet = 128'h10082C000010_deadbeef0013_8880_0010; // 0180c2000001 + 8808 + 0001
1260
 
1261 41 mohor
  Crc = 32'h6014fe08; // not a correct value
1262
 
1263
    @ (posedge MRxClk);
1264
    MRxDV=1'b1;
1265
 
1266
    for(tt=0; tt<15; tt=tt+1)
1267
    begin
1268
      MRxD=4'h5;              // preamble
1269
      @ (posedge MRxClk);
1270
    end
1271
    MRxD=4'hd;                // SFD
1272
 
1273
    for(tt=0; tt<32; tt=tt+1)
1274
    begin
1275
      Data = Packet << (tt*4);
1276
      @ (posedge MRxClk);
1277
      MRxD=Data[127:124];
1278
    end
1279
 
1280
    for(tt=0; tt<2; tt=tt+1)    // timer
1281
    begin
1282
      Data[15:0] = Timer << (tt*8);
1283
      @ (posedge MRxClk);
1284
      MRxD=Data[11:8];
1285
      @ (posedge MRxClk);
1286
      MRxD=Data[15:12];
1287
    end
1288
 
1289
    for(tt=0; tt<42; tt=tt+1)   // padding
1290
    begin
1291
      Data[7:0] = 8'h0;
1292
      @ (posedge MRxClk);
1293
      MRxD=Data[3:0];
1294
      @ (posedge MRxClk);
1295
      MRxD=Data[3:0];
1296
    end
1297
 
1298
    for(tt=0; tt<4; tt=tt+1)    // crc
1299
    begin
1300
      Data[31:0] = Crc << (tt*8);
1301
      @ (posedge MRxClk);
1302
      MRxD=Data[27:24];
1303
      @ (posedge MRxClk);
1304
      MRxD=Data[31:28];
1305
    end
1306
 
1307
 
1308
 
1309
    @ (posedge MRxClk);
1310
    MRxDV=1'b0;
1311
  end
1312
endtask
1313
`endif
1314
 
1315
 
1316 15 mohor
endmodule

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