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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_eth_top.v] - Blame information for rev 66

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1 66 mohor
//////////////////////////////////////////////////////////////////////
2 15 mohor
////                                                              ////
3
////  tb_eth_top.v                                                ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 41 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001 Authors                                   ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 66 mohor
// Revision 1.9  2002/02/14 20:14:38  billditt
45
// Added separate tests for Multicast, Unicast, Broadcast
46
//
47
// Revision 1.8  2002/02/12 20:24:00  mohor
48
// HASH0 and HASH1 register read/write added.
49
//
50 49 mohor
// Revision 1.7  2002/02/06 14:11:35  mohor
51
// non-DMA host interface added. Select the right configutation in eth_defines.
52
//
53 41 mohor
// Revision 1.6  2001/12/08 12:36:00  mohor
54
// TX_BD_NUM register added instead of the RB_BD_ADDR.
55
//
56 36 mohor
// Revision 1.5  2001/10/19 11:24:04  mohor
57
// Number of addresses (wb_adr_i) minimized.
58
//
59 23 mohor
// Revision 1.4  2001/10/19 08:46:53  mohor
60
// eth_timescale.v changed to timescale.v This is done because of the
61
// simulation of the few cores in a one joined project.
62
//
63 22 mohor
// Revision 1.3  2001/09/24 14:55:49  mohor
64
// Defines changed (All precede with ETH_). Small changes because some
65
// tools generate warnings when two operands are together. Synchronization
66
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
67
// demands).
68
//
69 19 mohor
// Revision 1.2  2001/08/15 14:04:30  mohor
70
// Signal names changed on the top level for easier pad insertion (ASIC).
71
//
72 17 mohor
// Revision 1.1  2001/08/06 14:41:09  mohor
73
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
74
// Include files fixed to contain no path.
75
// File names and module names changed ta have a eth_ prologue in the name.
76
// File eth_timescale.v is used to define timescale
77
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
78
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
79
// and Mdo_OE. The bidirectional signal must be created on the top level. This
80
// is done due to the ASIC tools.
81
//
82 15 mohor
// Revision 1.1  2001/07/30 21:46:09  mohor
83
// Directory structure changed. Files checked and joind together.
84
//
85
//
86
//
87
//
88
//
89
 
90
 
91
 
92
`include "eth_defines.v"
93 22 mohor
`include "timescale.v"
94 15 mohor
 
95
module tb_eth_top();
96
 
97
 
98
parameter Tp = 1;
99
 
100
 
101
reg           WB_CLK_I;
102
reg           WB_RST_I;
103
reg   [31:0]  WB_DAT_I;
104
 
105
reg   [31:0]  WB_ADR_I;
106
reg    [3:0]  WB_SEL_I;
107
reg           WB_WE_I;
108
reg           WB_CYC_I;
109
reg           WB_STB_I;
110
 
111
wire  [31:0]  WB_DAT_O;
112
wire          WB_ACK_O;
113
wire          WB_ERR_O;
114 41 mohor
reg    [1:0]  WB_ACK_I;
115
 
116
`ifdef WISHBONE_DMA
117 15 mohor
wire   [1:0]  WB_REQ_O;
118
wire   [1:0]  WB_ND_O;
119
wire          WB_RD_O;
120 41 mohor
`else
121
// WISHBONE master
122
wire    [31:0]    m_wb_adr_o;
123
wire     [3:0]    m_wb_sel_o;
124
wire              m_wb_we_o;
125
reg     [31:0]    m_wb_dat_i;
126
wire    [31:0]    m_wb_dat_o;
127
wire              m_wb_cyc_o;
128
wire              m_wb_stb_o;
129
reg               m_wb_ack_i;
130
reg               m_wb_err_i;
131
`endif
132 15 mohor
 
133
reg           MTxClk;
134
wire   [3:0]  MTxD;
135
wire          MTxEn;
136
wire          MTxErr;
137
 
138
reg           MRxClk;
139
reg    [3:0]  MRxD;
140
reg           MRxDV;
141
reg           MRxErr;
142
reg           MColl;
143
reg           MCrs;
144
 
145
reg           Mdi_I;
146
wire          Mdo_O;
147
wire          Mdo_OE;
148
wire          Mdc_O;
149
 
150
 
151
 
152
reg WishboneBusy;
153
reg StartTB;
154
reg [9:0] TxBDIndex;
155
reg [9:0] RxBDIndex;
156
 
157 41 mohor
`ifdef WISHBONE_DMA
158
`else
159
  integer mcd1;
160
  integer mcd2;
161
`endif
162 15 mohor
 
163
// Connecting Ethernet top module
164
 
165
eth_top ethtop
166
(
167
  // WISHBONE common
168 17 mohor
  .wb_clk_i(WB_CLK_I), .wb_rst_i(WB_RST_I), .wb_dat_i(WB_DAT_I), .wb_dat_o(WB_DAT_O),
169 15 mohor
 
170
  // WISHBONE slave
171 23 mohor
        .wb_adr_i(WB_ADR_I[11:2]), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I),   .wb_cyc_i(WB_CYC_I),
172 41 mohor
        .wb_stb_i(WB_STB_I),       .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O), .wb_ack_i(WB_ACK_I),
173
 
174
`ifdef WISHBONE_DMA
175
        .wb_req_o(WB_REQ_O), .wb_nd_o(WB_ND_O),   .wb_rd_o(WB_RD_O),
176
`else
177
// WISHBONE master
178
  .m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o), .m_wb_dat_i(m_wb_dat_i),
179
  .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o), .m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i),
180
  .m_wb_err_i(m_wb_err_i),
181
`endif
182 15 mohor
 
183
  //TX
184 19 mohor
  .mtx_clk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
185 15 mohor
 
186
  //RX
187 19 mohor
  .mrx_clk_pad_i(MRxClk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
188 17 mohor
  .mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),
189 15 mohor
 
190
  // MIIM
191 22 mohor
  .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoen_o(Mdo_OE),
192
 
193
  .int_o()
194 15 mohor
);
195
 
196
 
197
 
198
 
199
 
200
 
201
 
202
initial
203
begin
204
  WB_CLK_I  =  1'b0;
205 19 mohor
  WB_DAT_I  = 32'h0;
206
  WB_ADR_I  = 32'h0;
207
  WB_SEL_I  =  4'h0;
208
  WB_WE_I   =  1'b0;
209 15 mohor
  WB_CYC_I  =  1'b0;
210
  WB_STB_I  =  1'b0;
211 41 mohor
 
212
`ifdef WISHBONE_DMA
213 15 mohor
  WB_ACK_I  =  2'h0;
214 41 mohor
`else
215
  m_wb_ack_i = 0;
216
  m_wb_err_i = 0;
217
`endif
218 15 mohor
  MTxClk    =  1'b0;
219
  MRxClk    =  1'b0;
220
  MRxD      =  4'h0;
221
  MRxDV     =  1'b0;
222
  MRxErr    =  1'b0;
223
  MColl     =  1'b0;
224
  MCrs      =  1'b0;
225
  Mdi_I     =  1'b0;
226
 
227
  WishboneBusy = 1'b0;
228
  TxBDIndex = 10'h0;
229
  RxBDIndex = 10'h0;
230
end
231
 
232
 
233
// Reset pulse
234
initial
235
begin
236 41 mohor
`ifdef WISHBONE_DMA
237
`else
238
  mcd1 = $fopen("ethernet_tx.log");
239
  mcd2 = $fopen("ethernet_rx.log");
240
`endif
241
  WB_RST_I =  1'b1;
242 15 mohor
  #100 WB_RST_I =  1'b0;
243
  #100 StartTB  =  1'b1;
244
end
245
 
246
 
247
 
248
// Generating WB_CLK_I clock
249
always
250
begin
251 41 mohor
//  forever #2.5 WB_CLK_I = ~WB_CLK_I;  // 2*2.5 ns -> 200.0 MHz    
252 19 mohor
//  forever #5 WB_CLK_I = ~WB_CLK_I;  // 2*5 ns -> 100.0 MHz    
253 15 mohor
//  forever #10 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 50.0 MHz    
254
  forever #15 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 33.3 MHz    
255
//  forever #18 WB_CLK_I = ~WB_CLK_I;  // 2*18 ns -> 27.7 MHz    
256 41 mohor
//  forever #25 WB_CLK_I = ~WB_CLK_I;  // 2*25 ns -> 20.0 MHz
257
//  forever #50 WB_CLK_I = ~WB_CLK_I;  // 2*50 ns -> 10.0 MHz
258
//  forever #55 WB_CLK_I = ~WB_CLK_I;  // 2*55 ns ->  9.1 MHz    
259 15 mohor
end
260
 
261
// Generating MTxClk clock
262
always
263
begin
264
  #3 forever #20 MTxClk = ~MTxClk;   // 2*20 ns -> 25 MHz
265
//  #3 forever #200 MTxClk = ~MTxClk;
266
end
267
 
268
// Generating MRxClk clock
269
always
270
begin
271
  #16 forever #20 MRxClk = ~MRxClk;   // 2*20 ns -> 25 MHz
272
//  #16 forever #250 MRxClk = ~MRxClk;
273
end
274
 
275 41 mohor
`ifdef WISHBONE_DMA
276 15 mohor
initial
277
begin
278
  wait(StartTB);  // Start of testbench
279
 
280 22 mohor
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 1
281
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 0
282 36 mohor
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
283 22 mohor
  WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR<<2});     // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
284
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
285 15 mohor
 
286
  SendPacket(16'h0015, 1'b0);
287
  SendPacket(16'h0043, 1'b1);   // Control frame
288
  SendPacket(16'h0025, 1'b0);
289
  SendPacket(16'h0045, 1'b0);
290
  SendPacket(16'h0025, 1'b0);
291
 
292
  ReceivePacket(16'h0012, 1'b1);    // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
293
  ReceivePacket(16'h0011, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
294
  ReceivePacket(16'h0016, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
295
  ReceivePacket(16'h0017, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
296
  ReceivePacket(16'h0018, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
297
 
298
 
299 22 mohor
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
300 15 mohor
 
301 23 mohor
  WishboneRead({24'h04, (8'h0<<2)});       // Read from TxBD register
302
  WishboneRead({24'h04, (8'h1<<2)});       // Read from TxBD register
303
  WishboneRead({24'h04, (8'h2<<2)});       // Read from TxBD register
304
  WishboneRead({24'h04, (8'h3<<2)});       // Read from TxBD register
305
  WishboneRead({24'h04, (8'h4<<2)});       // Read from TxBD register
306 15 mohor
 
307 23 mohor
  WishboneRead({22'h01, (10'h80<<2)});       // Read from RxBD register
308
  WishboneRead({22'h01, (10'h81<<2)});       // Read from RxBD register
309
  WishboneRead({22'h01, (10'h82<<2)});       // Read from RxBD register
310
  WishboneRead({22'h01, (10'h83<<2)});       // Read from RxBD register
311
  WishboneRead({22'h01, (10'h84<<2)});       // Read from RxBD register
312 15 mohor
 
313
  #10000 $stop;
314
end
315
 
316
 
317
 
318
 
319
 
320
 
321
 
322
task WishboneWrite;
323
  input [31:0] Data;
324
  input [31:0] Address;
325
  integer ii;
326
 
327
  begin
328
    wait (~WishboneBusy);
329
    WishboneBusy = 1;
330
    @ (posedge WB_CLK_I);
331
    #1;
332
    WB_ADR_I = Address;
333
    WB_DAT_I = Data;
334
    WB_WE_I  = 1'b1;
335
    WB_CYC_I = 1'b1;
336
    WB_STB_I = 1'b1;
337
    WB_SEL_I = 4'hf;
338
 
339 19 mohor
    wait(WB_ACK_O);   // waiting for acknowledge response
340
 
341
    // Writing information about the access to the screen
342 15 mohor
    @ (posedge WB_CLK_I);
343 23 mohor
      if(~Address[11] & ~Address[10])
344 22 mohor
        $write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
345 15 mohor
      else
346 23 mohor
      if(~Address[11] & Address[10])
347 36 mohor
        if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
348 15 mohor
          begin
349 22 mohor
            $write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address);
350 23 mohor
            if(Data[9])
351 15 mohor
              $write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);
352
          end
353
        else
354 22 mohor
          $write("\nWrite to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
355 15 mohor
      else
356 22 mohor
        $write("\nWB write ??????????????     Data: 0x%x      Addr: 0x%0x", Data, Address);
357 15 mohor
    #1;
358
    WB_ADR_I = 32'hx;
359
    WB_DAT_I = 32'hx;
360
    WB_WE_I  = 1'bx;
361
    WB_CYC_I = 1'b0;
362
    WB_STB_I = 1'b0;
363
    WB_SEL_I = 4'hx;
364
    #5 WishboneBusy = 0;
365
  end
366
endtask
367
 
368
 
369
task WishboneRead;
370
  input [31:0] Address;
371
  reg   [31:0] Data;
372
  integer ii;
373
 
374
  begin
375
    wait (~WishboneBusy);
376
    WishboneBusy = 1;
377
    @ (posedge WB_CLK_I);
378
    #1;
379
    WB_ADR_I = Address;
380
    WB_WE_I  = 1'b0;
381
    WB_CYC_I = 1'b1;
382
    WB_STB_I = 1'b1;
383
    WB_SEL_I = 4'hf;
384
 
385
    for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1)   // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
386
    begin
387
      @ (posedge WB_CLK_I);
388
      Data = WB_DAT_O;
389
    end
390
 
391
    if(ii==20)
392
      begin
393
        $display("\nERROR: Task WishboneRead(Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)",
394
          Address, $time);
395
        #50 $stop;
396
      end
397
 
398
    @ (posedge WB_CLK_I);
399 23 mohor
      if(~Address[11] & ~Address[10])
400 22 mohor
        $write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
401 15 mohor
      else
402 23 mohor
      if(~Address[11] & Address[10])
403 36 mohor
        if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
404 15 mohor
          begin
405 22 mohor
            $write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address);
406 15 mohor
          end
407
        else
408 22 mohor
          $write("\nRead from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
409 15 mohor
      else
410 22 mohor
        $write("\nWB read  ?????????    Data: 0x%x      Addr: 0x%0x", Data, Address);
411 15 mohor
    #1;
412
    WB_ADR_I = 32'hx;
413
    WB_WE_I  = 1'bx;
414
    WB_CYC_I = 1'b0;
415
    WB_STB_I = 1'b0;
416
    WB_SEL_I = 4'hx;
417
    #5 WishboneBusy = 0;
418
  end
419
endtask
420
 
421
 
422
 
423
 
424
task SendPacket;
425
  input [15:0]  Length;
426
  input         ControlFrame;
427
  reg           Wrap;
428
  reg [31:0]    TempAddr;
429
  reg [31:0]    TempData;
430
 
431
  begin
432
    if(TxBDIndex == 3)    // Only 4 buffer descriptors are used
433
      Wrap = 1'b1;
434
    else
435
      Wrap = 1'b0;
436
 
437 23 mohor
    TempAddr = {22'h01, (TxBDIndex<<2)};
438 22 mohor
    TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]};  // Ready and Wrap = 1
439 15 mohor
 
440
    #1;
441
    if(TxBDIndex == 3)    // Only 4 buffer descriptors are used
442
      TxBDIndex = 0;
443
    else
444
      TxBDIndex = TxBDIndex + 1;
445
 
446
    fork
447
      begin
448
        WishboneWrite(TempData, TempAddr); // Writing status to TxBD
449
      end
450
 
451
      begin
452
        if(~ControlFrame)
453
        WaitingForTxDMARequest(4'h1, Length); // Delay, DMALength
454
      end
455
    join
456
  end
457
endtask
458
 
459
 
460
 
461
task ReceivePacket;    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
462
  input [15:0] LengthRx;
463
  input        RxControlFrame;
464
  reg        WrapRx;
465
  reg [31:0] TempRxAddr;
466
  reg [31:0] TempRxData;
467
  reg abc;
468
  begin
469
    if(RxBDIndex == 3)    // Only 4 buffer descriptors are used
470
      WrapRx = 1'b1;
471
    else
472
      WrapRx = 1'b0;
473
 
474 36 mohor
    TempRxAddr = {22'h01, ((tb_eth_top.ethtop.r_TxBDNum + RxBDIndex)<<2)};
475 15 mohor
 
476 22 mohor
    TempRxData = {LengthRx[15:0], 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]};  // Ready and WrapRx = 1 or 0
477 15 mohor
 
478
    #1;
479
    if(RxBDIndex == 3)    // Only 4 buffer descriptors are used
480
      RxBDIndex = 0;
481
    else
482
      RxBDIndex = RxBDIndex + 1;
483
 
484
    abc=1;
485
    WishboneWrite(TempRxData, TempRxAddr); // Writing status to RxBD
486
    abc=0;
487
    fork
488
      begin
489
        #200;
490
        if(RxControlFrame)
491
          GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.
492
        else
493
          GetDataOnMRxD(LengthRx); // LengthRx bytes is comming on MRxD[3:0] signals
494
      end
495
 
496
      begin
497
        if(RxControlFrame)
498
          WaitingForRxDMARequest(4'h1, 16'h40); // Delay, DMALength = 64 bytes.
499
        else
500
          WaitingForRxDMARequest(4'h1, LengthRx); // Delay, DMALength
501
      end
502
    join
503
  end
504
endtask
505
 
506
 
507
 
508
task WaitingForTxDMARequest;
509
  input [3:0] Delay;
510
  input [15:0] DMALength;
511
  integer pp;
512
  reg [7:0]a, b, c, d;
513
 
514
  for(pp=0; pp*4<DMALength; pp=pp+1)
515
  begin
516
    a = 4*pp[7:0]+3;
517
    b = 4*pp[7:0]+2;
518
    c = 4*pp[7:0]+1;
519
    d = 4*pp[7:0]  ;
520
    @ (posedge WB_REQ_O[0]);
521
    repeat(Delay) @(posedge WB_CLK_I);
522
 
523
    wait (~WishboneBusy);
524
    WishboneBusy = 1;
525
    #1;
526
    WB_DAT_I = {a, b, c, d};
527 23 mohor
    WB_ADR_I = {22'h02, pp[9:0]};
528 15 mohor
    $display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);
529
 
530
    WB_WE_I  = 1'b1;
531
    WB_CYC_I = 1'b1;
532
    WB_STB_I = 1'b1;
533
    WB_SEL_I = 4'hf;
534
    WB_ACK_I[0] = 1'b1;
535
 
536
    @ (posedge WB_CLK_I);
537
    #1;
538
    WB_ADR_I = 32'hx;
539
    WB_DAT_I = 32'hx;
540
    WB_WE_I  = 1'bx;
541
    WB_CYC_I = 1'b0;
542
    WB_STB_I = 1'b0;
543
    WB_SEL_I = 4'hx;
544
    WB_ACK_I[0] = 1'b0;
545
    #5 WishboneBusy = 0;
546
  end
547
endtask
548
 
549
 
550
task WaitingForRxDMARequest;
551
  input [3:0] Delay;
552
  input [15:0] DMALengthRx;
553
  integer rr;
554
 
555
  for(rr=0; rr*4<DMALengthRx; rr=rr+1)
556
  begin
557
    @ (posedge WB_REQ_O[1]);
558
    repeat(Delay) @(posedge WB_CLK_I);
559
 
560
    wait (~WishboneBusy);
561
    WishboneBusy = 1;
562
    #1;
563 23 mohor
    WB_ADR_I = {22'h02, rr[9:0]};
564 15 mohor
    $display("task WaitingForRxDMARequest: rr=%0d, WB_ADR_I=0x%0h, WB_DAT_O=0x%0h", rr, WB_ADR_I, WB_DAT_O);
565
 
566
    WB_WE_I  = 1'b1;
567
    WB_CYC_I = 1'b1;
568
    WB_STB_I = 1'b1;
569
    WB_SEL_I = 4'hf;
570
    WB_ACK_I[1] = 1'b1;
571
 
572
    @ (posedge WB_CLK_I);
573
    #1;
574
    WB_ADR_I = 32'hx;
575
    WB_WE_I  = 1'bx;
576
    WB_CYC_I = 1'b0;
577
    WB_STB_I = 1'b0;
578
    WB_SEL_I = 4'hx;
579
    WB_ACK_I[1] = 1'b0;
580
    #5 WishboneBusy = 0;
581
  end
582
endtask
583
 
584
 
585
 
586
task GetDataOnMRxD;
587
  input [15:0] Len;
588
  integer tt;
589
 
590
  begin
591
    @ (posedge MRxClk);
592
    MRxDV=1'b1;
593
 
594
    for(tt=0; tt<15; tt=tt+1)
595
    begin
596
      MRxD=4'h5;              // preamble
597
      @ (posedge MRxClk);
598
    end
599
    MRxD=4'hd;                // SFD
600
 
601
    for(tt=0; tt<Len; tt=tt+1)
602
    begin
603
      @ (posedge MRxClk);
604
      MRxD=tt[3:0];
605
      @ (posedge MRxClk);
606
      MRxD=tt[7:4];
607
    end
608
    @ (posedge MRxClk);
609
    MRxDV=1'b0;
610
  end
611
endtask
612
 
613
 
614
task GetControlDataOnMRxD;
615
  input [15:0] Timer;
616
  reg [127:0] Packet;
617
  reg [127:0] Data;
618
  reg [31:0] Crc;
619
  integer tt;
620
 
621
  begin
622
  Packet = 128'h10082C000010_deadbeef0013_8880_0010; // 0180c2000001 + 8808 + 0001
623
  Crc = 32'h6014fe08; // not a correct value
624
 
625
    @ (posedge MRxClk);
626
    MRxDV=1'b1;
627
 
628
    for(tt=0; tt<15; tt=tt+1)
629
    begin
630
      MRxD=4'h5;              // preamble
631
      @ (posedge MRxClk);
632
    end
633
    MRxD=4'hd;                // SFD
634
 
635
    for(tt=0; tt<32; tt=tt+1)
636
    begin
637
      Data = Packet << (tt*4);
638
      @ (posedge MRxClk);
639
      MRxD=Data[127:124];
640
    end
641
 
642
    for(tt=0; tt<2; tt=tt+1)    // timer
643
    begin
644
      Data[15:0] = Timer << (tt*8);
645
      @ (posedge MRxClk);
646
      MRxD=Data[11:8];
647
      @ (posedge MRxClk);
648
      MRxD=Data[15:12];
649
    end
650
 
651
    for(tt=0; tt<42; tt=tt+1)   // padding
652
    begin
653
      Data[7:0] = 8'h0;
654
      @ (posedge MRxClk);
655
      MRxD=Data[3:0];
656
      @ (posedge MRxClk);
657
      MRxD=Data[3:0];
658
    end
659
 
660
    for(tt=0; tt<4; tt=tt+1)    // crc
661
    begin
662
      Data[31:0] = Crc << (tt*8);
663
      @ (posedge MRxClk);
664
      MRxD=Data[27:24];
665
      @ (posedge MRxClk);
666
      MRxD=Data[31:28];
667
    end
668
 
669
 
670
 
671
    @ (posedge MRxClk);
672
    MRxDV=1'b0;
673
  end
674
endtask
675
 
676 41 mohor
`else // No WISHBONE_DMA
677 15 mohor
 
678 41 mohor
initial
679
begin
680
  wait(StartTB);  // Start of testbench
681 66 mohor
 
682
  InitializeMemory;
683
 
684
// Select which test you want to run:
685
    TestTxAndRx;
686
  //  TestUnicast;
687
  //  TestBroadcast;
688
  //  TestMulticast;
689 51 billditt
end
690 66 mohor
 
691
task TestTxAndRx;
692 51 billditt
 begin
693 66 mohor
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 1
694
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 0
695
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
696 51 billditt
 
697 66 mohor
  WishboneWrite(32'h00002463, {26'h0, `ETH_MODER_ADR<<2});     // RxEn, Txen, CrcEn, Pad off, full duplex, r_IFG, promisc ON
698 51 billditt
 
699 66 mohor
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
700 51 billditt
 
701 66 mohor
  SendPacket(16'h0007, 1'b0);
702 51 billditt
  SendPacket(16'h0011, 1'b0);
703
  SendPacket(16'h0012, 1'b0);
704
  SendPacket(16'h0013, 1'b0);
705
  SendPacket(16'h0014, 1'b0);
706 15 mohor
 
707 51 billditt
  SendPacket(16'h0030, 1'b0);
708
  SendPacket(16'h0031, 1'b0);
709
  SendPacket(16'h0032, 1'b0);
710
  SendPacket(16'h0033, 1'b0);
711
  SendPacket(16'h0025, 1'b0);
712
  SendPacket(16'h0045, 1'b0);
713
  SendPacket(16'h0025, 1'b0);
714
  SendPacket(16'h0017, 1'b0);
715 41 mohor
 
716 66 mohor
  ReceivePacket(16'h0015, 1'b0, `MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
717
  ReceivePacket(16'h0016, 1'b0, `MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
718
  ReceivePacket(16'h0017, 1'b0, `MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
719
  ReceivePacket(16'h0018, 1'b0, `MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
720 41 mohor
 
721 51 billditt
  repeat(5000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
722 49 mohor
 
723 51 billditt
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
724
 
725
  WishboneRead({24'h04, (8'h0<<2)});       // Read from TxBD register
726
  WishboneRead({24'h04, (8'h1<<2)});       // Read from TxBD register
727
  WishboneRead({24'h04, (8'h2<<2)});       // Read from TxBD register
728
  WishboneRead({24'h04, (8'h3<<2)});       // Read from TxBD register
729
  WishboneRead({24'h04, (8'h4<<2)});       // Read from TxBD register
730
 
731
 
732
  WishboneRead({22'h01, (10'h80<<2)});       // Read from RxBD register
733
  WishboneRead({22'h01, (10'h81<<2)});       // Read from RxBD register
734
  WishboneRead({22'h01, (10'h82<<2)});       // Read from RxBD register
735
  WishboneRead({22'h01, (10'h83<<2)});       // Read from RxBD register
736
  WishboneRead({22'h01, (10'h84<<2)});       // Read from RxBD register
737
  WishboneRead({22'h01, (10'h85<<2)});       // Read from RxBD register
738
  WishboneRead({22'h01, (10'h86<<2)});       // Read from RxBD register
739
  WishboneRead({22'h01, (10'h87<<2)});       // Read from RxBD register
740 66 mohor
 
741 51 billditt
  #100000 $stop;
742 66 mohor
 end
743
endtask //TestTxAndRx
744 51 billditt
 
745 66 mohor
 
746 51 billditt
task TestUnicast;
747
 begin
748
  $display("\nBegin TestUnicast \n");
749
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 1
750
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 0
751
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
752 66 mohor
  WishboneWrite(32'h00002043, {26'h0, `ETH_MODER_ADR, 2'h0});     // RxEn, Txen, CrcEn, no Pad, r_IFG, promisc off, broadcast on
753 51 billditt
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); //r_TxFlow = 1
754
 
755 66 mohor
  $display("\n This Uniicast packet will be rejected, wrong address in MAC Address Regs\n");
756 51 billditt
 
757 66 mohor
  ReceivePacket(16'h0014, 1'b0,`UNICAST_XFR);
758 51 billditt
 
759
  WishboneWrite(32'h04030200, {26'h0,`ETH_MAC_ADDR0_ADR ,2'h0}); // Mac Address 
760
  WishboneWrite(32'h00000605, {26'h0,`ETH_MAC_ADDR1_ADR ,2'h0}); // Mac Address
761
 
762
  $display("\n Set Proper Unicast Address in MAC_ADDRESS regs, resend packet\n");
763
 
764 66 mohor
  ReceivePacket(16'h0015, 1'b0,`UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
765
  ReceivePacket(16'h0016, 1'b0,`UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
766
  ReceivePacket(16'h0017, 1'b0,`UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
767
  ReceivePacket(16'h0018, 1'b0,`UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
768 41 mohor
 
769
  repeat(5000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
770
 
771
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
772
 
773
  WishboneRead({22'h01, (10'h80<<2)});       // Read from RxBD register
774
  WishboneRead({22'h01, (10'h81<<2)});       // Read from RxBD register
775
  WishboneRead({22'h01, (10'h82<<2)});       // Read from RxBD register
776
  WishboneRead({22'h01, (10'h83<<2)});       // Read from RxBD register
777
  WishboneRead({22'h01, (10'h84<<2)});       // Read from RxBD register
778
  WishboneRead({22'h01, (10'h85<<2)});       // Read from RxBD register
779
  WishboneRead({22'h01, (10'h86<<2)});       // Read from RxBD register
780
  WishboneRead({22'h01, (10'h87<<2)});       // Read from RxBD register
781 66 mohor
  WishboneRead({22'h01, (10'h88<<2)});       // Read from RxBD register
782
  WishboneRead({22'h01, (10'h89<<2)});       // Read from RxBD register
783 51 billditt
 
784
  #100000 $stop;
785
  $display("\nEnd TestUnicast \n");
786
end
787
endtask //TestUnicast
788 41 mohor
 
789 51 billditt
task TestMulticast;
790
 begin
791
  $display("\nBegin TestMulticast \n");
792
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 1
793
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 0
794
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
795 66 mohor
  WishboneWrite(32'h00002043, {26'h0, `ETH_MODER_ADR, 2'h0});     // RxEn, Txen, CrcEn, No Pad, r_IFG, promiscuos off, broadcast enable
796
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); // r_TxFlow = 1
797 51 billditt
 
798 66 mohor
  $display("\n This Multicast packet will be rejected by Hash Filter\n");
799 51 billditt
 
800 66 mohor
  ReceivePacket(16'h0014, 1'b0,`MULTICAST_XFR);
801 51 billditt
 
802
  WishboneWrite(32'h00400000, {26'h0, `ETH_HASH1_ADR,2'h0}); // set bit 16, multicast hash 36
803 66 mohor
  WishboneRead({26'h0, `ETH_HASH1_ADR, 2'h0});  // read back
804 51 billditt
 
805
  $display("\n Set Hash Filter to accept this Multicast packet, resend packet\n");
806
 
807 66 mohor
  ReceivePacket(16'h0015, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
808
  ReceivePacket(16'h0016, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
809
  ReceivePacket(16'h0017, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
810
  ReceivePacket(16'h0018, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
811 51 billditt
 
812
  repeat(5000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
813
 
814
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
815
 
816
  WishboneRead({22'h01, (10'h80<<2)});       // Read from RxBD register
817
  WishboneRead({22'h01, (10'h81<<2)});       // Read from RxBD register
818
  WishboneRead({22'h01, (10'h82<<2)});       // Read from RxBD register
819
  WishboneRead({22'h01, (10'h83<<2)});       // Read from RxBD register
820
  WishboneRead({22'h01, (10'h84<<2)});       // Read from RxBD register
821
  WishboneRead({22'h01, (10'h85<<2)});       // Read from RxBD register
822
  WishboneRead({22'h01, (10'h86<<2)});       // Read from RxBD register
823
  WishboneRead({22'h01, (10'h87<<2)});       // Read from RxBD register
824
 
825 66 mohor
  $display("\nEnd TestMulticast \n");
826 41 mohor
  #100000 $stop;
827
end
828 51 billditt
endtask //TestMulticast
829 41 mohor
 
830
 
831 51 billditt
task TestBroadcast;
832
 begin
833 66 mohor
  $display("\n\n\nBegin TestBroadcast");
834 51 billditt
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 1
835
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 0
836
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
837 41 mohor
 
838 66 mohor
  WishboneWrite(32'h0000A04b, {26'h0, `ETH_MODER_ADR, 2'h0});     // PadEn, CrcEn, IFG=accept, Reject Broadcast, TxEn, RxEn
839
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); // r_TxFlow = 1
840 51 billditt
 
841 66 mohor
  $display("\nThis Broadcast packet will be rejected, r_BRO = 1");
842
  ReceivePacket(16'h0014, 1'b0,`BROADCAST_XFR);
843 51 billditt
 
844 66 mohor
  $display("\nSet r_Bro = 0, resend packet");
845
  WishboneWrite(32'h0000A043, {26'h0, `ETH_MODER_ADR, 2'h0});  // PadEn, CrcEn, IFG=accept, Accept Broadcast, TxEn, RxEn
846
  ReceivePacket(16'h0015, 1'b0,`BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
847 51 billditt
 
848 66 mohor
  $display("\n This Broadcast packet will be rejected, r_BRO = 1");
849
  WishboneWrite(32'h0000A04b, {26'h0, `ETH_MODER_ADR, 2'h0});     // PadEn, CrcEn, IFG=accept, Reject Broadcast, TxEn, RxEn
850
  ReceivePacket(16'h0016, 1'b0,`BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
851
  ReceivePacket(16'h0017, 1'b0,`BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
852 51 billditt
 
853 66 mohor
  $display("\n Set r_Bro = 0, resend packet");
854
  WishboneWrite(32'h0000A043, {26'h0, `ETH_MODER_ADR, 2'h0});  // PadEn, CrcEn, IFG=accept, Accept Broadcast, TxEn, RxEn
855
  ReceivePacket(16'h0018, 1'b0,`BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
856 51 billditt
 
857
  repeat(5000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
858
 
859
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
860
 
861
  WishboneRead({22'h01, (10'h80<<2)});       // Read from RxBD register
862
  WishboneRead({22'h01, (10'h81<<2)});       // Read from RxBD register
863
  WishboneRead({22'h01, (10'h82<<2)});       // Read from RxBD register
864
  WishboneRead({22'h01, (10'h83<<2)});       // Read from RxBD register
865
  WishboneRead({22'h01, (10'h84<<2)});       // Read from RxBD register
866
  WishboneRead({22'h01, (10'h85<<2)});       // Read from RxBD register
867
  WishboneRead({22'h01, (10'h86<<2)});       // Read from RxBD register
868
  WishboneRead({22'h01, (10'h87<<2)});       // Read from RxBD register
869
 
870
  #100000 $stop;
871
  $display("\nEnd TestBroadcast \n");
872
end
873
endtask //TestBroadcast
874
 
875
 
876 41 mohor
always @ (posedge WB_CLK_I)
877
begin
878
  if(m_wb_cyc_o & m_wb_stb_o) // Add valid address range
879
    begin
880
      repeat(3) @ (posedge WB_CLK_I);
881
        begin
882 66 mohor
          m_wb_ack_i <=#Tp 1'b1;
883 41 mohor
          if(~m_wb_we_o)
884
            begin
885
              #Tp m_wb_dat_i = m_wb_adr_o + 1'b1; // For easier following of the data
886
              $fdisplay(mcd1, "(%0t) master read (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_i);
887
            end
888
          else
889
            $fdisplay(mcd2, "(%0t) master write (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_o);
890
        end
891
      @ (posedge WB_CLK_I);
892
      m_wb_ack_i <=#Tp 1'b0;
893
    end
894
end
895
 
896
// Generating error
897
always @ (posedge WB_CLK_I)
898
begin
899
  if(m_wb_cyc_o & m_wb_stb_o & ~(&m_wb_sel_o))  // Add false address range
900
    m_wb_err_i <=#Tp 1'b1;
901
end
902
 
903
always @ (posedge WB_CLK_I)
904
  if(tb_eth_top.ethtop.wishbone.RxStatusWrite)
905
    $fdisplay(mcd2, "");  // newline added
906
 
907
task WishboneWrite;
908
  input [31:0] Data;
909
  input [31:0] Address;
910
  integer ii;
911
 
912
  begin
913
    wait (~WishboneBusy);
914
    WishboneBusy = 1;
915
    @ (posedge WB_CLK_I);
916
    #1;
917
    WB_ADR_I = Address;
918
    WB_DAT_I = Data;
919
    WB_WE_I  = 1'b1;
920
    WB_CYC_I = 1'b1;
921
    WB_STB_I = 1'b1;
922
    WB_SEL_I = 4'hf;
923
 
924
 
925
    wait(WB_ACK_O);   // waiting for acknowledge response
926
 
927
    // Writing information about the access to the screen
928
    @ (posedge WB_CLK_I);
929
      if(~Address[11] & ~Address[10])
930
        $write("\n(%0t) Write to register (Data: 0x%x, Reg. Addr: 0x%0x)", $time, Data, Address);
931
      else
932
      if(~Address[11] & Address[10])
933
        if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
934
          begin
935
            $write("\n(%0t) Write to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", $time, Data, Address);
936 66 mohor
            if(Address[9:2] == tb_eth_top.ethtop.r_TxBDNum-2'h2)
937
              $write("(%0t) Send Control packet\n", $time);
938 41 mohor
          end
939
        else
940
          $write("\n(%0t) Write to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", $time, Data, Address);
941
      else
942
        $write("\n(%0t) WB write ??????????????     Data: 0x%x      Addr: 0x%0x", $time, Data, Address);
943
    #1;
944
    WB_ADR_I = 32'hx;
945
    WB_DAT_I = 32'hx;
946
    WB_WE_I  = 1'bx;
947
    WB_CYC_I = 1'b0;
948
    WB_STB_I = 1'b0;
949
    WB_SEL_I = 4'hx;
950
    #5 WishboneBusy = 0;
951
  end
952
endtask
953
 
954
 
955
task WishboneRead;
956
  input [31:0] Address;
957
 
958
  begin
959
    wait (~WishboneBusy);
960
    WishboneBusy = 1;
961
    @ (posedge WB_CLK_I);
962
    #1;
963
    WB_ADR_I = Address;
964
    WB_WE_I  = 1'b0;
965
    WB_CYC_I = 1'b1;
966
    WB_STB_I = 1'b1;
967
    WB_SEL_I = 4'hf;
968
 
969
    wait(WB_ACK_O);   // waiting for acknowledge response
970
    @ (posedge WB_CLK_I);
971
 
972
      if(~Address[11] & ~Address[10])
973
        $write("\n(%0t) Read from register (Data: 0x%x, Reg. Addr: 0x%0x)", $time, WB_DAT_O, Address);
974
      else
975
      if(~Address[11] & Address[10])
976
        if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
977
          begin
978
            $write("\n(%0t) Read from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", $time, WB_DAT_O, Address);
979
          end
980
        else
981
          $write("\n(%0t) Read from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", $time, WB_DAT_O, Address);
982
      else
983
        $write("\n(%0t) WB read  ?????????    Data: 0x%x      Addr: 0x%0x", $time, WB_DAT_O, Address);
984
    #1;
985
    WB_ADR_I = 32'hx;
986
    WB_WE_I  = 1'bx;
987
    WB_CYC_I = 1'b0;
988
    WB_STB_I = 1'b0;
989
    WB_SEL_I = 4'hx;
990
    #5 WishboneBusy = 0;
991
  end
992
endtask
993
 
994
 
995
 
996
 
997
task SendPacket;
998
  input [15:0]  Length;
999
  input         ControlFrame;
1000
  reg           Wrap;
1001
  reg [31:0]    TempAddr;
1002
  reg [31:0]    TempData;
1003
 
1004
  begin
1005
//    if(TxBDIndex == 6)    // Only 3 buffer descriptors are used 
1006
//      Wrap = 1'b1;
1007
//    else
1008
      Wrap = 1'b0;    // At the moment no wrap bit is set
1009
 
1010
    // Writing buffer pointer
1011
    TempAddr = {22'h01, ((TxBDIndex + 1'b1)<<2)};
1012
    TempData = 32'h78563411;
1013
    WishboneWrite(TempData, TempAddr); // buffer pointer
1014
 
1015
 
1016 66 mohor
    TempAddr = {22'h01, (TxBDIndex<<2)};
1017 41 mohor
 
1018
    TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]};  // Ready and Wrap = 1
1019
 
1020
    #1;
1021
//    if(TxBDIndex == 6)    // Only 4 buffer descriptors are used
1022
//      TxBDIndex = 0;
1023
//    else
1024
      TxBDIndex = TxBDIndex + 2;
1025
 
1026
    WishboneWrite(TempData, TempAddr); // Writing status to TxBD
1027
  end
1028
endtask
1029
 
1030
 
1031
 
1032
task ReceivePacket;    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
1033
  input [15:0] LengthRx;
1034
  input        RxControlFrame;
1035 51 billditt
  input [31:0] TransferType;  //Broadcast,Unicast,Multicast
1036 41 mohor
  reg        WrapRx;
1037
  reg [31:0] TempRxAddr;
1038
  reg [31:0] TempRxData;
1039
  reg abc;
1040
  begin
1041
//    if(RxBDIndex == 6)    // Only 3 buffer descriptors are used
1042
//      WrapRx = 1'b1;
1043
//    else
1044
      WrapRx = 1'b0;
1045
 
1046
    TempRxAddr = {22'h01, ((tb_eth_top.ethtop.r_TxBDNum + RxBDIndex + 1'b1)<<2)};
1047
    TempRxData = 32'h73507350 + RxBDIndex;
1048
    WishboneWrite(TempRxData, TempRxAddr); // Writing Rx pointer
1049
 
1050
 
1051
    TempRxAddr = {22'h01, ((tb_eth_top.ethtop.r_TxBDNum + RxBDIndex)<<2)};
1052
//    TempRxData = {LengthRx[15:0], 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]};  // Ready and WrapRx = 1 or 0
1053
    TempRxData = {16'h0, 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]};  // Ready and WrapRx = 1 or 0
1054
 
1055
    #1;
1056
//    if(RxBDIndex == 6)    // Only 4 buffer descriptors are used
1057
//      RxBDIndex = 0;
1058
//    else
1059
      RxBDIndex = RxBDIndex + 2;
1060
 
1061
    abc=1;
1062
    WishboneWrite(TempRxData, TempRxAddr); // Writing status to RxBD
1063
    abc=0;
1064
 
1065
      begin
1066
        #200;
1067
        if(RxControlFrame)
1068
          GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.
1069
        else
1070 66 mohor
          GetDataOnMRxD(LengthRx, TransferType); // LengthRx bytes is comming on MRxD[3:0] signals
1071 41 mohor
      end
1072
 
1073
  end
1074
endtask
1075
 
1076
 
1077
task GetDataOnMRxD;
1078
  input [15:0] Len;
1079 51 billditt
  input [31:0] TransferType;
1080 41 mohor
  integer tt;
1081
 
1082
  begin
1083
    @ (posedge MRxClk);
1084
    MRxDV=1'b1;
1085
 
1086
    for(tt=0; tt<15; tt=tt+1)
1087
    begin
1088
      MRxD=4'h5;              // preamble
1089
      @ (posedge MRxClk);
1090
    end
1091
    MRxD=4'hd;                // SFD
1092 51 billditt
 
1093
  for(tt=1; tt<(Len+1); tt=tt+1)
1094
 
1095 41 mohor
    begin
1096 51 billditt
 
1097 41 mohor
      @ (posedge MRxClk);
1098 51 billditt
          if(TransferType == `UNICAST_XFR && tt == 1)
1099
           MRxD= 4'h0;   // Unicast transfer
1100
          else if(TransferType == `BROADCAST_XFR && tt < 7)
1101
           MRxD = 4'hf;
1102
          else
1103
       MRxD=tt[3:0]; // Multicast transfer
1104 66 mohor
 
1105
    @ (posedge MRxClk);
1106 51 billditt
 
1107
           if(TransferType == `BROADCAST_XFR && tt < 7)
1108
            MRxD = 4'hf;
1109
          else
1110
        MRxD=tt[7:4];
1111 41 mohor
    end
1112 51 billditt
 
1113 41 mohor
    @ (posedge MRxClk);
1114
    MRxDV=1'b0;
1115
  end
1116
endtask
1117
 
1118
 
1119
task GetControlDataOnMRxD;
1120
  input [15:0] Timer;
1121
  reg [127:0] Packet;
1122
  reg [127:0] Data;
1123
  reg [31:0] Crc;
1124
  integer tt;
1125
 
1126
  begin
1127 66 mohor
  Packet = 128'h10082C000010_deadbeef0013_8880_0010; // 0180c2000001 + 8808 + 0001
1128 41 mohor
  Crc = 32'h6014fe08; // not a correct value
1129
 
1130
    @ (posedge MRxClk);
1131
    MRxDV=1'b1;
1132
 
1133
    for(tt=0; tt<15; tt=tt+1)
1134
    begin
1135
      MRxD=4'h5;              // preamble
1136
      @ (posedge MRxClk);
1137
    end
1138
    MRxD=4'hd;                // SFD
1139
 
1140
    for(tt=0; tt<32; tt=tt+1)
1141
    begin
1142
      Data = Packet << (tt*4);
1143
      @ (posedge MRxClk);
1144
      MRxD=Data[127:124];
1145
    end
1146
 
1147
    for(tt=0; tt<2; tt=tt+1)    // timer
1148
    begin
1149
      Data[15:0] = Timer << (tt*8);
1150
      @ (posedge MRxClk);
1151
      MRxD=Data[11:8];
1152
      @ (posedge MRxClk);
1153
      MRxD=Data[15:12];
1154
    end
1155
 
1156
    for(tt=0; tt<42; tt=tt+1)   // padding
1157
    begin
1158
      Data[7:0] = 8'h0;
1159
      @ (posedge MRxClk);
1160
      MRxD=Data[3:0];
1161
      @ (posedge MRxClk);
1162
      MRxD=Data[3:0];
1163
    end
1164
 
1165
    for(tt=0; tt<4; tt=tt+1)    // crc
1166
    begin
1167
      Data[31:0] = Crc << (tt*8);
1168
      @ (posedge MRxClk);
1169
      MRxD=Data[27:24];
1170
      @ (posedge MRxClk);
1171
      MRxD=Data[31:28];
1172
    end
1173
 
1174
 
1175
 
1176
    @ (posedge MRxClk);
1177
    MRxDV=1'b0;
1178
  end
1179
endtask
1180 66 mohor
 
1181
task InitializeMemory;
1182
  reg [9:0] mem_addr;
1183
 
1184
  begin
1185
    for(mem_addr=0; mem_addr<=10'h0ff; mem_addr=mem_addr+1'b1)
1186
      WishboneWrite(32'h0, {22'h01, mem_addr<<2}); // Writing status to RxBD
1187
  end
1188
endtask
1189
 
1190
 
1191 41 mohor
`endif
1192
 
1193
 
1194 15 mohor
endmodule

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