OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_eth_top.v] - Blame information for rev 80

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 66 mohor
//////////////////////////////////////////////////////////////////////
2 15 mohor
////                                                              ////
3
////  tb_eth_top.v                                                ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 41 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001 Authors                                   ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 80 mohor
// Revision 1.11  2002/02/16 13:06:59  mohor
45
// EXTERNAL_DMA used instead of WISHBONE_DMA.
46
//
47 67 mohor
// Revision 1.10  2002/02/16 07:22:15  mohor
48
// Testbench fixed, code simplified, unused signals removed.
49
//
50 66 mohor
// Revision 1.9  2002/02/14 20:14:38  billditt
51
// Added separate tests for Multicast, Unicast, Broadcast
52
//
53
// Revision 1.8  2002/02/12 20:24:00  mohor
54
// HASH0 and HASH1 register read/write added.
55
//
56 49 mohor
// Revision 1.7  2002/02/06 14:11:35  mohor
57
// non-DMA host interface added. Select the right configutation in eth_defines.
58
//
59 41 mohor
// Revision 1.6  2001/12/08 12:36:00  mohor
60
// TX_BD_NUM register added instead of the RB_BD_ADDR.
61
//
62 36 mohor
// Revision 1.5  2001/10/19 11:24:04  mohor
63
// Number of addresses (wb_adr_i) minimized.
64
//
65 23 mohor
// Revision 1.4  2001/10/19 08:46:53  mohor
66
// eth_timescale.v changed to timescale.v This is done because of the
67
// simulation of the few cores in a one joined project.
68
//
69 22 mohor
// Revision 1.3  2001/09/24 14:55:49  mohor
70
// Defines changed (All precede with ETH_). Small changes because some
71
// tools generate warnings when two operands are together. Synchronization
72
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
73
// demands).
74
//
75 19 mohor
// Revision 1.2  2001/08/15 14:04:30  mohor
76
// Signal names changed on the top level for easier pad insertion (ASIC).
77
//
78 17 mohor
// Revision 1.1  2001/08/06 14:41:09  mohor
79
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
80
// Include files fixed to contain no path.
81
// File names and module names changed ta have a eth_ prologue in the name.
82
// File eth_timescale.v is used to define timescale
83
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
84
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
85
// and Mdo_OE. The bidirectional signal must be created on the top level. This
86
// is done due to the ASIC tools.
87
//
88 15 mohor
// Revision 1.1  2001/07/30 21:46:09  mohor
89
// Directory structure changed. Files checked and joind together.
90
//
91
//
92
//
93
//
94
//
95
 
96
 
97
 
98
`include "eth_defines.v"
99 22 mohor
`include "timescale.v"
100 15 mohor
 
101
module tb_eth_top();
102
 
103
 
104
parameter Tp = 1;
105
 
106
 
107
reg           WB_CLK_I;
108
reg           WB_RST_I;
109
reg   [31:0]  WB_DAT_I;
110
 
111
reg   [31:0]  WB_ADR_I;
112
reg    [3:0]  WB_SEL_I;
113
reg           WB_WE_I;
114
reg           WB_CYC_I;
115
reg           WB_STB_I;
116
 
117
wire  [31:0]  WB_DAT_O;
118
wire          WB_ACK_O;
119
wire          WB_ERR_O;
120 41 mohor
reg    [1:0]  WB_ACK_I;
121
 
122 67 mohor
`ifdef EXTERNAL_DMA
123 15 mohor
wire   [1:0]  WB_REQ_O;
124
wire   [1:0]  WB_ND_O;
125
wire          WB_RD_O;
126 41 mohor
`else
127
// WISHBONE master
128
wire    [31:0]    m_wb_adr_o;
129
wire     [3:0]    m_wb_sel_o;
130
wire              m_wb_we_o;
131
reg     [31:0]    m_wb_dat_i;
132
wire    [31:0]    m_wb_dat_o;
133
wire              m_wb_cyc_o;
134
wire              m_wb_stb_o;
135
reg               m_wb_ack_i;
136
reg               m_wb_err_i;
137
`endif
138 15 mohor
 
139
reg           MTxClk;
140
wire   [3:0]  MTxD;
141
wire          MTxEn;
142
wire          MTxErr;
143
 
144
reg           MRxClk;
145
reg    [3:0]  MRxD;
146
reg           MRxDV;
147
reg           MRxErr;
148
reg           MColl;
149
reg           MCrs;
150
 
151
reg           Mdi_I;
152
wire          Mdo_O;
153
wire          Mdo_OE;
154
wire          Mdc_O;
155
 
156
 
157
 
158
reg WishboneBusy;
159
reg StartTB;
160
reg [9:0] TxBDIndex;
161
reg [9:0] RxBDIndex;
162
 
163 67 mohor
`ifdef EXTERNAL_DMA
164 41 mohor
`else
165
  integer mcd1;
166
  integer mcd2;
167
`endif
168 15 mohor
 
169
// Connecting Ethernet top module
170
 
171
eth_top ethtop
172
(
173
  // WISHBONE common
174 17 mohor
  .wb_clk_i(WB_CLK_I), .wb_rst_i(WB_RST_I), .wb_dat_i(WB_DAT_I), .wb_dat_o(WB_DAT_O),
175 15 mohor
 
176
  // WISHBONE slave
177 23 mohor
        .wb_adr_i(WB_ADR_I[11:2]), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I),   .wb_cyc_i(WB_CYC_I),
178 80 mohor
        .wb_stb_i(WB_STB_I),       .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O),
179 41 mohor
 
180 67 mohor
`ifdef EXTERNAL_DMA
181 80 mohor
        .wb_ack_i(WB_ACK_I), .wb_req_o(WB_REQ_O), .wb_nd_o(WB_ND_O),   .wb_rd_o(WB_RD_O),
182 41 mohor
`else
183
// WISHBONE master
184
  .m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o), .m_wb_dat_i(m_wb_dat_i),
185
  .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o), .m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i),
186
  .m_wb_err_i(m_wb_err_i),
187
`endif
188 15 mohor
 
189
  //TX
190 19 mohor
  .mtx_clk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
191 15 mohor
 
192
  //RX
193 19 mohor
  .mrx_clk_pad_i(MRxClk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
194 17 mohor
  .mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),
195 15 mohor
 
196
  // MIIM
197 22 mohor
  .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoen_o(Mdo_OE),
198
 
199
  .int_o()
200 15 mohor
);
201
 
202
 
203
 
204
 
205
 
206
 
207
 
208
initial
209
begin
210
  WB_CLK_I  =  1'b0;
211 19 mohor
  WB_DAT_I  = 32'h0;
212
  WB_ADR_I  = 32'h0;
213
  WB_SEL_I  =  4'h0;
214
  WB_WE_I   =  1'b0;
215 15 mohor
  WB_CYC_I  =  1'b0;
216
  WB_STB_I  =  1'b0;
217 41 mohor
 
218 67 mohor
`ifdef EXTERNAL_DMA
219 15 mohor
  WB_ACK_I  =  2'h0;
220 41 mohor
`else
221
  m_wb_ack_i = 0;
222
  m_wb_err_i = 0;
223
`endif
224 15 mohor
  MTxClk    =  1'b0;
225
  MRxClk    =  1'b0;
226
  MRxD      =  4'h0;
227
  MRxDV     =  1'b0;
228
  MRxErr    =  1'b0;
229
  MColl     =  1'b0;
230
  MCrs      =  1'b0;
231
  Mdi_I     =  1'b0;
232
 
233
  WishboneBusy = 1'b0;
234
  TxBDIndex = 10'h0;
235
  RxBDIndex = 10'h0;
236
end
237
 
238
 
239
// Reset pulse
240
initial
241
begin
242 67 mohor
`ifdef EXTERNAL_DMA
243 41 mohor
`else
244
  mcd1 = $fopen("ethernet_tx.log");
245
  mcd2 = $fopen("ethernet_rx.log");
246
`endif
247
  WB_RST_I =  1'b1;
248 15 mohor
  #100 WB_RST_I =  1'b0;
249
  #100 StartTB  =  1'b1;
250
end
251
 
252
 
253
 
254
// Generating WB_CLK_I clock
255
always
256
begin
257 41 mohor
//  forever #2.5 WB_CLK_I = ~WB_CLK_I;  // 2*2.5 ns -> 200.0 MHz    
258 19 mohor
//  forever #5 WB_CLK_I = ~WB_CLK_I;  // 2*5 ns -> 100.0 MHz    
259 15 mohor
//  forever #10 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 50.0 MHz    
260
  forever #15 WB_CLK_I = ~WB_CLK_I;  // 2*10 ns -> 33.3 MHz    
261
//  forever #18 WB_CLK_I = ~WB_CLK_I;  // 2*18 ns -> 27.7 MHz    
262 41 mohor
//  forever #25 WB_CLK_I = ~WB_CLK_I;  // 2*25 ns -> 20.0 MHz
263
//  forever #50 WB_CLK_I = ~WB_CLK_I;  // 2*50 ns -> 10.0 MHz
264
//  forever #55 WB_CLK_I = ~WB_CLK_I;  // 2*55 ns ->  9.1 MHz    
265 15 mohor
end
266
 
267
// Generating MTxClk clock
268
always
269
begin
270
  #3 forever #20 MTxClk = ~MTxClk;   // 2*20 ns -> 25 MHz
271
//  #3 forever #200 MTxClk = ~MTxClk;
272
end
273
 
274
// Generating MRxClk clock
275
always
276
begin
277
  #16 forever #20 MRxClk = ~MRxClk;   // 2*20 ns -> 25 MHz
278
//  #16 forever #250 MRxClk = ~MRxClk;
279
end
280
 
281 67 mohor
`ifdef EXTERNAL_DMA
282 15 mohor
initial
283
begin
284
  wait(StartTB);  // Start of testbench
285
 
286 22 mohor
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 1
287
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 0
288 36 mohor
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
289 22 mohor
  WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR<<2});     // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
290
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
291 15 mohor
 
292
  SendPacket(16'h0015, 1'b0);
293
  SendPacket(16'h0043, 1'b1);   // Control frame
294
  SendPacket(16'h0025, 1'b0);
295
  SendPacket(16'h0045, 1'b0);
296
  SendPacket(16'h0025, 1'b0);
297
 
298
  ReceivePacket(16'h0012, 1'b1);    // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
299
  ReceivePacket(16'h0011, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
300
  ReceivePacket(16'h0016, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
301
  ReceivePacket(16'h0017, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
302
  ReceivePacket(16'h0018, 1'b0);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
303
 
304
 
305 22 mohor
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
306 15 mohor
 
307 23 mohor
  WishboneRead({24'h04, (8'h0<<2)});       // Read from TxBD register
308
  WishboneRead({24'h04, (8'h1<<2)});       // Read from TxBD register
309
  WishboneRead({24'h04, (8'h2<<2)});       // Read from TxBD register
310
  WishboneRead({24'h04, (8'h3<<2)});       // Read from TxBD register
311
  WishboneRead({24'h04, (8'h4<<2)});       // Read from TxBD register
312 15 mohor
 
313 23 mohor
  WishboneRead({22'h01, (10'h80<<2)});       // Read from RxBD register
314
  WishboneRead({22'h01, (10'h81<<2)});       // Read from RxBD register
315
  WishboneRead({22'h01, (10'h82<<2)});       // Read from RxBD register
316
  WishboneRead({22'h01, (10'h83<<2)});       // Read from RxBD register
317
  WishboneRead({22'h01, (10'h84<<2)});       // Read from RxBD register
318 15 mohor
 
319
  #10000 $stop;
320
end
321
 
322
 
323
 
324
 
325
 
326
 
327
 
328
task WishboneWrite;
329
  input [31:0] Data;
330
  input [31:0] Address;
331
  integer ii;
332
 
333
  begin
334
    wait (~WishboneBusy);
335
    WishboneBusy = 1;
336
    @ (posedge WB_CLK_I);
337
    #1;
338
    WB_ADR_I = Address;
339
    WB_DAT_I = Data;
340
    WB_WE_I  = 1'b1;
341
    WB_CYC_I = 1'b1;
342
    WB_STB_I = 1'b1;
343
    WB_SEL_I = 4'hf;
344
 
345 19 mohor
    wait(WB_ACK_O);   // waiting for acknowledge response
346
 
347
    // Writing information about the access to the screen
348 15 mohor
    @ (posedge WB_CLK_I);
349 23 mohor
      if(~Address[11] & ~Address[10])
350 22 mohor
        $write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
351 15 mohor
      else
352 23 mohor
      if(~Address[11] & Address[10])
353 36 mohor
        if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
354 15 mohor
          begin
355 22 mohor
            $write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address);
356 23 mohor
            if(Data[9])
357 15 mohor
              $write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);
358
          end
359
        else
360 22 mohor
          $write("\nWrite to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
361 15 mohor
      else
362 22 mohor
        $write("\nWB write ??????????????     Data: 0x%x      Addr: 0x%0x", Data, Address);
363 15 mohor
    #1;
364
    WB_ADR_I = 32'hx;
365
    WB_DAT_I = 32'hx;
366
    WB_WE_I  = 1'bx;
367
    WB_CYC_I = 1'b0;
368
    WB_STB_I = 1'b0;
369
    WB_SEL_I = 4'hx;
370
    #5 WishboneBusy = 0;
371
  end
372
endtask
373
 
374
 
375
task WishboneRead;
376
  input [31:0] Address;
377
  reg   [31:0] Data;
378
  integer ii;
379
 
380
  begin
381
    wait (~WishboneBusy);
382
    WishboneBusy = 1;
383
    @ (posedge WB_CLK_I);
384
    #1;
385
    WB_ADR_I = Address;
386
    WB_WE_I  = 1'b0;
387
    WB_CYC_I = 1'b1;
388
    WB_STB_I = 1'b1;
389
    WB_SEL_I = 4'hf;
390
 
391
    for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1)   // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
392
    begin
393
      @ (posedge WB_CLK_I);
394
      Data = WB_DAT_O;
395
    end
396
 
397
    if(ii==20)
398
      begin
399
        $display("\nERROR: Task WishboneRead(Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)",
400
          Address, $time);
401
        #50 $stop;
402
      end
403
 
404
    @ (posedge WB_CLK_I);
405 23 mohor
      if(~Address[11] & ~Address[10])
406 22 mohor
        $write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address);
407 15 mohor
      else
408 23 mohor
      if(~Address[11] & Address[10])
409 36 mohor
        if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
410 15 mohor
          begin
411 22 mohor
            $write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address);
412 15 mohor
          end
413
        else
414 22 mohor
          $write("\nRead from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address);
415 15 mohor
      else
416 22 mohor
        $write("\nWB read  ?????????    Data: 0x%x      Addr: 0x%0x", Data, Address);
417 15 mohor
    #1;
418
    WB_ADR_I = 32'hx;
419
    WB_WE_I  = 1'bx;
420
    WB_CYC_I = 1'b0;
421
    WB_STB_I = 1'b0;
422
    WB_SEL_I = 4'hx;
423
    #5 WishboneBusy = 0;
424
  end
425
endtask
426
 
427
 
428
 
429
 
430
task SendPacket;
431
  input [15:0]  Length;
432
  input         ControlFrame;
433
  reg           Wrap;
434
  reg [31:0]    TempAddr;
435
  reg [31:0]    TempData;
436
 
437
  begin
438
    if(TxBDIndex == 3)    // Only 4 buffer descriptors are used
439
      Wrap = 1'b1;
440
    else
441
      Wrap = 1'b0;
442
 
443 23 mohor
    TempAddr = {22'h01, (TxBDIndex<<2)};
444 22 mohor
    TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]};  // Ready and Wrap = 1
445 15 mohor
 
446
    #1;
447
    if(TxBDIndex == 3)    // Only 4 buffer descriptors are used
448
      TxBDIndex = 0;
449
    else
450
      TxBDIndex = TxBDIndex + 1;
451
 
452
    fork
453
      begin
454
        WishboneWrite(TempData, TempAddr); // Writing status to TxBD
455
      end
456
 
457
      begin
458
        if(~ControlFrame)
459
        WaitingForTxDMARequest(4'h1, Length); // Delay, DMALength
460
      end
461
    join
462
  end
463
endtask
464
 
465
 
466
 
467
task ReceivePacket;    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
468
  input [15:0] LengthRx;
469
  input        RxControlFrame;
470
  reg        WrapRx;
471
  reg [31:0] TempRxAddr;
472
  reg [31:0] TempRxData;
473
  reg abc;
474
  begin
475
    if(RxBDIndex == 3)    // Only 4 buffer descriptors are used
476
      WrapRx = 1'b1;
477
    else
478
      WrapRx = 1'b0;
479
 
480 36 mohor
    TempRxAddr = {22'h01, ((tb_eth_top.ethtop.r_TxBDNum + RxBDIndex)<<2)};
481 15 mohor
 
482 22 mohor
    TempRxData = {LengthRx[15:0], 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]};  // Ready and WrapRx = 1 or 0
483 15 mohor
 
484
    #1;
485
    if(RxBDIndex == 3)    // Only 4 buffer descriptors are used
486
      RxBDIndex = 0;
487
    else
488
      RxBDIndex = RxBDIndex + 1;
489
 
490
    abc=1;
491
    WishboneWrite(TempRxData, TempRxAddr); // Writing status to RxBD
492
    abc=0;
493
    fork
494
      begin
495
        #200;
496
        if(RxControlFrame)
497
          GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.
498
        else
499
          GetDataOnMRxD(LengthRx); // LengthRx bytes is comming on MRxD[3:0] signals
500
      end
501
 
502
      begin
503
        if(RxControlFrame)
504
          WaitingForRxDMARequest(4'h1, 16'h40); // Delay, DMALength = 64 bytes.
505
        else
506
          WaitingForRxDMARequest(4'h1, LengthRx); // Delay, DMALength
507
      end
508
    join
509
  end
510
endtask
511
 
512
 
513
 
514
task WaitingForTxDMARequest;
515
  input [3:0] Delay;
516
  input [15:0] DMALength;
517
  integer pp;
518
  reg [7:0]a, b, c, d;
519
 
520
  for(pp=0; pp*4<DMALength; pp=pp+1)
521
  begin
522
    a = 4*pp[7:0]+3;
523
    b = 4*pp[7:0]+2;
524
    c = 4*pp[7:0]+1;
525
    d = 4*pp[7:0]  ;
526
    @ (posedge WB_REQ_O[0]);
527
    repeat(Delay) @(posedge WB_CLK_I);
528
 
529
    wait (~WishboneBusy);
530
    WishboneBusy = 1;
531
    #1;
532
    WB_DAT_I = {a, b, c, d};
533 23 mohor
    WB_ADR_I = {22'h02, pp[9:0]};
534 15 mohor
    $display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);
535
 
536
    WB_WE_I  = 1'b1;
537
    WB_CYC_I = 1'b1;
538
    WB_STB_I = 1'b1;
539
    WB_SEL_I = 4'hf;
540
    WB_ACK_I[0] = 1'b1;
541
 
542
    @ (posedge WB_CLK_I);
543
    #1;
544
    WB_ADR_I = 32'hx;
545
    WB_DAT_I = 32'hx;
546
    WB_WE_I  = 1'bx;
547
    WB_CYC_I = 1'b0;
548
    WB_STB_I = 1'b0;
549
    WB_SEL_I = 4'hx;
550
    WB_ACK_I[0] = 1'b0;
551
    #5 WishboneBusy = 0;
552
  end
553
endtask
554
 
555
 
556
task WaitingForRxDMARequest;
557
  input [3:0] Delay;
558
  input [15:0] DMALengthRx;
559
  integer rr;
560
 
561
  for(rr=0; rr*4<DMALengthRx; rr=rr+1)
562
  begin
563
    @ (posedge WB_REQ_O[1]);
564
    repeat(Delay) @(posedge WB_CLK_I);
565
 
566
    wait (~WishboneBusy);
567
    WishboneBusy = 1;
568
    #1;
569 23 mohor
    WB_ADR_I = {22'h02, rr[9:0]};
570 15 mohor
    $display("task WaitingForRxDMARequest: rr=%0d, WB_ADR_I=0x%0h, WB_DAT_O=0x%0h", rr, WB_ADR_I, WB_DAT_O);
571
 
572
    WB_WE_I  = 1'b1;
573
    WB_CYC_I = 1'b1;
574
    WB_STB_I = 1'b1;
575
    WB_SEL_I = 4'hf;
576
    WB_ACK_I[1] = 1'b1;
577
 
578
    @ (posedge WB_CLK_I);
579
    #1;
580
    WB_ADR_I = 32'hx;
581
    WB_WE_I  = 1'bx;
582
    WB_CYC_I = 1'b0;
583
    WB_STB_I = 1'b0;
584
    WB_SEL_I = 4'hx;
585
    WB_ACK_I[1] = 1'b0;
586
    #5 WishboneBusy = 0;
587
  end
588
endtask
589
 
590
 
591
 
592
task GetDataOnMRxD;
593
  input [15:0] Len;
594
  integer tt;
595
 
596
  begin
597
    @ (posedge MRxClk);
598
    MRxDV=1'b1;
599
 
600
    for(tt=0; tt<15; tt=tt+1)
601
    begin
602
      MRxD=4'h5;              // preamble
603
      @ (posedge MRxClk);
604
    end
605
    MRxD=4'hd;                // SFD
606
 
607
    for(tt=0; tt<Len; tt=tt+1)
608
    begin
609
      @ (posedge MRxClk);
610
      MRxD=tt[3:0];
611
      @ (posedge MRxClk);
612
      MRxD=tt[7:4];
613
    end
614
    @ (posedge MRxClk);
615
    MRxDV=1'b0;
616
  end
617
endtask
618
 
619
 
620
task GetControlDataOnMRxD;
621
  input [15:0] Timer;
622
  reg [127:0] Packet;
623
  reg [127:0] Data;
624
  reg [31:0] Crc;
625
  integer tt;
626
 
627
  begin
628
  Packet = 128'h10082C000010_deadbeef0013_8880_0010; // 0180c2000001 + 8808 + 0001
629
  Crc = 32'h6014fe08; // not a correct value
630
 
631
    @ (posedge MRxClk);
632
    MRxDV=1'b1;
633
 
634
    for(tt=0; tt<15; tt=tt+1)
635
    begin
636
      MRxD=4'h5;              // preamble
637
      @ (posedge MRxClk);
638
    end
639
    MRxD=4'hd;                // SFD
640
 
641
    for(tt=0; tt<32; tt=tt+1)
642
    begin
643
      Data = Packet << (tt*4);
644
      @ (posedge MRxClk);
645
      MRxD=Data[127:124];
646
    end
647
 
648
    for(tt=0; tt<2; tt=tt+1)    // timer
649
    begin
650
      Data[15:0] = Timer << (tt*8);
651
      @ (posedge MRxClk);
652
      MRxD=Data[11:8];
653
      @ (posedge MRxClk);
654
      MRxD=Data[15:12];
655
    end
656
 
657
    for(tt=0; tt<42; tt=tt+1)   // padding
658
    begin
659
      Data[7:0] = 8'h0;
660
      @ (posedge MRxClk);
661
      MRxD=Data[3:0];
662
      @ (posedge MRxClk);
663
      MRxD=Data[3:0];
664
    end
665
 
666
    for(tt=0; tt<4; tt=tt+1)    // crc
667
    begin
668
      Data[31:0] = Crc << (tt*8);
669
      @ (posedge MRxClk);
670
      MRxD=Data[27:24];
671
      @ (posedge MRxClk);
672
      MRxD=Data[31:28];
673
    end
674
 
675
 
676
 
677
    @ (posedge MRxClk);
678
    MRxDV=1'b0;
679
  end
680
endtask
681
 
682 67 mohor
`else // No EXTERNAL_DMA
683 15 mohor
 
684 41 mohor
initial
685
begin
686
  wait(StartTB);  // Start of testbench
687 66 mohor
 
688
  InitializeMemory;
689
 
690
// Select which test you want to run:
691
    TestTxAndRx;
692
  //  TestUnicast;
693
  //  TestBroadcast;
694
  //  TestMulticast;
695 51 billditt
end
696 66 mohor
 
697
task TestTxAndRx;
698 51 billditt
 begin
699 66 mohor
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 1
700
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2});     // r_Rst = 0
701
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
702 51 billditt
 
703 66 mohor
  WishboneWrite(32'h00002463, {26'h0, `ETH_MODER_ADR<<2});     // RxEn, Txen, CrcEn, Pad off, full duplex, r_IFG, promisc ON
704 51 billditt
 
705 66 mohor
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
706 51 billditt
 
707 66 mohor
  SendPacket(16'h0007, 1'b0);
708 51 billditt
  SendPacket(16'h0011, 1'b0);
709
  SendPacket(16'h0012, 1'b0);
710
  SendPacket(16'h0013, 1'b0);
711
  SendPacket(16'h0014, 1'b0);
712 15 mohor
 
713 51 billditt
  SendPacket(16'h0030, 1'b0);
714
  SendPacket(16'h0031, 1'b0);
715
  SendPacket(16'h0032, 1'b0);
716
  SendPacket(16'h0033, 1'b0);
717
  SendPacket(16'h0025, 1'b0);
718
  SendPacket(16'h0045, 1'b0);
719
  SendPacket(16'h0025, 1'b0);
720
  SendPacket(16'h0017, 1'b0);
721 41 mohor
 
722 66 mohor
  ReceivePacket(16'h0015, 1'b0, `MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
723
  ReceivePacket(16'h0016, 1'b0, `MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
724
  ReceivePacket(16'h0017, 1'b0, `MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
725
  ReceivePacket(16'h0018, 1'b0, `MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
726 41 mohor
 
727 51 billditt
  repeat(5000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
728 49 mohor
 
729 51 billditt
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
730
 
731
  WishboneRead({24'h04, (8'h0<<2)});       // Read from TxBD register
732
  WishboneRead({24'h04, (8'h1<<2)});       // Read from TxBD register
733
  WishboneRead({24'h04, (8'h2<<2)});       // Read from TxBD register
734
  WishboneRead({24'h04, (8'h3<<2)});       // Read from TxBD register
735
  WishboneRead({24'h04, (8'h4<<2)});       // Read from TxBD register
736
 
737
 
738
  WishboneRead({22'h01, (10'h80<<2)});       // Read from RxBD register
739
  WishboneRead({22'h01, (10'h81<<2)});       // Read from RxBD register
740
  WishboneRead({22'h01, (10'h82<<2)});       // Read from RxBD register
741
  WishboneRead({22'h01, (10'h83<<2)});       // Read from RxBD register
742
  WishboneRead({22'h01, (10'h84<<2)});       // Read from RxBD register
743
  WishboneRead({22'h01, (10'h85<<2)});       // Read from RxBD register
744
  WishboneRead({22'h01, (10'h86<<2)});       // Read from RxBD register
745
  WishboneRead({22'h01, (10'h87<<2)});       // Read from RxBD register
746 66 mohor
 
747 51 billditt
  #100000 $stop;
748 66 mohor
 end
749
endtask //TestTxAndRx
750 51 billditt
 
751 66 mohor
 
752 51 billditt
task TestUnicast;
753
 begin
754
  $display("\nBegin TestUnicast \n");
755
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 1
756
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 0
757
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
758 66 mohor
  WishboneWrite(32'h00002043, {26'h0, `ETH_MODER_ADR, 2'h0});     // RxEn, Txen, CrcEn, no Pad, r_IFG, promisc off, broadcast on
759 51 billditt
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); //r_TxFlow = 1
760
 
761 66 mohor
  $display("\n This Uniicast packet will be rejected, wrong address in MAC Address Regs\n");
762 51 billditt
 
763 66 mohor
  ReceivePacket(16'h0014, 1'b0,`UNICAST_XFR);
764 51 billditt
 
765
  WishboneWrite(32'h04030200, {26'h0,`ETH_MAC_ADDR0_ADR ,2'h0}); // Mac Address 
766
  WishboneWrite(32'h00000605, {26'h0,`ETH_MAC_ADDR1_ADR ,2'h0}); // Mac Address
767
 
768
  $display("\n Set Proper Unicast Address in MAC_ADDRESS regs, resend packet\n");
769
 
770 66 mohor
  ReceivePacket(16'h0015, 1'b0,`UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
771
  ReceivePacket(16'h0016, 1'b0,`UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
772
  ReceivePacket(16'h0017, 1'b0,`UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
773
  ReceivePacket(16'h0018, 1'b0,`UNICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
774 41 mohor
 
775
  repeat(5000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
776
 
777
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
778
 
779
  WishboneRead({22'h01, (10'h80<<2)});       // Read from RxBD register
780
  WishboneRead({22'h01, (10'h81<<2)});       // Read from RxBD register
781
  WishboneRead({22'h01, (10'h82<<2)});       // Read from RxBD register
782
  WishboneRead({22'h01, (10'h83<<2)});       // Read from RxBD register
783
  WishboneRead({22'h01, (10'h84<<2)});       // Read from RxBD register
784
  WishboneRead({22'h01, (10'h85<<2)});       // Read from RxBD register
785
  WishboneRead({22'h01, (10'h86<<2)});       // Read from RxBD register
786
  WishboneRead({22'h01, (10'h87<<2)});       // Read from RxBD register
787 66 mohor
  WishboneRead({22'h01, (10'h88<<2)});       // Read from RxBD register
788
  WishboneRead({22'h01, (10'h89<<2)});       // Read from RxBD register
789 51 billditt
 
790
  #100000 $stop;
791
  $display("\nEnd TestUnicast \n");
792
end
793
endtask //TestUnicast
794 41 mohor
 
795 51 billditt
task TestMulticast;
796
 begin
797
  $display("\nBegin TestMulticast \n");
798
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 1
799
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 0
800
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
801 66 mohor
  WishboneWrite(32'h00002043, {26'h0, `ETH_MODER_ADR, 2'h0});     // RxEn, Txen, CrcEn, No Pad, r_IFG, promiscuos off, broadcast enable
802
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); // r_TxFlow = 1
803 51 billditt
 
804 66 mohor
  $display("\n This Multicast packet will be rejected by Hash Filter\n");
805 51 billditt
 
806 66 mohor
  ReceivePacket(16'h0014, 1'b0,`MULTICAST_XFR);
807 51 billditt
 
808
  WishboneWrite(32'h00400000, {26'h0, `ETH_HASH1_ADR,2'h0}); // set bit 16, multicast hash 36
809 66 mohor
  WishboneRead({26'h0, `ETH_HASH1_ADR, 2'h0});  // read back
810 51 billditt
 
811
  $display("\n Set Hash Filter to accept this Multicast packet, resend packet\n");
812
 
813 66 mohor
  ReceivePacket(16'h0015, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
814
  ReceivePacket(16'h0016, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
815
  ReceivePacket(16'h0017, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
816
  ReceivePacket(16'h0018, 1'b0,`MULTICAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
817 51 billditt
 
818
  repeat(5000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
819
 
820
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
821
 
822
  WishboneRead({22'h01, (10'h80<<2)});       // Read from RxBD register
823
  WishboneRead({22'h01, (10'h81<<2)});       // Read from RxBD register
824
  WishboneRead({22'h01, (10'h82<<2)});       // Read from RxBD register
825
  WishboneRead({22'h01, (10'h83<<2)});       // Read from RxBD register
826
  WishboneRead({22'h01, (10'h84<<2)});       // Read from RxBD register
827
  WishboneRead({22'h01, (10'h85<<2)});       // Read from RxBD register
828
  WishboneRead({22'h01, (10'h86<<2)});       // Read from RxBD register
829
  WishboneRead({22'h01, (10'h87<<2)});       // Read from RxBD register
830
 
831 66 mohor
  $display("\nEnd TestMulticast \n");
832 41 mohor
  #100000 $stop;
833
end
834 51 billditt
endtask //TestMulticast
835 41 mohor
 
836
 
837 51 billditt
task TestBroadcast;
838
 begin
839 66 mohor
  $display("\n\n\nBegin TestBroadcast");
840 51 billditt
  WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 1
841
  WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0});     // r_Rst = 0
842
  WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
843 41 mohor
 
844 66 mohor
  WishboneWrite(32'h0000A04b, {26'h0, `ETH_MODER_ADR, 2'h0});     // PadEn, CrcEn, IFG=accept, Reject Broadcast, TxEn, RxEn
845
  WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); // r_TxFlow = 1
846 51 billditt
 
847 66 mohor
  $display("\nThis Broadcast packet will be rejected, r_BRO = 1");
848
  ReceivePacket(16'h0014, 1'b0,`BROADCAST_XFR);
849 51 billditt
 
850 66 mohor
  $display("\nSet r_Bro = 0, resend packet");
851
  WishboneWrite(32'h0000A043, {26'h0, `ETH_MODER_ADR, 2'h0});  // PadEn, CrcEn, IFG=accept, Accept Broadcast, TxEn, RxEn
852
  ReceivePacket(16'h0015, 1'b0,`BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
853 51 billditt
 
854 66 mohor
  $display("\n This Broadcast packet will be rejected, r_BRO = 1");
855
  WishboneWrite(32'h0000A04b, {26'h0, `ETH_MODER_ADR, 2'h0});     // PadEn, CrcEn, IFG=accept, Reject Broadcast, TxEn, RxEn
856
  ReceivePacket(16'h0016, 1'b0,`BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
857
  ReceivePacket(16'h0017, 1'b0,`BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
858 51 billditt
 
859 66 mohor
  $display("\n Set r_Bro = 0, resend packet");
860
  WishboneWrite(32'h0000A043, {26'h0, `ETH_MODER_ADR, 2'h0});  // PadEn, CrcEn, IFG=accept, Accept Broadcast, TxEn, RxEn
861
  ReceivePacket(16'h0018, 1'b0,`BROADCAST_XFR);    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
862 51 billditt
 
863
  repeat(5000) @ (posedge MRxClk);        // Waiting some time for all accesses to finish before reading out the statuses.
864
 
865
  WishboneRead({26'h0, `ETH_MODER_ADR});   // Read from MODER register
866
 
867
  WishboneRead({22'h01, (10'h80<<2)});       // Read from RxBD register
868
  WishboneRead({22'h01, (10'h81<<2)});       // Read from RxBD register
869
  WishboneRead({22'h01, (10'h82<<2)});       // Read from RxBD register
870
  WishboneRead({22'h01, (10'h83<<2)});       // Read from RxBD register
871
  WishboneRead({22'h01, (10'h84<<2)});       // Read from RxBD register
872
  WishboneRead({22'h01, (10'h85<<2)});       // Read from RxBD register
873
  WishboneRead({22'h01, (10'h86<<2)});       // Read from RxBD register
874
  WishboneRead({22'h01, (10'h87<<2)});       // Read from RxBD register
875
 
876
  #100000 $stop;
877
  $display("\nEnd TestBroadcast \n");
878
end
879
endtask //TestBroadcast
880
 
881
 
882 41 mohor
always @ (posedge WB_CLK_I)
883
begin
884
  if(m_wb_cyc_o & m_wb_stb_o) // Add valid address range
885
    begin
886
      repeat(3) @ (posedge WB_CLK_I);
887
        begin
888 66 mohor
          m_wb_ack_i <=#Tp 1'b1;
889 41 mohor
          if(~m_wb_we_o)
890
            begin
891
              #Tp m_wb_dat_i = m_wb_adr_o + 1'b1; // For easier following of the data
892
              $fdisplay(mcd1, "(%0t) master read (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_i);
893
            end
894
          else
895
            $fdisplay(mcd2, "(%0t) master write (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_o);
896
        end
897
      @ (posedge WB_CLK_I);
898
      m_wb_ack_i <=#Tp 1'b0;
899
    end
900
end
901
 
902
// Generating error
903
always @ (posedge WB_CLK_I)
904
begin
905
  if(m_wb_cyc_o & m_wb_stb_o & ~(&m_wb_sel_o))  // Add false address range
906
    m_wb_err_i <=#Tp 1'b1;
907
end
908
 
909
always @ (posedge WB_CLK_I)
910
  if(tb_eth_top.ethtop.wishbone.RxStatusWrite)
911
    $fdisplay(mcd2, "");  // newline added
912
 
913
task WishboneWrite;
914
  input [31:0] Data;
915
  input [31:0] Address;
916
  integer ii;
917
 
918
  begin
919
    wait (~WishboneBusy);
920
    WishboneBusy = 1;
921
    @ (posedge WB_CLK_I);
922
    #1;
923
    WB_ADR_I = Address;
924
    WB_DAT_I = Data;
925
    WB_WE_I  = 1'b1;
926
    WB_CYC_I = 1'b1;
927
    WB_STB_I = 1'b1;
928
    WB_SEL_I = 4'hf;
929
 
930
 
931
    wait(WB_ACK_O);   // waiting for acknowledge response
932
 
933
    // Writing information about the access to the screen
934
    @ (posedge WB_CLK_I);
935
      if(~Address[11] & ~Address[10])
936
        $write("\n(%0t) Write to register (Data: 0x%x, Reg. Addr: 0x%0x)", $time, Data, Address);
937
      else
938
      if(~Address[11] & Address[10])
939
        if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
940
          begin
941
            $write("\n(%0t) Write to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", $time, Data, Address);
942 66 mohor
            if(Address[9:2] == tb_eth_top.ethtop.r_TxBDNum-2'h2)
943
              $write("(%0t) Send Control packet\n", $time);
944 41 mohor
          end
945
        else
946
          $write("\n(%0t) Write to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", $time, Data, Address);
947
      else
948
        $write("\n(%0t) WB write ??????????????     Data: 0x%x      Addr: 0x%0x", $time, Data, Address);
949
    #1;
950
    WB_ADR_I = 32'hx;
951
    WB_DAT_I = 32'hx;
952
    WB_WE_I  = 1'bx;
953
    WB_CYC_I = 1'b0;
954
    WB_STB_I = 1'b0;
955
    WB_SEL_I = 4'hx;
956
    #5 WishboneBusy = 0;
957
  end
958
endtask
959
 
960
 
961
task WishboneRead;
962
  input [31:0] Address;
963
 
964
  begin
965
    wait (~WishboneBusy);
966
    WishboneBusy = 1;
967
    @ (posedge WB_CLK_I);
968
    #1;
969
    WB_ADR_I = Address;
970
    WB_WE_I  = 1'b0;
971
    WB_CYC_I = 1'b1;
972
    WB_STB_I = 1'b1;
973
    WB_SEL_I = 4'hf;
974
 
975
    wait(WB_ACK_O);   // waiting for acknowledge response
976
    @ (posedge WB_CLK_I);
977
 
978
      if(~Address[11] & ~Address[10])
979
        $write("\n(%0t) Read from register (Data: 0x%x, Reg. Addr: 0x%0x)", $time, WB_DAT_O, Address);
980
      else
981
      if(~Address[11] & Address[10])
982
        if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
983
          begin
984
            $write("\n(%0t) Read from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", $time, WB_DAT_O, Address);
985
          end
986
        else
987
          $write("\n(%0t) Read from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", $time, WB_DAT_O, Address);
988
      else
989
        $write("\n(%0t) WB read  ?????????    Data: 0x%x      Addr: 0x%0x", $time, WB_DAT_O, Address);
990
    #1;
991
    WB_ADR_I = 32'hx;
992
    WB_WE_I  = 1'bx;
993
    WB_CYC_I = 1'b0;
994
    WB_STB_I = 1'b0;
995
    WB_SEL_I = 4'hx;
996
    #5 WishboneBusy = 0;
997
  end
998
endtask
999
 
1000
 
1001
 
1002
 
1003
task SendPacket;
1004
  input [15:0]  Length;
1005
  input         ControlFrame;
1006
  reg           Wrap;
1007
  reg [31:0]    TempAddr;
1008
  reg [31:0]    TempData;
1009
 
1010
  begin
1011
//    if(TxBDIndex == 6)    // Only 3 buffer descriptors are used 
1012
//      Wrap = 1'b1;
1013
//    else
1014
      Wrap = 1'b0;    // At the moment no wrap bit is set
1015
 
1016
    // Writing buffer pointer
1017
    TempAddr = {22'h01, ((TxBDIndex + 1'b1)<<2)};
1018
    TempData = 32'h78563411;
1019
    WishboneWrite(TempData, TempAddr); // buffer pointer
1020
 
1021
 
1022 66 mohor
    TempAddr = {22'h01, (TxBDIndex<<2)};
1023 41 mohor
 
1024
    TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]};  // Ready and Wrap = 1
1025
 
1026
    #1;
1027
//    if(TxBDIndex == 6)    // Only 4 buffer descriptors are used
1028
//      TxBDIndex = 0;
1029
//    else
1030
      TxBDIndex = TxBDIndex + 2;
1031
 
1032
    WishboneWrite(TempData, TempAddr); // Writing status to TxBD
1033
  end
1034
endtask
1035
 
1036
 
1037
 
1038
task ReceivePacket;    // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
1039
  input [15:0] LengthRx;
1040
  input        RxControlFrame;
1041 51 billditt
  input [31:0] TransferType;  //Broadcast,Unicast,Multicast
1042 41 mohor
  reg        WrapRx;
1043
  reg [31:0] TempRxAddr;
1044
  reg [31:0] TempRxData;
1045
  reg abc;
1046
  begin
1047
//    if(RxBDIndex == 6)    // Only 3 buffer descriptors are used
1048
//      WrapRx = 1'b1;
1049
//    else
1050
      WrapRx = 1'b0;
1051
 
1052
    TempRxAddr = {22'h01, ((tb_eth_top.ethtop.r_TxBDNum + RxBDIndex + 1'b1)<<2)};
1053
    TempRxData = 32'h73507350 + RxBDIndex;
1054
    WishboneWrite(TempRxData, TempRxAddr); // Writing Rx pointer
1055
 
1056
 
1057
    TempRxAddr = {22'h01, ((tb_eth_top.ethtop.r_TxBDNum + RxBDIndex)<<2)};
1058
//    TempRxData = {LengthRx[15:0], 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]};  // Ready and WrapRx = 1 or 0
1059
    TempRxData = {16'h0, 1'b1, 1'b0, WrapRx, 5'h0, RxBDIndex[7:0]};  // Ready and WrapRx = 1 or 0
1060
 
1061
    #1;
1062
//    if(RxBDIndex == 6)    // Only 4 buffer descriptors are used
1063
//      RxBDIndex = 0;
1064
//    else
1065
      RxBDIndex = RxBDIndex + 2;
1066
 
1067
    abc=1;
1068
    WishboneWrite(TempRxData, TempRxAddr); // Writing status to RxBD
1069
    abc=0;
1070
 
1071
      begin
1072
        #200;
1073
        if(RxControlFrame)
1074
          GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.
1075
        else
1076 66 mohor
          GetDataOnMRxD(LengthRx, TransferType); // LengthRx bytes is comming on MRxD[3:0] signals
1077 41 mohor
      end
1078
 
1079
  end
1080
endtask
1081
 
1082
 
1083
task GetDataOnMRxD;
1084
  input [15:0] Len;
1085 51 billditt
  input [31:0] TransferType;
1086 41 mohor
  integer tt;
1087
 
1088
  begin
1089
    @ (posedge MRxClk);
1090
    MRxDV=1'b1;
1091
 
1092
    for(tt=0; tt<15; tt=tt+1)
1093
    begin
1094
      MRxD=4'h5;              // preamble
1095
      @ (posedge MRxClk);
1096
    end
1097
    MRxD=4'hd;                // SFD
1098 51 billditt
 
1099
  for(tt=1; tt<(Len+1); tt=tt+1)
1100
 
1101 41 mohor
    begin
1102 51 billditt
 
1103 41 mohor
      @ (posedge MRxClk);
1104 51 billditt
          if(TransferType == `UNICAST_XFR && tt == 1)
1105
           MRxD= 4'h0;   // Unicast transfer
1106
          else if(TransferType == `BROADCAST_XFR && tt < 7)
1107
           MRxD = 4'hf;
1108
          else
1109
       MRxD=tt[3:0]; // Multicast transfer
1110 66 mohor
 
1111
    @ (posedge MRxClk);
1112 51 billditt
 
1113
           if(TransferType == `BROADCAST_XFR && tt < 7)
1114
            MRxD = 4'hf;
1115
          else
1116
        MRxD=tt[7:4];
1117 41 mohor
    end
1118 51 billditt
 
1119 41 mohor
    @ (posedge MRxClk);
1120
    MRxDV=1'b0;
1121
  end
1122
endtask
1123
 
1124
 
1125
task GetControlDataOnMRxD;
1126
  input [15:0] Timer;
1127
  reg [127:0] Packet;
1128
  reg [127:0] Data;
1129
  reg [31:0] Crc;
1130
  integer tt;
1131
 
1132
  begin
1133 66 mohor
  Packet = 128'h10082C000010_deadbeef0013_8880_0010; // 0180c2000001 + 8808 + 0001
1134 41 mohor
  Crc = 32'h6014fe08; // not a correct value
1135
 
1136
    @ (posedge MRxClk);
1137
    MRxDV=1'b1;
1138
 
1139
    for(tt=0; tt<15; tt=tt+1)
1140
    begin
1141
      MRxD=4'h5;              // preamble
1142
      @ (posedge MRxClk);
1143
    end
1144
    MRxD=4'hd;                // SFD
1145
 
1146
    for(tt=0; tt<32; tt=tt+1)
1147
    begin
1148
      Data = Packet << (tt*4);
1149
      @ (posedge MRxClk);
1150
      MRxD=Data[127:124];
1151
    end
1152
 
1153
    for(tt=0; tt<2; tt=tt+1)    // timer
1154
    begin
1155
      Data[15:0] = Timer << (tt*8);
1156
      @ (posedge MRxClk);
1157
      MRxD=Data[11:8];
1158
      @ (posedge MRxClk);
1159
      MRxD=Data[15:12];
1160
    end
1161
 
1162
    for(tt=0; tt<42; tt=tt+1)   // padding
1163
    begin
1164
      Data[7:0] = 8'h0;
1165
      @ (posedge MRxClk);
1166
      MRxD=Data[3:0];
1167
      @ (posedge MRxClk);
1168
      MRxD=Data[3:0];
1169
    end
1170
 
1171
    for(tt=0; tt<4; tt=tt+1)    // crc
1172
    begin
1173
      Data[31:0] = Crc << (tt*8);
1174
      @ (posedge MRxClk);
1175
      MRxD=Data[27:24];
1176
      @ (posedge MRxClk);
1177
      MRxD=Data[31:28];
1178
    end
1179
 
1180
 
1181
 
1182
    @ (posedge MRxClk);
1183
    MRxDV=1'b0;
1184
  end
1185
endtask
1186 66 mohor
 
1187
task InitializeMemory;
1188
  reg [9:0] mem_addr;
1189
 
1190
  begin
1191
    for(mem_addr=0; mem_addr<=10'h0ff; mem_addr=mem_addr+1'b1)
1192
      WishboneWrite(32'h0, {22'h01, mem_addr<<2}); // Writing status to RxBD
1193
  end
1194
endtask
1195
 
1196
 
1197 41 mohor
`endif
1198
 
1199
 
1200 15 mohor
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.