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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Blame information for rev 279

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1 116 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  tb_ethernet.v                                               ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9 169 mohor
////      - Tadej Markovic, tadej@opencores.org                   ////
10 243 tadejm
////      - Igor Mohor,     igorM@opencores.org                  ////
11 116 mohor
////                                                              ////
12 169 mohor
////  All additional information is available in the Readme.txt   ////
13 116 mohor
////  file.                                                       ////
14
////                                                              ////
15
//////////////////////////////////////////////////////////////////////
16
////                                                              ////
17
//// Copyright (C) 2001, 2002 Authors                             ////
18
////                                                              ////
19
//// This source file may be used and distributed without         ////
20
//// restriction provided that this copyright statement is not    ////
21
//// removed from the file and that any derivative work contains  ////
22
//// the original copyright notice and the associated disclaimer. ////
23
////                                                              ////
24
//// This source file is free software; you can redistribute it   ////
25
//// and/or modify it under the terms of the GNU Lesser General   ////
26
//// Public License as published by the Free Software Foundation; ////
27
//// either version 2.1 of the License, or (at your option) any   ////
28
//// later version.                                               ////
29
////                                                              ////
30
//// This source is distributed in the hope that it will be       ////
31
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
32
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
33
//// PURPOSE.  See the GNU Lesser General Public License for more ////
34
//// details.                                                     ////
35
////                                                              ////
36
//// You should have received a copy of the GNU Lesser General    ////
37
//// Public License along with this source; if not, download it   ////
38
//// from http://www.opencores.org/lgpl.shtml                     ////
39
////                                                              ////
40
//////////////////////////////////////////////////////////////////////
41
//
42
// CVS Revision History
43
//
44
// $Log: not supported by cvs2svn $
45 279 mohor
// Revision 1.26  2003/01/22 19:40:10  tadejm
46
// Backup version. Not fully working.
47
//
48 274 tadejm
// Revision 1.25  2002/11/27 16:21:55  mohor
49
// Full duplex control frames tested.
50
//
51 267 mohor
// Revision 1.24  2002/11/22 17:29:42  mohor
52
// Flow control test almost finished.
53
//
54 266 mohor
// Revision 1.23  2002/11/22 02:12:16  mohor
55
// test_mac_full_duplex_flow_control tests pretty much finished.
56
// TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
57
// FRM. AT 4 TX BD ( 10Mbps ) finished.
58
// TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
59
// TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
60
//
61 263 mohor
// Revision 1.22  2002/11/21 13:56:50  mohor
62
// test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
63
// finished.
64
//
65 260 mohor
// Revision 1.21  2002/11/19 20:27:45  mohor
66
// Temp version.
67
//
68 254 mohor
// Revision 1.20  2002/11/19 17:41:19  tadejm
69
// Just some updates.
70
//
71 252 tadejm
// Revision 1.19  2002/11/14 13:12:47  tadejm
72
// Late collision is not reported any more.
73
//
74 243 tadejm
// Revision 1.18  2002/10/18 17:03:34  tadejm
75
// Changed BIST scan signals.
76
//
77 227 tadejm
// Revision 1.17  2002/10/18 13:58:22  tadejm
78
// Some code changed due to bug fixes.
79
//
80 223 tadejm
// Revision 1.16  2002/10/09 13:16:51  tadejm
81
// Just back-up; not completed testbench and some testcases are not
82
// wotking properly yet.
83
//
84 209 tadejm
// Revision 1.15  2002/09/20 14:29:12  tadej
85
// Full duplex tests modified and testbench bug repaired.
86
//
87 194 tadej
// Revision 1.14  2002/09/18 17:56:38  tadej
88
// Some additional reports added
89
//
90 192 tadej
// Revision 1.13  2002/09/16 17:53:49  tadej
91
// Full duplex test improved.
92
//
93 182 tadej
// Revision 1.12  2002/09/16 15:10:42  mohor
94
// MIIM test look better.
95
//
96 181 mohor
// Revision 1.11  2002/09/13 19:18:04  mohor
97
// Bench outputs data to display every 128 bytes.
98
//
99 180 mohor
// Revision 1.10  2002/09/13 18:44:29  mohor
100
// Beautiful tests merget together
101
//
102 179 mohor
// Revision 1.9  2002/09/13 18:41:45  mohor
103
// Rearanged testcases
104
//
105 178 mohor
// Revision 1.8  2002/09/13 14:50:15  mohor
106
// Bug in MIIM fixed.
107
//
108 177 mohor
// Revision 1.7  2002/09/13 12:29:14  mohor
109
// Headers changed.
110
//
111 170 mohor
// Revision 1.6  2002/09/13 11:57:20  mohor
112
// New testbench. Thanks to Tadej M - "The Spammer".
113
//
114 121 mohor
// Revision 1.2  2002/07/19 14:02:47  mohor
115
// Clock mrx_clk set to 2.5 MHz.
116
//
117 117 mohor
// Revision 1.1  2002/07/19 13:57:53  mohor
118
// Testing environment also includes traffic cop, memory interface and host
119
// interface.
120 116 mohor
//
121
//
122
//
123
//
124 117 mohor
//
125 116 mohor
 
126
 
127 169 mohor
`include "eth_phy_defines.v"
128
`include "wb_model_defines.v"
129 116 mohor
`include "tb_eth_defines.v"
130
`include "eth_defines.v"
131
`include "timescale.v"
132
 
133
module tb_ethernet();
134
 
135
 
136 169 mohor
reg           wb_clk;
137
reg           wb_rst;
138
wire          wb_int;
139 116 mohor
 
140 169 mohor
wire          mtx_clk;  // This goes to PHY
141
wire          mrx_clk;  // This goes to PHY
142 116 mohor
 
143
wire   [3:0]  MTxD;
144
wire          MTxEn;
145
wire          MTxErr;
146
 
147 169 mohor
wire   [3:0]  MRxD;     // This goes to PHY
148
wire          MRxDV;    // This goes to PHY
149
wire          MRxErr;   // This goes to PHY
150
wire          MColl;    // This goes to PHY
151
wire          MCrs;     // This goes to PHY
152 116 mohor
 
153
wire          Mdi_I;
154
wire          Mdo_O;
155
wire          Mdo_OE;
156 169 mohor
tri           Mdio_IO;
157 116 mohor
wire          Mdc_O;
158
 
159
 
160 169 mohor
parameter Tp = 1;
161 116 mohor
 
162 121 mohor
 
163 116 mohor
// Ethernet Slave Interface signals
164 169 mohor
wire [31:0] eth_sl_wb_adr;
165 116 mohor
wire [31:0] eth_sl_wb_adr_i, eth_sl_wb_dat_o, eth_sl_wb_dat_i;
166
wire  [3:0] eth_sl_wb_sel_i;
167
wire        eth_sl_wb_we_i, eth_sl_wb_cyc_i, eth_sl_wb_stb_i, eth_sl_wb_ack_o, eth_sl_wb_err_o;
168
 
169
// Ethernet Master Interface signals
170
wire [31:0] eth_ma_wb_adr_o, eth_ma_wb_dat_i, eth_ma_wb_dat_o;
171
wire  [3:0] eth_ma_wb_sel_o;
172
wire        eth_ma_wb_we_o, eth_ma_wb_cyc_o, eth_ma_wb_stb_o, eth_ma_wb_ack_i, eth_ma_wb_err_i;
173
 
174
 
175
 
176
 
177
// Connecting Ethernet top module
178 169 mohor
eth_top eth_top
179 116 mohor
(
180
  // WISHBONE common
181 169 mohor
  .wb_clk_i(wb_clk),              .wb_rst_i(wb_rst),
182 116 mohor
 
183
  // WISHBONE slave
184 169 mohor
  .wb_adr_i(eth_sl_wb_adr_i[11:2]), .wb_sel_i(eth_sl_wb_sel_i),   .wb_we_i(eth_sl_wb_we_i),
185
  .wb_cyc_i(eth_sl_wb_cyc_i),       .wb_stb_i(eth_sl_wb_stb_i),   .wb_ack_o(eth_sl_wb_ack_o),
186
  .wb_err_o(eth_sl_wb_err_o),       .wb_dat_i(eth_sl_wb_dat_i),   .wb_dat_o(eth_sl_wb_dat_o),
187 116 mohor
 
188
  // WISHBONE master
189
  .m_wb_adr_o(eth_ma_wb_adr_o),     .m_wb_sel_o(eth_ma_wb_sel_o), .m_wb_we_o(eth_ma_wb_we_o),
190
  .m_wb_dat_i(eth_ma_wb_dat_i),     .m_wb_dat_o(eth_ma_wb_dat_o), .m_wb_cyc_o(eth_ma_wb_cyc_o),
191
  .m_wb_stb_o(eth_ma_wb_stb_o),     .m_wb_ack_i(eth_ma_wb_ack_i), .m_wb_err_i(eth_ma_wb_err_i),
192
 
193
  //TX
194
  .mtx_clk_pad_i(mtx_clk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
195
 
196
  //RX
197
  .mrx_clk_pad_i(mrx_clk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
198
  .mcoll_pad_i(MColl),    .mcrs_pad_i(MCrs),
199
 
200
  // MIIM
201
  .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoe_o(Mdo_OE),
202
 
203 169 mohor
  .int_o(wb_int)
204 227 tadejm
 
205
  // Bist
206
`ifdef ETH_BIST
207
  ,
208
  .scanb_rst      (1'b0),
209
  .scanb_clk      (1'b0),
210
  .scanb_si       (1'b0),
211
  .scanb_so       (),
212
  .scanb_en       (1'b0)
213
`endif
214 116 mohor
);
215
 
216
 
217
 
218 169 mohor
// Connecting Ethernet PHY Module
219
assign Mdio_IO = Mdo_OE ? Mdo_O : 1'bz ;
220
assign Mdi_I   = Mdio_IO;
221
integer phy_log_file_desc;
222
 
223
eth_phy eth_phy
224 116 mohor
(
225 169 mohor
  // WISHBONE reset
226
  .m_rst_n_i(!wb_rst),
227 116 mohor
 
228 169 mohor
  // MAC TX
229
  .mtx_clk_o(mtx_clk),    .mtxd_i(MTxD),    .mtxen_i(MTxEn),    .mtxerr_i(MTxErr),
230
 
231
  // MAC RX
232
  .mrx_clk_o(mrx_clk),    .mrxd_o(MRxD),    .mrxdv_o(MRxDV),    .mrxerr_o(MRxErr),
233
  .mcoll_o(MColl),        .mcrs_o(MCrs),
234
 
235
  // MIIM
236
  .mdc_i(Mdc_O),          .md_io(Mdio_IO),
237
 
238
  // SYSTEM
239
  .phy_log(phy_log_file_desc)
240 116 mohor
);
241
 
242
 
243 169 mohor
 
244
// Connecting WB Master as Host Interface
245
integer host_log_file_desc;
246
 
247
WB_MASTER_BEHAVIORAL wb_master
248 116 mohor
(
249 169 mohor
    .CLK_I(wb_clk),
250
    .RST_I(wb_rst),
251
    .TAG_I({`WB_TAG_WIDTH{1'b0}}),
252
    .TAG_O(),
253
    .ACK_I(eth_sl_wb_ack_o),
254
    .ADR_O(eth_sl_wb_adr), // only eth_sl_wb_adr_i[11:2] used
255
    .CYC_O(eth_sl_wb_cyc_i),
256
    .DAT_I(eth_sl_wb_dat_o),
257
    .DAT_O(eth_sl_wb_dat_i),
258
    .ERR_I(eth_sl_wb_err_o),
259
    .RTY_I(1'b0),  // inactive (1'b0)
260
    .SEL_O(eth_sl_wb_sel_i),
261
    .STB_O(eth_sl_wb_stb_i),
262
    .WE_O (eth_sl_wb_we_i),
263
    .CAB_O()       // NOT USED for now!
264
);
265
 
266
assign eth_sl_wb_adr_i = {20'h0, eth_sl_wb_adr[11:2], 2'h0};
267
 
268
 
269
 
270
// Connecting WB Slave as Memory Interface Module
271
integer memory_log_file_desc;
272
 
273
WB_SLAVE_BEHAVIORAL wb_slave
274
(
275
    .CLK_I(wb_clk),
276
    .RST_I(wb_rst),
277
    .ACK_O(eth_ma_wb_ack_i),
278
    .ADR_I(eth_ma_wb_adr_o),
279
    .CYC_I(eth_ma_wb_cyc_o),
280
    .DAT_O(eth_ma_wb_dat_i),
281
    .DAT_I(eth_ma_wb_dat_o),
282
    .ERR_O(eth_ma_wb_err_i),
283
    .RTY_O(),      // NOT USED for now!
284
    .SEL_I(eth_ma_wb_sel_o),
285
    .STB_I(eth_ma_wb_stb_o),
286
    .WE_I (eth_ma_wb_we_o),
287
    .CAB_I(1'b0)   // inactive (1'b0)
288
);
289
 
290
 
291
 
292
// Connecting WISHBONE Bus Monitors to ethernet master and slave interfaces
293
integer wb_s_mon_log_file_desc ;
294
integer wb_m_mon_log_file_desc ;
295
 
296
WB_BUS_MON wb_eth_slave_bus_mon
297
(
298 116 mohor
  // WISHBONE common
299 169 mohor
  .CLK_I(wb_clk),
300
  .RST_I(wb_rst),
301 116 mohor
 
302 169 mohor
  // WISHBONE slave
303
  .ACK_I(eth_sl_wb_ack_o),
304
  .ADDR_O({20'h0, eth_sl_wb_adr_i[11:2], 2'b0}),
305
  .CYC_O(eth_sl_wb_cyc_i),
306
  .DAT_I(eth_sl_wb_dat_o),
307
  .DAT_O(eth_sl_wb_dat_i),
308
  .ERR_I(eth_sl_wb_err_o),
309
  .RTY_I(1'b0),
310
  .SEL_O(eth_sl_wb_sel_i),
311
  .STB_O(eth_sl_wb_stb_i),
312
  .WE_O (eth_sl_wb_we_i),
313
  .TAG_I({`WB_TAG_WIDTH{1'b0}}),
314
  .TAG_O(),
315
  .CAB_O(1'b0),
316
  .log_file_desc (wb_s_mon_log_file_desc)
317
);
318
 
319
WB_BUS_MON wb_eth_master_bus_mon
320
(
321
  // WISHBONE common
322
  .CLK_I(wb_clk),
323
  .RST_I(wb_rst),
324
 
325 116 mohor
  // WISHBONE master
326 169 mohor
  .ACK_I(eth_ma_wb_ack_i),
327
  .ADDR_O(eth_ma_wb_adr_o),
328
  .CYC_O(eth_ma_wb_cyc_o),
329
  .DAT_I(eth_ma_wb_dat_i),
330
  .DAT_O(eth_ma_wb_dat_o),
331
  .ERR_I(eth_ma_wb_err_i),
332
  .RTY_I(1'b0),
333
  .SEL_O(eth_ma_wb_sel_o),
334
  .STB_O(eth_ma_wb_stb_o),
335
  .WE_O (eth_ma_wb_we_o),
336
  .TAG_I({`WB_TAG_WIDTH{1'b0}}),
337
  .TAG_O(),
338
  .CAB_O(1'b0),
339
  .log_file_desc(wb_m_mon_log_file_desc)
340 116 mohor
);
341
 
342
 
343
 
344 169 mohor
reg         StartTB;
345
integer     tb_log_file;
346 116 mohor
 
347 169 mohor
initial
348
begin
349
  tb_log_file = $fopen("../log/eth_tb.log");
350
  if (tb_log_file < 2)
351
  begin
352
    $display("*E Could not open/create testbench log file in ../log/ directory!");
353
    $finish;
354
  end
355
  $fdisplay(tb_log_file, "========================== ETHERNET IP Core Testbench results ===========================");
356
  $fdisplay(tb_log_file, " ");
357 116 mohor
 
358 169 mohor
  phy_log_file_desc = $fopen("../log/eth_tb_phy.log");
359
  if (phy_log_file_desc < 2)
360
  begin
361
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_phy.log file in ../log/ directory!");
362
    $finish;
363
  end
364
  $fdisplay(phy_log_file_desc, "================ PHY Module  Testbench access log ================");
365
  $fdisplay(phy_log_file_desc, " ");
366
 
367
  memory_log_file_desc = $fopen("../log/eth_tb_memory.log");
368
  if (memory_log_file_desc < 2)
369
  begin
370
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_memory.log file in ../log/ directory!");
371
    $finish;
372
  end
373
  $fdisplay(memory_log_file_desc, "=============== MEMORY Module Testbench access log ===============");
374
  $fdisplay(memory_log_file_desc, " ");
375
 
376
  host_log_file_desc = $fopen("../log/eth_tb_host.log");
377
  if (host_log_file_desc < 2)
378
  begin
379
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_host.log file in ../log/ directory!");
380
    $finish;
381
  end
382
  $fdisplay(host_log_file_desc, "================ HOST Module Testbench access log ================");
383
  $fdisplay(host_log_file_desc, " ");
384
 
385
  wb_s_mon_log_file_desc = $fopen("../log/eth_tb_wb_s_mon.log");
386
  if (wb_s_mon_log_file_desc < 2)
387
  begin
388
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_wb_s_mon.log file in ../log/ directory!");
389
    $finish;
390
  end
391
  $fdisplay(wb_s_mon_log_file_desc, "============== WISHBONE Slave Bus Monitor error log ==============");
392
  $fdisplay(wb_s_mon_log_file_desc, " ");
393
  $fdisplay(wb_s_mon_log_file_desc, "   Only ERRONEOUS conditions are logged !");
394
  $fdisplay(wb_s_mon_log_file_desc, " ");
395
 
396
  wb_m_mon_log_file_desc = $fopen("../log/eth_tb_wb_m_mon.log");
397
  if (wb_m_mon_log_file_desc < 2)
398
  begin
399
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_wb_m_mon.log file in ../log/ directory!");
400
    $finish;
401
  end
402
  $fdisplay(wb_m_mon_log_file_desc, "============= WISHBONE Master Bus Monitor  error log =============");
403
  $fdisplay(wb_m_mon_log_file_desc, " ");
404
  $fdisplay(wb_m_mon_log_file_desc, "   Only ERRONEOUS conditions are logged !");
405
  $fdisplay(wb_m_mon_log_file_desc, " ");
406
 
407 243 tadejm
  // Reset pulse
408
  wb_rst =  1'b1;
409
  #423 wb_rst =  1'b0;
410
 
411 169 mohor
  // Clear memories
412
  clear_memories;
413 243 tadejm
  clear_buffer_descriptors;
414 169 mohor
 
415
  #423 StartTB  =  1'b1;
416
end
417
 
418
 
419
 
420
// Generating wb_clk clock
421 116 mohor
initial
422
begin
423 169 mohor
  wb_clk=0;
424
//  forever #2.5 wb_clk = ~wb_clk;  // 2*2.5 ns -> 200.0 MHz    
425 274 tadejm
//  forever #5 wb_clk = ~wb_clk;  // 2*5 ns -> 100.0 MHz    
426 169 mohor
//  forever #10 wb_clk = ~wb_clk;  // 2*10 ns -> 50.0 MHz    
427
//  forever #12.5 wb_clk = ~wb_clk;  // 2*12.5 ns -> 40 MHz    
428 274 tadejm
  forever #15 wb_clk = ~wb_clk;  // 2*10 ns -> 33.3 MHz    
429 209 tadejm
//  forever #20 wb_clk = ~wb_clk;  // 2*20 ns -> 25 MHz    
430 169 mohor
//  forever #25 wb_clk = ~wb_clk;  // 2*25 ns -> 20.0 MHz
431
//  forever #31.25 wb_clk = ~wb_clk;  // 2*31.25 ns -> 16.0 MHz    
432
//  forever #50 wb_clk = ~wb_clk;  // 2*50 ns -> 10.0 MHz
433
//  forever #55 wb_clk = ~wb_clk;  // 2*55 ns ->  9.1 MHz    
434 116 mohor
end
435
 
436
 
437
 
438 169 mohor
integer      tests_successfull;
439
integer      tests_failed;
440
reg [799:0]  test_name; // used for tb_log_file
441 121 mohor
 
442 169 mohor
reg   [3:0]  wbm_init_waits; // initial wait cycles between CYC_O and STB_O of WB Master
443
reg   [3:0]  wbm_subseq_waits; // subsequent wait cycles between STB_Os of WB Master
444
reg   [2:0]  wbs_waits; // wait cycles befor WB Slave responds
445
reg   [7:0]  wbs_retries; // if RTY response, then this is the number of retries before ACK
446
 
447 274 tadejm
reg          wbm_working; // tasks wbm_write and wbm_read set signal when working and reset it when stop working
448
 
449
 
450 116 mohor
initial
451
begin
452 169 mohor
  wait(StartTB);  // Start of testbench
453
 
454
  // Initial global values
455
  tests_successfull = 0;
456
  tests_failed = 0;
457 274 tadejm
 
458
  wbm_working = 0;
459 169 mohor
 
460
  wbm_init_waits = 4'h1;
461
  wbm_subseq_waits = 4'h3;
462
  wbs_waits = 4'h1;
463
  wbs_retries = 8'h2;
464
  wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
465
 
466 274 tadejm
  // set DIFFERENT mrx_clk to mtx_clk!
467
//  eth_phy.set_mrx_equal_mtx = 1'b0;
468 169 mohor
 
469
  //  Call tests
470
  //  ----------
471 274 tadejm
//    test_access_to_mac_reg(0, 0);           // 0 - 3
472 194 tadej
//    test_mii(0, 17);                        // 0 - 17
473 169 mohor
  test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
474
  eth_phy.carrier_sense_real_delay(0);
475 274 tadejm
//    test_mac_full_duplex_transmit(0, 23);    // 0 - (21)
476 279 mohor
    test_mac_full_duplex_transmit(0, 21);    // 0 - (21)
477
//    test_mac_full_duplex_receive(2, 3);     // 0 - 13
478 274 tadejm
//    test_mac_full_duplex_flow_control(0, 4);  // 0 - 5   What 5 stands for ?
479
                                              // 4 is executed, everything is OK
480
//    test_mac_half_duplex_flow(0, 0);
481 169 mohor
 
482 243 tadejm
  test_note("PHY generates 'real delayed' Carrier sense and Collision signals for following tests");
483 169 mohor
  eth_phy.carrier_sense_real_delay(1);
484
 
485
 
486
  // Finish test's logs
487
  test_summary;
488
  $display("\n\n END of SIMULATION");
489
  $fclose(tb_log_file | phy_log_file_desc | memory_log_file_desc | host_log_file_desc);
490
  $fclose(wb_s_mon_log_file_desc | wb_m_mon_log_file_desc);
491
 
492
  $stop;
493 116 mohor
end
494 169 mohor
 
495 116 mohor
 
496 169 mohor
 
497
//////////////////////////////////////////////////////////////
498
// Test tasks
499
//////////////////////////////////////////////////////////////
500
 
501
task test_access_to_mac_reg;
502
  input  [31:0]  start_task;
503
  input  [31:0]  end_task;
504
  integer        bit_start_1;
505
  integer        bit_end_1;
506
  integer        bit_start_2;
507
  integer        bit_end_2;
508
  integer        num_of_reg;
509
  integer        i_addr;
510
  integer        i_data;
511
  integer        i_length;
512
  integer        tmp_data;
513
  reg    [31:0]  tx_bd_num;
514
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
515
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
516
  integer        i;
517
  integer        i1;
518
  integer        i2;
519
  integer        i3;
520
  integer        fail;
521 178 mohor
  integer        test_num;
522 169 mohor
  reg    [31:0]  addr;
523
  reg    [31:0]  data;
524
  reg    [31:0]  data_max;
525 116 mohor
begin
526 169 mohor
// ACCESS TO MAC REGISTERS TEST
527
test_heading("ACCESS TO MAC REGISTERS TEST");
528
$display(" ");
529
$display("ACCESS TO MAC REGISTERS TEST");
530
fail = 0;
531
 
532 192 tadej
// reset MAC registers
533
hard_reset;
534
// reset MAC and MII LOGIC with soft reset
535 274 tadejm
//reset_mac;
536
//reset_mii;
537 169 mohor
 
538 192 tadej
 
539 178 mohor
//////////////////////////////////////////////////////////////////////
540
////                                                              ////
541
////  test_access_to_mac_reg:                                     ////
542
////                                                              ////
543
////  0: Walking 1 with single cycles across MAC regs.            ////
544
////  1: Walking 1 with single cycles across MAC buffer descript. ////
545
////  2: Test max reg. values and reg. values after writing       ////
546
////     inverse reset values and hard reset of the MAC           ////
547
////  3: Test buffer desc. RAM preserving values after hard reset ////
548
////     of the MAC and resetting the logic                       ////
549
////                                                              ////
550
//////////////////////////////////////////////////////////////////////
551 194 tadej
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
552 169 mohor
begin
553
 
554 178 mohor
  ////////////////////////////////////////////////////////////////////
555
  ////                                                            ////
556
  ////  Walking 1 with single cycles across MAC regs.             ////
557
  ////                                                            ////
558
  ////////////////////////////////////////////////////////////////////
559
  if (test_num == 0) // Walking 1 with single cycles across MAC regs.
560 194 tadej
  begin
561
    // TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
562
    test_name   = "TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
563
    `TIME; $display("  TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
564 178 mohor
 
565 194 tadej
    data = 0;
566
    for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
567
      begin
568
        wbm_init_waits = i;
569
        wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
570
        for (i_addr = 0; i_addr <= 32'h4C; i_addr = i_addr + 4) // register address
571
          begin
572
            addr = `ETH_BASE + i_addr;
573
            // set ranges of R/W bits
574
            case (addr)
575
              `ETH_MODER:
576
                begin
577
                  bit_start_1 = 0;
578
                  bit_end_1   = 16;
579
                  bit_start_2 = 32; // not used
580
                  bit_end_2   = 32; // not used
581
                end
582
              `ETH_INT: // READONLY - tested within INT test
583
                begin
584
                  bit_start_1 = 32; // not used
585
                  bit_end_1   = 32; // not used
586
                  bit_start_2 = 32; // not used
587
                  bit_end_2   = 32; // not used
588
                end
589
              `ETH_INT_MASK:
590
                begin
591
                  bit_start_1 = 0;
592
                  bit_end_1   = 6;
593
                  bit_start_2 = 32; // not used
594
                  bit_end_2   = 32; // not used
595
                end
596
              `ETH_IPGT:
597
                begin
598
                  bit_start_1 = 0;
599
                  bit_end_1   = 6;
600
                  bit_start_2 = 32; // not used
601
                  bit_end_2   = 32; // not used
602
                end
603
              `ETH_IPGR1:
604
                begin
605
                  bit_start_1 = 0;
606
                  bit_end_1   = 6;
607
                  bit_start_2 = 32; // not used
608
                  bit_end_2   = 32; // not used
609
                end
610
              `ETH_IPGR2:
611
                begin
612
                  bit_start_1 = 0;
613
                  bit_end_1   = 6;
614
                  bit_start_2 = 32; // not used
615
                  bit_end_2   = 32; // not used
616
                end
617
              `ETH_PACKETLEN:
618
                begin
619
                  bit_start_1 = 0;
620
                  bit_end_1   = 31;
621
                  bit_start_2 = 32; // not used
622
                  bit_end_2   = 32; // not used
623
                end
624
              `ETH_COLLCONF:
625
                begin
626
                  bit_start_1 = 0;
627
                  bit_end_1   = 5;
628
                  bit_start_2 = 16;
629
                  bit_end_2   = 19;
630
                end
631
              `ETH_TX_BD_NUM:
632
                begin
633
                  bit_start_1 = 0;
634
                  bit_end_1   = 7;
635
                  bit_start_2 = 32; // not used
636
                  bit_end_2   = 32; // not used
637
                end
638
              `ETH_CTRLMODER:
639
                begin
640
                  bit_start_1 = 0;
641
                  bit_end_1   = 2;
642
                  bit_start_2 = 32; // not used
643
                  bit_end_2   = 32; // not used
644
                end
645
              `ETH_MIIMODER:
646
                begin
647
                  bit_start_1 = 0;
648
                  bit_end_1   = 9;
649
                  bit_start_2 = 32; // not used
650
                  bit_end_2   = 32; // not used
651
                end
652
              `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
653
                begin
654
                  bit_start_1 = 32; // not used
655
                  bit_end_1   = 32; // not used
656
                  bit_start_2 = 32; // not used
657
                  bit_end_2   = 32; // not used
658
                end
659
              `ETH_MIIADDRESS:
660
                begin
661
                  bit_start_1 = 0;
662
                  bit_end_1   = 4;
663
                  bit_start_2 = 8;
664
                  bit_end_2   = 12;
665
                end
666
              `ETH_MIITX_DATA:
667
                begin
668
                  bit_start_1 = 0;
669
                  bit_end_1   = 15;
670
                  bit_start_2 = 32; // not used
671
                  bit_end_2   = 32; // not used
672
                end
673
              `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
674
                begin
675
                  bit_start_1 = 32; // not used
676
                  bit_end_1   = 32; // not used
677
                  bit_start_2 = 32; // not used
678
                  bit_end_2   = 32; // not used
679
                end
680
              `ETH_MIISTATUS: // READONLY - tested within MIIM test
681
                begin
682
                  bit_start_1 = 32; // not used
683
                  bit_end_1   = 32; // not used
684
                  bit_start_2 = 32; // not used
685
                  bit_end_2   = 32; // not used
686
                end
687
              `ETH_MAC_ADDR0:
688
                begin
689
                  bit_start_1 = 0;
690
                  bit_end_1   = 31;
691
                  bit_start_2 = 32; // not used
692
                  bit_end_2   = 32; // not used
693 178 mohor
                  end
694 194 tadej
              `ETH_MAC_ADDR1:
695
                begin
696
                  bit_start_1 = 0;
697
                  bit_end_1   = 15;
698
                  bit_start_2 = 32; // not used
699
                  bit_end_2   = 32; // not used
700
                end
701
              `ETH_HASH_ADDR0:
702
                begin
703
                  bit_start_1 = 0;
704
                  bit_end_1   = 31;
705
                  bit_start_2 = 32; // not used
706
                  bit_end_2   = 32; // not used
707
                end
708
              default: // `ETH_HASH_ADDR1:
709
                begin
710
                  bit_start_1 = 0;
711
                  bit_end_1   = 31;
712
                  bit_start_2 = 32; // not used
713
                  bit_end_2   = 32; // not used
714
                end
715
            endcase
716
 
717
            for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
718
              begin
719
                data = 1'b1 << i_data;
720
                if ( (addr == `ETH_MIICOMMAND) && (i_data <= 2) ) // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
721
                  ;
722
                else
723 178 mohor
                  begin
724 194 tadej
                    wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
725 274 tadejm
                    wait (wbm_working == 0);
726 194 tadej
                    wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
727
                    if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
728
                         ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
729
                      begin
730
                        if (tmp_data !== data)
731 178 mohor
                        begin
732 194 tadej
                          fail = fail + 1;
733
                          test_fail("RW bit of the MAC register was not written or not read");
734
                          `TIME;
735
                          $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
736
                                    wbm_init_waits, addr, data, tmp_data);
737
                        end
738
                      end
739
                    else // data should not be equal to tmp_data
740
                      begin
741
                        if (tmp_data === data)
742 178 mohor
                          begin
743
                            fail = fail + 1;
744 194 tadej
                            test_fail("NON RW bit of the MAC register was written, but it shouldn't be");
745 178 mohor
                            `TIME;
746 194 tadej
                            $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
747 178 mohor
                                      wbm_init_waits, addr, data, tmp_data);
748
                          end
749 194 tadej
                      end
750
                  end
751
              end
752
          end
753
      end
754 209 tadejm
    // INTERMEDIATE DISPLAYS (The only one)
755
    $display("    ->buffer descriptors tested with 0, 1, 2, 3 and 4 bus delay cycles");
756 194 tadej
    if(fail == 0)
757
      test_ok;
758
    else
759
      fail = 0;    // Errors were reported previously
760
  end
761 178 mohor
 
762
 
763
  ////////////////////////////////////////////////////////////////////
764
  ////                                                            ////
765
  ////  Walking 1 with single cycles across MAC buffer descript.  ////
766
  ////                                                            ////
767
  ////////////////////////////////////////////////////////////////////
768
  if (test_num == 1) // Start Walking 1 with single cycles across MAC buffer descript.
769 169 mohor
  begin
770 194 tadej
    // TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )
771
    test_name   = "TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )";
772
    `TIME; $display("  TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )");
773 178 mohor
 
774
    data = 0;
775
    // set TX and RX buffer descriptors
776
    tx_bd_num = 32'h40;
777
    wbm_write(`ETH_TX_BD_NUM, tx_bd_num, 4'hF, 1, 0, 0);
778
    for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
779
    begin
780 169 mohor
      wbm_init_waits = i;
781
      wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
782 178 mohor
      for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
783 169 mohor
      begin
784
        addr = `ETH_BASE + i_addr;
785 178 mohor
        if (i_addr < (32'h400 + (tx_bd_num << 3))) // TX buffer descriptors
786
        begin
787
          // set ranges of R/W bits
788
          case (addr[3])
789
            1'b0: // buffer control bits
790
            begin
791
              bit_start_1 = 0;
792
              bit_end_1   = 31; // 8;
793
              bit_start_2 = 11;
794
              bit_end_2   = 31;
795
            end
796
            default: // 1'b1: // buffer pointer
797
            begin
798
              bit_start_1 = 0;
799
              bit_end_1   = 31;
800
              bit_start_2 = 32; // not used
801
              bit_end_2   = 32; // not used
802
            end
803
          endcase
804
        end
805
        else // RX buffer descriptors
806
        begin
807
          // set ranges of R/W bits
808
          case (addr[3])
809
            1'b0: // buffer control bits
810
            begin
811
              bit_start_1 = 0;
812
              bit_end_1   = 31; // 7;
813
              bit_start_2 = 13;
814
              bit_end_2   = 31;
815
            end
816
            default: // 1'b1: // buffer pointer
817
            begin
818
              bit_start_1 = 0;
819
              bit_end_1   = 31;
820
              bit_start_2 = 32; // not used
821
              bit_end_2   = 32; // not used
822
            end
823
          endcase
824
        end
825
 
826 169 mohor
        for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
827
        begin
828
          data = 1'b1 << i_data;
829 178 mohor
          if ( (addr[3] == 0) && (i_data == 15) ) // DO NOT WRITE to this bit !!!
830
            ;
831 169 mohor
          else
832
          begin
833
            wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
834
            wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
835
            if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
836
                 ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
837
            begin
838
              if (tmp_data !== data)
839
              begin
840
                fail = fail + 1;
841 178 mohor
                test_fail("RW bit of the MAC buffer descriptors was not written or not read");
842 169 mohor
                `TIME;
843
                $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
844
                          wbm_init_waits, addr, data, tmp_data);
845
              end
846
            end
847
            else // data should not be equal to tmp_data
848
            begin
849
              if (tmp_data === data)
850
              begin
851
                fail = fail + 1;
852 178 mohor
                test_fail("NON RW bit of the MAC buffer descriptors was written, but it shouldn't be");
853 169 mohor
                `TIME;
854
                $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
855
                          wbm_init_waits, addr, data, tmp_data);
856
              end
857
            end
858
          end
859
        end
860
      end
861 178 mohor
      // INTERMEDIATE DISPLAYS
862
      case (i)
863 209 tadejm
        0:       $display("    ->buffer descriptors tested with 0 bus delay");
864
        1:       $display("    ->buffer descriptors tested with 1 bus delay cycle");
865
        2:       $display("    ->buffer descriptors tested with 2 bus delay cycles");
866
        3:       $display("    ->buffer descriptors tested with 3 bus delay cycles");
867
        default: $display("    ->buffer descriptors tested with 4 bus delay cycles");
868 178 mohor
      endcase
869
    end
870
    if(fail == 0)
871
      test_ok;
872
    else
873
      fail = 0;
874 169 mohor
  end
875 178 mohor
 
876
 
877
  ////////////////////////////////////////////////////////////////////
878
  ////                                                            ////
879
  ////  Test max reg. values and reg. values after writing        ////
880
  ////  inverse reset values and hard reset of the MAC            ////
881
  ////                                                            ////
882
  ////////////////////////////////////////////////////////////////////
883
  if (test_num == 2) // Start this task
884 169 mohor
  begin
885 194 tadej
    // TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC
886 178 mohor
    test_name   =
887 194 tadej
      "TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC";
888 178 mohor
    `TIME; $display(
889 194 tadej
      "  TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC");
890 178 mohor
 
891
    // reset MAC registers
892
    hard_reset;
893
    for (i = 0; i <= 4; i = i + 1) // 0, 2 - WRITE; 1, 3, 4 - READ
894 169 mohor
    begin
895 178 mohor
      for (i_addr = 0; i_addr <= 32'h4C; i_addr = i_addr + 4) // register address
896 169 mohor
      begin
897 178 mohor
        addr = `ETH_BASE + i_addr;
898
        // set ranges of R/W bits
899
        case (addr)
900
          `ETH_MODER:
901 169 mohor
          begin
902 178 mohor
            data = 32'h0000_A800;
903
            data_max = 32'h0001_FFFF;
904 169 mohor
          end
905 178 mohor
          `ETH_INT: // READONLY - tested within INT test
906 169 mohor
          begin
907 178 mohor
            data = 32'h0000_0000;
908
            data_max = 32'h0000_0000;
909 169 mohor
          end
910
          `ETH_INT_MASK:
911 178 mohor
          begin
912
            data = 32'h0000_0000;
913
            data_max = 32'h0000_007F;
914
          end
915 169 mohor
          `ETH_IPGT:
916 178 mohor
          begin
917
            data = 32'h0000_0012;
918
            data_max = 32'h0000_007F;
919
          end
920 169 mohor
          `ETH_IPGR1:
921 178 mohor
          begin
922
            data = 32'h0000_000C;
923
            data_max = 32'h0000_007F;
924
          end
925 169 mohor
          `ETH_IPGR2:
926 178 mohor
          begin
927
            data = 32'h0000_0012;
928
            data_max = 32'h0000_007F;
929
          end
930 169 mohor
          `ETH_PACKETLEN:
931 178 mohor
          begin
932
            data = 32'h0040_0600;
933
            data_max = 32'hFFFF_FFFF;
934
          end
935 169 mohor
          `ETH_COLLCONF:
936 178 mohor
          begin
937
            data = 32'h000F_003F;
938
            data_max = 32'h000F_003F;
939
          end
940 169 mohor
          `ETH_TX_BD_NUM:
941 178 mohor
          begin
942
            data = 32'h0000_0040;
943
            data_max = 32'h0000_0080;
944
          end
945 169 mohor
          `ETH_CTRLMODER:
946 178 mohor
          begin
947
            data = 32'h0000_0000;
948
            data_max = 32'h0000_0007;
949
          end
950 169 mohor
          `ETH_MIIMODER:
951 178 mohor
          begin
952
            data = 32'h0000_0064;
953
            data_max = 32'h0000_03FF;
954
          end
955 169 mohor
          `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
956 178 mohor
          begin
957
            data = 32'h0000_0000;
958
            data_max = 32'h0000_0007;
959
          end
960 169 mohor
          `ETH_MIIADDRESS:
961 178 mohor
          begin
962
            data = 32'h0000_0000;
963
            data_max = 32'h0000_1F1F;
964
          end
965 169 mohor
          `ETH_MIITX_DATA:
966 178 mohor
          begin
967
            data = 32'h0000_0000;
968
            data_max = 32'h0000_FFFF;
969
          end
970 169 mohor
          `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
971
          begin
972 178 mohor
            data = 32'h0000_0000;
973
            data_max = 32'h0000_0000;
974 169 mohor
          end
975 178 mohor
          `ETH_MIISTATUS: // READONLY - tested within MIIM test
976 169 mohor
          begin
977 178 mohor
            data = 32'h0000_0000;
978
            data_max = 32'h0000_0000;
979 169 mohor
          end
980 178 mohor
          `ETH_MAC_ADDR0:
981 169 mohor
          begin
982 178 mohor
            data = 32'h0000_0000;
983
            data_max = 32'hFFFF_FFFF;
984 169 mohor
          end
985 178 mohor
          `ETH_MAC_ADDR1:
986 169 mohor
          begin
987 178 mohor
            data = 32'h0000_0000;
988
            data_max = 32'h0000_FFFF;
989 169 mohor
          end
990 178 mohor
          `ETH_HASH_ADDR0:
991 169 mohor
          begin
992 178 mohor
            data = 32'h0000_0000;
993
            data_max = 32'hFFFF_FFFF;
994 169 mohor
          end
995 178 mohor
          default: // `ETH_HASH_ADDR1:
996 169 mohor
          begin
997 178 mohor
            data = 32'h0000_0000;
998
            data_max = 32'hFFFF_FFFF;
999 169 mohor
          end
1000
        endcase
1001 178 mohor
 
1002
        wbm_init_waits = {$random} % 3;
1003
        wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
1004
        if (i == 0)
1005 274 tadejm
        begin
1006 178 mohor
          wbm_write(addr, ~data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1007 274 tadejm
        end
1008 178 mohor
        else if (i == 2)
1009 274 tadejm
        begin
1010 178 mohor
          wbm_write(addr, 32'hFFFFFFFF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1011 274 tadejm
        end
1012 178 mohor
        else if ((i == 1) || (i == 4))
1013 169 mohor
        begin
1014 178 mohor
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1015
          if (tmp_data !== data)
1016
          begin
1017
            fail = fail + 1;
1018
            test_fail("RESET value of the MAC register is not correct");
1019
            `TIME;
1020
            $display("  addr %h, data %h, tmp_data %h", addr, data, tmp_data);
1021
          end
1022 169 mohor
        end
1023 178 mohor
        else // check maximum values
1024 169 mohor
        begin
1025
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1026 178 mohor
          if (addr == `ETH_TX_BD_NUM) // previous data should remain in this register
1027 169 mohor
          begin
1028
            if (tmp_data !== data)
1029
            begin
1030
              fail = fail + 1;
1031 178 mohor
              test_fail("Previous value of the TX_BD_NUM register did not remain");
1032 169 mohor
              `TIME;
1033 178 mohor
              $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1034 169 mohor
            end
1035 178 mohor
            // try maximum (80)
1036
            wbm_write(addr, data_max, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1037
            wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1038
            if (tmp_data !== data_max)
1039
            begin
1040
              fail = fail + 1;
1041
              test_fail("MAX value of the TX_BD_NUM register is not correct");
1042
              `TIME;
1043
              $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1044
            end
1045
            // try one less than maximum (80)
1046
            wbm_write(addr, (data_max - 1), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1047
            wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1048
            if (tmp_data !== (data_max - 1))
1049
            begin
1050
              fail = fail + 1;
1051
              test_fail("ONE less than MAX value of the TX_BD_NUM register is not correct");
1052
              `TIME;
1053
              $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1054
            end
1055
            // try one more than maximum (80)
1056
            wbm_write(addr, (data_max + 1), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1057
            wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1058
            if (tmp_data !== (data_max - 1)) // previous data should remain in this register
1059
            begin
1060
              fail = fail + 1;
1061
              test_fail("Previous value of the TX_BD_NUM register did not remain");
1062
              `TIME;
1063
              $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1064
            end
1065 169 mohor
          end
1066 178 mohor
          else
1067 169 mohor
          begin
1068 178 mohor
            if (tmp_data !== data_max)
1069 169 mohor
            begin
1070
              fail = fail + 1;
1071 178 mohor
              test_fail("MAX value of the MAC register is not correct");
1072 169 mohor
              `TIME;
1073 178 mohor
              $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1074 169 mohor
            end
1075
          end
1076
        end
1077
      end
1078 178 mohor
      // reset MAC registers
1079
      if ((i == 0) || (i == 3))
1080
        hard_reset;
1081 169 mohor
    end
1082 178 mohor
    if(fail == 0)
1083
      test_ok;
1084
    else
1085
      fail = 0;
1086 169 mohor
  end
1087 116 mohor
 
1088 156 mohor
 
1089 181 mohor
  ////////////////////////////////////////////////////////////////////
1090
  ////                                                            ////
1091
  ////  Test buffer desc. ram preserving values after hard reset  ////
1092
  ////  of the mac and reseting the logic                         ////
1093
  ////                                                            ////
1094
  ////////////////////////////////////////////////////////////////////
1095 178 mohor
  if (test_num == 3) // Start this task
1096 169 mohor
  begin
1097 194 tadej
    // TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC
1098
    test_name   = "TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC";
1099 178 mohor
    `TIME;
1100 194 tadej
    $display("  TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");
1101 178 mohor
 
1102
    // reset MAC registers
1103
    hard_reset;
1104
    // reset LOGIC with soft reset
1105 274 tadejm
//    reset_mac;
1106
//    reset_mii;
1107 178 mohor
    for (i = 0; i <= 3; i = i + 1) // 0, 2 - WRITE; 1, 3 - READ
1108 169 mohor
    begin
1109 178 mohor
      for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
1110 169 mohor
      begin
1111 178 mohor
        addr = `ETH_BASE + i_addr;
1112
 
1113
        wbm_init_waits = {$random} % 3;
1114
        wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
1115
        if (i == 0)
1116 169 mohor
        begin
1117 178 mohor
          data = 32'hFFFFFFFF;
1118
          wbm_write(addr, 32'hFFFFFFFF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1119 169 mohor
        end
1120 178 mohor
        else if (i == 2)
1121 169 mohor
        begin
1122 178 mohor
          data = 32'h00000000;
1123
          wbm_write(addr, 32'h00000000, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1124 169 mohor
        end
1125
        else
1126
        begin
1127 178 mohor
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1128
          if (tmp_data !== data)
1129 169 mohor
          begin
1130
            fail = fail + 1;
1131 178 mohor
            test_fail("PRESERVED value of the MAC buffer descriptors is not correct");
1132 169 mohor
            `TIME;
1133 178 mohor
            $display("  addr %h, data %h, tmp_data %h", addr, data, tmp_data);
1134 169 mohor
          end
1135
        end
1136
      end
1137 178 mohor
      if ((i == 0) || (i == 2))
1138
      begin
1139
        // reset MAC registers
1140
        hard_reset;
1141
        // reset LOGIC with soft reset
1142 274 tadejm
//        reset_mac;
1143
//        reset_mii;
1144 178 mohor
      end
1145 169 mohor
    end
1146 178 mohor
    if(fail == 0)
1147
      test_ok;
1148
    else
1149
    fail = 0;
1150 169 mohor
  end
1151 116 mohor
 
1152
 
1153 178 mohor
  if (test_num == 4) // Start this task
1154 169 mohor
  begin
1155 194 tadej
        /*  // TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
1156
          test_name   = "TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
1157
          `TIME; $display("  TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
1158 178 mohor
 
1159
          data = 0;
1160
          burst_data = 0;
1161
          burst_tmp_data = 0;
1162
          i_length = 10; // two bursts for length 20
1163
          for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
1164
          begin
1165
            for (i1 = 0; i1 <= 4; i1 = i1 + 1) // for initial wait cycles on WB bus
1166
            begin
1167
              wbm_init_waits = i;
1168
              wbm_subseq_waits = i1;
1169
              #1;
1170
              for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
1171
              begin
1172
                data = 1'b1 << i_data;
1173
                #1;
1174
                for (i2 = 32'h4C; i2 >= 0; i2 = i2 - 4)
1175
                begin
1176
                  burst_data = burst_data << 32;
1177
                  // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
1178
                  if ( ((`ETH_BASE + i2) == `ETH_MIICOMMAND) && (i_data <= 2) )
1179
                  begin
1180
                    #1 burst_data[31:0] = 0;
1181
                  end
1182
                  else
1183
                  begin
1184
                    #1 burst_data[31:0] = data;
1185
                  end
1186
                end
1187
                #1;
1188
                // 2 burst writes
1189
                addr = `ETH_BASE; // address of a first burst
1190
                wbm_write(addr, burst_data[(32 * 10 - 1):0], 4'hF, i_length, wbm_init_waits, wbm_subseq_waits);
1191
                burst_tmp_data = burst_data >> (32 * i_length);
1192
                addr = addr + 32'h28; // address of a second burst
1193
                wbm_write(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length, wbm_init_waits, wbm_subseq_waits);
1194
                #1;
1195
                // 2 burst reads
1196
                addr = `ETH_BASE; // address of a first burst
1197
                wbm_read(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length,
1198
                         wbm_init_waits, wbm_subseq_waits); // first burst
1199
                burst_tmp_data = burst_tmp_data << (32 * i_length);
1200
                addr = addr + 32'h28; // address of a second burst
1201
                wbm_read(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length,
1202
                         wbm_init_waits, wbm_subseq_waits); // second burst
1203
                #1;
1204
                for (i2 = 0; i2 <= 32'h4C; i2 = i2 + 4)
1205
                begin
1206
                  // set ranges of R/W bits
1207
                  case (`ETH_BASE + i2)
1208
                  `ETH_MODER:
1209
                    begin
1210
                      bit_start_1 = 0;
1211
                      bit_end_1   = 16;
1212
                      bit_start_2 = 32; // not used
1213
                      bit_end_2   = 32; // not used
1214
                    end
1215
                  `ETH_INT: // READONLY - tested within INT test
1216
                    begin
1217
                      bit_start_1 = 32; // not used
1218
                      bit_end_1   = 32; // not used
1219
                      bit_start_2 = 32; // not used
1220
                      bit_end_2   = 32; // not used
1221
                    end
1222
                  `ETH_INT_MASK:
1223
                    begin
1224
                      bit_start_1 = 0;
1225
                      bit_end_1   = 6;
1226
                      bit_start_2 = 32; // not used
1227
                      bit_end_2   = 32; // not used
1228
                    end
1229
                  `ETH_IPGT:
1230
                    begin
1231
                      bit_start_1 = 0;
1232
                      bit_end_1   = 6;
1233
                      bit_start_2 = 32; // not used
1234
                      bit_end_2   = 32; // not used
1235
                    end
1236
                  `ETH_IPGR1:
1237
                    begin
1238
                      bit_start_1 = 0;
1239
                      bit_end_1   = 6;
1240
                      bit_start_2 = 32; // not used
1241
                      bit_end_2   = 32; // not used
1242
                    end
1243
                  `ETH_IPGR2:
1244
                    begin
1245
                      bit_start_1 = 0;
1246
                      bit_end_1   = 6;
1247
                      bit_start_2 = 32; // not used
1248
                      bit_end_2   = 32; // not used
1249
                    end
1250
                  `ETH_PACKETLEN:
1251
                    begin
1252
                      bit_start_1 = 0;
1253
                      bit_end_1   = 31;
1254
                      bit_start_2 = 32; // not used
1255
                      bit_end_2   = 32; // not used
1256
                    end
1257
                  `ETH_COLLCONF:
1258
                    begin
1259
                      bit_start_1 = 0;
1260
                      bit_end_1   = 5;
1261
                      bit_start_2 = 16;
1262
                      bit_end_2   = 19;
1263
                    end
1264
                  `ETH_TX_BD_NUM:
1265
                    begin
1266
                      bit_start_1 = 0;
1267
                      bit_end_1   = 7;
1268
                      bit_start_2 = 32; // not used
1269
                      bit_end_2   = 32; // not used
1270
                    end
1271
                  `ETH_CTRLMODER:
1272
                    begin
1273
                      bit_start_1 = 0;
1274
                      bit_end_1   = 2;
1275
                      bit_start_2 = 32; // not used
1276
                      bit_end_2   = 32; // not used
1277
                    end
1278
                  `ETH_MIIMODER:
1279
                    begin
1280
                      bit_start_1 = 0;
1281
                      bit_end_1   = 9;
1282
                      bit_start_2 = 32; // not used
1283
                      bit_end_2   = 32; // not used
1284
                    end
1285
                  `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
1286
                    begin
1287
                      bit_start_1 = 32; // not used
1288
                      bit_end_1   = 32; // not used
1289
                      bit_start_2 = 32; // not used
1290
                      bit_end_2   = 32; // not used
1291
                    end
1292
                  `ETH_MIIADDRESS:
1293
                    begin
1294
                      bit_start_1 = 0;
1295
                      bit_end_1   = 4;
1296
                      bit_start_2 = 8;
1297
                      bit_end_2   = 12;
1298
                    end
1299
                  `ETH_MIITX_DATA:
1300
                    begin
1301
                      bit_start_1 = 0;
1302
                      bit_end_1   = 15;
1303
                      bit_start_2 = 32; // not used
1304
                      bit_end_2   = 32; // not used
1305
                    end
1306
                  `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
1307
                    begin
1308
                      bit_start_1 = 32; // not used
1309
                      bit_end_1   = 32; // not used
1310
                      bit_start_2 = 32; // not used
1311
                      bit_end_2   = 32; // not used
1312
                    end
1313
                  `ETH_MIISTATUS: // READONLY - tested within MIIM test
1314
                    begin
1315
                      bit_start_1 = 32; // not used
1316
                      bit_end_1   = 32; // not used
1317
                      bit_start_2 = 32; // not used
1318
                      bit_end_2   = 32; // not used
1319
                    end
1320
                  `ETH_MAC_ADDR0:
1321
                    begin
1322
                      bit_start_1 = 0;
1323
                      bit_end_1   = 31;
1324
                      bit_start_2 = 32; // not used
1325
                      bit_end_2   = 32; // not used
1326
                    end
1327
                  `ETH_MAC_ADDR1:
1328
                    begin
1329
                      bit_start_1 = 0;
1330
                      bit_end_1   = 15;
1331
                      bit_start_2 = 32; // not used
1332
                      bit_end_2   = 32; // not used
1333
                    end
1334
                  `ETH_HASH_ADDR0:
1335
                    begin
1336
                      bit_start_1 = 0;
1337
                      bit_end_1   = 31;
1338
                      bit_start_2 = 32; // not used
1339
                      bit_end_2   = 32; // not used
1340
                    end
1341
                  default: // `ETH_HASH_ADDR1:
1342
                    begin
1343
                      bit_start_1 = 0;
1344
                      bit_end_1   = 31;
1345
                      bit_start_2 = 32; // not used
1346
                      bit_end_2   = 32; // not used
1347
                    end
1348
                  endcase
1349
                  #1;
1350
                  // 3 LSBits of MIICOMMAND are NOT written !!!
1351
                  if ( ((`ETH_BASE + i2) == `ETH_MIICOMMAND) && (i_data <= 2) )
1352
                  begin
1353
                    if (burst_tmp_data[31:0] !== burst_data[31:0])
1354
                    begin
1355
                      fail = fail + 1;
1356
                      test_fail("NON WR bit of the MAC MIICOMMAND register was wrong written or read");
1357
                      `TIME;
1358
                      $display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
1359
                                wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
1360
                    end
1361
                  end
1362
                  else
1363
                  begin
1364
                    if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
1365
                         ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
1366
                    begin
1367
                      if (burst_tmp_data[31:0] !== burst_data[31:0])
1368
                      begin
1369
                        fail = fail + 1;
1370
                        test_fail("RW bit of the MAC register was not written or not read");
1371
                        `TIME;
1372
                        $display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
1373
                                  wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
1374
                      end
1375
                    end
1376
                    else // data should not be equal to tmp_data
1377
                    begin
1378
                      if (burst_tmp_data[31:0] === burst_data[31:0])
1379
                      begin
1380
                        fail = fail + 1;
1381
                        test_fail("NON RW bit of the MAC register was written, but it shouldn't be");
1382
                        `TIME;
1383
                        $display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
1384
                                  wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
1385
                      end
1386
                    end
1387
                  end
1388
                  burst_tmp_data = burst_tmp_data >> 32;
1389
                  burst_data = burst_data >> 32;
1390
                end
1391
              end
1392
            end
1393
          end
1394
          if(fail == 0)
1395
            test_ok;
1396
          else
1397
            fail = 0;*/
1398
  end
1399 116 mohor
 
1400 169 mohor
end
1401 156 mohor
 
1402 169 mohor
end
1403
endtask // test_access_to_mac_reg
1404 156 mohor
 
1405
 
1406 169 mohor
task test_mii;
1407
  input  [31:0]  start_task;
1408
  input  [31:0]  end_task;
1409
  integer        i;
1410
  integer        i1;
1411
  integer        i2;
1412
  integer        i3;
1413
  integer        cnt;
1414
  integer        fail;
1415 181 mohor
  integer        test_num;
1416 169 mohor
  reg     [8:0]  clk_div; // only 8 bits are valid!
1417
  reg     [4:0]  phy_addr;
1418
  reg     [4:0]  reg_addr;
1419
  reg     [15:0] phy_data;
1420
  reg     [15:0] tmp_data;
1421
begin
1422
// MIIM MODULE TEST
1423
test_heading("MIIM MODULE TEST");
1424
$display(" ");
1425
$display("MIIM MODULE TEST");
1426
fail = 0;
1427 156 mohor
 
1428 192 tadej
// reset MAC registers
1429
hard_reset;
1430
// reset MAC and MII LOGIC with soft reset
1431 274 tadejm
//reset_mac;
1432
//reset_mii;
1433 116 mohor
 
1434 194 tadej
 
1435 181 mohor
//////////////////////////////////////////////////////////////////////
1436
////                                                              ////
1437
////  test_mii:                                                   ////
1438
////                                                              ////
1439
////  0:  Test clock divider of mii management module with all    ////
1440
////      possible frequences.                                    ////
1441
////  1:  Test various readings from 'real' phy registers.        ////
1442
////  2:  Test various writings to 'real' phy registers (control  ////
1443
////      and non writable registers)                             ////
1444
////  3:  Test reset phy through mii management module            ////
1445
////  4:  Test 'walking one' across phy address (with and without ////
1446
////      preamble)                                               ////
1447
////  5:  Test 'walking one' across phy's register address (with  ////
1448
////      and without preamble)                                   ////
1449
////  6:  Test 'walking one' across phy's data (with and without  ////
1450
////      preamble)                                               ////
1451
////  7:  Test reading from phy with wrong phy address (host      ////
1452
////      reading high 'z' data)                                  ////
1453
////  8:  Test writing to phy with wrong phy address and reading  ////
1454
////      from correct one                                        ////
1455
////  9:  Test sliding stop scan command immediately after read   ////
1456
////      request (with and without preamble)                     ////
1457
//// 10:  Test sliding stop scan command immediately after write  ////
1458
////      request (with and without preamble)                     ////
1459
//// 11:  Test busy and nvalid status durations during write      ////
1460
////      (with and without preamble)                             ////
1461
//// 12:  Test busy and nvalid status durations during write      ////
1462
////      (with and without preamble)                             ////
1463
//// 13:  Test busy and nvalid status durations during scan (with ////
1464
////      and without preamble)                                   ////
1465
//// 14:  Test scan status from phy with detecting link-fail bit  ////
1466
////      (with and without preamble)                             ////
1467
//// 15:  Test scan status from phy with sliding link-fail bit    ////
1468
////      (with and without preamble)                             ////
1469
//// 16:  Test sliding stop scan command immediately after scan   ////
1470
////      request (with and without preamble)                     ////
1471
//// 17:  Test sliding stop scan command after 2. scan (with and  ////
1472
////      without preamble)                                       ////
1473
////                                                              ////
1474
//////////////////////////////////////////////////////////////////////
1475 194 tadej
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
1476 169 mohor
begin
1477 194 tadej
 
1478 181 mohor
  ////////////////////////////////////////////////////////////////////
1479
  ////                                                            ////
1480
  ////  Test clock divider of mii management module with all      ////
1481
  ////  possible frequences.                                      ////
1482
  ////                                                            ////
1483
  ////////////////////////////////////////////////////////////////////
1484
  if (test_num == 0) // Test clock divider of mii management module with all possible frequences.
1485 169 mohor
  begin
1486 194 tadej
    // TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES
1487
    test_name   = "TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES";
1488
    `TIME; $display("  TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES");
1489 181 mohor
 
1490
    wait(Mdc_O); // wait for MII clock to be 1
1491
    for(clk_div = 0; clk_div <= 255; clk_div = clk_div + 1)
1492
    begin
1493
      i1 = 0;
1494
      i2 = 0;
1495
      #Tp mii_set_clk_div(clk_div[7:0]);
1496
      @(posedge Mdc_O);
1497
      #Tp;
1498
      fork
1499 169 mohor
        begin
1500 181 mohor
          @(posedge Mdc_O);
1501 169 mohor
          #Tp;
1502 181 mohor
          disable count_i1;
1503
          disable count_i2;
1504 169 mohor
        end
1505 181 mohor
        begin: count_i1
1506
          forever
1507
          begin
1508
            @(posedge wb_clk);
1509
            i1 = i1 + 1;
1510
            #Tp;
1511
          end
1512
        end
1513
        begin: count_i2
1514
          forever
1515
          begin
1516
            @(negedge wb_clk);
1517
            i2 = i2 + 1;
1518
            #Tp;
1519
          end
1520
        end
1521
      join
1522
      if((clk_div[7:0] == 0) || (clk_div[7:0] == 1) || (clk_div[7:0] == 2) || (clk_div[7:0] == 3))
1523
      begin
1524
        if((i1 == i2) && (i1 == 2))
1525 169 mohor
        begin
1526
        end
1527 181 mohor
        else
1528
        begin
1529
          fail = fail + 1;
1530 209 tadejm
          test_fail("Clock divider of MII module did'nt divide frequency corectly (it should divide by 2)");
1531 181 mohor
        end
1532 169 mohor
      end
1533
      else
1534
      begin
1535 181 mohor
        if((i1 == i2) && (i1 == {clk_div[7:1], 1'b0}))
1536
        begin
1537
        end
1538
        else
1539
        begin
1540
          fail = fail + 1;
1541
          test_fail("Clock divider of MII module did'nt divide frequency corectly");
1542
        end
1543 169 mohor
      end
1544
    end
1545 181 mohor
    if(fail == 0)
1546
      test_ok;
1547 169 mohor
    else
1548 181 mohor
      fail = 0;
1549
  end
1550
 
1551
 
1552
  ////////////////////////////////////////////////////////////////////
1553
  ////                                                            ////
1554
  ////  Test various readings from 'real' phy registers.          ////
1555
  ////                                                            ////
1556
  ////////////////////////////////////////////////////////////////////
1557
  if (test_num == 1) // Test various readings from 'real' phy registers.
1558
  begin
1559 194 tadej
    // TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS
1560
    test_name   = "TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS";
1561
    `TIME; $display("  TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS");
1562 181 mohor
 
1563
    // set the fastest possible MII
1564
    clk_div = 0;
1565
    mii_set_clk_div(clk_div[7:0]);
1566
    // set address
1567
    reg_addr = 5'h1F;
1568
    phy_addr = 5'h1;
1569
    while(reg_addr >= 5'h4)
1570 169 mohor
    begin
1571 181 mohor
      // read request
1572
      #Tp mii_read_req(phy_addr, reg_addr);
1573
      check_mii_busy; // wait for read to finish
1574
      // read data
1575 274 tadejm
      wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1576 181 mohor
      if (phy_data !== 16'hDEAD)
1577 169 mohor
      begin
1578 181 mohor
        test_fail("Wrong data was read from PHY from 'not used' address space");
1579
        fail = fail + 1;
1580 169 mohor
      end
1581 181 mohor
      if (reg_addr == 5'h4) // go out of for loop
1582
        reg_addr = 5'h3;
1583 169 mohor
      else
1584 181 mohor
        reg_addr = reg_addr - 5'h9;
1585 169 mohor
    end
1586 181 mohor
 
1587
    // set address
1588
    reg_addr = 5'h3;
1589
    // read request
1590
    #Tp mii_read_req(phy_addr, reg_addr);
1591
    check_mii_busy; // wait for read to finish
1592
    // read data
1593 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1594 181 mohor
    if (phy_data !== {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM})
1595
    begin
1596
      test_fail("Wrong data was read from PHY from ID register 2");
1597
      fail = fail + 1;
1598
    end
1599
    if(fail == 0)
1600
      test_ok;
1601
    else
1602
      fail = 0;
1603 169 mohor
  end
1604 116 mohor
 
1605
 
1606 181 mohor
  ////////////////////////////////////////////////////////////////////
1607
  ////                                                            ////
1608
  ////  Test various writings to 'real' phy registers (control    ////
1609
  ////  and non writable registers)                               ////
1610
  ////                                                            ////
1611
  ////////////////////////////////////////////////////////////////////
1612
  if (test_num == 2) // 
1613 169 mohor
  begin
1614 194 tadej
    // TEST 2: VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )
1615
    test_name   = "TEST 2: VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )";
1616
    `TIME; $display("  TEST 2: VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )");
1617 181 mohor
 
1618
    // negate data and try to write into unwritable register
1619
    tmp_data = ~phy_data;
1620
    // write request
1621
    #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1622
    check_mii_busy; // wait for write to finish
1623 169 mohor
    // read request
1624
    #Tp mii_read_req(phy_addr, reg_addr);
1625
    check_mii_busy; // wait for read to finish
1626
    // read data
1627 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1628 181 mohor
    if (tmp_data !== phy_data)
1629
    begin
1630
      test_fail("Data was written into unwritable PHY register - ID register 2");
1631
      fail = fail + 1;
1632
    end
1633
 
1634
    // set address
1635
    reg_addr = 5'h0; // control register
1636
    // read request
1637
    #Tp mii_read_req(phy_addr, reg_addr);
1638
    check_mii_busy; // wait for read to finish
1639
    // read data
1640 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1641 181 mohor
    // write request
1642
    phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
1643
    #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1644
    check_mii_busy; // wait for write to finish
1645
    // read request
1646
    #Tp mii_read_req(phy_addr, reg_addr);
1647
    check_mii_busy; // wait for read to finish
1648
    // read data
1649 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1650 181 mohor
    if (phy_data !== 16'h7DFF)
1651 169 mohor
    begin
1652 181 mohor
      test_fail("Data was not correctly written into OR read from writable PHY register - control register");
1653 169 mohor
      fail = fail + 1;
1654
    end
1655 181 mohor
    // write request
1656
    #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1657
    check_mii_busy; // wait for write to finish
1658
    // read request
1659
    #Tp mii_read_req(phy_addr, reg_addr);
1660
    check_mii_busy; // wait for read to finish
1661
    // read data
1662 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1663 181 mohor
    if (phy_data !== tmp_data)
1664
    begin
1665
      test_fail("Data was not correctly written into OR read from writable PHY register - control register");
1666
      fail = fail + 1;
1667
    end
1668
    if(fail == 0)
1669
      test_ok;
1670 116 mohor
    else
1671 181 mohor
      fail = 0;
1672 169 mohor
  end
1673 116 mohor
 
1674
 
1675 181 mohor
  ////////////////////////////////////////////////////////////////////
1676
  ////                                                            ////
1677
  ////  Test reset phy through mii management module              ////
1678
  ////                                                            ////
1679
  ////////////////////////////////////////////////////////////////////
1680
  if (test_num == 3) // 
1681 169 mohor
  begin
1682 194 tadej
    // TEST 3: RESET PHY THROUGH MII MANAGEMENT MODULE
1683
    test_name   = "TEST 3: RESET PHY THROUGH MII MANAGEMENT MODULE";
1684
    `TIME; $display("  TEST 3: RESET PHY THROUGH MII MANAGEMENT MODULE");
1685 181 mohor
 
1686
    // set address
1687
    reg_addr = 5'h0; // control register
1688
    // write request
1689
    phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
1690
    #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1691
    check_mii_busy; // wait for write to finish
1692
    // read request
1693
    #Tp mii_read_req(phy_addr, reg_addr);
1694
    check_mii_busy; // wait for read to finish
1695
    // read data
1696 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1697 181 mohor
    if (phy_data !== tmp_data)
1698
    begin
1699
      test_fail("Data was not correctly written into OR read from writable PHY register - control register");
1700
      fail = fail + 1;
1701
    end
1702
    // set reset bit - selfclearing bit in PHY
1703
    phy_data = phy_data | 16'h8000;
1704
    // write request
1705
    #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1706
    check_mii_busy; // wait for write to finish
1707
    // read request
1708
    #Tp mii_read_req(phy_addr, reg_addr);
1709
    check_mii_busy; // wait for read to finish
1710
    // read data
1711 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1712 181 mohor
    // check self clearing of reset bit
1713
    if (tmp_data[15] !== 1'b0)
1714
    begin
1715
      test_fail("Reset bit should be self cleared - control register");
1716
      fail = fail + 1;
1717
    end
1718
    // check reset value of control register
1719
    if (tmp_data !== {2'h0, (`LED_CFG1 || `LED_CFG2), `LED_CFG1, 3'h0, `LED_CFG3, 8'h0})
1720
    begin
1721
      test_fail("PHY was not reset correctly AND/OR reset bit not self cleared");
1722
      fail = fail + 1;
1723
    end
1724
    if(fail == 0)
1725
      test_ok;
1726
    else
1727
      fail = 0;
1728 169 mohor
  end
1729
 
1730
 
1731 181 mohor
  ////////////////////////////////////////////////////////////////////
1732
  ////                                                            ////
1733
  ////  Test 'walking one' across phy address (with and without   ////
1734
  ////  preamble)                                                 ////
1735
  ////                                                            ////
1736
  ////////////////////////////////////////////////////////////////////
1737
  if (test_num == 4) // 
1738 169 mohor
  begin
1739 194 tadej
    // TEST 4: 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )
1740
    test_name   = "TEST 4: 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )";
1741
    `TIME; $display("  TEST 4: 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )");
1742 181 mohor
 
1743
    // set PHY to test mode
1744
    #Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
1745
    for (i = 0; i <= 1; i = i + 1)
1746 169 mohor
    begin
1747 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
1748
      #Tp eth_phy.clear_test_regs;
1749
      // MII mode register
1750
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}), 4'hF, 1, wbm_init_waits,
1751
                wbm_subseq_waits);
1752
      // walk one across phy address
1753
      for (phy_addr = 5'h1; phy_addr > 5'h0; phy_addr = phy_addr << 1)
1754 169 mohor
      begin
1755 181 mohor
        reg_addr = $random;
1756
        tmp_data = $random;
1757
        // write request
1758
        #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1759
        check_mii_busy; // wait for write to finish
1760
        // read request
1761
        #Tp mii_read_req(phy_addr, reg_addr);
1762
        check_mii_busy; // wait for read to finish
1763
        // read data
1764 274 tadejm
        wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1765 181 mohor
        #Tp;
1766
        if (phy_data !== tmp_data)
1767
        begin
1768
          if (i)
1769
            test_fail("Data was not correctly written into OR read from test registers (without preamble)");
1770
          else
1771
            test_fail("Data was not correctly written into OR read from test registers (with preamble)");
1772
          fail = fail + 1;
1773
        end
1774
        @(posedge wb_clk);
1775
        #Tp;
1776 169 mohor
      end
1777
    end
1778 181 mohor
    // set PHY to normal mode
1779
    #Tp eth_phy.test_regs(0);
1780
    #Tp eth_phy.preamble_suppresed(0);
1781
    // MII mode register
1782
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1783
    if(fail == 0)
1784
      test_ok;
1785
    else
1786
      fail = 0;
1787 169 mohor
  end
1788
 
1789
 
1790 181 mohor
  ////////////////////////////////////////////////////////////////////
1791
  ////                                                            ////
1792
  ////  Test 'walking one' across phy's register address (with    ////
1793
  ////  and without preamble)                                     ////
1794
  ////                                                            ////
1795
  ////////////////////////////////////////////////////////////////////
1796
  if (test_num == 5) // 
1797 169 mohor
  begin
1798 194 tadej
    // TEST 5: 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )
1799
    test_name   = "TEST 5: 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )";
1800
    `TIME; $display("  TEST 5: 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )");
1801 181 mohor
 
1802
    // set PHY to test mode
1803
    #Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
1804
    for (i = 0; i <= 1; i = i + 1)
1805 169 mohor
    begin
1806 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
1807
      #Tp eth_phy.clear_test_regs;
1808
      // MII mode register
1809
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}), 4'hF, 1, wbm_init_waits,
1810
                wbm_subseq_waits);
1811
      // walk one across reg address
1812
      for (reg_addr = 5'h1; reg_addr > 5'h0; reg_addr = reg_addr << 1)
1813 169 mohor
      begin
1814 181 mohor
        phy_addr = $random;
1815
        tmp_data = $random;
1816
        // write request
1817
        #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1818
        check_mii_busy; // wait for write to finish
1819
        // read request
1820
        #Tp mii_read_req(phy_addr, reg_addr);
1821
        check_mii_busy; // wait for read to finish
1822
        // read data
1823 274 tadejm
        wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1824 181 mohor
        #Tp;
1825
        if (phy_data !== tmp_data)
1826
        begin
1827
          if (i)
1828
            test_fail("Data was not correctly written into OR read from test registers (without preamble)");
1829
          else
1830
            test_fail("Data was not correctly written into OR read from test registers (with preamble)");
1831
          fail = fail + 1;
1832
        end
1833
        @(posedge wb_clk);
1834
        #Tp;
1835 169 mohor
      end
1836
    end
1837 181 mohor
    // set PHY to normal mode
1838
    #Tp eth_phy.test_regs(0);
1839
    #Tp eth_phy.preamble_suppresed(0);
1840
    // MII mode register
1841
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1842
    if(fail == 0)
1843
      test_ok;
1844
    else
1845
      fail = 0;
1846 169 mohor
  end
1847
 
1848
 
1849 181 mohor
  ////////////////////////////////////////////////////////////////////
1850
  ////                                                            ////
1851
  ////  Test 'walking one' across phy's data (with and without    ////
1852
  ////  preamble)                                                 ////
1853
  ////                                                            ////
1854
  ////////////////////////////////////////////////////////////////////
1855
  if (test_num == 6) // 
1856 169 mohor
  begin
1857 194 tadej
    // TEST 6: 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )
1858
    test_name   = "TEST 6: 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )";
1859
    `TIME; $display("  TEST 6: 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )");
1860 181 mohor
 
1861
    // set PHY to test mode
1862
    #Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
1863
    for (i = 0; i <= 1; i = i + 1)
1864 169 mohor
    begin
1865 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
1866
      #Tp eth_phy.clear_test_regs;
1867
      // MII mode register
1868
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}), 4'hF, 1, wbm_init_waits,
1869
                wbm_subseq_waits);
1870
      // walk one across data
1871
      for (tmp_data = 16'h1; tmp_data > 16'h0; tmp_data = tmp_data << 1)
1872 169 mohor
      begin
1873 181 mohor
        phy_addr = $random;
1874
        reg_addr = $random;
1875
        // write request
1876
        #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1877
        check_mii_busy; // wait for write to finish
1878
        // read request
1879
        #Tp mii_read_req(phy_addr, reg_addr);
1880
        check_mii_busy; // wait for read to finish
1881
        // read data
1882 274 tadejm
        wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1883 181 mohor
        #Tp;
1884
        if (phy_data !== tmp_data)
1885
        begin
1886
          if (i)
1887
            test_fail("Data was not correctly written into OR read from test registers (without preamble)");
1888
          else
1889
            test_fail("Data was not correctly written into OR read from test registers (with preamble)");
1890
          fail = fail + 1;
1891
        end
1892
        @(posedge wb_clk);
1893
        #Tp;
1894 169 mohor
      end
1895
    end
1896 181 mohor
    // set PHY to normal mode
1897
    #Tp eth_phy.test_regs(0);
1898
    #Tp eth_phy.preamble_suppresed(0);
1899
    // MII mode register
1900
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1901
    if(fail == 0)
1902
      test_ok;
1903
    else
1904
      fail = 0;
1905 169 mohor
  end
1906
 
1907
 
1908 181 mohor
  ////////////////////////////////////////////////////////////////////
1909
  ////                                                            ////
1910
  ////  Test reading from phy with wrong phy address (host        ////
1911
  ////  reading high 'z' data)                                    ////
1912
  ////                                                            ////
1913
  ////////////////////////////////////////////////////////////////////
1914
  if (test_num == 7) // 
1915 169 mohor
  begin
1916 194 tadej
    // TEST 7: READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )
1917
    test_name   = "TEST 7: READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )";
1918
    `TIME; $display("  TEST 7: READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )");
1919 181 mohor
 
1920
    phy_addr = 5'h2; // wrong PHY address
1921
    // read request
1922
    #Tp mii_read_req(phy_addr, reg_addr);
1923
    check_mii_busy; // wait for read to finish
1924
    // read data
1925
    $display("  => Two errors will be displayed from WB Bus Monitor, because correct HIGH Z data was read");
1926 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1927 181 mohor
    if (tmp_data !== 16'hzzzz)
1928
    begin
1929
      test_fail("Data was read from PHY register with wrong PHY address - control register");
1930
      fail = fail + 1;
1931
    end
1932
    if(fail == 0)
1933
      test_ok;
1934
    else
1935
      fail = 0;
1936 169 mohor
  end
1937
 
1938
 
1939 181 mohor
  ////////////////////////////////////////////////////////////////////
1940
  ////                                                            ////
1941
  ////  Test writing to phy with wrong phy address and reading    ////
1942
  ////  from correct one                                          ////
1943
  ////                                                            ////
1944
  ////////////////////////////////////////////////////////////////////
1945
  if (test_num == 8) // 
1946 169 mohor
  begin
1947 194 tadej
    // TEST 8: WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE
1948
    test_name   = "TEST 8: WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE";
1949
    `TIME; $display("  TEST 8: WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE");
1950 181 mohor
 
1951
    // set address
1952
    reg_addr = 5'h0; // control register
1953
    phy_addr = 5'h2; // wrong PHY address
1954
    // write request
1955
    phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
1956
    #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1957
    check_mii_busy; // wait for write to finish
1958
 
1959
    phy_addr = 5'h1; // correct PHY address
1960
    // read request
1961
    #Tp mii_read_req(phy_addr, reg_addr);
1962
    check_mii_busy; // wait for read to finish
1963
    // read data
1964 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1965 181 mohor
    if (phy_data === tmp_data)
1966
    begin
1967
      test_fail("Data was written into PHY register with wrong PHY address - control register");
1968
      fail = fail + 1;
1969
    end
1970
    if(fail == 0)
1971
      test_ok;
1972
    else
1973
      fail = 0;
1974 169 mohor
  end
1975
 
1976
 
1977 181 mohor
  ////////////////////////////////////////////////////////////////////
1978
  ////                                                            ////
1979
  ////  Test sliding stop scan command immediately after read     ////
1980
  ////  request (with and without preamble)                       ////
1981
  ////                                                            ////
1982
  ////////////////////////////////////////////////////////////////////
1983
  if (test_num == 9) // 
1984 169 mohor
  begin
1985 194 tadej
    // TEST 9: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )
1986
    test_name = "TEST 9: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )";
1987 181 mohor
    `TIME;
1988 194 tadej
    $display("  TEST 9: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )");
1989 181 mohor
 
1990
    for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
1991 169 mohor
    begin
1992 181 mohor
      #Tp eth_phy.preamble_suppresed(i2);
1993
      // MII mode register
1994
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
1995
               wbm_subseq_waits);
1996
      i = 0;
1997
      cnt = 0;
1998
      while (i < 80) // delay for sliding of writing a STOP SCAN command
1999 169 mohor
      begin
2000 181 mohor
        for (i3 = 0; i3 <= 1; i3 = i3 + 1) // choose read or write after read will be finished
2001
        begin
2002
          // set address
2003
          reg_addr = 5'h0; // control register
2004
          phy_addr = 5'h1; // correct PHY address
2005
          cnt = 0;
2006
          // read request
2007
          #Tp mii_read_req(phy_addr, reg_addr);
2008
          fork
2009
            begin
2010
              repeat(i) @(posedge Mdc_O);
2011
              // write command 0x0 into MII command register
2012
              // MII command written while read in progress
2013
              wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2014
              @(posedge wb_clk);
2015
              #Tp check_mii_busy; // wait for read to finish
2016
            end
2017
            begin
2018
              // wait for serial bus to become active
2019
              wait(Mdio_IO !== 1'bz);
2020
              // count transfer length
2021
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
2022
              begin
2023
                @(posedge Mdc_O);
2024
                #Tp cnt = cnt + 1;
2025
              end
2026
            end
2027
          join
2028
          // check transfer length
2029
          if (i2) // without preamble
2030 169 mohor
          begin
2031 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
2032
            begin
2033
              test_fail("Read request did not proceed correctly, while SCAN STOP command was written");
2034
              fail = fail + 1;
2035
            end
2036 169 mohor
          end
2037 181 mohor
          else // with preamble
2038 169 mohor
          begin
2039 181 mohor
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
2040
            begin
2041
              test_fail("Read request did not proceed correctly, while SCAN STOP command was written");
2042
              fail = fail + 1;
2043
            end
2044
          end
2045
          // check the BUSY signal to see if the bus is still IDLE
2046
          for (i1 = 0; i1 < 8; i1 = i1 + 1)
2047
            check_mii_busy; // wait for bus to become idle
2048
 
2049
          // try normal write or read after read was finished
2050
          #Tp phy_data = {8'h7D, (i[7:0] + 1)};
2051
          #Tp cnt = 0;
2052
          if (i3 == 0) // write after read
2053
          begin
2054
            // write request
2055
            #Tp mii_write_req(phy_addr, reg_addr, phy_data);
2056 169 mohor
            // wait for serial bus to become active
2057
            wait(Mdio_IO !== 1'bz);
2058
            // count transfer length
2059 181 mohor
            while(Mdio_IO !== 1'bz)
2060 169 mohor
            begin
2061
              @(posedge Mdc_O);
2062
              #Tp cnt = cnt + 1;
2063
            end
2064 181 mohor
            @(posedge Mdc_O);
2065
            // read request
2066
            #Tp mii_read_req(phy_addr, reg_addr);
2067
            check_mii_busy; // wait for read to finish
2068
            // read and check data
2069 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2070 181 mohor
            if (phy_data !== tmp_data)
2071
            begin
2072
              test_fail("Data was not correctly written into OR read from PHY register - control register");
2073
              fail = fail + 1;
2074
            end
2075 169 mohor
          end
2076 181 mohor
          else // read after read
2077 169 mohor
          begin
2078 181 mohor
            // read request
2079
            #Tp mii_read_req(phy_addr, reg_addr);
2080
            // wait for serial bus to become active
2081
            wait(Mdio_IO !== 1'bz);
2082
            // count transfer length
2083
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
2084
            begin
2085
              @(posedge Mdc_O);
2086
              #Tp cnt = cnt + 1;
2087
            end
2088 169 mohor
            @(posedge Mdc_O);
2089 181 mohor
            check_mii_busy; // wait for read to finish
2090
            // read and check data
2091 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2092 181 mohor
            if (phy_data !== tmp_data)
2093
            begin
2094
              test_fail("Data was not correctly written into OR read from PHY register - control register");
2095
              fail = fail + 1;
2096
            end
2097 169 mohor
          end
2098 181 mohor
          // check if transfer was a proper length
2099
          if (i2) // without preamble
2100 169 mohor
          begin
2101 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
2102
            begin
2103
              test_fail("New request did not proceed correctly, after read request");
2104
              fail = fail + 1;
2105
            end
2106 169 mohor
          end
2107 181 mohor
          else // with preamble
2108 169 mohor
          begin
2109 181 mohor
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
2110
            begin
2111
              test_fail("New request did not proceed correctly, after read request");
2112
              fail = fail + 1;
2113
            end
2114 169 mohor
          end
2115
        end
2116 181 mohor
        #Tp;
2117
        // set delay of writing the command
2118 169 mohor
        if (i2) // without preamble
2119
        begin
2120 181 mohor
          case(i)
2121
            0, 1:               i = i + 1;
2122
            18, 19, 20, 21, 22,
2123
            23, 24, 25, 26, 27,
2124
            28, 29, 30, 31, 32,
2125
            33, 34, 35:         i = i + 1;
2126
            36:                 i = 80;
2127
            default:            i = 18;
2128
          endcase
2129 169 mohor
        end
2130
        else // with preamble
2131
        begin
2132 181 mohor
          case(i)
2133
            0, 1:               i = i + 1;
2134
            50, 51, 52, 53, 54,
2135
            55, 56, 57, 58, 59,
2136
            60, 61, 62, 63, 64,
2137
            65, 66, 67:         i = i + 1;
2138
            68:                 i = 80;
2139
            default:            i = 50;
2140
          endcase
2141 169 mohor
        end
2142 181 mohor
        @(posedge wb_clk);
2143 169 mohor
      end
2144
    end
2145 181 mohor
    // set PHY to normal mode
2146
    #Tp eth_phy.preamble_suppresed(0);
2147
    // MII mode register
2148
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2149
    if(fail == 0)
2150
      test_ok;
2151
    else
2152
      fail = 0;
2153 169 mohor
  end
2154
 
2155
 
2156 181 mohor
  ////////////////////////////////////////////////////////////////////
2157
  ////                                                            ////
2158
  ////  Test sliding stop scan command immediately after write    ////
2159
  ////  request (with and without preamble)                       ////
2160
  ////                                                            ////
2161
  ////////////////////////////////////////////////////////////////////
2162
  if (test_num == 10) // 
2163 169 mohor
  begin
2164 194 tadej
    // TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )
2165
    test_name = "TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )";
2166 181 mohor
    `TIME;
2167 194 tadej
    $display("  TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )");
2168 181 mohor
 
2169
    for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
2170 169 mohor
    begin
2171 181 mohor
      #Tp eth_phy.preamble_suppresed(i2);
2172
      // MII mode register
2173
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
2174
                wbm_subseq_waits);
2175
      i = 0;
2176
      cnt = 0;
2177
      while (i < 80) // delay for sliding of writing a STOP SCAN command
2178 169 mohor
      begin
2179 181 mohor
        for (i3 = 0; i3 <= 1; i3 = i3 + 1) // choose read or write after write will be finished
2180
        begin
2181
          // set address
2182
          reg_addr = 5'h0; // control register
2183
          phy_addr = 5'h1; // correct PHY address
2184
          cnt = 0;
2185
          // write request
2186
          phy_data = {8'h75, (i[7:0] + 1)};
2187
          #Tp mii_write_req(phy_addr, reg_addr, phy_data);
2188
          fork
2189
            begin
2190
              repeat(i) @(posedge Mdc_O);
2191
              // write command 0x0 into MII command register
2192
              // MII command written while read in progress
2193
              wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2194
              @(posedge wb_clk);
2195
              #Tp check_mii_busy; // wait for write to finish
2196
            end
2197
            begin
2198
              // wait for serial bus to become active
2199
              wait(Mdio_IO !== 1'bz);
2200
              // count transfer length
2201
              while(Mdio_IO !== 1'bz)
2202
              begin
2203
                @(posedge Mdc_O);
2204
                #Tp cnt = cnt + 1;
2205
              end
2206
            end
2207
          join
2208
          // check transfer length
2209
          if (i2) // without preamble
2210 169 mohor
          begin
2211 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
2212
            begin
2213
              test_fail("Write request did not proceed correctly, while SCAN STOP command was written");
2214
              fail = fail + 1;
2215
            end
2216 169 mohor
          end
2217 181 mohor
          else // with preamble
2218 169 mohor
          begin
2219 181 mohor
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
2220
            begin
2221
              test_fail("Write request did not proceed correctly, while SCAN STOP command was written");
2222
              fail = fail + 1;
2223
            end
2224
          end
2225
          // check the BUSY signal to see if the bus is still IDLE
2226
          for (i1 = 0; i1 < 8; i1 = i1 + 1)
2227
            check_mii_busy; // wait for bus to become idle
2228
 
2229
          // try normal write or read after write was finished
2230
          #Tp cnt = 0;
2231
          if (i3 == 0) // write after write
2232
          begin
2233
            phy_data = {8'h7A, (i[7:0] + 1)};
2234
            // write request
2235
            #Tp mii_write_req(phy_addr, reg_addr, phy_data);
2236 169 mohor
            // wait for serial bus to become active
2237
            wait(Mdio_IO !== 1'bz);
2238
            // count transfer length
2239
            while(Mdio_IO !== 1'bz)
2240
            begin
2241
              @(posedge Mdc_O);
2242
              #Tp cnt = cnt + 1;
2243
            end
2244 181 mohor
            @(posedge Mdc_O);
2245
            // read request
2246
            #Tp mii_read_req(phy_addr, reg_addr);
2247
            check_mii_busy; // wait for read to finish
2248
            // read and check data
2249 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, tmp_data , 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2250 181 mohor
            if (phy_data !== tmp_data)
2251
            begin
2252
              test_fail("Data was not correctly written into OR read from PHY register - control register");
2253
              fail = fail + 1;
2254
            end
2255 169 mohor
          end
2256 181 mohor
          else // read after write
2257 169 mohor
          begin
2258 181 mohor
            // read request
2259
            #Tp mii_read_req(phy_addr, reg_addr);
2260
            // wait for serial bus to become active
2261
            wait(Mdio_IO !== 1'bz);
2262
            // count transfer length
2263
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
2264
            begin
2265
              @(posedge Mdc_O);
2266
              #Tp cnt = cnt + 1;
2267
            end
2268 169 mohor
            @(posedge Mdc_O);
2269 181 mohor
            check_mii_busy; // wait for read to finish
2270
            // read and check data
2271 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, tmp_data , 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2272 181 mohor
            if (phy_data !== tmp_data)
2273
            begin
2274
              test_fail("Data was not correctly written into OR read from PHY register - control register");
2275
              fail = fail + 1;
2276
            end
2277 169 mohor
          end
2278 181 mohor
          // check if transfer was a proper length
2279
          if (i2) // without preamble
2280 169 mohor
          begin
2281 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
2282
            begin
2283
              test_fail("New request did not proceed correctly, after write request");
2284
              fail = fail + 1;
2285
            end
2286 169 mohor
          end
2287 181 mohor
          else // with preamble
2288 169 mohor
          begin
2289 181 mohor
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
2290
            begin
2291
              test_fail("New request did not proceed correctly, after write request");
2292
              fail = fail + 1;
2293
            end
2294 169 mohor
          end
2295
        end
2296 181 mohor
        #Tp;
2297
        // set delay of writing the command
2298 169 mohor
        if (i2) // without preamble
2299
        begin
2300 181 mohor
          case(i)
2301
            0, 1:               i = i + 1;
2302
            18, 19, 20, 21, 22,
2303
            23, 24, 25, 26, 27,
2304
            28, 29, 30, 31, 32,
2305
            33, 34, 35:         i = i + 1;
2306
            36:                 i = 80;
2307
            default:            i = 18;
2308
          endcase
2309 169 mohor
        end
2310
        else // with preamble
2311
        begin
2312 181 mohor
          case(i)
2313
            0, 1:               i = i + 1;
2314
            50, 51, 52, 53, 54,
2315
            55, 56, 57, 58, 59,
2316
            60, 61, 62, 63, 64,
2317
            65, 66, 67:         i = i + 1;
2318
            68:                 i = 80;
2319
            default:            i = 50;
2320
          endcase
2321 169 mohor
        end
2322 181 mohor
        @(posedge wb_clk);
2323 169 mohor
      end
2324
    end
2325 181 mohor
    // set PHY to normal mode
2326
    #Tp eth_phy.preamble_suppresed(0);
2327
    // MII mode register
2328
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2329
    if(fail == 0)
2330
      test_ok;
2331
    else
2332
      fail = 0;
2333 169 mohor
  end
2334
 
2335
 
2336 181 mohor
  ////////////////////////////////////////////////////////////////////
2337
  ////                                                            ////
2338
  ////  Test busy and nvalid status durations during write (with  ////
2339
  ////  and without preamble)                                     ////
2340
  ////                                                            ////
2341
  ////////////////////////////////////////////////////////////////////
2342
  if (test_num == 11) // 
2343 169 mohor
  begin
2344 194 tadej
    // TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )
2345
    test_name   = "TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )";
2346
    `TIME; $display("  TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )");
2347 181 mohor
 
2348
    reset_mii; // reset MII
2349
    // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2350
    #Tp eth_phy.link_up_down(1);
2351
    // set the MII
2352
    clk_div = 64;
2353
    mii_set_clk_div(clk_div[7:0]);
2354
    // set address
2355
    reg_addr = 5'h1; // status register
2356
    phy_addr = 5'h1; // correct PHY address
2357
 
2358
    for (i = 0; i <= 1; i = i + 1)
2359 169 mohor
    begin
2360 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
2361
      // MII mode register
2362
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2363
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2364
      @(posedge Mdc_O);
2365
      // write request
2366
      #Tp mii_write_req(phy_addr, reg_addr, 16'h5A5A);
2367
      // read data from MII status register - Busy and Nvalid bits
2368 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2369 181 mohor
 
2370
      // check MII IO signal and Busy and Nvalid bits
2371
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2372 169 mohor
      begin
2373 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");
2374
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2375
        begin
2376
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2377
          fail = fail + 1;
2378
        end
2379
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2380
        begin
2381
          test_fail("Nvalid signal was set during write");
2382
          fail = fail + 1;
2383
        end
2384 169 mohor
      end
2385 181 mohor
      else // Busy bit should already be set to '1', due to reads from MII status register
2386 169 mohor
      begin
2387 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2388
        begin
2389
          test_fail("Busy signal should be set after write, due to reads from MII status register");
2390
          fail = fail + 1;
2391
        end
2392
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2393
        begin
2394
          test_fail("Nvalid signal was set during write");
2395
          fail = fail + 1;
2396
        end
2397 169 mohor
      end
2398 181 mohor
 
2399
      // wait for serial bus to become active
2400
      wait(Mdio_IO !== 1'bz);
2401
      // count transfer bits
2402
      if (i)
2403 169 mohor
      begin
2404 181 mohor
        repeat(32) @(posedge Mdc_O);
2405 169 mohor
      end
2406 181 mohor
      else
2407 169 mohor
      begin
2408 181 mohor
        repeat(64) @(posedge Mdc_O);
2409 169 mohor
      end
2410 181 mohor
      // read data from MII status register - Busy and Nvalid bits
2411 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2412 181 mohor
 
2413
      // check MII IO signal and Busy and Nvalid bits
2414
      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2415 169 mohor
      begin
2416 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2417
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2418
        begin
2419
          test_fail("Busy signal should be set while MII IO signal is not active anymore");
2420
          fail = fail + 1;
2421
        end
2422
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2423
        begin
2424
          test_fail("Nvalid signal was set during write");
2425
          fail = fail + 1;
2426
        end
2427 169 mohor
      end
2428 181 mohor
      else // Busy bit should still be set to '1'
2429 169 mohor
      begin
2430 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2431
        begin
2432
          test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2433
          fail = fail + 1;
2434
        end
2435
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2436
        begin
2437
          test_fail("Nvalid signal was set during write");
2438
          fail = fail + 1;
2439
        end
2440 169 mohor
      end
2441 181 mohor
 
2442
      // wait for next negative clock edge
2443
      @(negedge Mdc_O);
2444 169 mohor
      // read data from MII status register - Busy and Nvalid bits
2445 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2446 181 mohor
 
2447 169 mohor
      // check MII IO signal and Busy and Nvalid bits
2448
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2449
      begin
2450
        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2451
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2452
        begin
2453
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2454
          fail = fail + 1;
2455
        end
2456
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2457
        begin
2458
          test_fail("Nvalid signal was set during write");
2459
          fail = fail + 1;
2460
        end
2461
      end
2462 181 mohor
      else // Busy bit should still be set to '1'
2463 169 mohor
      begin
2464
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2465
        begin
2466 181 mohor
          test_fail("Busy signal should be set after MII IO signal become HIGH Z");
2467
          fail = fail + 1;
2468 169 mohor
        end
2469 181 mohor
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2470 169 mohor
        begin
2471 181 mohor
          test_fail("Nvalid signal was set during write");
2472
          fail = fail + 1;
2473
        end
2474
      end
2475
 
2476
      // wait for Busy to become inactive
2477
      i1 = 0;
2478
      while (i1 <= 2)
2479
      begin
2480
        // wait for next positive clock edge
2481
        @(posedge Mdc_O);
2482
        // read data from MII status register - Busy and Nvalid bits
2483 274 tadejm
        wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2484 181 mohor
 
2485
        // check MII IO signal and Busy and Nvalid bits
2486
        if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2487
        begin
2488
          test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2489
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2490 169 mohor
          begin
2491 181 mohor
            test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2492 169 mohor
            fail = fail + 1;
2493
          end
2494 181 mohor
          if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2495
          begin
2496
            test_fail("Nvalid signal was set during write");
2497
            fail = fail + 1;
2498
          end
2499 169 mohor
        end
2500 181 mohor
        else // wait for Busy bit to be set to '0'
2501 169 mohor
        begin
2502 181 mohor
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2503
          begin
2504
            i1 = 3; // end of Busy checking
2505
          end
2506
          else
2507
          begin
2508
            if (i1 == 2)
2509
            begin
2510
              test_fail("Busy signal should be cleared after 2 periods after MII IO signal become HIGH Z");
2511
              fail = fail + 1;
2512
            end
2513
            #Tp i1 = i1 + 1;
2514
          end
2515
          if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2516
          begin
2517
            test_fail("Nvalid signal was set after write");
2518
            fail = fail + 1;
2519
          end
2520 169 mohor
        end
2521
      end
2522
    end
2523 181 mohor
    // set PHY to normal mode
2524
    #Tp eth_phy.preamble_suppresed(0);
2525
    // MII mode register
2526
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2527
    if(fail == 0)
2528
      test_ok;
2529
    else
2530
      fail = 0;
2531 116 mohor
  end
2532
 
2533
 
2534 181 mohor
  ////////////////////////////////////////////////////////////////////
2535
  ////                                                            ////
2536
  ////  Test busy and nvalid status durations during write (with  ////
2537
  ////  and without preamble)                                     ////
2538
  ////                                                            ////
2539
  ////////////////////////////////////////////////////////////////////
2540
  if (test_num == 12) // 
2541 169 mohor
  begin
2542 194 tadej
    // TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )
2543
    test_name   = "TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )";
2544
    `TIME; $display("  TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )");
2545 181 mohor
 
2546
    reset_mii; // reset MII
2547
    // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2548
    #Tp eth_phy.link_up_down(1);
2549
    // set the MII
2550
    clk_div = 64;
2551
    mii_set_clk_div(clk_div[7:0]);
2552
    // set address
2553
    reg_addr = 5'h1; // status register
2554
    phy_addr = 5'h1; // correct PHY address
2555
 
2556
    for (i = 0; i <= 1; i = i + 1)
2557 169 mohor
    begin
2558 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
2559
      // MII mode register
2560
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2561
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2562 169 mohor
      @(posedge Mdc_O);
2563 181 mohor
      // read request
2564
      #Tp mii_read_req(phy_addr, reg_addr);
2565 169 mohor
      // read data from MII status register - Busy and Nvalid bits
2566 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2567 181 mohor
 
2568 169 mohor
      // check MII IO signal and Busy and Nvalid bits
2569
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2570
      begin
2571 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");
2572 169 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2573
        begin
2574 181 mohor
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2575 169 mohor
          fail = fail + 1;
2576
        end
2577
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2578
        begin
2579
          test_fail("Nvalid signal was set during read");
2580
          fail = fail + 1;
2581
        end
2582
      end
2583 181 mohor
      else // Busy bit should already be set to '1', due to reads from MII status register
2584 169 mohor
      begin
2585
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2586
        begin
2587 181 mohor
          test_fail("Busy signal should be set after read, due to reads from MII status register");
2588
          fail = fail + 1;
2589 169 mohor
        end
2590
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2591
        begin
2592 181 mohor
          test_fail("Nvalid signal was set during read");
2593 169 mohor
          fail = fail + 1;
2594
        end
2595
      end
2596 181 mohor
 
2597
      // wait for serial bus to become active
2598
      wait(Mdio_IO !== 1'bz);
2599
      // count transfer bits
2600
      if (i)
2601 169 mohor
      begin
2602 181 mohor
        repeat(31) @(posedge Mdc_O);
2603 169 mohor
      end
2604 181 mohor
      else
2605 169 mohor
      begin
2606 181 mohor
        repeat(63) @(posedge Mdc_O);
2607 169 mohor
      end
2608 181 mohor
      // wait for next negative clock edge
2609
      @(negedge Mdc_O);
2610
      // read data from MII status register - Busy and Nvalid bits
2611 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2612 181 mohor
 
2613
      // check MII IO signal and Busy and Nvalid bits
2614
      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2615 169 mohor
      begin
2616 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2617
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2618
        begin
2619
          test_fail("Busy signal should be set while MII IO signal is not active anymore");
2620
          fail = fail + 1;
2621
        end
2622
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2623
        begin
2624
          test_fail("Nvalid signal was set during read");
2625
          fail = fail + 1;
2626
        end
2627 169 mohor
      end
2628 181 mohor
      else // Busy bit should still be set to '1'
2629 169 mohor
      begin
2630 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2631
        begin
2632
          test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2633
          fail = fail + 1;
2634
        end
2635
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2636
        begin
2637
          test_fail("Nvalid signal was set during read");
2638
          fail = fail + 1;
2639
        end
2640 169 mohor
      end
2641 181 mohor
 
2642 169 mohor
      // wait for next positive clock edge
2643
      @(posedge Mdc_O);
2644
      // read data from MII status register - Busy and Nvalid bits
2645 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2646 181 mohor
 
2647 169 mohor
      // check MII IO signal and Busy and Nvalid bits
2648
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2649
      begin
2650
        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2651 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2652 169 mohor
        begin
2653 181 mohor
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2654
          fail = fail + 1;
2655
        end
2656
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2657
        begin
2658
          test_fail("Nvalid signal was set during read");
2659
          fail = fail + 1;
2660
        end
2661
      end
2662
      else // Busy bit should still be set to '1'
2663
      begin
2664
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2665
        begin
2666
          test_fail("Busy signal should be set after MII IO signal become HIGH Z");
2667
          fail = fail + 1;
2668
        end
2669
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2670
        begin
2671
          test_fail("Nvalid signal was set during read");
2672
          fail = fail + 1;
2673
        end
2674
      end
2675
 
2676
      // wait for Busy to become inactive
2677
      i1 = 0;
2678
      while (i1 <= 2)
2679
      begin
2680
        // wait for next positive clock edge
2681
        @(posedge Mdc_O);
2682
        // read data from MII status register - Busy and Nvalid bits
2683 274 tadejm
        wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2684 181 mohor
 
2685
        // check MII IO signal and Busy and Nvalid bits
2686
        if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2687
        begin
2688
          test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2689 169 mohor
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2690
          begin
2691
            test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2692
            fail = fail + 1;
2693
          end
2694 181 mohor
          if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2695 169 mohor
          begin
2696 181 mohor
            test_fail("Nvalid signal was set during read");
2697 169 mohor
            fail = fail + 1;
2698
          end
2699
        end
2700 181 mohor
        else // wait for Busy bit to be set to '0'
2701 169 mohor
        begin
2702
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2703
          begin
2704
            i1 = 3; // end of Busy checking
2705
          end
2706
          else
2707
          begin
2708
            if (i1 == 2)
2709
            begin
2710
              test_fail("Busy signal should be cleared after 2 periods after MII IO signal become HIGH Z");
2711
              fail = fail + 1;
2712
            end
2713
            #Tp i1 = i1 + 1;
2714
          end
2715 181 mohor
          if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2716 169 mohor
          begin
2717 181 mohor
            test_fail("Nvalid signal was set after read");
2718 169 mohor
            fail = fail + 1;
2719
          end
2720
        end
2721
      end
2722
    end
2723 181 mohor
    // set PHY to normal mode
2724
    #Tp eth_phy.preamble_suppresed(0);
2725
    // MII mode register
2726
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2727
    if(fail == 0)
2728
      test_ok;
2729
    else
2730
      fail = 0;
2731 169 mohor
  end
2732
 
2733
 
2734 181 mohor
  ////////////////////////////////////////////////////////////////////
2735
  ////                                                            ////
2736
  ////  Test busy and nvalid status durations during scan (with   ////
2737
  ////  and without preamble)                                     ////
2738
  ////                                                            ////
2739
  ////////////////////////////////////////////////////////////////////
2740
  if (test_num == 13) // 
2741 169 mohor
  begin
2742 194 tadej
    // TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )
2743
    test_name   = "TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )";
2744
    `TIME; $display("  TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )");
2745 181 mohor
 
2746
    reset_mii; // reset MII
2747
    // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2748
    #Tp eth_phy.link_up_down(1);
2749
    // set the MII
2750
    clk_div = 64;
2751
    mii_set_clk_div(clk_div[7:0]);
2752
    // set address
2753
    reg_addr = 5'h1; // status register
2754
    phy_addr = 5'h1; // correct PHY address
2755
 
2756
    for (i = 0; i <= 1; i = i + 1)
2757 169 mohor
    begin
2758 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
2759
      // MII mode register
2760
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2761
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2762
      @(posedge Mdc_O);
2763
      // scan request
2764
      #Tp mii_scan_req(phy_addr, reg_addr);
2765
      // read data from MII status register - Busy and Nvalid bits
2766 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2767 181 mohor
 
2768
      // check MII IO signal and Busy and Nvalid bits
2769
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2770 169 mohor
      begin
2771 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");
2772
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2773
        begin
2774
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2775
          fail = fail + 1;
2776
        end
2777
        if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2778
        begin
2779
          test_fail("Nvalid signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2780
          fail = fail + 1;
2781
        end
2782 169 mohor
      end
2783 181 mohor
      else // Busy bit should already be set to '1', due to reads from MII status register
2784 169 mohor
      begin
2785 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2786
        begin
2787
          test_fail("Busy signal should be set after scan, due to reads from MII status register");
2788
          fail = fail + 1;
2789
        end
2790
        if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2791
        begin
2792
          test_fail("Nvalid signal should be set after scan, due to reads from MII status register");
2793
          fail = fail + 1;
2794
        end
2795 169 mohor
      end
2796 181 mohor
 
2797
      // wait for serial bus to become active
2798 169 mohor
      wait(Mdio_IO !== 1'bz);
2799 181 mohor
      // count transfer bits
2800
      if (i)
2801 169 mohor
      begin
2802 181 mohor
        repeat(21) @(posedge Mdc_O);
2803 169 mohor
      end
2804 181 mohor
      else
2805 169 mohor
      begin
2806 181 mohor
        repeat(53) @(posedge Mdc_O);
2807 169 mohor
      end
2808 181 mohor
      // stop scan
2809
      #Tp mii_scan_finish; // finish scan operation
2810
 
2811
      // wait for next positive clock edge
2812
      repeat(10) @(posedge Mdc_O);
2813
      // read data from MII status register - Busy and Nvalid bits
2814 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2815 181 mohor
 
2816
      // check MII IO signal and Busy and Nvalid bits
2817
      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2818 169 mohor
      begin
2819 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2820
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2821 169 mohor
        begin
2822 181 mohor
          test_fail("Busy signal should be set while MII IO signal is not active anymore");
2823 169 mohor
          fail = fail + 1;
2824
        end
2825 181 mohor
        // Nvalid signal can be cleared here - it is still Testbench error
2826 169 mohor
      end
2827 181 mohor
      else // Busy bit should still be set to '1', Nvalid bit should still be set to '1'
2828 169 mohor
      begin
2829 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2830 169 mohor
        begin
2831 181 mohor
          test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2832 169 mohor
          fail = fail + 1;
2833
        end
2834 181 mohor
        if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2835 169 mohor
        begin
2836 181 mohor
          test_fail("Nvalid signal should be set while MII IO signal not HIGH Z");
2837 169 mohor
          fail = fail + 1;
2838
        end
2839 181 mohor
      end
2840
 
2841
      // wait for next negative clock edge
2842
      @(negedge Mdc_O);
2843
      // read data from MII status register - Busy and Nvalid bits
2844 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2845 181 mohor
 
2846
      // check MII IO signal and Busy and Nvalid bits
2847
      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2848
      begin
2849
        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2850
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2851 169 mohor
        begin
2852 181 mohor
          test_fail("Busy signal should be set while MII IO signal is not active anymore");
2853
          fail = fail + 1;
2854 169 mohor
        end
2855 181 mohor
        // Nvalid signal can be cleared here - it is still Testbench error
2856 169 mohor
      end
2857 181 mohor
      else // Busy bit should still be set to '1', Nvalid bit should still be set to '1'
2858 169 mohor
      begin
2859 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2860 169 mohor
        begin
2861 181 mohor
          test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2862
          fail = fail + 1;
2863 169 mohor
        end
2864 181 mohor
        if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2865 169 mohor
        begin
2866 181 mohor
          test_fail("Nvalid signal should be set while MII IO signal not HIGH Z");
2867
          fail = fail + 1;
2868 169 mohor
        end
2869
      end
2870 181 mohor
 
2871
      // wait for next negative clock edge
2872
      @(posedge Mdc_O);
2873
      // read data from MII status register - Busy and Nvalid bits
2874 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2875 181 mohor
 
2876
      // check MII IO signal and Busy and Nvalid bits
2877
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2878 169 mohor
      begin
2879 181 mohor
        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2880
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2881 169 mohor
        begin
2882 181 mohor
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2883 169 mohor
          fail = fail + 1;
2884
        end
2885 181 mohor
        if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2886 169 mohor
        begin
2887 181 mohor
          test_fail("Nvalid signal was not set while MII IO signal is not HIGH Z");
2888 169 mohor
          fail = fail + 1;
2889
        end
2890
      end
2891 181 mohor
      else // Busy bit should still be set to '1', Nvalid bit can be set to '0'
2892 169 mohor
      begin
2893 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2894 169 mohor
        begin
2895 181 mohor
          test_fail("Busy signal should be set after MII IO signal become HIGH Z");
2896
          fail = fail + 1;
2897 169 mohor
        end
2898 181 mohor
        if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2899 169 mohor
        begin
2900 181 mohor
          i2 = 1; // check finished
2901 169 mohor
        end
2902 181 mohor
        else
2903 169 mohor
        begin
2904 181 mohor
          i2 = 0; // check must continue
2905 169 mohor
        end
2906
      end
2907 181 mohor
 
2908
      // wait for Busy to become inactive
2909
      i1 = 0;
2910
      while ((i1 <= 2) || (i2 == 0))
2911
      begin
2912
        // wait for next positive clock edge
2913
        @(posedge Mdc_O);
2914
        // read data from MII status register - Busy and Nvalid bits
2915 274 tadejm
        wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2916 181 mohor
 
2917
        // check MII IO signal and Busy and Nvalid bits
2918
        if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2919 169 mohor
        begin
2920 181 mohor
          test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2921
          if (i1 <= 2)
2922 169 mohor
          begin
2923 181 mohor
            if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2924 169 mohor
            begin
2925 181 mohor
              test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2926 169 mohor
              fail = fail + 1;
2927
            end
2928
          end
2929 181 mohor
          if (i2 == 0)
2930 169 mohor
          begin
2931 181 mohor
            if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2932 169 mohor
            begin
2933 181 mohor
              test_fail("Nvalid signal was not set while MII IO signal is not HIGH Z");
2934 169 mohor
              fail = fail + 1;
2935
            end
2936
          end
2937
        end
2938 181 mohor
        else // wait for Busy bit to be set to '0'
2939 169 mohor
        begin
2940 181 mohor
          if (i1 <= 2)
2941 169 mohor
          begin
2942 181 mohor
            if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2943 169 mohor
            begin
2944 181 mohor
              i1 = 3; // end of Busy checking
2945 169 mohor
            end
2946 181 mohor
            else
2947 169 mohor
            begin
2948 181 mohor
              if (i1 == 2)
2949 169 mohor
              begin
2950 181 mohor
                test_fail("Busy signal should be cleared after 2 periods after MII IO signal become HIGH Z");
2951 169 mohor
                fail = fail + 1;
2952
              end
2953 181 mohor
              #Tp i1 = i1 + 1;
2954 169 mohor
            end
2955 181 mohor
          end
2956
          if (i2 == 0)
2957
          begin
2958
            if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2959 169 mohor
            begin
2960 181 mohor
              i2 = 1;
2961 169 mohor
            end
2962 181 mohor
            else
2963
            begin
2964
              test_fail("Nvalid signal should be cleared after MII IO signal become HIGH Z");
2965
              fail = fail + 1;
2966
            end
2967 169 mohor
          end
2968
        end
2969 181 mohor
      end
2970
    end
2971
    // set PHY to normal mode
2972
    #Tp eth_phy.preamble_suppresed(0);
2973
    // MII mode register
2974
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2975
    if(fail == 0)
2976
      test_ok;
2977
    else
2978
      fail = 0;
2979
  end
2980
 
2981
 
2982
  ////////////////////////////////////////////////////////////////////
2983
  ////                                                            ////
2984
  ////  Test scan status from phy with detecting link-fail bit    ////
2985
  ////  (with and without preamble)                               ////
2986
  ////                                                            ////
2987
  ////////////////////////////////////////////////////////////////////
2988
  if (test_num == 14) // 
2989
  begin
2990 194 tadej
    // TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )
2991
    test_name   = "TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )";
2992
    `TIME; $display("  TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )");
2993 181 mohor
 
2994
    reset_mii; // reset MII
2995
    // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2996
    #Tp eth_phy.link_up_down(1);
2997
    // set MII speed
2998
    clk_div = 6;
2999
    mii_set_clk_div(clk_div[7:0]);
3000
    // set address
3001
    reg_addr = 5'h1; // status register
3002
    phy_addr = 5'h1; // correct PHY address
3003
 
3004
    // read request
3005
    #Tp mii_read_req(phy_addr, reg_addr);
3006
    check_mii_busy; // wait for read to finish
3007
    // read data from PHY status register - remember LINK-UP status
3008 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3009 181 mohor
 
3010
    for (i = 0; i <= 1; i = i + 1)
3011
    begin
3012
      #Tp eth_phy.preamble_suppresed(i);
3013
      // MII mode register
3014
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
3015
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3016
      if (i)
3017
      begin
3018
        // change saved data when preamble is suppressed
3019
        #Tp tmp_data = tmp_data | 16'h0040; // put bit 6 to ONE
3020
      end
3021
 
3022
      // scan request
3023
      #Tp mii_scan_req(phy_addr, reg_addr);
3024
      check_mii_scan_valid; // wait for scan to make first data valid
3025
 
3026 169 mohor
      fork
3027 181 mohor
      begin
3028 169 mohor
        repeat(2) @(posedge Mdc_O);
3029
        // read data from PHY status register
3030 274 tadejm
        wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3031 181 mohor
        if (phy_data !== tmp_data)
3032 169 mohor
        begin
3033 181 mohor
          test_fail("Data was not correctly scaned from status register");
3034 169 mohor
          fail = fail + 1;
3035
        end
3036
        // read data from MII status register
3037 274 tadejm
        wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3038 181 mohor
        if (phy_data[0] !== 1'b0)
3039 169 mohor
        begin
3040 181 mohor
          test_fail("Link FAIL bit was set in the MII status register");
3041 169 mohor
          fail = fail + 1;
3042
        end
3043
      end
3044
      begin
3045 181 mohor
      // Completely check second scan
3046 169 mohor
        #Tp cnt = 0;
3047
        // wait for serial bus to become active - second scan
3048
        wait(Mdio_IO !== 1'bz);
3049
        // count transfer length
3050 181 mohor
        while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i == 0)) || ((cnt == 15) && (i == 1)) )
3051 169 mohor
        begin
3052
          @(posedge Mdc_O);
3053
          #Tp cnt = cnt + 1;
3054
        end
3055
        // check transfer length
3056 181 mohor
        if (i) // without preamble
3057 169 mohor
        begin
3058
          if (cnt != 33) // at this value Mdio_IO is HIGH Z
3059
          begin
3060 181 mohor
            test_fail("Second scan request did not proceed correctly");
3061 169 mohor
            fail = fail + 1;
3062
          end
3063
        end
3064
        else // with preamble
3065
        begin
3066
          if (cnt != 65) // at this value Mdio_IO is HIGH Z
3067
          begin
3068 181 mohor
            test_fail("Second scan request did not proceed correctly");
3069 169 mohor
            fail = fail + 1;
3070
          end
3071
        end
3072
      end
3073
      join
3074 181 mohor
      // check third to fifth scans
3075
      for (i3 = 0; i3 <= 2; i3 = i3 + 1)
3076
      begin
3077
        fork
3078 169 mohor
        begin
3079
          repeat(2) @(posedge Mdc_O);
3080
          // read data from PHY status register
3081 274 tadejm
          wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3082 181 mohor
          if (phy_data !== tmp_data)
3083 169 mohor
          begin
3084 181 mohor
            test_fail("Data was not correctly scaned from status register");
3085
            fail = fail + 1;
3086 169 mohor
          end
3087
          // read data from MII status register
3088 274 tadejm
          wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3089 181 mohor
          if (phy_data[0] !== 1'b0)
3090 169 mohor
          begin
3091 181 mohor
            test_fail("Link FAIL bit was set in the MII status register");
3092
            fail = fail + 1;
3093 169 mohor
          end
3094 181 mohor
          if (i3 == 2) // after fourth scan read
3095 169 mohor
          begin
3096 181 mohor
            @(posedge Mdc_O);
3097
            // change saved data
3098
            #Tp tmp_data = tmp_data & 16'hFFFB; // put bit 3 to ZERO
3099
            // set link down
3100
            #Tp eth_phy.link_up_down(0);
3101 169 mohor
          end
3102
        end
3103
        begin
3104 181 mohor
        // Completely check scans
3105
          #Tp cnt = 0;
3106
          // wait for serial bus to become active - second scan
3107
          wait(Mdio_IO !== 1'bz);
3108
          // count transfer length
3109
          while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i == 0)) || ((cnt == 15) && (i == 1)) )
3110 169 mohor
          begin
3111 181 mohor
            @(posedge Mdc_O);
3112
            #Tp cnt = cnt + 1;
3113
          end
3114
          // check transfer length
3115
          if (i) // without preamble
3116
          begin
3117
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
3118 169 mohor
            begin
3119 181 mohor
              test_fail("Fifth scan request did not proceed correctly");
3120
              fail = fail + 1;
3121 169 mohor
            end
3122 181 mohor
          end
3123
          else // with preamble
3124
          begin
3125
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
3126 169 mohor
            begin
3127 181 mohor
              test_fail("Fifth scan request did not proceed correctly");
3128
              fail = fail + 1;
3129 169 mohor
            end
3130
          end
3131
        end
3132 181 mohor
        join
3133
      end
3134
 
3135
      fork
3136
      begin
3137
        repeat(2) @(posedge Mdc_O);
3138
        // read data from PHY status register
3139 274 tadejm
        wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3140 181 mohor
        if (phy_data !== tmp_data)
3141
        begin
3142
          test_fail("Data was not correctly scaned from status register");
3143
          fail = fail + 1;
3144
        end
3145
        // read data from MII status register
3146 274 tadejm
        wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3147 181 mohor
        if (phy_data[0] === 1'b0)
3148
        begin
3149
          test_fail("Link FAIL bit was not set in the MII status register");
3150
          fail = fail + 1;
3151
        end
3152
        // wait to see if data stayed latched
3153
        repeat(4) @(posedge Mdc_O);
3154
        // read data from PHY status register
3155 274 tadejm
        wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3156 181 mohor
        if (phy_data !== tmp_data)
3157
        begin
3158
          test_fail("Data was not latched correctly in status register");
3159
          fail = fail + 1;
3160
        end
3161
        // read data from MII status register
3162 274 tadejm
        wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3163 181 mohor
        if (phy_data[0] === 1'b0)
3164
        begin
3165
          test_fail("Link FAIL bit was not set in the MII status register");
3166
          fail = fail + 1;
3167
        end
3168
        // change saved data
3169
        #Tp tmp_data = tmp_data | 16'h0004; // put bit 2 to ONE
3170
        // set link up
3171
        #Tp eth_phy.link_up_down(1);
3172
      end
3173
      begin
3174
      // Wait for sixth scan
3175
        // wait for serial bus to become active - sixth scan
3176
        wait(Mdio_IO !== 1'bz);
3177
        // wait for serial bus to become inactive - turn-around cycle in sixth scan
3178
        wait(Mdio_IO === 1'bz);
3179
        // wait for serial bus to become active - end of turn-around cycle in sixth scan
3180
        wait(Mdio_IO !== 1'bz);
3181
        // wait for serial bus to become inactive - end of sixth scan
3182
        wait(Mdio_IO === 1'bz);
3183
      end
3184 169 mohor
      join
3185 181 mohor
 
3186
      @(posedge Mdc_O);
3187 169 mohor
      // read data from PHY status register
3188 274 tadejm
      wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3189 169 mohor
      if (phy_data !== tmp_data)
3190
      begin
3191 181 mohor
        test_fail("Data was not correctly scaned from status register");
3192 169 mohor
        fail = fail + 1;
3193
      end
3194
      // read data from MII status register
3195 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3196 169 mohor
      if (phy_data[0] !== 1'b0)
3197
      begin
3198
        test_fail("Link FAIL bit was set in the MII status register");
3199
        fail = fail + 1;
3200
      end
3201 181 mohor
      // wait to see if data stayed latched
3202
      repeat(4) @(posedge Mdc_O);
3203
      // read data from PHY status register
3204 274 tadejm
      wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3205 181 mohor
      if (phy_data !== tmp_data)
3206 169 mohor
      begin
3207 181 mohor
        test_fail("Data was not correctly scaned from status register");
3208
        fail = fail + 1;
3209 169 mohor
      end
3210 181 mohor
      // read data from MII status register
3211 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3212 181 mohor
      if (phy_data[0] !== 1'b0)
3213 169 mohor
      begin
3214 181 mohor
        test_fail("Link FAIL bit was set in the MII status register");
3215
        fail = fail + 1;
3216 169 mohor
      end
3217 181 mohor
 
3218
      // STOP SCAN
3219
      #Tp mii_scan_finish; // finish scan operation
3220
      #Tp check_mii_busy; // wait for scan to finish
3221 169 mohor
    end
3222 181 mohor
    // set PHY to normal mode
3223
    #Tp eth_phy.preamble_suppresed(0);
3224
    // MII mode register
3225
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3226
    if(fail == 0)
3227
      test_ok;
3228
    else
3229
      fail = 0;
3230 169 mohor
  end
3231
 
3232
 
3233 181 mohor
  ////////////////////////////////////////////////////////////////////
3234
  ////                                                            ////
3235
  ////  Test scan status from phy with sliding link-fail bit      ////
3236
  ////  (with and without preamble)                               ////
3237
  ////                                                            ////
3238
  ////////////////////////////////////////////////////////////////////
3239
  if (test_num == 15) // 
3240 169 mohor
  begin
3241 194 tadej
    // TEST 15: SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )
3242
    test_name   = "TEST 15: SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )";
3243
    `TIME; $display("  TEST 15: SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )");
3244 181 mohor
 
3245
    // set address
3246
    reg_addr = 5'h1; // status register
3247
    phy_addr = 5'h1; // correct PHY address
3248
 
3249
    // read request
3250
    #Tp mii_read_req(phy_addr, reg_addr);
3251
    check_mii_busy; // wait for read to finish
3252
    // read data from PHY status register - remember LINK-UP status
3253 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3254 181 mohor
 
3255
    for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
3256 169 mohor
    begin
3257 181 mohor
      #Tp eth_phy.preamble_suppresed(i2);
3258
      // MII mode register
3259
      #Tp wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
3260
                    wbm_subseq_waits);
3261
      if (i2)
3262 169 mohor
      begin
3263 181 mohor
        // change saved data when preamble is suppressed
3264
        #Tp tmp_data = tmp_data | 16'h0040; // put bit 6 to ONE
3265
      end
3266
 
3267
      i = 0;
3268
      while (i < 80) // delay for sliding of LinkFail bit
3269
      begin
3270
        // first there are two scans
3271
        #Tp cnt = 0;
3272 169 mohor
        // scan request
3273
        #Tp mii_scan_req(phy_addr, reg_addr);
3274 181 mohor
        #Tp check_mii_scan_valid; // wait for scan to make first data valid
3275
 
3276
        // check second scan
3277 169 mohor
        fork
3278 181 mohor
        begin
3279
          repeat(4) @(posedge Mdc_O);
3280
          // read data from PHY status register
3281 274 tadejm
          wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3282 181 mohor
          if (phy_data !== tmp_data)
3283 169 mohor
          begin
3284 181 mohor
            test_fail("Second data was not correctly scaned from status register");
3285
            fail = fail + 1;
3286 169 mohor
          end
3287 181 mohor
          // read data from MII status register
3288 274 tadejm
          wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3289 181 mohor
          if (phy_data[0] !== 1'b0)
3290
          begin
3291
            test_fail("Link FAIL bit was set in the MII status register");
3292
            fail = fail + 1;
3293
          end
3294
        end
3295
        begin
3296
        // Completely check scan
3297
          #Tp cnt = 0;
3298
          // wait for serial bus to become active - second scan
3299
          wait(Mdio_IO !== 1'bz);
3300
          // count transfer length
3301
          while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3302
          begin
3303
            @(posedge Mdc_O);
3304
            #Tp cnt = cnt + 1;
3305
          end
3306
          // check transfer length
3307
          if (i2) // without preamble
3308
          begin
3309
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
3310 169 mohor
            begin
3311 181 mohor
              test_fail("Second scan request did not proceed correctly");
3312
              fail = fail + 1;
3313 169 mohor
            end
3314 181 mohor
          end
3315
          else // with preamble
3316
          begin
3317
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
3318
            begin
3319
              test_fail("Second scan request did not proceed correctly");
3320
              fail = fail + 1;
3321
            end
3322
          end
3323
        end
3324
        join
3325
        // reset counter 
3326
        #Tp cnt = 0;
3327
        // SLIDING LINK DOWN and CHECK
3328
        fork
3329
          begin
3330
          // set link down
3331
            repeat(i) @(posedge Mdc_O);
3332
            // set link down
3333
            #Tp eth_phy.link_up_down(0);
3334
          end
3335
          begin
3336
          // check data in MII registers after each scan in this fork statement
3337 169 mohor
            if (i2) // without preamble
3338 181 mohor
              wait (cnt == 32);
3339
            else // with preamble
3340
              wait (cnt == 64);
3341
            repeat(3) @(posedge Mdc_O);
3342
            // read data from PHY status register
3343 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3344 181 mohor
            if ( ((i < 49) && !i2) || ((i < 17) && i2) )
3345 169 mohor
            begin
3346 181 mohor
              if (phy_data !== (tmp_data & 16'hFFFB)) // bit 3 is ZERO
3347 169 mohor
              begin
3348 181 mohor
                test_fail("Third data was not correctly scaned from status register");
3349 169 mohor
                fail = fail + 1;
3350
              end
3351
            end
3352 181 mohor
            else
3353 169 mohor
            begin
3354 181 mohor
              if (phy_data !== tmp_data)
3355 169 mohor
              begin
3356 181 mohor
                test_fail("Third data was not correctly scaned from status register");
3357 169 mohor
                fail = fail + 1;
3358
              end
3359
            end
3360 181 mohor
            // read data from MII status register
3361 274 tadejm
            wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3362 181 mohor
            if ( ((i < 49) && !i2) || ((i < 17) && i2) )
3363 169 mohor
            begin
3364 181 mohor
              if (phy_data[0] === 1'b0)
3365
              begin
3366
                test_fail("Link FAIL bit was not set in the MII status register");
3367
                fail = fail + 1;
3368
              end
3369 169 mohor
            end
3370 181 mohor
            else
3371 169 mohor
            begin
3372 181 mohor
              if (phy_data[0] !== 1'b0)
3373 169 mohor
              begin
3374 181 mohor
                test_fail("Link FAIL bit was set in the MII status register");
3375 169 mohor
                fail = fail + 1;
3376
              end
3377
            end
3378 181 mohor
          end
3379
          begin
3380
          // check length
3381
            for (i3 = 0; i3 <= 1; i3 = i3 + 1) // two scans
3382 169 mohor
            begin
3383 181 mohor
              #Tp cnt = 0;
3384
              // wait for serial bus to become active if there is more than one scan
3385
              wait(Mdio_IO !== 1'bz);
3386
              // count transfer length
3387
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3388 169 mohor
              begin
3389 181 mohor
                @(posedge Mdc_O);
3390
                #Tp cnt = cnt + 1;
3391 169 mohor
              end
3392 181 mohor
              // check transfer length
3393
              if (i2) // without preamble
3394
              begin
3395
                if (cnt != 33) // at this value Mdio_IO is HIGH Z
3396
                begin
3397
                  test_fail("3. or 4. scan request did not proceed correctly, while SCAN STOP was written");
3398
                  fail = fail + 1;
3399
                end
3400
              end
3401
              else // with preamble
3402
              begin
3403
                if (cnt != 65) // at this value Mdio_IO is HIGH Z
3404
                begin
3405
                  test_fail("3. or 4. scan request did not proceed correctly, while SCAN STOP was written");
3406
                  fail = fail + 1;
3407
                end
3408
              end
3409 169 mohor
            end
3410
          end
3411
        join
3412 181 mohor
        // reset counter
3413
        #Tp cnt = 0;
3414
        // check fifth scan and data from fourth scan
3415
        fork
3416 169 mohor
        begin
3417 181 mohor
          repeat(2) @(posedge Mdc_O);
3418
          // read data from PHY status register
3419 274 tadejm
          wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3420 181 mohor
          if (phy_data !== (tmp_data & 16'hFFFB)) // bit 3 is ZERO
3421 169 mohor
          begin
3422 181 mohor
            test_fail("4. data was not correctly scaned from status register");
3423
            fail = fail + 1;
3424 169 mohor
          end
3425 181 mohor
          // read data from MII status register
3426 274 tadejm
          wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3427 181 mohor
          if (phy_data[0] === 1'b0)
3428 169 mohor
          begin
3429 181 mohor
            test_fail("Link FAIL bit was not set in the MII status register");
3430 169 mohor
            fail = fail + 1;
3431
          end
3432
        end
3433
        begin
3434 181 mohor
        // Completely check intermediate scan
3435
          #Tp cnt = 0;
3436
          // wait for serial bus to become active - second scan
3437 169 mohor
          wait(Mdio_IO !== 1'bz);
3438
          // count transfer length
3439
          while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3440
          begin
3441
            @(posedge Mdc_O);
3442
            #Tp cnt = cnt + 1;
3443
          end
3444 181 mohor
          // check transfer length
3445
          if (i2) // without preamble
3446 169 mohor
          begin
3447 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
3448
            begin
3449
              test_fail("Fifth scan request did not proceed correctly");
3450
              fail = fail + 1;
3451
            end
3452 169 mohor
          end
3453 181 mohor
          else // with preamble
3454
          begin
3455
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
3456
            begin
3457
              test_fail("Fifth scan request did not proceed correctly");
3458
              fail = fail + 1;
3459
            end
3460
          end
3461 169 mohor
        end
3462 181 mohor
        join
3463
        // reset counter 
3464
        #Tp cnt = 0;
3465
        // SLIDING LINK UP and CHECK
3466
        fork
3467 169 mohor
          begin
3468 181 mohor
          // set link up
3469
            repeat(i) @(posedge Mdc_O);
3470
            // set link up
3471
            #Tp eth_phy.link_up_down(1);
3472 169 mohor
          end
3473 181 mohor
          begin
3474
          // check data in MII registers after each scan in this fork statement
3475
            repeat(2) @(posedge Mdc_O);
3476
            if (i2) // without preamble
3477
              wait (cnt == 32);
3478
            else // with preamble
3479
              wait (cnt == 64);
3480
            repeat(3) @(posedge Mdc_O);
3481
            // read data from PHY status register
3482 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3483 181 mohor
            if ( ((i < 49) && !i2) || ((i < 17) && i2) )
3484
            begin
3485
              if (phy_data !== tmp_data)
3486
              begin
3487
                test_fail("6. data was not correctly scaned from status register");
3488
                fail = fail + 1;
3489
              end
3490
            end
3491
            else
3492
            begin
3493
              if (phy_data !== (tmp_data & 16'hFFFB)) // bit 3 is ZERO
3494
              begin
3495
                test_fail("6. data was not correctly scaned from status register");
3496
                fail = fail + 1;
3497
              end
3498
            end
3499
            // read data from MII status register
3500 274 tadejm
            wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3501 181 mohor
            if ( ((i < 49) && !i2) || ((i < 17) && i2) )
3502
            begin
3503
              if (phy_data[0] !== 1'b0)
3504
              begin
3505
                test_fail("Link FAIL bit was set in the MII status register");
3506
                fail = fail + 1;
3507
              end
3508
            end
3509
            else
3510
            begin
3511
              if (phy_data[0] === 1'b0)
3512
              begin
3513
                test_fail("Link FAIL bit was not set in the MII status register");
3514
                fail = fail + 1;
3515
              end
3516
            end
3517
          end
3518
          begin
3519
          // check length
3520
            for (i3 = 0; i3 <= 1; i3 = i3 + 1) // two scans
3521
            begin
3522
              #Tp cnt = 0;
3523
              // wait for serial bus to become active if there is more than one scan
3524
              wait(Mdio_IO !== 1'bz);
3525
              // count transfer length
3526
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3527
              begin
3528
                @(posedge Mdc_O);
3529
                #Tp cnt = cnt + 1;
3530
              end
3531
              // check transfer length
3532
              if (i2) // without preamble
3533
              begin
3534
                if (cnt != 33) // at this value Mdio_IO is HIGH Z
3535
                begin
3536
                  test_fail("Scan request did not proceed correctly, while SCAN STOP was written");
3537
                  fail = fail + 1;
3538
                end
3539
              end
3540
              else // with preamble
3541
              begin
3542
                if (cnt != 65) // at this value Mdio_IO is HIGH Z
3543
                begin
3544
                  test_fail("Scan request did not proceed correctly, while SCAN STOP was written");
3545
                  fail = fail + 1;
3546
                end
3547
              end
3548
            end
3549
          end
3550
        join
3551
        // check last scan 
3552
        repeat(4) @(posedge Mdc_O);
3553
        // read data from PHY status register
3554 274 tadejm
        wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3555 181 mohor
        if (phy_data !== tmp_data)
3556
        begin
3557
          test_fail("7. data was not correctly scaned from status register");
3558
          fail = fail + 1;
3559 169 mohor
        end
3560 181 mohor
        // read data from MII status register
3561 274 tadejm
        wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3562 181 mohor
        if (phy_data[0] !== 1'b0)
3563
        begin
3564
          test_fail("Link FAIL bit was set in the MII status register");
3565
          fail = fail + 1;
3566
        end
3567
 
3568
        #Tp mii_scan_finish; // finish scan operation
3569
        #Tp check_mii_busy; // wait for scan to finish
3570
        #Tp;
3571
        // set delay of writing the command
3572
        if (i2) // without preamble
3573
        begin
3574
          case(i)
3575
            0,  1,  2,  3,  4:  i = i + 1;
3576
            13, 14, 15, 16, 17,
3577
            18, 19, 20, 21, 22,
3578
            23, 24, 25, 26, 27,
3579
            28, 29, 30, 31, 32,
3580
            33, 34, 35:         i = i + 1;
3581
            36:                 i = 80;
3582
            default:            i = 13;
3583
          endcase
3584
        end
3585 169 mohor
        else // with preamble
3586
        begin
3587 181 mohor
          case(i)
3588
            0,  1,  2,  3,  4:  i = i + 1;
3589
            45, 46, 47, 48, 49,
3590
            50, 51, 52, 53, 54,
3591
            55, 56, 57, 58, 59,
3592
            60, 61, 62, 63, 64,
3593
            65, 66, 67:         i = i + 1;
3594
            68:                 i = 80;
3595
            default:            i = 45;
3596
          endcase
3597 169 mohor
        end
3598 181 mohor
        @(posedge wb_clk);
3599
        #Tp;
3600 169 mohor
      end
3601
    end
3602 181 mohor
    // set PHY to normal mode
3603
    #Tp eth_phy.preamble_suppresed(0);
3604
    // MII mode register
3605
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3606
    if(fail == 0)
3607
      test_ok;
3608
    else
3609
      fail = 0;
3610 169 mohor
  end
3611
 
3612
 
3613 181 mohor
  ////////////////////////////////////////////////////////////////////
3614
  ////                                                            ////
3615
  ////  Test sliding stop scan command immediately after scan     ////
3616
  ////  request (with and without preamble)                       ////
3617
  ////                                                            ////
3618
  ////////////////////////////////////////////////////////////////////
3619
  if (test_num == 16) // 
3620 116 mohor
  begin
3621 194 tadej
    // TEST 16: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )
3622
    test_name = "TEST 16: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )";
3623 181 mohor
    `TIME;
3624 194 tadej
    $display("  TEST 16: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )");
3625 181 mohor
 
3626
    for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
3627 169 mohor
    begin
3628 181 mohor
      #Tp eth_phy.preamble_suppresed(i2);
3629
      // MII mode register
3630
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
3631
                wbm_subseq_waits);
3632
      i = 0;
3633
      cnt = 0;
3634
      while (i < 80) // delay for sliding of writing a STOP SCAN command
3635 169 mohor
      begin
3636 181 mohor
        for (i3 = 0; i3 <= 1; i3 = i3 + 1) // choose read or write after scan will be finished
3637 169 mohor
        begin
3638 181 mohor
          // set address
3639
          reg_addr = 5'h0; // control register
3640
          phy_addr = 5'h1; // correct PHY address
3641
          cnt = 0;
3642
          // scan request
3643
          #Tp mii_scan_req(phy_addr, reg_addr);
3644
          fork
3645
            begin
3646
              repeat(i) @(posedge Mdc_O);
3647
              // write command 0x0 into MII command register
3648
              // MII command written while scan in progress
3649
              wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3650
              @(posedge wb_clk);
3651
              #Tp check_mii_busy; // wait for scan to finish
3652
              @(posedge wb_clk);
3653
              disable check;
3654
            end
3655
            begin: check
3656
              // wait for serial bus to become active
3657
              wait(Mdio_IO !== 1'bz);
3658
              // count transfer length
3659
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3660
              begin
3661
                @(posedge Mdc_O);
3662
                #Tp cnt = cnt + 1;
3663
              end
3664
              // check transfer length
3665
              if (i2) // without preamble
3666
              begin
3667
                if (cnt != 33) // at this value Mdio_IO is HIGH Z
3668
                begin
3669
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3670
                  fail = fail + 1;
3671
                end
3672
              end
3673
              else // with preamble
3674
              begin
3675
                if (cnt != 65) // at this value Mdio_IO is HIGH Z
3676
                begin
3677
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3678
                  fail = fail + 1;
3679
                end
3680
              end
3681
              cnt = 0;
3682
              // wait for serial bus to become active if there is more than one scan
3683
              wait(Mdio_IO !== 1'bz);
3684
              // count transfer length
3685
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3686
              begin
3687
                @(posedge Mdc_O);
3688
                #Tp cnt = cnt + 1;
3689
              end
3690
              // check transfer length
3691
              if (i2) // without preamble
3692
              begin
3693
                if (cnt != 33) // at this value Mdio_IO is HIGH Z
3694
                begin
3695
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3696
                  fail = fail + 1;
3697
                end
3698
              end
3699
              else // with preamble
3700
              begin
3701
                if (cnt != 65) // at this value Mdio_IO is HIGH Z
3702
                begin
3703
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3704
                  fail = fail + 1;
3705
                end
3706
              end
3707
            end
3708
          join
3709
          // check the BUSY signal to see if the bus is still IDLE
3710
          for (i1 = 0; i1 < 8; i1 = i1 + 1)
3711
            check_mii_busy; // wait for bus to become idle
3712
 
3713
          // try normal write or read after scan was finished
3714
          phy_data = {8'h7D, (i[7:0] + 1)};
3715
          cnt = 0;
3716
          if (i3 == 0) // write after scan
3717 169 mohor
          begin
3718 181 mohor
            // write request
3719
            #Tp mii_write_req(phy_addr, reg_addr, phy_data);
3720
            // wait for serial bus to become active
3721
            wait(Mdio_IO !== 1'bz);
3722
            // count transfer length
3723
            while(Mdio_IO !== 1'bz)
3724
            begin
3725
              @(posedge Mdc_O);
3726
              #Tp cnt = cnt + 1;
3727
            end
3728 169 mohor
            @(posedge Mdc_O);
3729 181 mohor
            // read request
3730
            #Tp mii_read_req(phy_addr, reg_addr);
3731
            check_mii_busy; // wait for read to finish
3732
            // read and check data
3733 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3734 181 mohor
            if (phy_data !== tmp_data)
3735 169 mohor
            begin
3736 181 mohor
              test_fail("Data was not correctly written into OR read from PHY register - control register");
3737 169 mohor
              fail = fail + 1;
3738
            end
3739
          end
3740 181 mohor
          else // read after scan
3741 169 mohor
          begin
3742 181 mohor
            // read request
3743
            #Tp mii_read_req(phy_addr, reg_addr);
3744
            // wait for serial bus to become active
3745
            wait(Mdio_IO !== 1'bz);
3746
            // count transfer length
3747
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3748 169 mohor
            begin
3749 181 mohor
              @(posedge Mdc_O);
3750
              #Tp cnt = cnt + 1;
3751
            end
3752
            @(posedge Mdc_O);
3753
            check_mii_busy; // wait for read to finish
3754
            // read and check data
3755 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3756 181 mohor
            if (phy_data !== tmp_data)
3757
            begin
3758
              test_fail("Data was not correctly written into OR read from PHY register - control register");
3759 169 mohor
              fail = fail + 1;
3760
            end
3761
          end
3762 181 mohor
          // check if transfer was a proper length
3763 169 mohor
          if (i2) // without preamble
3764
          begin
3765
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
3766
            begin
3767 181 mohor
              test_fail("New request did not proceed correctly, after scan request");
3768 169 mohor
              fail = fail + 1;
3769
            end
3770
          end
3771
          else // with preamble
3772
          begin
3773
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
3774
            begin
3775 181 mohor
              test_fail("New request did not proceed correctly, after scan request");
3776 169 mohor
              fail = fail + 1;
3777
            end
3778
          end
3779
        end
3780 181 mohor
        #Tp;
3781
        // set delay of writing the command
3782
        if (i2) // without preamble
3783
        begin
3784
          case(i)
3785
            0, 1:               i = i + 1;
3786
            18, 19, 20, 21, 22,
3787
            23, 24, 25, 26, 27,
3788
            28, 29, 30, 31, 32,
3789
            33, 34, 35:         i = i + 1;
3790
            36:                 i = 80;
3791
            default:            i = 18;
3792
          endcase
3793
        end
3794
        else // with preamble
3795
        begin
3796
          case(i)
3797
            0, 1:               i = i + 1;
3798
            50, 51, 52, 53, 54,
3799
            55, 56, 57, 58, 59,
3800
            60, 61, 62, 63, 64,
3801
            65, 66, 67:         i = i + 1;
3802
            68:                 i = 80;
3803
            default:            i = 50;
3804
          endcase
3805
        end
3806
        @(posedge wb_clk);
3807
      end
3808
    end
3809
    // set PHY to normal mode
3810
    #Tp eth_phy.preamble_suppresed(0);
3811
    // MII mode register
3812
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3813
    if(fail == 0)
3814
      test_ok;
3815
    else
3816
      fail = 0;
3817
  end
3818 169 mohor
 
3819 181 mohor
 
3820
  ////////////////////////////////////////////////////////////////////
3821
  ////                                                            ////
3822
  ////  Test sliding stop scan command after 2. scan (with and    ////
3823
  ////  without preamble)                                         ////
3824
  ////                                                            ////
3825
  ////////////////////////////////////////////////////////////////////
3826
  if (test_num == 17) // 
3827
  begin
3828 194 tadej
    // TEST 17: SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )
3829
    test_name = "TEST 17: SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )";
3830
    `TIME; $display("  TEST 17: SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )");
3831 181 mohor
 
3832
    for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
3833
    begin
3834
      #Tp eth_phy.preamble_suppresed(i2);
3835
      // MII mode register
3836
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
3837
                wbm_subseq_waits);
3838
 
3839
      i = 0;
3840
      cnt = 0;
3841
      while (i < 80) // delay for sliding of writing a STOP SCAN command
3842
      begin
3843
        for (i3 = 0; i3 <= 1; i3 = i3 + 1) // choose read or write after scan will be finished
3844
        begin
3845
          // first there are two scans
3846
          // set address
3847
          reg_addr = 5'h0; // control register
3848
          phy_addr = 5'h1; // correct PHY address
3849
          cnt = 0;
3850
          // scan request
3851
          #Tp mii_scan_req(phy_addr, reg_addr);
3852
          // wait and check first 2 scans
3853 169 mohor
          begin
3854
            // wait for serial bus to become active
3855
            wait(Mdio_IO !== 1'bz);
3856
            // count transfer length
3857
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3858
            begin
3859
              @(posedge Mdc_O);
3860
              #Tp cnt = cnt + 1;
3861
            end
3862
            // check transfer length
3863
            if (i2) // without preamble
3864
            begin
3865
              if (cnt != 33) // at this value Mdio_IO is HIGH Z
3866
              begin
3867
                test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3868
                fail = fail + 1;
3869
              end
3870
            end
3871
            else // with preamble
3872
            begin
3873
              if (cnt != 65) // at this value Mdio_IO is HIGH Z
3874
              begin
3875
                test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3876
                fail = fail + 1;
3877
              end
3878
            end
3879
            cnt = 0;
3880
            // wait for serial bus to become active if there is more than one scan
3881
            wait(Mdio_IO !== 1'bz);
3882
            // count transfer length
3883
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3884
            begin
3885
              @(posedge Mdc_O);
3886
              #Tp cnt = cnt + 1;
3887
            end
3888
            // check transfer length
3889
            if (i2) // without preamble
3890
            begin
3891
              if (cnt != 33) // at this value Mdio_IO is HIGH Z
3892
              begin
3893
                test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3894
                fail = fail + 1;
3895
              end
3896
            end
3897
            else // with preamble
3898
            begin
3899
              if (cnt != 65) // at this value Mdio_IO is HIGH Z
3900
              begin
3901
                test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3902
                fail = fail + 1;
3903
              end
3904
            end
3905
          end
3906
 
3907 181 mohor
          // reset counter 
3908
          cnt = 0;
3909
          fork
3910
            begin
3911
              repeat(i) @(posedge Mdc_O);
3912
              // write command 0x0 into MII command register
3913
              // MII command written while scan in progress
3914
              wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3915
              @(posedge wb_clk);
3916
              #Tp check_mii_busy; // wait for scan to finish
3917
              @(posedge wb_clk);
3918
              disable check_3;
3919
            end
3920
            begin: check_3
3921
              // wait for serial bus to become active
3922
              wait(Mdio_IO !== 1'bz);
3923
              // count transfer length
3924
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3925
              begin
3926
                @(posedge Mdc_O);
3927
                #Tp cnt = cnt + 1;
3928
              end
3929
              // check transfer length
3930
              if (i2) // without preamble
3931
              begin
3932
                if (cnt != 33) // at this value Mdio_IO is HIGH Z
3933
                begin
3934
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3935
                  fail = fail + 1;
3936
                end
3937
              end
3938
              else // with preamble
3939
              begin
3940
                if (cnt != 65) // at this value Mdio_IO is HIGH Z
3941
                begin
3942
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3943
                  fail = fail + 1;
3944
                end
3945
              end
3946
              cnt = 0;
3947
              // wait for serial bus to become active if there is more than one scan
3948
              wait(Mdio_IO !== 1'bz);
3949
              // count transfer length
3950
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3951
              begin
3952
                @(posedge Mdc_O);
3953
                #Tp cnt = cnt + 1;
3954
              end
3955
              // check transfer length
3956
              if (i2) // without preamble
3957
              begin
3958
                if (cnt != 33) // at this value Mdio_IO is HIGH Z
3959
                begin
3960
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3961
                  fail = fail + 1;
3962
                end
3963
              end
3964
              else // with preamble
3965
              begin
3966
                if (cnt != 65) // at this value Mdio_IO is HIGH Z
3967
                begin
3968
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3969
                  fail = fail + 1;
3970
                end
3971
              end
3972
            end
3973
          join
3974
          // check the BUSY signal to see if the bus is still IDLE
3975
          for (i1 = 0; i1 < 8; i1 = i1 + 1)
3976
            check_mii_busy; // wait for bus to become idle
3977
 
3978
          // try normal write or read after scan was finished
3979
          phy_data = {8'h7D, (i[7:0] + 1)};
3980
          cnt = 0;
3981
          if (i3 == 0) // write after scan
3982 169 mohor
          begin
3983 181 mohor
            // write request
3984
            #Tp mii_write_req(phy_addr, reg_addr, phy_data);
3985
            // wait for serial bus to become active
3986
            wait(Mdio_IO !== 1'bz);
3987
            // count transfer length
3988
            while(Mdio_IO !== 1'bz)
3989
            begin
3990
              @(posedge Mdc_O);
3991
              #Tp cnt = cnt + 1;
3992
            end
3993 169 mohor
            @(posedge Mdc_O);
3994 181 mohor
            // read request
3995
            #Tp mii_read_req(phy_addr, reg_addr);
3996
            check_mii_busy; // wait for read to finish
3997
            // read and check data
3998 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3999 181 mohor
            if (phy_data !== tmp_data)
4000
            begin
4001
              test_fail("Data was not correctly written into OR read from PHY register - control register");
4002
              fail = fail + 1;
4003
            end
4004 169 mohor
          end
4005 181 mohor
          else // read after scan
4006 169 mohor
          begin
4007 181 mohor
            // read request
4008
            #Tp mii_read_req(phy_addr, reg_addr);
4009
            // wait for serial bus to become active
4010
            wait(Mdio_IO !== 1'bz);
4011
            // count transfer length
4012
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
4013
            begin
4014
              @(posedge Mdc_O);
4015
              #Tp cnt = cnt + 1;
4016
            end
4017
            @(posedge Mdc_O);
4018
            check_mii_busy; // wait for read to finish
4019
            // read and check data
4020 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4021 181 mohor
            if (phy_data !== tmp_data)
4022
            begin
4023
              test_fail("Data was not correctly written into OR read from PHY register - control register");
4024
              fail = fail + 1;
4025
            end
4026 169 mohor
          end
4027 181 mohor
          // check if transfer was a proper length
4028
          if (i2) // without preamble
4029 169 mohor
          begin
4030 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
4031
            begin
4032
              test_fail("New request did not proceed correctly, after scan request");
4033
              fail = fail + 1;
4034
            end
4035 169 mohor
          end
4036 181 mohor
          else // with preamble
4037 169 mohor
          begin
4038 181 mohor
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
4039
            begin
4040
              test_fail("New request did not proceed correctly, after scan request");
4041
              fail = fail + 1;
4042
            end
4043 169 mohor
          end
4044
        end
4045 181 mohor
        #Tp;
4046
        // set delay of writing the command
4047 169 mohor
        if (i2) // without preamble
4048
        begin
4049 181 mohor
          case(i)
4050
            0, 1:               i = i + 1;
4051
            18, 19, 20, 21, 22,
4052
            23, 24, 25, 26, 27,
4053
            28, 29, 30, 31, 32,
4054
            33, 34, 35:         i = i + 1;
4055
            36:                 i = 80;
4056
            default:            i = 18;
4057
          endcase
4058 169 mohor
        end
4059
        else // with preamble
4060
        begin
4061 181 mohor
          case(i)
4062
            0, 1:               i = i + 1;
4063
            50, 51, 52, 53, 54,
4064
            55, 56, 57, 58, 59,
4065
            60, 61, 62, 63, 64,
4066
            65, 66, 67:         i = i + 1;
4067
            68:                 i = 80;
4068
            default:            i = 50;
4069
          endcase
4070 169 mohor
        end
4071 181 mohor
        @(posedge wb_clk);
4072 116 mohor
      end
4073
    end
4074 181 mohor
    // set PHY to normal mode
4075
    #Tp eth_phy.preamble_suppresed(0);
4076
    // MII mode register
4077
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4078
    if(fail == 0)
4079
      test_ok;
4080
    else
4081
      fail = 0;
4082 169 mohor
  end
4083 116 mohor
 
4084 181 mohor
end   //  for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
4085
 
4086 169 mohor
end
4087
endtask // test_mii
4088
 
4089
 
4090
task test_mac_full_duplex_transmit;
4091
  input  [31:0]  start_task;
4092
  input  [31:0]  end_task;
4093
  integer        bit_start_1;
4094
  integer        bit_end_1;
4095
  integer        bit_start_2;
4096
  integer        bit_end_2;
4097
  integer        num_of_reg;
4098 209 tadejm
  integer        num_of_frames;
4099
  integer        num_of_bd;
4100 169 mohor
  integer        i_addr;
4101
  integer        i_data;
4102
  integer        i_length;
4103 209 tadejm
  integer        tmp_len;
4104
  integer        tmp_bd;
4105
  integer        tmp_bd_num;
4106 169 mohor
  integer        tmp_data;
4107 209 tadejm
  integer        tmp_ipgt;
4108 194 tadej
  integer        test_num;
4109 169 mohor
  reg    [31:0]  tx_bd_num;
4110
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
4111
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
4112
  integer        i;
4113
  integer        i1;
4114
  integer        i2;
4115
  integer        i3;
4116
  integer        fail;
4117
  integer        speed;
4118 279 mohor
  reg            no_underrun;
4119 209 tadejm
  reg            frame_started;
4120
  reg            frame_ended;
4121
  reg            wait_for_frame;
4122 169 mohor
  reg    [31:0]  addr;
4123
  reg    [31:0]  data;
4124
  reg    [31:0]  tmp;
4125
  reg    [ 7:0]  st_data;
4126
  reg    [15:0]  max_tmp;
4127
  reg    [15:0]  min_tmp;
4128 279 mohor
 
4129 169 mohor
begin
4130
// MAC FULL DUPLEX TRANSMIT TEST
4131
test_heading("MAC FULL DUPLEX TRANSMIT TEST");
4132
$display(" ");
4133
$display("MAC FULL DUPLEX TRANSMIT TEST");
4134
fail = 0;
4135
 
4136
// reset MAC registers
4137
hard_reset;
4138
// reset MAC and MII LOGIC with soft reset
4139 274 tadejm
//reset_mac;
4140
//reset_mii;
4141 169 mohor
// set wb slave response
4142
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
4143
 
4144
  /*
4145
  TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
4146
  -------------------------------------------------------------------------------------
4147
  set_tx_bd
4148
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0], len[15:0], irq, pad, crc, txpnt[31:0]);
4149
  set_tx_bd_wrap
4150
    (tx_bd_num_end[6:0]);
4151
  set_tx_bd_ready
4152
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
4153
  check_tx_bd
4154
    (tx_bd_num_start[6:0], tx_bd_status[31:0]);
4155
  clear_tx_bd
4156
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
4157
 
4158
  TASKS for set and control RX buffer descriptors:
4159
  ------------------------------------------------
4160
  set_rx_bd
4161
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0], irq, rxpnt[31:0]);
4162
  set_rx_bd_wrap
4163
    (rx_bd_num_end[6:0]);
4164
  set_rx_bd_empty
4165
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
4166
  check_rx_bd
4167
    (rx_bd_num_end[6:0], rx_bd_status);
4168
  clear_rx_bd
4169
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
4170
 
4171
  TASKS for set and check TX packets:
4172
  -----------------------------------
4173
  set_tx_packet
4174
    (txpnt[31:0], len[15:0], eth_start_data[7:0]);
4175
  check_tx_packet
4176
    (txpnt_wb[31:0], txpnt_phy[31:0], len[15:0], failure[31:0]);
4177
 
4178
  TASKS for set and check RX packets:
4179
  -----------------------------------
4180
  set_rx_packet
4181
    (rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
4182
  check_rx_packet
4183
    (rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
4184
 
4185
  TASKS for append and check CRC to/of TX packet:
4186
  -----------------------------------------------
4187
  append_tx_crc
4188
    (txpnt_wb[31:0], len[15:0], negated_crc);
4189
  check_tx_crc
4190
    (txpnt_phy[31:0], len[15:0], negated_crc, failure[31:0]);
4191
 
4192
  TASK for append CRC to RX packet (CRC is checked together with check_rx_packet):
4193
  --------------------------------------------------------------------------------
4194
  append_rx_crc
4195
    (rxpnt_phy[31:0], len[15:0], plus_nibble, negated_crc);
4196
  */
4197
 
4198 194 tadej
//////////////////////////////////////////////////////////////////////
4199
////                                                              ////
4200
////  test_mac_full_duplex_transmit:                              ////
4201
////                                                              ////
4202
////  0: Test no transmit when all buffers are RX ( 10Mbps ).     ////
4203
////  1: Test no transmit when all buffers are RX ( 100Mbps ).    ////
4204
////  2: Test transmit packets form MINFL to MAXFL sizes at       ////
4205
////     one TX buffer decriptor ( 10Mbps ).                      ////
4206
////  3: Test transmit packets form MINFL to MAXFL sizes at       ////
4207
////     one TX buffer decriptor ( 100Mbps ).                     ////
4208
////                                                              ////
4209
//////////////////////////////////////////////////////////////////////
4210
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
4211 169 mohor
begin
4212
 
4213 194 tadej
  ////////////////////////////////////////////////////////////////////
4214
  ////                                                            ////
4215
  ////  Test no transmit when all buffers are RX ( 10Mbps ).      ////
4216
  ////                                                            ////
4217
  ////////////////////////////////////////////////////////////////////
4218
  if (test_num == 0) // Test no transmit when all buffers are RX ( 10Mbps ).
4219 169 mohor
  begin
4220 194 tadej
    // TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )
4221
    test_name   = "TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )";
4222
    `TIME; $display("  TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )");
4223
 
4224
    // unmask interrupts
4225 209 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
4226 194 tadej
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4227
    // set all buffer descriptors to RX - must be set before TX enable
4228 274 tadejm
    wait (wbm_working == 0);
4229 194 tadej
    wbm_write(`ETH_TX_BD_NUM, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4230
    // enable TX, set full-duplex mode, padding and CRC appending
4231 274 tadejm
    wait (wbm_working == 0);
4232 194 tadej
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4233
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4234
 
4235
    // write to phy's control register for 10Mbps
4236
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
4237
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
4238
    speed = 10;
4239
 
4240
    i = 0;
4241
    while (i < 128)
4242 169 mohor
    begin
4243 194 tadej
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
4244 169 mohor
      begin
4245 194 tadej
        set_tx_packet((`MEMORY_BASE + (i1 * 200)), 100, 0);
4246
        set_tx_bd(i1, i1, 100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + (i1 * 200)));
4247 169 mohor
      end
4248 194 tadej
      set_tx_bd_wrap(i);
4249
      fork
4250
        begin
4251
          set_tx_bd_ready(0, i);
4252
          repeat(20) @(negedge mtx_clk);
4253
          #1 disable check_tx_en10;
4254
        end
4255
        begin: check_tx_en10
4256
          wait (MTxEn === 1'b1);
4257
          test_fail("Tramsmit should not start at all");
4258
          fail = fail + 1;
4259
          `TIME; $display("*E Transmit of %d packets should not start at all - active MTxEn", i);
4260
        end
4261
      join
4262
      for (i2 = 0; i2 < 20; i2 = i2 + 1)
4263 169 mohor
      begin
4264 194 tadej
        check_tx_bd(0, tmp);
4265
        #1;
4266
        if (tmp[15] === 1'b0)
4267
        begin
4268
          test_fail("Tramsmit should not start at all");
4269
          fail = fail + 1;
4270
          `TIME; $display("*E Transmit of %d packets should not start at all - ready is 0", i);
4271
        end
4272
        if (tmp[8:0] !== 0)
4273
        begin
4274
          test_fail("Tramsmit should not be finished since it should not start at all");
4275
          fail = fail + 1;
4276
          `TIME; $display("*E Transmit of should not be finished since it should not start at all");
4277
        end
4278
        @(posedge wb_clk);
4279 169 mohor
      end
4280 274 tadejm
      wait (wbm_working == 0);
4281 194 tadej
      wbm_read(`ETH_INT, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4282
      if (tmp[6:0] !== 0)
4283 169 mohor
      begin
4284 194 tadej
        test_fail("Tramsmit should not get INT since it should not start at all");
4285 169 mohor
        fail = fail + 1;
4286 194 tadej
        `TIME; $display("*E Transmit of should not get INT since it should not start at all");
4287 169 mohor
      end
4288 194 tadej
      clear_tx_bd(0, i);
4289
      if ((i < 5) || (i > 124))
4290
        i = i + 1;
4291
      else
4292
        i = i + 120;
4293 116 mohor
    end
4294 194 tadej
    // disable TX
4295 274 tadejm
    wait (wbm_working == 0);
4296 194 tadej
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4297
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4298
    if(fail == 0)
4299
      test_ok;
4300 116 mohor
    else
4301 194 tadej
      fail = 0;
4302 169 mohor
  end
4303 116 mohor
 
4304
 
4305 194 tadej
  ////////////////////////////////////////////////////////////////////
4306
  ////                                                            ////
4307
  ////  Test no transmit when all buffers are RX ( 100Mbps ).     ////
4308
  ////                                                            ////
4309
  ////////////////////////////////////////////////////////////////////
4310
  if (test_num == 1) // Test no transmit when all buffers are RX ( 100Mbps ).
4311 169 mohor
  begin
4312 194 tadej
    // TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )
4313
    test_name   = "TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )";
4314
    `TIME; $display("  TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )");
4315
 
4316
    // unmask interrupts
4317 274 tadejm
    wait (wbm_working == 0);
4318 209 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
4319 194 tadej
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4320
    // set all buffer descriptors to RX - must be set before TX enable
4321 274 tadejm
    wait (wbm_working == 0);
4322 194 tadej
    wbm_write(`ETH_TX_BD_NUM, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4323
    // enable TX, set full-duplex mode, padding and CRC appending
4324 274 tadejm
    wait (wbm_working == 0);
4325 194 tadej
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4326
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4327
 
4328
    // write to phy's control register for 100Mbps
4329
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
4330
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
4331
    speed = 100;
4332
 
4333
    i = 0;
4334
    while (i < 128)
4335 169 mohor
    begin
4336 194 tadej
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
4337 169 mohor
      begin
4338 194 tadej
        set_tx_packet((`MEMORY_BASE + (i1 * 200)), 100, 0);
4339
        set_tx_bd(i1, i1, 100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + (i1 * 200)));
4340 169 mohor
      end
4341 194 tadej
      set_tx_bd_wrap(i);
4342
      fork
4343
        begin
4344
          set_tx_bd_ready(0, i);
4345
          repeat(20) @(negedge mtx_clk);
4346
          #1 disable check_tx_en100;
4347
        end
4348
        begin: check_tx_en100
4349
          wait (MTxEn === 1'b1);
4350
          test_fail("Tramsmit should not start at all");
4351
          fail = fail + 1;
4352
          `TIME; $display("*E Transmit of %d packets should not start at all - active MTxEn", i);
4353
        end
4354
      join
4355
      for (i2 = 0; i2 < 20; i2 = i2 + 1)
4356 169 mohor
      begin
4357 194 tadej
        check_tx_bd(0, tmp);
4358
        #1;
4359
        if (tmp[15] === 1'b0)
4360
        begin
4361
          test_fail("Tramsmit should not start at all");
4362
          fail = fail + 1;
4363
          `TIME; $display("*E Transmit of %d packets should not start at all - ready is 0", i);
4364
        end
4365
        if (tmp[8:0] !== 0)
4366
        begin
4367
          test_fail("Tramsmit should not be finished since it should not start at all");
4368
          fail = fail + 1;
4369
          `TIME; $display("*E Transmit of should not be finished since it should not start at all");
4370
        end
4371
        @(posedge wb_clk);
4372 169 mohor
      end
4373 274 tadejm
      wait (wbm_working == 0);
4374 194 tadej
      wbm_read(`ETH_INT, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4375
      if (tmp[6:0] !== 0)
4376 169 mohor
      begin
4377 194 tadej
        test_fail("Tramsmit should not get INT since it should not start at all");
4378 169 mohor
        fail = fail + 1;
4379 194 tadej
        `TIME; $display("*E Transmit of should not get INT since it should not start at all");
4380 169 mohor
      end
4381 194 tadej
      clear_tx_bd(0, i);
4382
      if ((i < 5) || (i > 124))
4383
        i = i + 1;
4384
      else
4385
        i = i + 120;
4386 169 mohor
    end
4387 194 tadej
    // disable TX
4388 274 tadejm
    wait (wbm_working == 0);
4389 194 tadej
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4390
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4391
    if(fail == 0)
4392
      test_ok;
4393 169 mohor
    else
4394 194 tadej
      fail = 0;
4395 169 mohor
  end
4396
 
4397
 
4398 194 tadej
  ////////////////////////////////////////////////////////////////////
4399
  ////                                                            ////
4400
  ////  Test transmit packets form MINFL to MAXFL sizes at        ////
4401
  ////  one TX buffer decriptor ( 10Mbps ).                       ////
4402
  ////                                                            ////
4403
  ////////////////////////////////////////////////////////////////////
4404 209 tadejm
  if (test_num == 2) // without and with padding
4405 169 mohor
  begin
4406 194 tadej
    // TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )
4407
    test_name = "TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )";
4408
    `TIME; $display("  TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )");
4409
 
4410
    max_tmp = 0;
4411
    min_tmp = 0;
4412
    // set one TX buffer descriptor - must be set before TX enable
4413 274 tadejm
    wait (wbm_working == 0);
4414 194 tadej
    wbm_write(`ETH_TX_BD_NUM, 32'h1, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4415 209 tadejm
    // enable TX, set full-duplex mode, NO padding and CRC appending
4416 274 tadejm
    wait (wbm_working == 0);
4417 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
4418 194 tadej
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4419
    // prepare two packets of MAXFL length
4420 274 tadejm
    wait (wbm_working == 0);
4421 194 tadej
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4422
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
4423
    min_tmp = tmp[31:16];
4424 209 tadejm
    st_data = 8'h01;
4425
    set_tx_packet(`MEMORY_BASE, (max_tmp), st_data); // length without CRC
4426 194 tadej
    st_data = 8'h10;
4427 209 tadejm
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp), st_data); // length without CRC
4428 194 tadej
    // check WB INT signal
4429
    if (wb_int !== 1'b0)
4430 169 mohor
    begin
4431 194 tadej
      test_fail("WB INT signal should not be set");
4432
      fail = fail + 1;
4433 169 mohor
    end
4434 194 tadej
 
4435
    // write to phy's control register for 10Mbps
4436
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
4437
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
4438
    speed = 10;
4439
 
4440
    i_length = (min_tmp - 4);
4441
    while (i_length <= (max_tmp - 4))
4442 169 mohor
    begin
4443 194 tadej
      // choose generating carrier sense and collision for first and last 64 lengths of frames
4444
      case (i_length[1:0])
4445
      2'h0: // Interrupt is generated
4446 169 mohor
      begin
4447 194 tadej
        // enable interrupt generation
4448 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
4449 194 tadej
        // unmask interrupts
4450 274 tadejm
        wait (wbm_working == 0);
4451 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
4452 194 tadej
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4453
        // not detect carrier sense in FD and no collision
4454
        eth_phy.carrier_sense_tx_fd_detect(0);
4455
        eth_phy.collision(0);
4456 169 mohor
      end
4457 194 tadej
      2'h1: // Interrupt is not generated
4458 169 mohor
      begin
4459 194 tadej
        // enable interrupt generation
4460 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
4461 194 tadej
        // mask interrupts
4462 274 tadejm
        wait (wbm_working == 0);
4463 194 tadej
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4464
        // detect carrier sense in FD and no collision
4465
        eth_phy.carrier_sense_tx_fd_detect(1);
4466
        eth_phy.collision(0);
4467 169 mohor
      end
4468 194 tadej
      2'h2: // Interrupt is not generated
4469
      begin
4470
        // disable interrupt generation
4471 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
4472 194 tadej
        // unmask interrupts
4473 274 tadejm
        wait (wbm_working == 0);
4474 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
4475 194 tadej
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4476
        // not detect carrier sense in FD and set collision
4477
        eth_phy.carrier_sense_tx_fd_detect(0);
4478
        eth_phy.collision(1);
4479
      end
4480
      default: // 2'h3: // Interrupt is not generated
4481
      begin
4482
        // disable interrupt generation
4483 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
4484 194 tadej
        // mask interrupts
4485 274 tadejm
        wait (wbm_working == 0);
4486 194 tadej
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4487
        // detect carrier sense in FD and set collision
4488
        eth_phy.carrier_sense_tx_fd_detect(1);
4489
        eth_phy.collision(1);
4490
      end
4491
      endcase
4492
      eth_phy.set_tx_mem_addr(max_tmp);
4493
      // set wrap bit
4494
      set_tx_bd_wrap(0);
4495
      set_tx_bd_ready(0, 0);
4496 169 mohor
      #1 check_tx_bd(0, data);
4497 274 tadejm
 
4498
 
4499 194 tadej
      if (i_length < min_tmp) // just first four
4500 169 mohor
      begin
4501 194 tadej
        while (data[15] === 1)
4502
        begin
4503
          #1 check_tx_bd(0, data);
4504
          @(posedge wb_clk);
4505
        end
4506 209 tadejm
        repeat (1) @(posedge wb_clk);
4507 169 mohor
      end
4508 194 tadej
      else if (i_length > (max_tmp - 8)) // just last four
4509 192 tadej
      begin
4510 194 tadej
        tmp = 0;
4511
        wait (MTxEn === 1'b1); // start transmit
4512
        while (tmp < (i_length - 20))
4513
        begin
4514
          #1 tmp = tmp + 1;
4515
          @(posedge wb_clk);
4516
        end
4517
        #1 check_tx_bd(0, data);
4518
        while (data[15] === 1)
4519
        begin
4520
          #1 check_tx_bd(0, data);
4521
          @(posedge wb_clk);
4522
        end
4523 209 tadejm
        repeat (1) @(posedge wb_clk);
4524 192 tadej
      end
4525
      else
4526
      begin
4527 194 tadej
        wait (MTxEn === 1'b1); // start transmit
4528
        #1 check_tx_bd(0, data);
4529
        if (data[15] !== 1)
4530
        begin
4531
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
4532
          fail = fail + 1;
4533
        end
4534
        wait (MTxEn === 1'b0); // end transmit
4535
        while (data[15] === 1)
4536
        begin
4537
          #1 check_tx_bd(0, data);
4538
          @(posedge wb_clk);
4539
        end
4540
        repeat (1) @(posedge wb_clk);
4541 192 tadej
      end
4542 274 tadejm
 
4543 279 mohor
      repeat(5) @(posedge mtx_clk);  // Wait some time so PHY stores the CRC
4544 274 tadejm
 
4545 194 tadej
      // check length of a PACKET
4546
      if (eth_phy.tx_len != (i_length + 4))
4547 192 tadej
      begin
4548 194 tadej
        test_fail("Wrong length of the packet out from MAC");
4549 192 tadej
        fail = fail + 1;
4550
      end
4551 194 tadej
      // checking in the following if statement is performed only for first and last 64 lengths
4552
      if ( ((i_length + 4) <= (min_tmp + 64)) || ((i_length + 4) > (max_tmp - 64)) )
4553 192 tadej
      begin
4554 194 tadej
        // check transmitted TX packet data
4555
        if (i_length[0] == 0)
4556
        begin
4557 209 tadejm
          check_tx_packet((`MEMORY_BASE + i_length[1:0]), max_tmp, i_length, tmp);
4558 194 tadej
        end
4559
        else
4560
        begin
4561 209 tadejm
          check_tx_packet(((`MEMORY_BASE + i_length[1:0]) + max_tmp), max_tmp, i_length, tmp);
4562 194 tadej
        end
4563
        if (tmp > 0)
4564
        begin
4565
          test_fail("Wrong data of the transmitted packet");
4566
          fail = fail + 1;
4567
        end
4568
        // check transmited TX packet CRC
4569
        check_tx_crc(max_tmp, i_length, 1'b0, tmp); // length without CRC
4570 274 tadejm
 
4571 194 tadej
        if (tmp > 0)
4572
        begin
4573
          test_fail("Wrong CRC of the transmitted packet");
4574
          fail = fail + 1;
4575
        end
4576 192 tadej
      end
4577 194 tadej
      // check WB INT signal
4578
      if (i_length[1:0] == 2'h0)
4579 192 tadej
      begin
4580 194 tadej
        if (wb_int !== 1'b1)
4581
        begin
4582
          `TIME; $display("*E WB INT signal should be set");
4583
          test_fail("WB INT signal should be set");
4584
          fail = fail + 1;
4585
        end
4586 192 tadej
      end
4587 194 tadej
      else
4588 192 tadej
      begin
4589 194 tadej
        if (wb_int !== 1'b0)
4590
        begin
4591
          `TIME; $display("*E WB INT signal should not be set");
4592
          test_fail("WB INT signal should not be set");
4593
          fail = fail + 1;
4594
        end
4595 192 tadej
      end
4596 194 tadej
      // check TX buffer descriptor of a packet
4597
      check_tx_bd(0, data);
4598
      if (i_length[1] == 1'b0) // interrupt enabled
4599 192 tadej
      begin
4600 194 tadej
        if (data[15:0] !== 16'h7800)
4601
        begin
4602
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
4603
          test_fail("TX buffer descriptor status is not correct");
4604
          fail = fail + 1;
4605
        end
4606 192 tadej
      end
4607 194 tadej
      else // interrupt not enabled
4608 192 tadej
      begin
4609 194 tadej
        if (data[15:0] !== 16'h3800)
4610
        begin
4611
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
4612
          test_fail("TX buffer descriptor status is not correct");
4613
          fail = fail + 1;
4614
        end
4615 192 tadej
      end
4616 194 tadej
      // clear TX buffer descriptor
4617
      clear_tx_bd(0, 0);
4618
      // check interrupts
4619 274 tadejm
      wait (wbm_working == 0);
4620 194 tadej
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4621
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
4622 192 tadej
      begin
4623 194 tadej
        if ((data & `ETH_INT_TXB) !== 1'b1)
4624
        begin
4625
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
4626
          test_fail("Interrupt Transmit Buffer was not set");
4627
          fail = fail + 1;
4628
        end
4629
        if ((data & (~`ETH_INT_TXB)) !== 0)
4630
        begin
4631
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
4632
          test_fail("Other interrupts (except Transmit Buffer) were set");
4633
          fail = fail + 1;
4634
        end
4635 192 tadej
      end
4636 194 tadej
      else
4637 192 tadej
      begin
4638 194 tadej
        if (data !== 0)
4639
        begin
4640
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
4641
          test_fail("Any of interrupts (except Transmit Buffer) was set");
4642
          fail = fail + 1;
4643
        end
4644 192 tadej
      end
4645 194 tadej
      // clear interrupts
4646 274 tadejm
      wait (wbm_working == 0);
4647 194 tadej
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4648
      // check WB INT signal
4649
      if (wb_int !== 1'b0)
4650 192 tadej
      begin
4651 194 tadej
        test_fail("WB INT signal should not be set");
4652 192 tadej
        fail = fail + 1;
4653
      end
4654 194 tadej
      // INTERMEDIATE DISPLAYS
4655
      if ((i_length + 4) == (min_tmp + 64))
4656 209 tadejm
      begin
4657 194 tadej
        // starting length is min_tmp, ending length is (min_tmp + 64)
4658 209 tadejm
        $display("    pads appending to packets is NOT selected");
4659
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
4660 194 tadej
                 min_tmp, (min_tmp + 64));
4661 209 tadejm
        // set padding, remain the rest
4662 274 tadejm
        wait (wbm_working == 0);
4663 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4664
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4665
      end
4666 194 tadej
      else if ((i_length + 4) == (max_tmp - 16))
4667 209 tadejm
      begin
4668 194 tadej
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
4669 209 tadejm
        $display("    pads appending to packets is selected");
4670
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
4671 194 tadej
                 (min_tmp + 64 + 128), tmp_data);
4672 209 tadejm
        // reset padding, remain the rest
4673 274 tadejm
        wait (wbm_working == 0);
4674 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
4675
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4676
      end
4677 194 tadej
      else if ((i_length + 4) == max_tmp)
4678 209 tadejm
      begin
4679
        $display("    pads appending to packets is NOT selected");
4680
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
4681 194 tadej
                 (max_tmp - (4 + 16)), max_tmp);
4682 209 tadejm
      end
4683 194 tadej
      // set length (loop variable)
4684
      if ((i_length + 4) < (min_tmp + 64))
4685
        i_length = i_length + 1;
4686
      else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
4687
      begin
4688
        i_length = i_length + 128;
4689
        tmp_data = i_length + 4; // last tmp_data is ending length
4690
      end
4691
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
4692
        i_length = max_tmp - (4 + 16);
4693
      else if ((i_length + 4) >= (max_tmp - 16))
4694
        i_length = i_length + 1;
4695
      else
4696
      begin
4697
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
4698
        #10 $stop;
4699
      end
4700 192 tadej
    end
4701 194 tadej
    // disable TX
4702 274 tadejm
    wait (wbm_working == 0);
4703 194 tadej
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4704
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4705
    if(fail == 0)
4706
      test_ok;
4707
    else
4708
      fail = 0;
4709
  end
4710
 
4711
 
4712
  ////////////////////////////////////////////////////////////////////
4713
  ////                                                            ////
4714
  ////  Test transmit packets form MINFL to MAXFL sizes at        ////
4715
  ////  one TX buffer decriptor ( 100Mbps ).                      ////
4716
  ////                                                            ////
4717
  ////////////////////////////////////////////////////////////////////
4718 209 tadejm
  if (test_num == 3) // with and without padding
4719 194 tadej
  begin
4720
    // TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )
4721
    test_name = "TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )";
4722
    `TIME; $display("  TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )");
4723
 
4724
    max_tmp = 0;
4725
    min_tmp = 0;
4726
    // set one TX buffer descriptor - must be set before TX enable
4727 274 tadejm
    wait (wbm_working == 0);
4728 194 tadej
    wbm_write(`ETH_TX_BD_NUM, 32'h1, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4729 209 tadejm
    // enable TX, set full-duplex mode, NO padding and CRC appending
4730 274 tadejm
    wait (wbm_working == 0);
4731 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
4732 194 tadej
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4733
    // prepare two packets of MAXFL length
4734 274 tadejm
    wait (wbm_working == 0);
4735 194 tadej
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4736
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
4737
    min_tmp = tmp[31:16];
4738
    st_data = 8'h5A;
4739 209 tadejm
    set_tx_packet(`MEMORY_BASE, (max_tmp), st_data); // length without CRC
4740 194 tadej
    st_data = 8'h10;
4741 209 tadejm
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp), st_data); // length without CRC
4742 169 mohor
    // check WB INT signal
4743 192 tadej
    if (wb_int !== 1'b0)
4744 169 mohor
    begin
4745
      test_fail("WB INT signal should not be set");
4746
      fail = fail + 1;
4747
    end
4748 194 tadej
 
4749
    // write to phy's control register for 100Mbps
4750
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
4751
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
4752
    speed = 100;
4753 192 tadej
 
4754 194 tadej
    i_length = (min_tmp - 4);
4755
    while (i_length <= (max_tmp - 4))
4756 192 tadej
    begin
4757 194 tadej
      // choose generating carrier sense and collision
4758
      case (i_length[1:0])
4759
      2'h0: // Interrupt is generated
4760 192 tadej
      begin
4761 194 tadej
        // enable interrupt generation
4762 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
4763 194 tadej
        // unmask interrupts
4764 274 tadejm
        wait (wbm_working == 0);
4765 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
4766 194 tadej
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4767
        // not detect carrier sense in FD and no collision
4768
        eth_phy.carrier_sense_tx_fd_detect(0);
4769
        eth_phy.collision(0);
4770 192 tadej
      end
4771 194 tadej
      2'h1: // Interrupt is not generated
4772 192 tadej
      begin
4773 194 tadej
        // enable interrupt generation
4774 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
4775 194 tadej
        // mask interrupts
4776 274 tadejm
        wait (wbm_working == 0);
4777 194 tadej
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4778
        // detect carrier sense in FD and no collision
4779
        eth_phy.carrier_sense_tx_fd_detect(1);
4780
        eth_phy.collision(0);
4781 192 tadej
      end
4782 194 tadej
      2'h2: // Interrupt is not generated
4783
      begin
4784
        // disable interrupt generation
4785 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
4786 194 tadej
        // unmask interrupts
4787 274 tadejm
        wait (wbm_working == 0);
4788 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
4789 194 tadej
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4790
        // not detect carrier sense in FD and set collision
4791
        eth_phy.carrier_sense_tx_fd_detect(0);
4792
        eth_phy.collision(1);
4793
      end
4794
      default: // 2'h3: // Interrupt is not generated
4795
      begin
4796
        // disable interrupt generation
4797 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
4798 194 tadej
        // mask interrupts
4799 274 tadejm
        wait (wbm_working == 0);
4800 194 tadej
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4801
        // detect carrier sense in FD and set collision
4802
        eth_phy.carrier_sense_tx_fd_detect(1);
4803
        eth_phy.collision(1);
4804
      end
4805
      endcase
4806
      eth_phy.set_tx_mem_addr(max_tmp);
4807
      // set wrap bit
4808
      set_tx_bd_wrap(0);
4809
      set_tx_bd_ready(0, 0);
4810 192 tadej
      #1 check_tx_bd(0, data);
4811 194 tadej
      if (i_length < min_tmp) // just first four
4812 192 tadej
      begin
4813 194 tadej
        while (data[15] === 1)
4814
        begin
4815
          #1 check_tx_bd(0, data);
4816
          @(posedge wb_clk);
4817
        end
4818 209 tadejm
        repeat (1) @(posedge wb_clk);
4819 194 tadej
      end
4820
      else if (i_length > (max_tmp - 8)) // just last four
4821
      begin
4822
        tmp = 0;
4823
        wait (MTxEn === 1'b1); // start transmit
4824
        while (tmp < (i_length - 20))
4825
        begin
4826
          #1 tmp = tmp + 1;
4827
          @(posedge wb_clk);
4828
        end
4829 192 tadej
        #1 check_tx_bd(0, data);
4830 194 tadej
        while (data[15] === 1)
4831
        begin
4832
          #1 check_tx_bd(0, data);
4833
          @(posedge wb_clk);
4834
        end
4835 209 tadejm
        repeat (1) @(posedge wb_clk);
4836 192 tadej
      end
4837 194 tadej
      else
4838
      begin
4839
        wait (MTxEn === 1'b1); // start transmit
4840
        #1 check_tx_bd(0, data);
4841
        if (data[15] !== 1)
4842
        begin
4843
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
4844
          fail = fail + 1;
4845
        end
4846
        wait (MTxEn === 1'b0); // end transmit
4847
        while (data[15] === 1)
4848
        begin
4849
          #1 check_tx_bd(0, data);
4850
          @(posedge wb_clk);
4851
        end
4852
        repeat (1) @(posedge wb_clk);
4853
      end
4854
      // check length of a PACKET
4855
      if (eth_phy.tx_len != (i_length + 4))
4856
      begin
4857
        test_fail("Wrong length of the packet out from MAC");
4858
        fail = fail + 1;
4859
      end
4860 192 tadej
      // check transmitted TX packet data
4861
      if (i_length[0] == 0)
4862
      begin
4863 209 tadejm
        check_tx_packet((`MEMORY_BASE + i_length[1:0]), max_tmp, i_length, tmp);
4864 192 tadej
      end
4865
      else
4866
      begin
4867 209 tadejm
        check_tx_packet(((`MEMORY_BASE + i_length[1:0]) + max_tmp), max_tmp, i_length, tmp);
4868 192 tadej
      end
4869
      if (tmp > 0)
4870
      begin
4871
        test_fail("Wrong data of the transmitted packet");
4872
        fail = fail + 1;
4873
      end
4874
      // check transmited TX packet CRC
4875
      check_tx_crc(max_tmp, i_length, 1'b0, tmp); // length without CRC
4876
      if (tmp > 0)
4877
      begin
4878
        test_fail("Wrong CRC of the transmitted packet");
4879
        fail = fail + 1;
4880
      end
4881 194 tadej
      // check WB INT signal
4882
      if (i_length[1:0] == 2'h0)
4883 192 tadej
      begin
4884 194 tadej
        if (wb_int !== 1'b1)
4885
        begin
4886
          `TIME; $display("*E WB INT signal should be set");
4887
          test_fail("WB INT signal should be set");
4888
          fail = fail + 1;
4889
        end
4890 192 tadej
      end
4891 194 tadej
      else
4892 192 tadej
      begin
4893 194 tadej
        if (wb_int !== 1'b0)
4894
        begin
4895
          `TIME; $display("*E WB INT signal should not be set");
4896
          test_fail("WB INT signal should not be set");
4897
          fail = fail + 1;
4898
        end
4899 192 tadej
      end
4900 194 tadej
      // check TX buffer descriptor of a packet
4901
      check_tx_bd(0, data);
4902
      if (i_length[1] == 1'b0) // interrupt enabled
4903 192 tadej
      begin
4904 194 tadej
        if (data[15:0] !== 16'h7800)
4905
        begin
4906
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
4907
          test_fail("TX buffer descriptor status is not correct");
4908
          fail = fail + 1;
4909
        end
4910 192 tadej
      end
4911 194 tadej
      else // interrupt not enabled
4912 192 tadej
      begin
4913 194 tadej
        if (data[15:0] !== 16'h3800)
4914
        begin
4915
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
4916
          test_fail("TX buffer descriptor status is not correct");
4917
          fail = fail + 1;
4918
        end
4919 192 tadej
      end
4920 194 tadej
      // clear TX buffer descriptor
4921
      clear_tx_bd(0, 0);
4922
      // check interrupts
4923 274 tadejm
      wait (wbm_working == 0);
4924 194 tadej
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4925
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
4926 192 tadej
      begin
4927 194 tadej
        if ((data & `ETH_INT_TXB) !== 1'b1)
4928
        begin
4929
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
4930
          test_fail("Interrupt Transmit Buffer was not set");
4931
          fail = fail + 1;
4932
        end
4933
        if ((data & (~`ETH_INT_TXB)) !== 0)
4934
        begin
4935
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
4936
          test_fail("Other interrupts (except Transmit Buffer) were set");
4937
          fail = fail + 1;
4938
        end
4939 192 tadej
      end
4940 194 tadej
      else
4941 192 tadej
      begin
4942 194 tadej
        if (data !== 0)
4943
        begin
4944
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h", data);
4945
          test_fail("Any of interrupts (except Transmit Buffer) was set");
4946
          fail = fail + 1;
4947
        end
4948 192 tadej
      end
4949 194 tadej
      // clear interrupts
4950 274 tadejm
      wait (wbm_working == 0);
4951 194 tadej
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4952
      // check WB INT signal
4953
      if (wb_int !== 1'b0)
4954 192 tadej
      begin
4955 194 tadej
        test_fail("WB INT signal should not be set");
4956 192 tadej
        fail = fail + 1;
4957
      end
4958 194 tadej
      // INTERMEDIATE DISPLAYS
4959
      if ((i_length + 4) == (min_tmp + 64))
4960 209 tadejm
      begin
4961 194 tadej
        // starting length is min_tmp, ending length is (min_tmp + 64)
4962 209 tadejm
        $display("    pads appending to packets is NOT selected");
4963
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
4964 194 tadej
                 min_tmp, (min_tmp + 64));
4965 209 tadejm
        // set padding, remain the rest
4966 274 tadejm
        wait (wbm_working == 0);
4967 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4968
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4969
      end
4970 194 tadej
      else if ((i_length + 4) == (max_tmp - 16))
4971 209 tadejm
      begin
4972 194 tadej
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
4973 209 tadejm
        $display("    pads appending to packets is selected");
4974
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
4975 194 tadej
                 (min_tmp + 64 + 128), tmp_data);
4976 209 tadejm
        // reset padding, remain the rest
4977 274 tadejm
        wait (wbm_working == 0);
4978 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
4979
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4980
      end
4981 194 tadej
      else if ((i_length + 4) == max_tmp)
4982 209 tadejm
      begin
4983
        $display("    pads appending to packets is NOT selected");
4984
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
4985 194 tadej
                 (max_tmp - (4 + 16)), max_tmp);
4986 209 tadejm
      end
4987 194 tadej
      // set length (loop variable)
4988
      if ((i_length + 4) < (min_tmp + 64))
4989
        i_length = i_length + 1;
4990
      else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
4991
      begin
4992
        i_length = i_length + 128;
4993
        tmp_data = i_length + 4; // last tmp_data is ending length
4994
      end
4995
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
4996
        i_length = max_tmp - (4 + 16);
4997
      else if ((i_length + 4) >= (max_tmp - 16))
4998
        i_length = i_length + 1;
4999 192 tadej
      else
5000 194 tadej
      begin
5001
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
5002
        #10 $stop;
5003
      end
5004 179 mohor
    end
5005 194 tadej
    // disable TX
5006 274 tadejm
    wait (wbm_working == 0);
5007 194 tadej
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
5008
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5009
    if(fail == 0)
5010
      test_ok;
5011
    else
5012
      fail = 0;
5013 169 mohor
  end
5014
 
5015
 
5016 209 tadejm
  ////////////////////////////////////////////////////////////////////
5017
  ////                                                            ////
5018
  ////  Test transmit packets form MINFL to MAXFL sizes at        ////
5019
  ////  maximum TX buffer decriptors ( 10Mbps ).                  ////
5020
  ////                                                            ////
5021
  ////////////////////////////////////////////////////////////////////
5022
  if (test_num == 4) // without and with padding
5023
  begin
5024
    // TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps )
5025
    test_name = "TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps )";
5026
    `TIME; $display("  TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps )");
5027
 
5028
    // reset MAC registers
5029
    hard_reset;
5030
    // reset MAC and MII LOGIC with soft reset
5031 274 tadejm
//    reset_mac;
5032
//    reset_mii;
5033 209 tadejm
    // set wb slave response
5034
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
5035 192 tadej
 
5036 209 tadejm
    max_tmp = 0;
5037
    min_tmp = 0;
5038
    num_of_frames = 0;
5039
    num_of_bd = 0;
5040
    // set maximum TX buffer descriptors (128) - must be set before TX enable
5041 274 tadejm
    wait (wbm_working == 0);
5042 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5043
    // enable TX, set full-duplex mode, NO padding and CRC appending
5044 274 tadejm
    wait (wbm_working == 0);
5045 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
5046
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5047
    // prepare two packets of MAXFL length
5048 274 tadejm
    wait (wbm_working == 0);
5049 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5050
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
5051
    min_tmp = tmp[31:16];
5052
    st_data = 8'hA3;
5053
    set_tx_packet(`MEMORY_BASE, (max_tmp), st_data); // length without CRC
5054
    st_data = 8'h81;
5055
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp), st_data); // length without CRC
5056
    // check WB INT signal
5057
    if (wb_int !== 1'b0)
5058
    begin
5059
      test_fail("WB INT signal should not be set");
5060
      fail = fail + 1;
5061
    end
5062
 
5063
    // write to phy's control register for 10Mbps
5064
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
5065
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
5066
    speed = 10;
5067
 
5068
    i_length = (min_tmp - 4);
5069
    while (i_length <= (max_tmp - 4))
5070
    begin
5071
      // choose generating carrier sense and collision
5072
      case (i_length[1:0])
5073
      2'h0: // Interrupt is generated
5074
      begin
5075
        // Reset_tx_bd nable interrupt generation
5076
        // unmask interrupts
5077 274 tadejm
        wait (wbm_working == 0);
5078 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
5079
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5080
        // not detect carrier sense in FD and no collision
5081
        eth_phy.carrier_sense_tx_fd_detect(0);
5082
        eth_phy.collision(0);
5083
      end
5084
      2'h1: // Interrupt is not generated
5085
      begin
5086
        // set_tx_bd enable interrupt generation
5087
        // mask interrupts
5088 274 tadejm
        wait (wbm_working == 0);
5089 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5090
        // detect carrier sense in FD and no collision
5091
        eth_phy.carrier_sense_tx_fd_detect(1);
5092
        eth_phy.collision(0);
5093
      end
5094
      2'h2: // Interrupt is not generated
5095
      begin
5096
        // set_tx_bd disable the interrupt generation
5097
        // unmask interrupts
5098 274 tadejm
        wait (wbm_working == 0);
5099 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
5100
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5101
        // not detect carrier sense in FD and set collision
5102
        eth_phy.carrier_sense_tx_fd_detect(0);
5103
        eth_phy.collision(1);
5104
      end
5105
      default: // 2'h3: // Interrupt is not generated
5106
      begin
5107
        // set_tx_bd disable the interrupt generation
5108
        // mask interrupts
5109 274 tadejm
        wait (wbm_working == 0);
5110 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5111
        // detect carrier sense in FD and set collision
5112
        eth_phy.carrier_sense_tx_fd_detect(1);
5113
        eth_phy.collision(1);
5114
      end
5115
      endcase
5116
      // first destination address on ethernet PHY
5117
      if (i_length[0] == 0)
5118
        eth_phy.set_tx_mem_addr(0);
5119
      else
5120
        eth_phy.set_tx_mem_addr(max_tmp);
5121
      // first 8 frames are transmitted with TX BD 0 (wrap bit on TX BD 0)
5122
      // number of all frames is 154 (146 without first 8)
5123
      if (num_of_frames < 8)
5124
      begin
5125
        case (i_length[1:0])
5126
        2'h0: // Interrupt is generated
5127
        begin
5128
          // enable interrupt generation
5129
          set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
5130
          // interrupts are unmasked
5131
        end
5132
        2'h1: // Interrupt is not generated
5133
        begin
5134
          // enable interrupt generation
5135
          set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
5136
          // interrupts are masked
5137
        end
5138
        2'h2: // Interrupt is not generated
5139
        begin
5140
          // disable interrupt generation
5141
          set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
5142
          // interrupts are unmasked
5143
        end
5144
        default: // 2'h3: // Interrupt is not generated
5145
        begin
5146
          // disable interrupt generation
5147
          set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
5148
          // interrupts are masked
5149
        end
5150
        endcase
5151
        // set wrap bit
5152
        set_tx_bd_wrap(0);
5153
      end
5154
      // after first 8 number of frames, 128 frames form TX BD 0 to 127 will be transmitted
5155
      else if ((num_of_frames - 8) == 0)
5156
      begin
5157
        tmp_len = i_length; // length of frame
5158
        tmp_bd_num = 0; // TX BD number
5159
        while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
5160
        begin
5161
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
5162
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
5163
          if (tmp_len[0] == 0)
5164
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
5165
          else
5166
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
5167
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
5168
          if ((tmp_len + 4) < (min_tmp + 128))
5169
            tmp_len = tmp_len + 1;
5170
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5171
            tmp_len = 256;
5172
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5173
            tmp_len = tmp_len + 128;
5174
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
5175
            tmp_len = max_tmp - (4 + 16);
5176
          else if ((tmp_len + 4) >= (max_tmp - 16))
5177
            tmp_len = tmp_len + 1;
5178
          // set TX BD number
5179
          tmp_bd_num = tmp_bd_num + 1;
5180
        end
5181
        // set wrap bit
5182
        set_tx_bd_wrap(127);
5183
      end
5184
      // after 128 + first 8 number of frames, 19 frames form TX BD 0 to 18 will be transmitted
5185
      else if ((num_of_frames - 8) == 20) // 128
5186
      begin
5187
        tmp_len = tmp_len; // length of frame remaines from previous settings
5188
        tmp_bd_num = 0; // TX BD number
5189
        while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
5190
        begin
5191
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
5192
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
5193
          if (tmp_len[0] == 0)
5194
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
5195
          else
5196
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
5197
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
5198
          if ((tmp_len + 4) < (min_tmp + 128))
5199
            tmp_len = tmp_len + 1;
5200
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5201
            tmp_len = 256;
5202
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5203
            tmp_len = tmp_len + 128;
5204
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
5205
            tmp_len = max_tmp - (4 + 16);
5206
          else if ((tmp_len + 4) >= (max_tmp - 16))
5207
            tmp_len = tmp_len + 1;
5208
          // set TX BD number
5209
          tmp_bd_num = tmp_bd_num + 1;
5210
        end
5211
      end
5212
      // set ready bit
5213
      if (num_of_frames < 8)
5214
        set_tx_bd_ready(0, 0);
5215
      else if ((num_of_frames - 8) < 128)
5216
        set_tx_bd_ready((num_of_frames - 8), (num_of_frames - 8));
5217
      else if ((num_of_frames - 136) < 19)
5218
        set_tx_bd_ready((num_of_frames - 136), (num_of_frames - 136));
5219
      // CHECK END OF TRANSMITION
5220
      #1 check_tx_bd(num_of_bd, data);
5221
      if (i_length < min_tmp) // just first four
5222
      begin
5223
        while (data[15] === 1)
5224
        begin
5225
          #1 check_tx_bd(num_of_bd, data);
5226
          @(posedge wb_clk);
5227
        end
5228
        repeat (1) @(posedge wb_clk);
5229
      end
5230
      else if (i_length > (max_tmp - 8)) // just last four
5231
      begin
5232
        tmp = 0;
5233
        wait (MTxEn === 1'b1); // start transmit
5234
        while (tmp < (i_length - 20))
5235
        begin
5236
          #1 tmp = tmp + 1;
5237
          @(posedge wb_clk);
5238
        end
5239
        #1 check_tx_bd(num_of_bd, data);
5240
        while (data[15] === 1)
5241
        begin
5242
          #1 check_tx_bd(num_of_bd, data);
5243
          @(posedge wb_clk);
5244
        end
5245
        repeat (1) @(posedge wb_clk);
5246
      end
5247
      else
5248
      begin
5249
        wait (MTxEn === 1'b1); // start transmit
5250
        #1 check_tx_bd(num_of_bd, data);
5251
        if (data[15] !== 1)
5252
        begin
5253
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
5254
          fail = fail + 1;
5255
        end
5256
        wait (MTxEn === 1'b0); // end transmit
5257
        while (data[15] === 1)
5258
        begin
5259
          #1 check_tx_bd(num_of_bd, data);
5260
          @(posedge wb_clk);
5261
        end
5262
        repeat (1) @(posedge wb_clk);
5263
      end
5264
      // check length of a PACKET
5265
      if (eth_phy.tx_len != (i_length + 4))
5266
      begin
5267
        test_fail("Wrong length of the packet out from MAC");
5268
        fail = fail + 1;
5269
      end
5270
        // check transmitted TX packet data
5271
        if (i_length[0] == 0)
5272
        begin
5273
          check_tx_packet((`MEMORY_BASE + i_length[1:0]), 0, i_length, tmp);
5274
        end
5275
        else
5276
        begin
5277
          check_tx_packet(((`MEMORY_BASE + i_length[1:0]) + max_tmp), max_tmp, i_length, tmp);
5278
        end
5279
        if (tmp > 0)
5280
        begin
5281
          test_fail("Wrong data of the transmitted packet");
5282
          fail = fail + 1;
5283
        end
5284
        // check transmited TX packet CRC
5285
        if (i_length[0] == 0)
5286
          check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
5287
        else
5288
          check_tx_crc(max_tmp, i_length, 1'b0, tmp); // length without CRC
5289
        if (tmp > 0)
5290
        begin
5291
          test_fail("Wrong CRC of the transmitted packet");
5292
          fail = fail + 1;
5293
        end
5294
      // check WB INT signal
5295
      if (i_length[1:0] == 2'h0)
5296
      begin
5297
        if (wb_int !== 1'b1)
5298
        begin
5299
          `TIME; $display("*E WB INT signal should be set");
5300
          test_fail("WB INT signal should be set");
5301
          fail = fail + 1;
5302
        end
5303
      end
5304
      else
5305
      begin
5306
        if (wb_int !== 1'b0)
5307
        begin
5308
          `TIME; $display("*E WB INT signal should not be set");
5309
          test_fail("WB INT signal should not be set");
5310
          fail = fail + 1;
5311
        end
5312
      end
5313
      // check TX buffer descriptor of a packet
5314
      check_tx_bd(num_of_bd, data);
5315
      if (i_length[1] == 1'b0) // interrupt enabled
5316
      begin
5317
        if ( ((data[15:0] !== 16'h7800) && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
5318
             ((data[15:0] !== 16'h5800) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
5319
        begin
5320
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
5321
          test_fail("TX buffer descriptor status is not correct");
5322
          fail = fail + 1;
5323
        end
5324
      end
5325
      else // interrupt not enabled
5326
      begin
5327
        if ( ((data[15:0] !== 16'h3800)  && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
5328
             ((data[15:0] !== 16'h1800) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
5329
        begin
5330
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
5331
          test_fail("TX buffer descriptor status is not correct");
5332
          fail = fail + 1;
5333
        end
5334
      end
5335
      // clear first half of 8 frames from TX buffer descriptor 0
5336
      if (num_of_frames < 4)
5337
        clear_tx_bd(num_of_bd, num_of_bd);
5338
      // clear BD with wrap bit
5339
      if (num_of_frames == 140)
5340
        clear_tx_bd(127, 127);
5341
      // check interrupts
5342 274 tadejm
      wait (wbm_working == 0);
5343 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5344
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
5345
      begin
5346
        if ((data & `ETH_INT_TXB) !== 1'b1)
5347
        begin
5348
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
5349
          test_fail("Interrupt Transmit Buffer was not set");
5350
          fail = fail + 1;
5351
        end
5352
        if ((data & (~`ETH_INT_TXB)) !== 0)
5353
        begin
5354
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
5355
          test_fail("Other interrupts (except Transmit Buffer) were set");
5356
          fail = fail + 1;
5357
        end
5358
      end
5359
      else
5360
      begin
5361
        if (data !== 0)
5362
        begin
5363
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
5364
          test_fail("Any of interrupts (except Transmit Buffer) was set");
5365
          fail = fail + 1;
5366
        end
5367
      end
5368
      // clear interrupts
5369 274 tadejm
      wait (wbm_working == 0);
5370 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5371
      // check WB INT signal
5372
      if (wb_int !== 1'b0)
5373
      begin
5374
        test_fail("WB INT signal should not be set");
5375
        fail = fail + 1;
5376
      end
5377
      // INTERMEDIATE DISPLAYS
5378
      if ((i_length + 4) == (min_tmp + 7))
5379
      begin
5380
        // starting length is min_tmp, ending length is (min_tmp + 128)
5381
        $display("    pads appending to packets is NOT selected");
5382
        $display("    using only TX BD 0 out of 128 BDs assigned to TX (wrap at first BD - TX BD 0)");
5383
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
5384
                 min_tmp, (min_tmp + 7));
5385
        $display("    ->all packets were send from TX BD 0");
5386
        // set padding, remain the rest
5387 274 tadejm
        wait (wbm_working == 0);
5388 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
5389
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5390
      end
5391
      else if ((i_length + 4) == (min_tmp + 128))
5392
      begin
5393
        // starting length is min_tmp, ending length is (min_tmp + 128)
5394
        $display("    pads appending to packets is NOT selected");
5395
        $display("    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)");
5396
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
5397
                 (min_tmp + 8), (min_tmp + 128));
5398
        $display("    ->packets were send from TX BD %0d to TX BD %0d respectively",
5399
                 1'b0, num_of_bd);
5400
        tmp_bd = num_of_bd + 1;
5401
        // set padding, remain the rest
5402 274 tadejm
        wait (wbm_working == 0);
5403 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
5404
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5405
      end
5406
      else if ((i_length + 4) == (max_tmp - 16))
5407
      begin
5408
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
5409
        $display("    pads appending to packets is selected");
5410
        $display("    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)");
5411
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
5412
                 (min_tmp + 64 + 128), tmp_data);
5413
        if (tmp_bd > num_of_bd)
5414
          $display("    ->packets were send from TX BD %0d to TX BD 127 and from TX BD 0 to TX BD %0d respectively",
5415
                   tmp_bd, num_of_bd);
5416
        else
5417
          $display("    ->packets were send from TX BD %0d to TX BD %0d respectively",
5418
                   tmp_bd, num_of_bd);
5419
        tmp_bd = num_of_bd + 1;
5420
        // reset padding, remain the rest
5421 274 tadejm
        wait (wbm_working == 0);
5422 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
5423
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5424
      end
5425
      else if ((i_length + 4) == max_tmp)
5426
      begin
5427
        $display("    pads appending to packets is NOT selected");
5428
        $display("    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)");
5429
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
5430
                 (max_tmp - (4 + 16)), max_tmp);
5431
        if (tmp_bd > num_of_bd)
5432
          $display("    ->packets were send from TX BD %0d to TX BD 127 and from TX BD 0 to TX BD %0d respectively",
5433
                   tmp_bd, num_of_bd);
5434
        else
5435
          $display("    ->packets were send from TX BD %0d to TX BD %0d respectively",
5436
                   tmp_bd, num_of_bd);
5437
      end
5438
      // set length (loop variable)
5439
      if ((i_length + 4) < (min_tmp + 128))
5440
        i_length = i_length + 1;
5441
      else if ( ((i_length + 4) == (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
5442
        i_length = 256;
5443
      else if ( ((i_length + 4) > (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
5444
      begin
5445
        i_length = i_length + 128;
5446
        tmp_data = i_length + 4; // last tmp_data is ending length
5447
      end
5448
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
5449
        i_length = max_tmp - (4 + 16);
5450
      else if ((i_length + 4) >= (max_tmp - 16))
5451
        i_length = i_length + 1;
5452
      else
5453
      begin
5454
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
5455
        #10 $stop;
5456
      end
5457
      // the number of frame transmitted
5458
      num_of_frames = num_of_frames + 1;
5459
      if ((num_of_frames <= 8) || ((num_of_frames - 8) == 128))
5460
        num_of_bd = 0;
5461
      else
5462
        num_of_bd = num_of_bd + 1;
5463
    end
5464
    // disable TX
5465 274 tadejm
    wait (wbm_working == 0);
5466 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
5467
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5468
    @(posedge wb_clk);
5469
    if(fail == 0)
5470
      test_ok;
5471
    else
5472
      fail = 0;
5473
  end
5474
 
5475
 
5476
  ////////////////////////////////////////////////////////////////////
5477
  ////                                                            ////
5478
  ////  Test transmit packets form MINFL to MAXFL sizes at        ////
5479
  ////  maximum TX buffer decriptors ( 100Mbps ).                 ////
5480
  ////                                                            ////
5481
  ////////////////////////////////////////////////////////////////////
5482
  if (test_num == 5) // with and without padding
5483
  begin
5484
    // TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps )
5485
    test_name = "TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps )";
5486
    `TIME; $display("  TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps )");
5487
 
5488
    // reset MAC registers
5489
    hard_reset;
5490
    // reset MAC and MII LOGIC with soft reset
5491 274 tadejm
//    reset_mac;
5492
//    reset_mii;
5493 209 tadejm
    // set wb slave response
5494
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
5495
 
5496
    max_tmp = 0;
5497
    min_tmp = 0;
5498
    num_of_frames = 0;
5499
    num_of_bd = 0;
5500
    // set maximum TX buffer descriptors (128) - must be set before TX enable
5501 274 tadejm
    wait (wbm_working == 0);
5502 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5503
    // enable TX, set full-duplex mode, NO padding and CRC appending
5504 274 tadejm
    wait (wbm_working == 0);
5505 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
5506
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5507
    // prepare two packets of MAXFL length
5508 274 tadejm
    wait (wbm_working == 0);
5509 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5510
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
5511
    min_tmp = tmp[31:16];
5512
    st_data = 8'hA5;
5513
    set_tx_packet(`MEMORY_BASE, (max_tmp), st_data); // length without CRC
5514
    st_data = 8'h71;
5515
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp), st_data); // length without CRC
5516
    // check WB INT signal
5517
    if (wb_int !== 1'b0)
5518
    begin
5519
      test_fail("WB INT signal should not be set");
5520
      fail = fail + 1;
5521
    end
5522
 
5523
    // write to phy's control register for 100Mbps
5524
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
5525
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
5526
    speed = 100;
5527
 
5528
    i_length = (min_tmp - 4);
5529
    while (i_length <= (max_tmp - 4))
5530
    begin
5531
      // choose generating carrier sense and collision
5532
      case (i_length[1:0])
5533
      2'h0: // Interrupt is generated
5534
      begin
5535
        // Reset_tx_bd nable interrupt generation
5536
        // unmask interrupts
5537 274 tadejm
        wait (wbm_working == 0);
5538 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
5539
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5540
        // not detect carrier sense in FD and no collision
5541
        eth_phy.carrier_sense_tx_fd_detect(0);
5542
        eth_phy.collision(0);
5543
      end
5544
      2'h1: // Interrupt is not generated
5545
      begin
5546
        // set_tx_bd enable interrupt generation
5547
        // mask interrupts
5548 274 tadejm
        wait (wbm_working == 0);
5549 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5550
        // detect carrier sense in FD and no collision
5551
        eth_phy.carrier_sense_tx_fd_detect(1);
5552
        eth_phy.collision(0);
5553
      end
5554
      2'h2: // Interrupt is not generated
5555
      begin
5556
        // set_tx_bd disable the interrupt generation
5557
        // unmask interrupts
5558 274 tadejm
        wait (wbm_working == 0);
5559 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
5560
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5561
        // not detect carrier sense in FD and set collision
5562
        eth_phy.carrier_sense_tx_fd_detect(0);
5563
        eth_phy.collision(1);
5564
      end
5565
      default: // 2'h3: // Interrupt is not generated
5566
      begin
5567
        // set_tx_bd disable the interrupt generation
5568
        // mask interrupts
5569 274 tadejm
        wait (wbm_working == 0);
5570 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5571
        // detect carrier sense in FD and set collision
5572
        eth_phy.carrier_sense_tx_fd_detect(1);
5573
        eth_phy.collision(1);
5574
      end
5575
      endcase
5576
      // first destination address on ethernet PHY
5577
      if (i_length[0] == 0)
5578
        eth_phy.set_tx_mem_addr(0);
5579
      else
5580
        eth_phy.set_tx_mem_addr(max_tmp);
5581
      // first 8 frames are transmitted with TX BD 0 (wrap bit on TX BD 0)
5582
      // number of all frames is 154 (146 without first 8)
5583
      if (num_of_frames < 8)
5584
      begin
5585
        case (i_length[1:0])
5586
        2'h0: // Interrupt is generated
5587
        begin
5588
          // enable interrupt generation
5589
          set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
5590
          // interrupts are unmasked
5591
        end
5592
        2'h1: // Interrupt is not generated
5593
        begin
5594
          // enable interrupt generation
5595
          set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
5596
          // interrupts are masked
5597
        end
5598
        2'h2: // Interrupt is not generated
5599
        begin
5600
          // disable interrupt generation
5601
          set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
5602
          // interrupts are unmasked
5603
        end
5604
        default: // 2'h3: // Interrupt is not generated
5605
        begin
5606
          // disable interrupt generation
5607
          set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
5608
          // interrupts are masked
5609
        end
5610
        endcase
5611
        // set wrap bit
5612
        set_tx_bd_wrap(0);
5613
      end
5614
      // after first 8 number of frames, 128 frames form TX BD 0 to 127 will be transmitted
5615
      else if ((num_of_frames - 8) == 0)
5616
      begin
5617
        tmp_len = i_length; // length of frame
5618
        tmp_bd_num = 0; // TX BD number
5619
        while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
5620
        begin
5621
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
5622
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
5623
          if (tmp_len[0] == 0)
5624
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
5625
          else
5626
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
5627
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
5628
          if ((tmp_len + 4) < (min_tmp + 128))
5629
            tmp_len = tmp_len + 1;
5630
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5631
            tmp_len = 256;
5632
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5633
            tmp_len = tmp_len + 128;
5634
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
5635
            tmp_len = max_tmp - (4 + 16);
5636
          else if ((tmp_len + 4) >= (max_tmp - 16))
5637
            tmp_len = tmp_len + 1;
5638
          // set TX BD number
5639
          tmp_bd_num = tmp_bd_num + 1;
5640
        end
5641
        // set wrap bit
5642
        set_tx_bd_wrap(127);
5643
      end
5644
      // after 128 + first 8 number of frames, 19 frames form TX BD 0 to 18 will be transmitted
5645
      else if ((num_of_frames - 8) == 20) // 128
5646
      begin
5647
        tmp_len = tmp_len; // length of frame remaines from previous settings
5648
        tmp_bd_num = 0; // TX BD number
5649
        while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
5650
        begin
5651
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
5652
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
5653
          if (tmp_len[0] == 0)
5654
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
5655
          else
5656
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
5657
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
5658
          if ((tmp_len + 4) < (min_tmp + 128))
5659
            tmp_len = tmp_len + 1;
5660
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5661
            tmp_len = 256;
5662
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5663
            tmp_len = tmp_len + 128;
5664
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
5665
            tmp_len = max_tmp - (4 + 16);
5666
          else if ((tmp_len + 4) >= (max_tmp - 16))
5667
            tmp_len = tmp_len + 1;
5668
          // set TX BD number
5669
          tmp_bd_num = tmp_bd_num + 1;
5670
        end
5671
      end
5672
      // set ready bit
5673
      if (num_of_frames < 8)
5674
        set_tx_bd_ready(0, 0);
5675
      else if ((num_of_frames - 8) < 128)
5676
        set_tx_bd_ready((num_of_frames - 8), (num_of_frames - 8));
5677
      else if ((num_of_frames - 136) < 19)
5678
        set_tx_bd_ready((num_of_frames - 136), (num_of_frames - 136));
5679
      // CHECK END OF TRANSMITION
5680
      #1 check_tx_bd(num_of_bd, data);
5681
      if (i_length < min_tmp) // just first four
5682
      begin
5683
        while (data[15] === 1)
5684
        begin
5685
          #1 check_tx_bd(num_of_bd, data);
5686
          @(posedge wb_clk);
5687
        end
5688
        repeat (1) @(posedge wb_clk);
5689
      end
5690
      else if (i_length > (max_tmp - 8)) // just last four
5691
      begin
5692
        tmp = 0;
5693
        wait (MTxEn === 1'b1); // start transmit
5694
        while (tmp < (i_length - 20))
5695
        begin
5696
          #1 tmp = tmp + 1;
5697
          @(posedge wb_clk);
5698
        end
5699
        #1 check_tx_bd(num_of_bd, data);
5700
        while (data[15] === 1)
5701
        begin
5702
          #1 check_tx_bd(num_of_bd, data);
5703
          @(posedge wb_clk);
5704
        end
5705
        repeat (1) @(posedge wb_clk);
5706
      end
5707
      else
5708
      begin
5709
        wait (MTxEn === 1'b1); // start transmit
5710
        #1 check_tx_bd(num_of_bd, data);
5711
        if (data[15] !== 1)
5712
        begin
5713
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
5714
          fail = fail + 1;
5715
        end
5716
        wait (MTxEn === 1'b0); // end transmit
5717
        while (data[15] === 1)
5718
        begin
5719
          #1 check_tx_bd(num_of_bd, data);
5720
          @(posedge wb_clk);
5721
        end
5722
        repeat (1) @(posedge wb_clk);
5723
      end
5724
      // check length of a PACKET
5725
      if (eth_phy.tx_len != (i_length + 4))
5726
      begin
5727
        test_fail("Wrong length of the packet out from MAC");
5728
        fail = fail + 1;
5729
      end
5730
      // checking in the following if statement is performed only for first and last 64 lengths
5731
        // check transmitted TX packet data
5732
        if (i_length[0] == 0)
5733
        begin
5734
          check_tx_packet((`MEMORY_BASE + i_length[1:0]), 0, i_length, tmp);
5735
        end
5736
        else
5737
        begin
5738
          check_tx_packet(((`MEMORY_BASE + i_length[1:0]) + max_tmp), max_tmp, i_length, tmp);
5739
        end
5740
        if (tmp > 0)
5741
        begin
5742
          test_fail("Wrong data of the transmitted packet");
5743
          fail = fail + 1;
5744
        end
5745
        // check transmited TX packet CRC
5746
        if (i_length[0] == 0)
5747
          check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
5748
        else
5749
          check_tx_crc(max_tmp, i_length, 1'b0, tmp); // length without CRC
5750
        if (tmp > 0)
5751
        begin
5752
          test_fail("Wrong CRC of the transmitted packet");
5753
          fail = fail + 1;
5754
        end
5755
      // check WB INT signal
5756
      if (i_length[1:0] == 2'h0)
5757
      begin
5758
        if (wb_int !== 1'b1)
5759
        begin
5760
          `TIME; $display("*E WB INT signal should be set");
5761
          test_fail("WB INT signal should be set");
5762
          fail = fail + 1;
5763
        end
5764
      end
5765
      else
5766
      begin
5767
        if (wb_int !== 1'b0)
5768
        begin
5769
          `TIME; $display("*E WB INT signal should not be set");
5770
          test_fail("WB INT signal should not be set");
5771
          fail = fail + 1;
5772
        end
5773
      end
5774
      // check TX buffer descriptor of a packet
5775
      check_tx_bd(num_of_bd, data);
5776
      if (i_length[1] == 1'b0) // interrupt enabled
5777
      begin
5778
        if ( ((data[15:0] !== 16'h7800) && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
5779
             ((data[15:0] !== 16'h5800) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
5780
        begin
5781
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
5782
          test_fail("TX buffer descriptor status is not correct");
5783
          fail = fail + 1;
5784
        end
5785
      end
5786
      else // interrupt not enabled
5787
      begin
5788
        if ( ((data[15:0] !== 16'h3800)  && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
5789
             ((data[15:0] !== 16'h1800) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
5790
        begin
5791
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
5792
          test_fail("TX buffer descriptor status is not correct");
5793
          fail = fail + 1;
5794
        end
5795
      end
5796
      // clear first half of 8 frames from TX buffer descriptor 0
5797
      if (num_of_frames < 4)
5798
        clear_tx_bd(num_of_bd, num_of_bd);
5799
      // clear BD with wrap bit
5800
      if (num_of_frames == 140)
5801
        clear_tx_bd(127, 127);
5802
      // check interrupts
5803 274 tadejm
      wait (wbm_working == 0);
5804 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5805
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
5806
      begin
5807
        if ((data & `ETH_INT_TXB) !== 1'b1)
5808
        begin
5809
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
5810
          test_fail("Interrupt Transmit Buffer was not set");
5811
          fail = fail + 1;
5812
        end
5813
        if ((data & (~`ETH_INT_TXB)) !== 0)
5814
        begin
5815
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
5816
          test_fail("Other interrupts (except Transmit Buffer) were set");
5817
          fail = fail + 1;
5818
        end
5819
      end
5820
      else
5821
      begin
5822
        if (data !== 0)
5823
        begin
5824
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
5825
          test_fail("Any of interrupts (except Transmit Buffer) was set");
5826
          fail = fail + 1;
5827
        end
5828
      end
5829
      // clear interrupts
5830 274 tadejm
      wait (wbm_working == 0);
5831 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5832
      // check WB INT signal
5833
      if (wb_int !== 1'b0)
5834
      begin
5835
        test_fail("WB INT signal should not be set");
5836
        fail = fail + 1;
5837
      end
5838
      // INTERMEDIATE DISPLAYS
5839
      if ((i_length + 4) == (min_tmp + 7))
5840
      begin
5841
        // starting length is min_tmp, ending length is (min_tmp + 128)
5842
        $display("    pads appending to packets is NOT selected");
5843
        $display("    using only TX BD 0 out of 128 BDs assigned to TX (wrap at first BD - TX BD 0)");
5844
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
5845
                 min_tmp, (min_tmp + 7));
5846
        $display("    ->all packets were send from TX BD 0");
5847
        // set padding, remain the rest
5848 274 tadejm
        wait (wbm_working == 0);
5849 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
5850
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5851
      end
5852
      else if ((i_length + 4) == (min_tmp + 128))
5853
      begin
5854
        // starting length is min_tmp, ending length is (min_tmp + 128)
5855
        $display("    pads appending to packets is NOT selected");
5856
        $display("    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)");
5857
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
5858
                 (min_tmp + 8), (min_tmp + 128));
5859
        $display("    ->packets were send from TX BD %0d to TX BD %0d respectively",
5860
                 1'b0, num_of_bd);
5861
        tmp_bd = num_of_bd + 1;
5862
        // set padding, remain the rest
5863 274 tadejm
        wait (wbm_working == 0);
5864 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
5865
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5866
      end
5867
      else if ((i_length + 4) == (max_tmp - 16))
5868
      begin
5869
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
5870
        $display("    pads appending to packets is selected");
5871
        $display("    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)");
5872
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
5873
                 (min_tmp + 64 + 128), tmp_data);
5874
        if (tmp_bd > num_of_bd)
5875
          $display("    ->packets were send from TX BD %0d to TX BD 127 and from TX BD 0 to TX BD %0d respectively",
5876
                   tmp_bd, num_of_bd);
5877
        else
5878
          $display("    ->packets were send from TX BD %0d to TX BD %0d respectively",
5879
                   tmp_bd, num_of_bd);
5880
        tmp_bd = num_of_bd + 1;
5881
        // reset padding, remain the rest
5882 274 tadejm
        wait (wbm_working == 0);
5883 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
5884
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5885
      end
5886
      else if ((i_length + 4) == max_tmp)
5887
      begin
5888
        $display("    pads appending to packets is NOT selected");
5889
        $display("    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)");
5890
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
5891
                 (max_tmp - (4 + 16)), max_tmp);
5892
        if (tmp_bd > num_of_bd)
5893
          $display("    ->packets were send from TX BD %0d to TX BD 127 and from TX BD 0 to TX BD %0d respectively",
5894
                   tmp_bd, num_of_bd);
5895
        else
5896
          $display("    ->packets were send from TX BD %0d to TX BD %0d respectively",
5897
                   tmp_bd, num_of_bd);
5898
      end
5899
      // set length (loop variable)
5900
      if ((i_length + 4) < (min_tmp + 128))
5901
        i_length = i_length + 1;
5902
      else if ( ((i_length + 4) == (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
5903
        i_length = 256;
5904
      else if ( ((i_length + 4) > (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
5905
      begin
5906
        i_length = i_length + 128;
5907
        tmp_data = i_length + 4; // last tmp_data is ending length
5908
      end
5909
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
5910
        i_length = max_tmp - (4 + 16);
5911
      else if ((i_length + 4) >= (max_tmp - 16))
5912
        i_length = i_length + 1;
5913
      else
5914
      begin
5915
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
5916
        #10 $stop;
5917
      end
5918
      // the number of frame transmitted
5919
      num_of_frames = num_of_frames + 1;
5920
      if ((num_of_frames <= 8) || ((num_of_frames - 8) == 128))
5921
        num_of_bd = 0;
5922
      else
5923
        num_of_bd = num_of_bd + 1;
5924
    end
5925
    // disable TX
5926 274 tadejm
    wait (wbm_working == 0);
5927 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
5928
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5929
    @(posedge wb_clk);
5930
    if(fail == 0)
5931
      test_ok;
5932
    else
5933
      fail = 0;
5934
  end
5935
 
5936
 
5937
  ////////////////////////////////////////////////////////////////////
5938
  ////                                                            ////
5939
  ////  Test transmit packets form 0 to (MINFL - 1) sizes at      ////
5940
  ////  8 TX buffer decriptors ( 10Mbps ).                        ////
5941
  ////                                                            ////
5942
  ////////////////////////////////////////////////////////////////////
5943
  if (test_num == 6) // 
5944
  begin
5945
    // TEST 6: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )
5946
    test_name = "TEST 6: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )";
5947
    `TIME; $display("  TEST 6: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )");
5948
 
5949
    // reset MAC registers
5950
    hard_reset;
5951
    // reset MAC and MII LOGIC with soft reset
5952 274 tadejm
//    reset_mac;
5953
//    reset_mii;
5954 209 tadejm
    // set wb slave response
5955
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
5956
 
5957
    max_tmp = 0;
5958
    min_tmp = 0;
5959
    // set 8 TX buffer descriptors - must be set before TX enable
5960 274 tadejm
    wait (wbm_working == 0);
5961 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h8, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5962
    // enable TX, set full-duplex mode, padding and CRC appending
5963 274 tadejm
    wait (wbm_working == 0);
5964 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
5965
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5966
    // prepare two packets of MAXFL length
5967 274 tadejm
    wait (wbm_working == 0);
5968 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5969
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
5970
    min_tmp = tmp[31:16];
5971
    st_data = 8'h12;
5972
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
5973
    st_data = 8'h34;
5974
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp - 4), st_data); // length without CRC
5975
    // check WB INT signal
5976
    if (wb_int !== 1'b0)
5977
    begin
5978
      test_fail("WB INT signal should not be set");
5979
      fail = fail + 1;
5980
    end
5981
 
5982
    // write to phy's control register for 10Mbps
5983
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
5984
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
5985
    speed = 10;
5986
 
5987
    frame_started = 0;
5988
    num_of_frames = 0;
5989
    num_of_bd = 0;
5990
    i_length = 0; // 0;
5991
    while (i_length < 70) // (min_tmp - 4))
5992
    begin
5993
      #1;
5994
      // choose generating carrier sense and collision
5995
      case (i_length[1:0])
5996
      2'h0: // Interrupt is generated
5997
      begin
5998
        // Reset_tx_bd nable interrupt generation
5999
        // unmask interrupts
6000 274 tadejm
        wait (wbm_working == 0);
6001 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
6002
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6003
        // not detect carrier sense in FD and no collision
6004
        eth_phy.carrier_sense_tx_fd_detect(0);
6005
        eth_phy.collision(0);
6006
      end
6007
      2'h1: // Interrupt is not generated
6008
      begin
6009
        // set_tx_bd enable interrupt generation
6010
        // mask interrupts
6011 274 tadejm
        wait (wbm_working == 0);
6012 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6013
        // detect carrier sense in FD and no collision
6014
        eth_phy.carrier_sense_tx_fd_detect(1);
6015
        eth_phy.collision(0);
6016
      end
6017
      2'h2: // Interrupt is not generated
6018
      begin
6019
        // set_tx_bd disable the interrupt generation
6020
        // unmask interrupts
6021 274 tadejm
        wait (wbm_working == 0);
6022 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
6023
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6024
        // not detect carrier sense in FD and set collision
6025
        eth_phy.carrier_sense_tx_fd_detect(0);
6026
        eth_phy.collision(1);
6027
      end
6028
      default: // 2'h3: // Interrupt is not generated
6029
      begin
6030
        // set_tx_bd disable the interrupt generation
6031
        // mask interrupts
6032 274 tadejm
        wait (wbm_working == 0);
6033 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6034
        // detect carrier sense in FD and set collision
6035
        eth_phy.carrier_sense_tx_fd_detect(1);
6036
        eth_phy.collision(1);
6037
      end
6038
      endcase
6039
      #1;
6040
      // first destination address on ethernet PHY
6041
      eth_phy.set_tx_mem_addr(num_of_frames * 16);
6042
      // SET packets and wrap bit
6043
      // num_of_frames <= 9 => wrap set to TX BD 0
6044
      if (num_of_frames <= 9)
6045
      begin
6046
        tmp_len = i_length; // length of frame
6047
        tmp_bd_num = 0; // TX BD number
6048
        // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6049
        // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6050
        if (tmp_len[0] == 0)
6051
          set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6052
        else
6053
          set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6054
        // set wrap bit
6055
        set_tx_bd_wrap(0);
6056
      end
6057
      // 10 <= num_of_frames < 18 => wrap set to TX BD 3
6058
      else if ((num_of_frames == 10) || (num_of_frames == 14))
6059
      begin
6060
        tmp_len = i_length; // length of frame
6061
        tmp_bd_num = 0; // TX BD number
6062
        while (tmp_bd_num < 4) //
6063
        begin
6064
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6065
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6066
          if (tmp_len[0] == 0)
6067
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6068
          else
6069
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6070
          tmp_len = tmp_len + 1;
6071
          // set TX BD number
6072
          tmp_bd_num = tmp_bd_num + 1;
6073
        end
6074
        // set wrap bit
6075
        set_tx_bd_wrap(3);
6076
      end
6077
      // 18 <= num_of_frames < 28 => wrap set to TX BD 4
6078
      else if ((num_of_frames == 18) || (num_of_frames == 23))
6079
      begin
6080
        tmp_len = i_length; // length of frame
6081
        tmp_bd_num = 0; // TX BD number
6082
        while (tmp_bd_num < 5) //
6083
        begin
6084
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6085
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6086
          if (tmp_len[0] == 0)
6087
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6088
          else
6089
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6090
          tmp_len = tmp_len + 1;
6091
          // set TX BD number
6092
          tmp_bd_num = tmp_bd_num + 1;
6093
        end
6094
        // set wrap bit
6095
        set_tx_bd_wrap(4);
6096
      end
6097
      // 28 <= num_of_frames < 40 => wrap set to TX BD 5
6098
      else if ((num_of_frames == 28) || (num_of_frames == 34))
6099
      begin
6100
        tmp_len = i_length; // length of frame
6101
        tmp_bd_num = 0; // TX BD number
6102
        while (tmp_bd_num < 6) //
6103
        begin
6104
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6105
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6106
          if (tmp_len[0] == 0)
6107
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6108
          else
6109
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6110
          tmp_len = tmp_len + 1;
6111
          // set TX BD number
6112
          tmp_bd_num = tmp_bd_num + 1;
6113
        end
6114
        // set wrap bit
6115
        set_tx_bd_wrap(5);
6116
      end
6117
      // 40 <= num_of_frames < 54 => wrap set to TX BD 6
6118
      else if ((num_of_frames == 40) || (num_of_frames == 47))
6119
      begin
6120
        tmp_len = i_length; // length of frame
6121
        tmp_bd_num = 0; // TX BD number
6122
        while (tmp_bd_num < 7) //
6123
        begin
6124
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6125
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6126
          if (tmp_len[0] == 0)
6127
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6128
          else
6129
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6130
          tmp_len = tmp_len + 1;
6131
          // set TX BD number
6132
          tmp_bd_num = tmp_bd_num + 1;
6133
        end
6134
        // set wrap bit
6135
        set_tx_bd_wrap(6);
6136
      end
6137
      // 54 <= num_of_frames < 70 => wrap set to TX BD 7
6138
      else if ((num_of_frames == 54) || (num_of_frames == 62))
6139
      begin
6140
        tmp_len = i_length; // length of frame
6141
        tmp_bd_num = 0; // TX BD number
6142
        while (tmp_bd_num < 8) //
6143
        begin
6144
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6145
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6146
          if (tmp_len[0] == 0)
6147
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6148
          else
6149
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6150
          tmp_len = tmp_len + 1;
6151
          // set TX BD number
6152
          tmp_bd_num = tmp_bd_num + 1;
6153
        end
6154
        // set wrap bit
6155
        set_tx_bd_wrap(7);
6156
      end
6157
      #1;
6158
      // SET ready bit
6159
      if (num_of_frames < 10)
6160
        set_tx_bd_ready(0, 0);
6161
      else if (num_of_frames < 14)
6162
        set_tx_bd_ready((num_of_frames - 10), (num_of_frames - 10));
6163
      else if (num_of_frames < 18)
6164
        set_tx_bd_ready((num_of_frames - 14), (num_of_frames - 14));
6165
      else if (num_of_frames < 23)
6166
        set_tx_bd_ready((num_of_frames - 18), (num_of_frames - 18));
6167
      else if (num_of_frames < 28)
6168
        set_tx_bd_ready((num_of_frames - 23), (num_of_frames - 23));
6169
      else if (num_of_frames < 34)
6170
        set_tx_bd_ready((num_of_frames - 28), (num_of_frames - 28));
6171
      else if (num_of_frames < 40)
6172
        set_tx_bd_ready((num_of_frames - 34), (num_of_frames - 34));
6173
      else if (num_of_frames < 47)
6174
        set_tx_bd_ready((num_of_frames - 40), (num_of_frames - 40));
6175
      else if (num_of_frames < 54)
6176
        set_tx_bd_ready((num_of_frames - 47), (num_of_frames - 47));
6177
      else if (num_of_frames < 62)
6178
        set_tx_bd_ready((num_of_frames - 54), (num_of_frames - 54));
6179
      else if (num_of_frames < 70)
6180
        set_tx_bd_ready((num_of_frames - 62), (num_of_frames - 62));
6181
      // CHECK END OF TRANSMITION
6182
      frame_started = 0;
6183
      if (num_of_frames >= 5)
6184
        #1 check_tx_bd(num_of_bd, data);
6185
      fork
6186
      begin: fr_st
6187
        wait (MTxEn === 1'b1); // start transmit
6188
        frame_started = 1;
6189
      end
6190
      begin
6191
        repeat (30) @(posedge mtx_clk);
6192
        if (num_of_frames < 5)
6193
        begin
6194
          if (frame_started == 1)
6195
          begin
6196
            `TIME; $display("*E Frame should NOT start!");
6197
          end
6198
          disable fr_st;
6199
        end
6200
        else
6201
        begin
6202
          if (frame_started == 0)
6203
          begin
6204
            `TIME; $display("*W Frame should start!");
6205
            disable fr_st;
6206
          end
6207
        end
6208
      end
6209
      join
6210
      // check packets larger than 4 bytes
6211
      if (num_of_frames >= 5)
6212
      begin
6213
        wait (MTxEn === 1'b0); // end transmit
6214
        while (data[15] === 1)
6215
        begin
6216
          #1 check_tx_bd(num_of_bd, data);
6217
          @(posedge wb_clk);
6218
        end
6219
        repeat (1) @(posedge wb_clk);
6220
        // check length of a PACKET
6221
        if (i_length <= (min_tmp - 4))
6222
        begin
6223
          if (eth_phy.tx_len != min_tmp)
6224
          begin
6225
            test_fail("Wrong length of the packet out from MAC");
6226
            fail = fail + 1;
6227
          end
6228
        end
6229
        else
6230
        begin
6231
          if (eth_phy.tx_len != (i_length + 4))
6232
          begin
6233
            test_fail("Wrong length of the packet out from MAC");
6234
            fail = fail + 1;
6235
          end
6236
        end
6237
        // check transmitted TX packet data
6238
        if (i_length[0] == 0)
6239
        begin
6240
          #1 check_tx_packet(`MEMORY_BASE, (num_of_frames * 16), i_length, tmp);
6241
        end
6242
        else
6243
        begin
6244
          #1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
6245
        end
6246
        if (tmp > 0)
6247
        begin
6248
          test_fail("Wrong data of the transmitted packet");
6249
          fail = fail + 1;
6250
        end
6251
        // check transmited TX packet CRC
6252
        if (num_of_frames < (min_tmp - 4))
6253
          #1 check_tx_crc((num_of_frames * 16), (min_tmp - 4), 1'b0, tmp); // length without CRC
6254
        else
6255
          #1 check_tx_crc((num_of_frames * 16), i_length, 1'b0, tmp); // length without CRC
6256
        if (tmp > 0)
6257
        begin
6258
          test_fail("Wrong CRC of the transmitted packet");
6259
          fail = fail + 1;
6260
        end
6261
      end
6262
      // check WB INT signal
6263
      if ((i_length[1:0] == 2'h0) && (num_of_frames >= 5))
6264
      begin
6265
        if (wb_int !== 1'b1)
6266
        begin
6267
          `TIME; $display("*E WB INT signal should be set");
6268
          test_fail("WB INT signal should be set");
6269
          fail = fail + 1;
6270
        end
6271
      end
6272
      else
6273
      begin
6274
        if (wb_int !== 1'b0)
6275
        begin
6276
          `TIME; $display("*E WB INT signal should not be set");
6277
          test_fail("WB INT signal should not be set");
6278
          fail = fail + 1;
6279
        end
6280
      end
6281
      // check TX buffer descriptor of a packet
6282
      check_tx_bd(num_of_bd, data);
6283
      if (num_of_frames >= 5)
6284
      begin
6285
        if (i_length[1] == 1'b0) // interrupt enabled
6286
        begin
6287
          if ( (data[15:0] !== 16'h7800) && // wrap bit
6288
               (data[15:0] !== 16'h5800) ) // without wrap bit
6289
          begin
6290
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
6291
            test_fail("TX buffer descriptor status is not correct");
6292
            fail = fail + 1;
6293
          end
6294
        end
6295
        else // interrupt not enabled
6296
        begin
6297
          if ( (data[15:0] !== 16'h3800) && // wrap bit
6298
               (data[15:0] !== 16'h1800) ) // without wrap bit
6299
          begin
6300
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
6301
            test_fail("TX buffer descriptor status is not correct");
6302
            fail = fail + 1;
6303
          end
6304
        end
6305
      end
6306
      else
6307
      begin
6308
        if (data[15] !== 1'b1)
6309
        begin
6310
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
6311
          test_fail("TX buffer descriptor status is not correct");
6312
          fail = fail + 1;
6313
        end
6314
      end
6315
      // clear TX BD with wrap bit
6316
      if (num_of_frames == 63)
6317
        clear_tx_bd(16, 16);
6318
      // check interrupts
6319 274 tadejm
      wait (wbm_working == 0);
6320 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6321
      if ( ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1)) && (num_of_frames >= 5) )
6322
      begin
6323
        if ((data & `ETH_INT_TXB) !== 1'b1)
6324
        begin
6325
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
6326
          test_fail("Interrupt Transmit Buffer was not set");
6327
          fail = fail + 1;
6328
        end
6329
        if ((data & (~`ETH_INT_TXB)) !== 0)
6330
        begin
6331
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
6332
          test_fail("Other interrupts (except Transmit Buffer) were set");
6333
          fail = fail + 1;
6334
        end
6335
      end
6336
      else
6337
      begin
6338
        if (data !== 0)
6339
        begin
6340
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
6341
          test_fail("Any of interrupts (except Transmit Buffer) was set");
6342
          fail = fail + 1;
6343
        end
6344
      end
6345
      // clear interrupts
6346 274 tadejm
      wait (wbm_working == 0);
6347 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6348
      // check WB INT signal
6349
      if (wb_int !== 1'b0)
6350
      begin
6351
        test_fail("WB INT signal should not be set");
6352
        fail = fail + 1;
6353
      end
6354
      // INTERMEDIATE DISPLAYS
6355
      if (i_length == 3)
6356
      begin
6357
        $display("    pads appending to packets is selected");
6358
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
6359
        $display("    ->packets with lengths from %0d to %0d are not transmitted (length increasing by 1 byte)",
6360
                 0, 3);
6361
      end
6362
      else if (i_length == 9)
6363
      begin
6364
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
6365
        $display("    ->packet with length 4 is not transmitted (length increasing by 1 byte)");
6366
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6367
                 5, 9);
6368
      end
6369
      else if (i_length == 17)
6370
      begin
6371
        $display("    using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3)");
6372
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6373
                 10, 17);
6374
      end
6375
      else if (i_length == 27)
6376
      begin
6377
        $display("    using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4)");
6378
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6379
                 18, 27);
6380
      end
6381
      else if (i_length == 40)
6382
      begin
6383
        $display("    using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5)");
6384
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6385
                 28, 40);
6386
      end
6387
      else if (i_length == 54)
6388
      begin
6389
        $display("    using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6)");
6390
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6391
                 41, 54);
6392
      end
6393
      else if (i_length == 69)
6394
      begin
6395
        $display("    using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7)");
6396
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6397
                 55, 69);
6398
      end
6399
      // set length (loop variable)
6400
      i_length = i_length + 1;
6401
      // the number of frame transmitted
6402
      num_of_frames = num_of_frames + 1;
6403
      if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
6404
          (num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
6405
          (num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
6406
          (num_of_frames == 54) || (num_of_frames == 62))
6407
        num_of_bd = 0;
6408
      else
6409
        num_of_bd = num_of_bd + 1;
6410
    end
6411
    // disable TX
6412 274 tadejm
    wait (wbm_working == 0);
6413 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
6414
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6415
    @(posedge wb_clk);
6416
    if(fail == 0)
6417
      test_ok;
6418
    else
6419
      fail = 0;
6420
  end
6421
 
6422
 
6423
  ////////////////////////////////////////////////////////////////////
6424
  ////                                                            ////
6425
  ////  Test transmit packets form 0 to (MINFL - 1) sizes at      ////
6426
  ////  8 TX buffer decriptors ( 100Mbps ).                       ////
6427
  ////                                                            ////
6428
  ////////////////////////////////////////////////////////////////////
6429
  if (test_num == 7) // 
6430
  begin
6431
    // TEST 7: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )
6432
    test_name = "TEST 7: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )";
6433
    `TIME; $display("  TEST 7: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )");
6434
 
6435
    // reset MAC registers
6436
    hard_reset;
6437
    // reset MAC and MII LOGIC with soft reset
6438 274 tadejm
//    reset_mac;
6439
//    reset_mii;
6440 209 tadejm
    // set wb slave response
6441
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
6442
 
6443
    max_tmp = 0;
6444
    min_tmp = 0;
6445
    // set 8 TX buffer descriptors - must be set before TX enable
6446 274 tadejm
    wait (wbm_working == 0);
6447 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h8, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6448
    // enable TX, set full-duplex mode, padding and CRC appending
6449 274 tadejm
    wait (wbm_working == 0);
6450 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
6451
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6452
    // prepare two packets of MAXFL length
6453 274 tadejm
    wait (wbm_working == 0);
6454 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6455
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
6456
    min_tmp = tmp[31:16];
6457
    st_data = 8'h12;
6458
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
6459
    st_data = 8'h34;
6460
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp - 4), st_data); // length without CRC
6461
    // check WB INT signal
6462
    if (wb_int !== 1'b0)
6463
    begin
6464
      test_fail("WB INT signal should not be set");
6465
      fail = fail + 1;
6466
    end
6467
 
6468
    // write to phy's control register for 100Mbps
6469
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
6470
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
6471
    speed = 100;
6472
 
6473
    frame_started = 0;
6474
    num_of_frames = 0;
6475
    num_of_bd = 0;
6476
    i_length = 0; // 0;
6477
    while (i_length < 70) // (min_tmp - 4))
6478
    begin
6479
      #1;
6480
      // choose generating carrier sense and collision
6481
      case (i_length[1:0])
6482
      2'h0: // Interrupt is generated
6483
      begin
6484
        // Reset_tx_bd nable interrupt generation
6485
        // unmask interrupts
6486 274 tadejm
        wait (wbm_working == 0);
6487 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
6488
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6489
        // not detect carrier sense in FD and no collision
6490
        eth_phy.carrier_sense_tx_fd_detect(0);
6491
        eth_phy.collision(0);
6492
      end
6493
      2'h1: // Interrupt is not generated
6494
      begin
6495
        // set_tx_bd enable interrupt generation
6496
        // mask interrupts
6497 274 tadejm
        wait (wbm_working == 0);
6498 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6499
        // detect carrier sense in FD and no collision
6500
        eth_phy.carrier_sense_tx_fd_detect(1);
6501
        eth_phy.collision(0);
6502
      end
6503
      2'h2: // Interrupt is not generated
6504
      begin
6505
        // set_tx_bd disable the interrupt generation
6506
        // unmask interrupts
6507 274 tadejm
        wait (wbm_working == 0);
6508 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
6509
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6510
        // not detect carrier sense in FD and set collision
6511
        eth_phy.carrier_sense_tx_fd_detect(0);
6512
        eth_phy.collision(1);
6513
      end
6514
      default: // 2'h3: // Interrupt is not generated
6515
      begin
6516
        // set_tx_bd disable the interrupt generation
6517
        // mask interrupts
6518 274 tadejm
        wait (wbm_working == 0);
6519 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6520
        // detect carrier sense in FD and set collision
6521
        eth_phy.carrier_sense_tx_fd_detect(1);
6522
        eth_phy.collision(1);
6523
      end
6524
      endcase
6525
      #1;
6526
      // first destination address on ethernet PHY
6527
      eth_phy.set_tx_mem_addr(num_of_frames * 16);
6528
      // SET packets and wrap bit
6529
      // num_of_frames <= 9 => wrap set to TX BD 0
6530
      if (num_of_frames <= 9)
6531
      begin
6532
        tmp_len = i_length; // length of frame
6533
        tmp_bd_num = 0; // TX BD number
6534
        // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6535
        // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6536
        if (tmp_len[0] == 0)
6537
          set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6538
        else
6539
          set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6540
        // set wrap bit
6541
        set_tx_bd_wrap(0);
6542
      end
6543
      // 10 <= num_of_frames < 18 => wrap set to TX BD 3
6544
      else if ((num_of_frames == 10) || (num_of_frames == 14))
6545
      begin
6546
        tmp_len = i_length; // length of frame
6547
        tmp_bd_num = 0; // TX BD number
6548
        while (tmp_bd_num < 4) //
6549
        begin
6550
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6551
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6552
          if (tmp_len[0] == 0)
6553
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6554
          else
6555
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6556
          tmp_len = tmp_len + 1;
6557
          // set TX BD number
6558
          tmp_bd_num = tmp_bd_num + 1;
6559
        end
6560
        // set wrap bit
6561
        set_tx_bd_wrap(3);
6562
      end
6563
      // 18 <= num_of_frames < 28 => wrap set to TX BD 4
6564
      else if ((num_of_frames == 18) || (num_of_frames == 23))
6565
      begin
6566
        tmp_len = i_length; // length of frame
6567
        tmp_bd_num = 0; // TX BD number
6568
        while (tmp_bd_num < 5) //
6569
        begin
6570
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6571
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6572
          if (tmp_len[0] == 0)
6573
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6574
          else
6575
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6576
          tmp_len = tmp_len + 1;
6577
          // set TX BD number
6578
          tmp_bd_num = tmp_bd_num + 1;
6579
        end
6580
        // set wrap bit
6581
        set_tx_bd_wrap(4);
6582
      end
6583
      // 28 <= num_of_frames < 40 => wrap set to TX BD 5
6584
      else if ((num_of_frames == 28) || (num_of_frames == 34))
6585
      begin
6586
        tmp_len = i_length; // length of frame
6587
        tmp_bd_num = 0; // TX BD number
6588
        while (tmp_bd_num < 6) //
6589
        begin
6590
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6591
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6592
          if (tmp_len[0] == 0)
6593
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6594
          else
6595
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6596
          tmp_len = tmp_len + 1;
6597
          // set TX BD number
6598
          tmp_bd_num = tmp_bd_num + 1;
6599
        end
6600
        // set wrap bit
6601
        set_tx_bd_wrap(5);
6602
      end
6603
      // 40 <= num_of_frames < 54 => wrap set to TX BD 6
6604
      else if ((num_of_frames == 40) || (num_of_frames == 47))
6605
      begin
6606
        tmp_len = i_length; // length of frame
6607
        tmp_bd_num = 0; // TX BD number
6608
        while (tmp_bd_num < 7) //
6609
        begin
6610
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6611
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6612
          if (tmp_len[0] == 0)
6613
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6614
          else
6615
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6616
          tmp_len = tmp_len + 1;
6617
          // set TX BD number
6618
          tmp_bd_num = tmp_bd_num + 1;
6619
        end
6620
        // set wrap bit
6621
        set_tx_bd_wrap(6);
6622
      end
6623
      // 54 <= num_of_frames < 70 => wrap set to TX BD 7
6624
      else if ((num_of_frames == 54) || (num_of_frames == 62))
6625
      begin
6626
        tmp_len = i_length; // length of frame
6627
        tmp_bd_num = 0; // TX BD number
6628
        while (tmp_bd_num < 8) //
6629
        begin
6630
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6631
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6632
          if (tmp_len[0] == 0)
6633
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6634
          else
6635
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6636
          tmp_len = tmp_len + 1;
6637
          // set TX BD number
6638
          tmp_bd_num = tmp_bd_num + 1;
6639
        end
6640
        // set wrap bit
6641
        set_tx_bd_wrap(7);
6642
      end
6643
      #1;
6644
      // SET ready bit
6645
      if (num_of_frames < 10)
6646
        set_tx_bd_ready(0, 0);
6647
      else if (num_of_frames < 14)
6648
        set_tx_bd_ready((num_of_frames - 10), (num_of_frames - 10));
6649
      else if (num_of_frames < 18)
6650
        set_tx_bd_ready((num_of_frames - 14), (num_of_frames - 14));
6651
      else if (num_of_frames < 23)
6652
        set_tx_bd_ready((num_of_frames - 18), (num_of_frames - 18));
6653
      else if (num_of_frames < 28)
6654
        set_tx_bd_ready((num_of_frames - 23), (num_of_frames - 23));
6655
      else if (num_of_frames < 34)
6656
        set_tx_bd_ready((num_of_frames - 28), (num_of_frames - 28));
6657
      else if (num_of_frames < 40)
6658
        set_tx_bd_ready((num_of_frames - 34), (num_of_frames - 34));
6659
      else if (num_of_frames < 47)
6660
        set_tx_bd_ready((num_of_frames - 40), (num_of_frames - 40));
6661
      else if (num_of_frames < 54)
6662
        set_tx_bd_ready((num_of_frames - 47), (num_of_frames - 47));
6663
      else if (num_of_frames < 62)
6664
        set_tx_bd_ready((num_of_frames - 54), (num_of_frames - 54));
6665
      else if (num_of_frames < 70)
6666
        set_tx_bd_ready((num_of_frames - 62), (num_of_frames - 62));
6667
      // CHECK END OF TRANSMITION
6668
      frame_started = 0;
6669
      if (num_of_frames >= 5)
6670
        #1 check_tx_bd(num_of_bd, data);
6671
      fork
6672
      begin: fr_st1
6673
        wait (MTxEn === 1'b1); // start transmit
6674
        frame_started = 1;
6675
      end
6676
      begin
6677 279 mohor
        repeat (50) @(posedge mtx_clk);     // Increased from 30 to 50
6678 209 tadejm
        if (num_of_frames < 5)
6679
        begin
6680
          if (frame_started == 1)
6681
          begin
6682
            `TIME; $display("*E Frame should NOT start!");
6683
          end
6684
          disable fr_st1;
6685
        end
6686
        else
6687
        begin
6688
          if (frame_started == 0)
6689
          begin
6690
            `TIME; $display("*W Frame should start!");
6691
            disable fr_st1;
6692
          end
6693
        end
6694
      end
6695
      join
6696
      // check packets larger than 4 bytes
6697
      if (num_of_frames >= 5)
6698
      begin
6699
        wait (MTxEn === 1'b0); // end transmit
6700
        while (data[15] === 1)
6701
        begin
6702
          #1 check_tx_bd(num_of_bd, data);
6703
          @(posedge wb_clk);
6704
        end
6705
        repeat (1) @(posedge wb_clk);
6706
        // check length of a PACKET
6707
        if (i_length <= (min_tmp - 4))
6708
        begin
6709
          if (eth_phy.tx_len != min_tmp)
6710
          begin
6711
            test_fail("Wrong length of the packet out from MAC");
6712
            fail = fail + 1;
6713
          end
6714
        end
6715
        else
6716
        begin
6717
          if (eth_phy.tx_len != (i_length + 4))
6718
          begin
6719
            test_fail("Wrong length of the packet out from MAC");
6720
            fail = fail + 1;
6721
          end
6722
        end
6723
        // check transmitted TX packet data
6724
        if (i_length[0] == 0)
6725
        begin
6726
          #1 check_tx_packet(`MEMORY_BASE, (num_of_frames * 16), i_length, tmp);
6727
        end
6728
        else
6729
        begin
6730
          #1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
6731
        end
6732
        if (tmp > 0)
6733
        begin
6734
          test_fail("Wrong data of the transmitted packet");
6735
          fail = fail + 1;
6736
        end
6737
        // check transmited TX packet CRC
6738
        if (num_of_frames < (min_tmp - 4))
6739
          #1 check_tx_crc((num_of_frames * 16), (min_tmp - 4), 1'b0, tmp); // length without CRC
6740
        else
6741
          #1 check_tx_crc((num_of_frames * 16), i_length, 1'b0, tmp); // length without CRC
6742
        if (tmp > 0)
6743
        begin
6744
          test_fail("Wrong CRC of the transmitted packet");
6745
          fail = fail + 1;
6746
        end
6747
      end
6748
      // check WB INT signal
6749
      if ((i_length[1:0] == 2'h0) && (num_of_frames >= 5))
6750
      begin
6751
        if (wb_int !== 1'b1)
6752
        begin
6753
          `TIME; $display("*E WB INT signal should be set");
6754
          test_fail("WB INT signal should be set");
6755
          fail = fail + 1;
6756
        end
6757
      end
6758
      else
6759
      begin
6760
        if (wb_int !== 1'b0)
6761
        begin
6762
          `TIME; $display("*E WB INT signal should not be set");
6763
          test_fail("WB INT signal should not be set");
6764
          fail = fail + 1;
6765
        end
6766
      end
6767
      // check TX buffer descriptor of a packet
6768
      check_tx_bd(num_of_bd, data);
6769
      if (num_of_frames >= 5)
6770
      begin
6771
        if (i_length[1] == 1'b0) // interrupt enabled
6772
        begin
6773
          if ( (data[15:0] !== 16'h7800) && // wrap bit
6774
               (data[15:0] !== 16'h5800) ) // without wrap bit
6775
          begin
6776
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
6777
            test_fail("TX buffer descriptor status is not correct");
6778
            fail = fail + 1;
6779
          end
6780
        end
6781
        else // interrupt not enabled
6782
        begin
6783
          if ( (data[15:0] !== 16'h3800) && // wrap bit
6784
               (data[15:0] !== 16'h1800) ) // without wrap bit
6785
          begin
6786
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
6787
            test_fail("TX buffer descriptor status is not correct");
6788
            fail = fail + 1;
6789
          end
6790
        end
6791
      end
6792
      else
6793
      begin
6794
        if (data[15] !== 1'b1)
6795
        begin
6796
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
6797
          test_fail("TX buffer descriptor status is not correct");
6798
          fail = fail + 1;
6799
        end
6800
      end
6801
      // clear TX BD with wrap bit
6802
      if (num_of_frames == 63)
6803
        clear_tx_bd(16, 16);
6804
      // check interrupts
6805 274 tadejm
      wait (wbm_working == 0);
6806 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6807
      if ( ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1)) && (num_of_frames >= 5) )
6808
      begin
6809
        if ((data & `ETH_INT_TXB) !== 1'b1)
6810
        begin
6811
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
6812
          test_fail("Interrupt Transmit Buffer was not set");
6813
          fail = fail + 1;
6814
        end
6815
        if ((data & (~`ETH_INT_TXB)) !== 0)
6816
        begin
6817
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
6818
          test_fail("Other interrupts (except Transmit Buffer) were set");
6819
          fail = fail + 1;
6820
        end
6821
      end
6822
      else
6823
      begin
6824
        if (data !== 0)
6825
        begin
6826
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
6827
          test_fail("Any of interrupts (except Transmit Buffer) was set");
6828
          fail = fail + 1;
6829
        end
6830
      end
6831
      // clear interrupts
6832 274 tadejm
      wait (wbm_working == 0);
6833 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6834
      // check WB INT signal
6835
      if (wb_int !== 1'b0)
6836
      begin
6837
        test_fail("WB INT signal should not be set");
6838
        fail = fail + 1;
6839
      end
6840
      // INTERMEDIATE DISPLAYS
6841
      if (i_length == 3)
6842
      begin
6843
        $display("    pads appending to packets is selected");
6844
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
6845
        $display("    ->packets with lengths from %0d to %0d are not transmitted (length increasing by 1 byte)",
6846
                 0, 3);
6847
      end
6848
      else if (i_length == 9)
6849
      begin
6850
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
6851
        $display("    ->packet with length 4 is not transmitted (length increasing by 1 byte)");
6852
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6853
                 5, 9);
6854
      end
6855
      else if (i_length == 17)
6856
      begin
6857
        $display("    using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3)");
6858
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6859
                 10, 17);
6860
      end
6861
      else if (i_length == 27)
6862
      begin
6863
        $display("    using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4)");
6864
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6865
                 18, 27);
6866
      end
6867
      else if (i_length == 40)
6868
      begin
6869
        $display("    using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5)");
6870
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6871
                 28, 40);
6872
      end
6873
      else if (i_length == 54)
6874
      begin
6875
        $display("    using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6)");
6876
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6877
                 41, 54);
6878
      end
6879
      else if (i_length == 69)
6880
      begin
6881
        $display("    using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7)");
6882
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6883
                 55, 69);
6884
      end
6885
      // set length (loop variable)
6886
      i_length = i_length + 1;
6887
      // the number of frame transmitted
6888
      num_of_frames = num_of_frames + 1;
6889
      if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
6890
          (num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
6891
          (num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
6892
          (num_of_frames == 54) || (num_of_frames == 62))
6893
        num_of_bd = 0;
6894
      else
6895
        num_of_bd = num_of_bd + 1;
6896
    end
6897
    // disable TX
6898
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
6899
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6900
    @(posedge wb_clk);
6901
    if(fail == 0)
6902
      test_ok;
6903
    else
6904
      fail = 0;
6905
  end
6906
 
6907
 
6908
  ////////////////////////////////////////////////////////////////////
6909
  ////                                                            ////
6910 243 tadejm
  ////  Test transmit packets (no pads) from 0 to (MINFL - 1)     ////
6911 209 tadejm
  ////  sizes at 8 TX buffer decriptors ( 10Mbps ).               ////
6912
  ////                                                            ////
6913
  ////////////////////////////////////////////////////////////////////
6914
  if (test_num == 8) // 
6915
  begin
6916 243 tadejm
    // TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )
6917
    test_name = "TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )";
6918
    `TIME; $display("  TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )");
6919 279 mohor
 
6920 209 tadejm
    // reset MAC registers
6921
    hard_reset;
6922
    // reset MAC and MII LOGIC with soft reset
6923 274 tadejm
//    reset_mac;
6924
//    reset_mii;
6925 209 tadejm
    // set wb slave response
6926
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
6927
 
6928
    max_tmp = 0;
6929
    min_tmp = 0;
6930
    // set 8 TX buffer descriptors - must be set before TX enable
6931 274 tadejm
    wait (wbm_working == 0);
6932 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h8, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6933
    // enable TX, set full-duplex mode, padding and CRC appending
6934 274 tadejm
    wait (wbm_working == 0);
6935 243 tadejm
//    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
6936
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD,
6937 209 tadejm
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6938
    // prepare two packets of MAXFL length
6939 274 tadejm
    wait (wbm_working == 0);
6940 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6941
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
6942
    min_tmp = tmp[31:16];
6943
    st_data = 8'h12;
6944
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
6945
    st_data = 8'h34;
6946
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp - 4), st_data); // length without CRC
6947
    // check WB INT signal
6948
    if (wb_int !== 1'b0)
6949
    begin
6950
      test_fail("WB INT signal should not be set");
6951
      fail = fail + 1;
6952
    end
6953
 
6954
    // write to phy's control register for 10Mbps
6955
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
6956
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
6957
    speed = 10;
6958
 
6959
    frame_started = 0;
6960
    num_of_frames = 0;
6961
    num_of_bd = 0;
6962
    i_length = 0; // 0;
6963
    while (i_length < 70) // (min_tmp - 4))
6964
    begin
6965
      #1;
6966
      // choose generating carrier sense and collision
6967
      case (i_length[1:0])
6968
      2'h0: // Interrupt is generated
6969
      begin
6970
        // Reset_tx_bd nable interrupt generation
6971
        // unmask interrupts
6972 274 tadejm
        wait (wbm_working == 0);
6973 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
6974
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6975
        // not detect carrier sense in FD and no collision
6976
        eth_phy.carrier_sense_tx_fd_detect(0);
6977
        eth_phy.collision(0);
6978
      end
6979
      2'h1: // Interrupt is not generated
6980
      begin
6981
        // set_tx_bd enable interrupt generation
6982
        // mask interrupts
6983 274 tadejm
        wait (wbm_working == 0);
6984 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6985
        // detect carrier sense in FD and no collision
6986
        eth_phy.carrier_sense_tx_fd_detect(1);
6987
        eth_phy.collision(0);
6988
      end
6989
      2'h2: // Interrupt is not generated
6990
      begin
6991
        // set_tx_bd disable the interrupt generation
6992
        // unmask interrupts
6993 274 tadejm
        wait (wbm_working == 0);
6994 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
6995
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6996
        // not detect carrier sense in FD and set collision
6997
        eth_phy.carrier_sense_tx_fd_detect(0);
6998
        eth_phy.collision(1);
6999
      end
7000
      default: // 2'h3: // Interrupt is not generated
7001
      begin
7002
        // set_tx_bd disable the interrupt generation
7003
        // mask interrupts
7004 274 tadejm
        wait (wbm_working == 0);
7005 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7006
        // detect carrier sense in FD and set collision
7007
        eth_phy.carrier_sense_tx_fd_detect(1);
7008
        eth_phy.collision(1);
7009
      end
7010
      endcase
7011 243 tadejm
//      // append CRC
7012
//      if ((i_length[0] == 1'b0) && (num_of_frames >= 6))
7013
//      begin
7014
//        append_tx_crc(`MEMORY_BASE, i_length, 1'b0);
7015
//      end
7016 209 tadejm
      #1;
7017
      // first destination address on ethernet PHY
7018
      eth_phy.set_tx_mem_addr(num_of_frames * 16);
7019
      // SET packets and wrap bit
7020
      // num_of_frames <= 9 => wrap set to TX BD 0
7021 243 tadejm
      if (num_of_frames <= 5)
7022
        begin
7023
          tmp_len = i_length; // length of frame
7024
          tmp_bd_num = 0; // TX BD number
7025
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7026
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7027 274 tadejm
 
7028 243 tadejm
          if (tmp_len[0] == 0) // CRC appended by 'HARDWARE'
7029 279 mohor
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, `MEMORY_BASE);
7030 243 tadejm
          else
7031 279 mohor
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
7032 243 tadejm
          // set wrap bit
7033
          set_tx_bd_wrap(0);
7034
        end
7035
        else if (num_of_frames <= 9)
7036
        begin
7037
          tmp_len = i_length; // length of frame
7038
          tmp_bd_num = 0; // TX BD number
7039
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7040
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7041
          if (tmp_len[0] == 0) // CRC appended by 'SOFTWARE'
7042 279 mohor
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
7043 243 tadejm
          else
7044
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
7045
          // set wrap bit
7046
          set_tx_bd_wrap(0);
7047 279 mohor
        end
7048
        // 10 <= num_of_frames < 18 => wrap set to TX BD 3
7049
        else if ((num_of_frames == 10) || (num_of_frames == 14))
7050 209 tadejm
        begin
7051 279 mohor
          tmp_len = i_length; // length of frame
7052
          tmp_bd_num = 0; // TX BD number
7053
          while (tmp_bd_num < 4)
7054
          begin
7055
            // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7056
            // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7057
            if (tmp_len[0] == 0)
7058
              set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
7059
            else
7060
              set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
7061
            tmp_len = tmp_len + 1;
7062
            // set TX BD number
7063
            tmp_bd_num = tmp_bd_num + 1;
7064
          end
7065
          // set wrap bit
7066
          set_tx_bd_wrap(3);
7067 209 tadejm
        end
7068
      // 18 <= num_of_frames < 28 => wrap set to TX BD 4
7069
      else if ((num_of_frames == 18) || (num_of_frames == 23))
7070
      begin
7071
        tmp_len = i_length; // length of frame
7072
        tmp_bd_num = 0; // TX BD number
7073
        while (tmp_bd_num < 5) //
7074
        begin
7075
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7076
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7077
          if (tmp_len[0] == 0)
7078 279 mohor
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
7079 243 tadejm
          else // when (num_of_frames == 23), (i_length == 23) and therefor i_length[0] == 1 !!!
7080
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1],
7081
                      ((num_of_frames == 23) && (tmp_bd_num == 0)), 1'b1, (`MEMORY_BASE + max_tmp));
7082 279 mohor
 
7083 209 tadejm
          tmp_len = tmp_len + 1;
7084
          // set TX BD number
7085
          tmp_bd_num = tmp_bd_num + 1;
7086
        end
7087
        // set wrap bit
7088
        set_tx_bd_wrap(4);
7089
      end
7090
      // 28 <= num_of_frames < 40 => wrap set to TX BD 5
7091
      else if ((num_of_frames == 28) || (num_of_frames == 34))
7092
      begin
7093
        tmp_len = i_length; // length of frame
7094
        tmp_bd_num = 0; // TX BD number
7095
        while (tmp_bd_num < 6) //
7096
        begin
7097
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7098
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7099
          if (tmp_len[0] == 0)
7100 279 mohor
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
7101 209 tadejm
          else
7102 243 tadejm
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
7103 209 tadejm
          tmp_len = tmp_len + 1;
7104
          // set TX BD number
7105
          tmp_bd_num = tmp_bd_num + 1;
7106
        end
7107
        // set wrap bit
7108
        set_tx_bd_wrap(5);
7109
      end
7110
      // 40 <= num_of_frames < 54 => wrap set to TX BD 6
7111
      else if ((num_of_frames == 40) || (num_of_frames == 47))
7112
      begin
7113
        tmp_len = i_length; // length of frame
7114
        tmp_bd_num = 0; // TX BD number
7115
        while (tmp_bd_num < 7) //
7116
        begin
7117
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7118
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7119
          if (tmp_len[0] == 0)
7120 279 mohor
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
7121 209 tadejm
          else
7122 243 tadejm
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
7123 209 tadejm
          tmp_len = tmp_len + 1;
7124
          // set TX BD number
7125
          tmp_bd_num = tmp_bd_num + 1;
7126
        end
7127
        // set wrap bit
7128
        set_tx_bd_wrap(6);
7129
      end
7130
      // 54 <= num_of_frames < 70 => wrap set to TX BD 7
7131
      else if ((num_of_frames == 54) || (num_of_frames == 62))
7132
      begin
7133
        tmp_len = i_length; // length of frame
7134
        tmp_bd_num = 0; // TX BD number
7135
        while (tmp_bd_num < 8) //
7136
        begin
7137
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7138
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7139
          if (tmp_len[0] == 0)
7140 279 mohor
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
7141 209 tadejm
          else
7142 243 tadejm
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
7143 209 tadejm
          tmp_len = tmp_len + 1;
7144
          // set TX BD number
7145
          tmp_bd_num = tmp_bd_num + 1;
7146
        end
7147
        // set wrap bit
7148
        set_tx_bd_wrap(7);
7149
      end
7150
      #1;
7151
      // SET ready bit
7152
      if (num_of_frames < 10)
7153
        set_tx_bd_ready(0, 0);
7154
      else if (num_of_frames < 14)
7155
        set_tx_bd_ready((num_of_frames - 10), (num_of_frames - 10));
7156
      else if (num_of_frames < 18)
7157
        set_tx_bd_ready((num_of_frames - 14), (num_of_frames - 14));
7158
      else if (num_of_frames < 23)
7159
        set_tx_bd_ready((num_of_frames - 18), (num_of_frames - 18));
7160
      else if (num_of_frames < 28)
7161
        set_tx_bd_ready((num_of_frames - 23), (num_of_frames - 23));
7162
      else if (num_of_frames < 34)
7163
        set_tx_bd_ready((num_of_frames - 28), (num_of_frames - 28));
7164
      else if (num_of_frames < 40)
7165
        set_tx_bd_ready((num_of_frames - 34), (num_of_frames - 34));
7166
      else if (num_of_frames < 47)
7167
        set_tx_bd_ready((num_of_frames - 40), (num_of_frames - 40));
7168
      else if (num_of_frames < 54)
7169
        set_tx_bd_ready((num_of_frames - 47), (num_of_frames - 47));
7170
      else if (num_of_frames < 62)
7171
        set_tx_bd_ready((num_of_frames - 54), (num_of_frames - 54));
7172
      else if (num_of_frames < 70)
7173
        set_tx_bd_ready((num_of_frames - 62), (num_of_frames - 62));
7174
      // CHECK END OF TRANSMITION
7175
      frame_started = 0;
7176
      if (num_of_frames >= 5)
7177
        #1 check_tx_bd(num_of_bd, data);
7178
      fork
7179
      begin: fr_st2
7180
        wait (MTxEn === 1'b1); // start transmit
7181
        frame_started = 1;
7182
      end
7183
      begin
7184
        repeat (30) @(posedge mtx_clk);
7185
        if (num_of_frames < 5)
7186
        begin
7187
          if (frame_started == 1)
7188
          begin
7189
            `TIME; $display("*E Frame should NOT start!");
7190
          end
7191
          disable fr_st2;
7192
        end
7193
        else
7194
        begin
7195
          if (frame_started == 0)
7196
          begin
7197
            `TIME; $display("*W Frame should start!");
7198
            disable fr_st2;
7199
          end
7200
        end
7201
      end
7202
      join
7203 279 mohor
 
7204
 
7205 209 tadejm
      // check packets larger than 4 bytes
7206
      if (num_of_frames >= 5)
7207
      begin
7208
        wait (MTxEn === 1'b0); // end transmit
7209
        while (data[15] === 1)
7210
        begin
7211
          #1 check_tx_bd(num_of_bd, data);
7212
          @(posedge wb_clk);
7213
        end
7214
        repeat (1) @(posedge wb_clk);
7215 274 tadejm
 
7216
 
7217 279 mohor
        // check length of a PACKET     // Check this if it is OK igor
7218
        if (num_of_frames < 6)
7219
          begin
7220
            if (eth_phy.tx_len != (i_length + 4))
7221
              begin
7222
                `TIME; $display("*E Wrong length of the packet out from MAC");
7223
                test_fail("Wrong length of the packet out from MAC");
7224
                fail = fail + 1;
7225
              end
7226
          end
7227
        else if (num_of_frames != 23) // 6 - 53 except 23
7228
          begin
7229
            if (i_length[0] == 1'b0)
7230
              begin
7231
                if (eth_phy.tx_len != i_length)
7232
                  begin
7233
                    `TIME; $display("*E Wrong length of the packet out from MAC");
7234
                    test_fail("Wrong length of the packet out from MAC");
7235
                    fail = fail + 1;
7236
                  end
7237
              end
7238
            else
7239
              begin
7240
                if (eth_phy.tx_len != (i_length + 4))
7241
                  begin
7242
                    `TIME; $display("*E Wrong length of the packet out from MAC");
7243
                    test_fail("Wrong length of the packet out from MAC");
7244
                    fail = fail + 1;
7245
                  end
7246
              end
7247
          end
7248
        else // num_of_frames == 23
7249
          begin
7250
            if (data[12]) // Padding
7251
              begin
7252
                if (eth_phy.tx_len != (64))
7253
                  begin
7254
                    `TIME; $display("*E Wrong length of the packet out from MAC");
7255
                    test_fail("Wrong length of the packet out from MAC");
7256
                    fail = fail + 1;
7257
                  end
7258
              end
7259
            else
7260
              begin
7261
                if (eth_phy.tx_len != (i_length + 4))
7262
                  begin
7263
                    `TIME; $display("*E Wrong length of the packet out from MAC");
7264
                    test_fail("Wrong length of the packet out from MAC");
7265
                    fail = fail + 1;
7266
                  end
7267
              end
7268
          end
7269
 
7270 209 tadejm
        // check transmitted TX packet data
7271
        if (i_length[0] == 0)
7272
        begin
7273
          #1 check_tx_packet(`MEMORY_BASE, (num_of_frames * 16), i_length, tmp);
7274
        end
7275 243 tadejm
        else if (num_of_frames == 23) // i_length[0] == 1 here
7276
        begin
7277 279 mohor
          #1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
7278
          #1 check_tx_packet( 0, (num_of_frames * 16 + i_length), (min_tmp - i_length - 4), tmp);
7279 243 tadejm
        end
7280 209 tadejm
        else
7281
        begin
7282
          #1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
7283
        end
7284
        if (tmp > 0)
7285
        begin
7286
          test_fail("Wrong data of the transmitted packet");
7287
          fail = fail + 1;
7288
        end
7289
        // check transmited TX packet CRC
7290 243 tadejm
        #1;
7291
        if ((i_length[0] == 1'b0) && (num_of_frames >= 6))
7292
        begin
7293
        end
7294
        else
7295
          check_tx_crc((num_of_frames * 16), (eth_phy.tx_len - 4), 1'b0, tmp); // length without CRC
7296 209 tadejm
        if (tmp > 0)
7297
        begin
7298
          test_fail("Wrong CRC of the transmitted packet");
7299
          fail = fail + 1;
7300
        end
7301
      end
7302
      // check WB INT signal
7303
      if ((i_length[1:0] == 2'h0) && (num_of_frames >= 5))
7304
      begin
7305
        if (wb_int !== 1'b1)
7306
        begin
7307
          `TIME; $display("*E WB INT signal should be set");
7308
          test_fail("WB INT signal should be set");
7309
          fail = fail + 1;
7310
        end
7311
      end
7312
      else
7313
      begin
7314
        if (wb_int !== 1'b0)
7315
        begin
7316
          `TIME; $display("*E WB INT signal should not be set");
7317
          test_fail("WB INT signal should not be set");
7318
          fail = fail + 1;
7319
        end
7320
      end
7321
      // check TX buffer descriptor of a packet
7322
      check_tx_bd(num_of_bd, data);
7323 279 mohor
 
7324 209 tadejm
      if (num_of_frames >= 5)
7325
      begin
7326 243 tadejm
        if ((i_length[1] == 1'b0) && (i_length[0] == 1'b0)) // interrupt enabled
7327 209 tadejm
        begin
7328 243 tadejm
          if ( (data[15:0] !== 16'h6000) &&  // wrap bit
7329
               (data[15:0] !== 16'h4000) )  // without wrap bit
7330 209 tadejm
          begin
7331 279 mohor
            `TIME; $display("*E TX buffer descriptor status is not correct 1: %0h", data[15:0]);
7332 209 tadejm
            test_fail("TX buffer descriptor status is not correct");
7333
            fail = fail + 1;
7334
          end
7335
        end
7336 243 tadejm
        else if ((i_length[1] == 1'b1) && (i_length[0] == 1'b0)) // interrupt not enabled
7337 209 tadejm
        begin
7338 243 tadejm
          if ( (data[15:0] !== 16'h2000) && // wrap bit
7339
               (data[15:0] !== 16'h0000) ) // without wrap bit
7340
          begin
7341 279 mohor
            `TIME; $display("*E TX buffer descriptor status is not correct 2: %0h", data[15:0]);
7342 243 tadejm
            test_fail("TX buffer descriptor status is not correct");
7343
            fail = fail + 1;
7344
          end
7345
        end
7346
        else if ((i_length[1] == 1'b0) && (i_length[0] == 1'b1)) // interrupt enabled
7347
        begin
7348
          if ( (data[15:0] !== 16'h6800) && // wrap bit
7349
               (data[15:0] !== 16'h4800) ) // without wrap bit
7350
          begin
7351 279 mohor
            `TIME; $display("*E TX buffer descriptor status is not correct 3: %0h", data[15:0]);
7352 243 tadejm
            test_fail("TX buffer descriptor status is not correct");
7353
            fail = fail + 1;
7354
          end
7355
        end
7356
        else if (num_of_frames != 23) // ((i_length[1] == 1'b1) && (i_length[0] == 1'b1)) // interrupt not enabled
7357
        begin
7358
          if ( (data[15:0] !== 16'h2800) && // wrap bit
7359
               (data[15:0] !== 16'h0800) ) // without wrap bit
7360
          begin
7361 279 mohor
            `TIME; $display("*E TX buffer descriptor status is not correct 4: %0h", data[15:0]);
7362 243 tadejm
            test_fail("TX buffer descriptor status is not correct");
7363
            fail = fail + 1;
7364
          end
7365
        end
7366
        else // ((num_of_frames != 23) && (i_length[1] == 1'b1) && (i_length[0] == 1'b1)) // interrupt not enabled
7367
        begin
7368 209 tadejm
          if ( (data[15:0] !== 16'h3800) && // wrap bit
7369
               (data[15:0] !== 16'h1800) ) // without wrap bit
7370
          begin
7371 279 mohor
            `TIME; $display("*E TX buffer descriptor status is not correct 5: %0h", data[15:0]);
7372 209 tadejm
            test_fail("TX buffer descriptor status is not correct");
7373
            fail = fail + 1;
7374
          end
7375
        end
7376
      end
7377
      else
7378
      begin
7379
        if (data[15] !== 1'b1)
7380
        begin
7381
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
7382
          test_fail("TX buffer descriptor status is not correct");
7383
          fail = fail + 1;
7384
        end
7385
      end
7386
      // clear TX BD with wrap bit
7387
      if (num_of_frames == 63)
7388
        clear_tx_bd(16, 16);
7389
      // check interrupts
7390 274 tadejm
      wait (wbm_working == 0);
7391 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7392
      if ( ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1)) && (num_of_frames >= 5) )
7393
      begin
7394
        if ((data & `ETH_INT_TXB) !== 1'b1)
7395
        begin
7396
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
7397
          test_fail("Interrupt Transmit Buffer was not set");
7398
          fail = fail + 1;
7399
        end
7400
        if ((data & (~`ETH_INT_TXB)) !== 0)
7401
        begin
7402
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
7403
          test_fail("Other interrupts (except Transmit Buffer) were set");
7404
          fail = fail + 1;
7405
        end
7406
      end
7407
      else
7408
      begin
7409
        if (data !== 0)
7410
        begin
7411
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
7412
          test_fail("Any of interrupts (except Transmit Buffer) was set");
7413
          fail = fail + 1;
7414
        end
7415
      end
7416
      // clear interrupts
7417 274 tadejm
      wait (wbm_working == 0);
7418 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7419
      // check WB INT signal
7420
      if (wb_int !== 1'b0)
7421
      begin
7422
        test_fail("WB INT signal should not be set");
7423
        fail = fail + 1;
7424
      end
7425
      // INTERMEDIATE DISPLAYS
7426
      if (i_length == 3)
7427
      begin
7428 279 mohor
        $display("    pads appending to packets is not selected (except for 0x23)");
7429 209 tadejm
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
7430
        $display("    ->packets with lengths from %0d to %0d are not transmitted (length increasing by 1 byte)",
7431
                 0, 3);
7432
      end
7433
      else if (i_length == 9)
7434
      begin
7435
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
7436
        $display("    ->packet with length 4 is not transmitted (length increasing by 1 byte)");
7437
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7438
                 5, 9);
7439
      end
7440
      else if (i_length == 17)
7441
      begin
7442
        $display("    using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3)");
7443
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7444
                 10, 17);
7445
      end
7446
      else if (i_length == 27)
7447
      begin
7448
        $display("    using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4)");
7449
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7450
                 18, 27);
7451
      end
7452
      else if (i_length == 40)
7453
      begin
7454
        $display("    using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5)");
7455
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7456
                 28, 40);
7457
      end
7458
      else if (i_length == 54)
7459
      begin
7460
        $display("    using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6)");
7461
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7462
                 41, 54);
7463
      end
7464
      else if (i_length == 69)
7465
      begin
7466
        $display("    using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7)");
7467
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7468
                 55, 69);
7469
      end
7470
      // set length (loop variable)
7471
      i_length = i_length + 1;
7472
      // the number of frame transmitted
7473
      num_of_frames = num_of_frames + 1;
7474
      if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
7475
          (num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
7476
          (num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
7477
          (num_of_frames == 54) || (num_of_frames == 62))
7478
        num_of_bd = 0;
7479
      else
7480
        num_of_bd = num_of_bd + 1;
7481
    end
7482
    // disable TX
7483 274 tadejm
    wait (wbm_working == 0);
7484 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
7485
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7486
    @(posedge wb_clk);
7487
    if(fail == 0)
7488
      test_ok;
7489
    else
7490
      fail = 0;
7491
  end
7492
 
7493
 
7494
  ////////////////////////////////////////////////////////////////////
7495
  ////                                                            ////
7496 243 tadejm
  ////  Test transmit packets (no pads) form 0 to (MINFL - 1)     ////
7497 209 tadejm
  ////  sizes at 8 TX buffer decriptors ( 100Mbps ).              ////
7498
  ////                                                            ////
7499
  ////////////////////////////////////////////////////////////////////
7500
  if (test_num == 9) // 
7501
  begin
7502 243 tadejm
    // TEST 9: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )
7503
    test_name = "TEST 9: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )";
7504
    `TIME; $display("  TEST 9: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )");
7505 209 tadejm
 
7506
    // reset MAC registers
7507
    hard_reset;
7508
    // reset MAC and MII LOGIC with soft reset
7509 274 tadejm
//    reset_mac;
7510
//    reset_mii;
7511 209 tadejm
    // set wb slave response
7512
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
7513
 
7514
    max_tmp = 0;
7515
    min_tmp = 0;
7516
    // set 8 TX buffer descriptors - must be set before TX enable
7517 274 tadejm
    wait (wbm_working == 0);
7518 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h8, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7519
    // enable TX, set full-duplex mode, padding and CRC appending
7520 274 tadejm
    wait (wbm_working == 0);
7521 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
7522
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7523
    // prepare two packets of MAXFL length
7524 274 tadejm
    wait (wbm_working == 0);
7525 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7526
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
7527
    min_tmp = tmp[31:16];
7528
    st_data = 8'h12;
7529
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
7530
    st_data = 8'h34;
7531
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp - 4), st_data); // length without CRC
7532
    // check WB INT signal
7533
    if (wb_int !== 1'b0)
7534
    begin
7535
      test_fail("WB INT signal should not be set");
7536
      fail = fail + 1;
7537
    end
7538
 
7539
    // write to phy's control register for 100Mbps
7540
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
7541
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
7542
    speed = 100;
7543
 
7544
    frame_started = 0;
7545
    num_of_frames = 0;
7546
    num_of_bd = 0;
7547
    i_length = 0; // 0;
7548
    while (i_length < 70) // (min_tmp - 4))
7549
    begin
7550
      #1;
7551
      // choose generating carrier sense and collision
7552
      case (i_length[1:0])
7553
      2'h0: // Interrupt is generated
7554
      begin
7555
        // Reset_tx_bd nable interrupt generation
7556
        // unmask interrupts
7557 274 tadejm
        wait (wbm_working == 0);
7558 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
7559
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7560
        // not detect carrier sense in FD and no collision
7561
        eth_phy.carrier_sense_tx_fd_detect(0);
7562
        eth_phy.collision(0);
7563
      end
7564
      2'h1: // Interrupt is not generated
7565
      begin
7566
        // set_tx_bd enable interrupt generation
7567
        // mask interrupts
7568 274 tadejm
        wait (wbm_working == 0);
7569 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7570
        // detect carrier sense in FD and no collision
7571
        eth_phy.carrier_sense_tx_fd_detect(1);
7572
        eth_phy.collision(0);
7573
      end
7574
      2'h2: // Interrupt is not generated
7575
      begin
7576
        // set_tx_bd disable the interrupt generation
7577
        // unmask interrupts
7578 274 tadejm
        wait (wbm_working == 0);
7579 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
7580
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7581
        // not detect carrier sense in FD and set collision
7582
        eth_phy.carrier_sense_tx_fd_detect(0);
7583
        eth_phy.collision(1);
7584
      end
7585
      default: // 2'h3: // Interrupt is not generated
7586
      begin
7587
        // set_tx_bd disable the interrupt generation
7588
        // mask interrupts
7589 274 tadejm
        wait (wbm_working == 0);
7590 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7591
        // detect carrier sense in FD and set collision
7592
        eth_phy.carrier_sense_tx_fd_detect(1);
7593
        eth_phy.collision(1);
7594
      end
7595
      endcase
7596
      #1;
7597
      // first destination address on ethernet PHY
7598
      eth_phy.set_tx_mem_addr(num_of_frames * 16);
7599
      // SET packets and wrap bit
7600
      // num_of_frames <= 9 => wrap set to TX BD 0
7601
      if (num_of_frames <= 9)
7602
      begin
7603
        tmp_len = i_length; // length of frame
7604
        tmp_bd_num = 0; // TX BD number
7605
        // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7606
        // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7607
        if (tmp_len[0] == 0)
7608
          set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
7609
        else
7610
          set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
7611
        // set wrap bit
7612
        set_tx_bd_wrap(0);
7613
      end
7614
      // 10 <= num_of_frames < 18 => wrap set to TX BD 3
7615
      else if ((num_of_frames == 10) || (num_of_frames == 14))
7616
      begin
7617
        tmp_len = i_length; // length of frame
7618
        tmp_bd_num = 0; // TX BD number
7619
        while (tmp_bd_num < 4) //
7620
        begin
7621
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7622
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7623
          if (tmp_len[0] == 0)
7624
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
7625
          else
7626
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
7627
          tmp_len = tmp_len + 1;
7628
          // set TX BD number
7629
          tmp_bd_num = tmp_bd_num + 1;
7630
        end
7631
        // set wrap bit
7632
        set_tx_bd_wrap(3);
7633
      end
7634
      // 18 <= num_of_frames < 28 => wrap set to TX BD 4
7635
      else if ((num_of_frames == 18) || (num_of_frames == 23))
7636
      begin
7637
        tmp_len = i_length; // length of frame
7638
        tmp_bd_num = 0; // TX BD number
7639
        while (tmp_bd_num < 5) //
7640
        begin
7641
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7642
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7643
          if (tmp_len[0] == 0)
7644
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
7645
          else
7646
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
7647
          tmp_len = tmp_len + 1;
7648
          // set TX BD number
7649
          tmp_bd_num = tmp_bd_num + 1;
7650
        end
7651
        // set wrap bit
7652
        set_tx_bd_wrap(4);
7653
      end
7654
      // 28 <= num_of_frames < 40 => wrap set to TX BD 5
7655
      else if ((num_of_frames == 28) || (num_of_frames == 34))
7656
      begin
7657
        tmp_len = i_length; // length of frame
7658
        tmp_bd_num = 0; // TX BD number
7659
        while (tmp_bd_num < 6) //
7660
        begin
7661
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7662
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7663
          if (tmp_len[0] == 0)
7664
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
7665
          else
7666
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
7667
          tmp_len = tmp_len + 1;
7668
          // set TX BD number
7669
          tmp_bd_num = tmp_bd_num + 1;
7670
        end
7671
        // set wrap bit
7672
        set_tx_bd_wrap(5);
7673
      end
7674
      // 40 <= num_of_frames < 54 => wrap set to TX BD 6
7675
      else if ((num_of_frames == 40) || (num_of_frames == 47))
7676
      begin
7677
        tmp_len = i_length; // length of frame
7678
        tmp_bd_num = 0; // TX BD number
7679
        while (tmp_bd_num < 7) //
7680
        begin
7681
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7682
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7683
          if (tmp_len[0] == 0)
7684
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
7685
          else
7686
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
7687
          tmp_len = tmp_len + 1;
7688
          // set TX BD number
7689
          tmp_bd_num = tmp_bd_num + 1;
7690
        end
7691
        // set wrap bit
7692
        set_tx_bd_wrap(6);
7693
      end
7694
      // 54 <= num_of_frames < 70 => wrap set to TX BD 7
7695
      else if ((num_of_frames == 54) || (num_of_frames == 62))
7696
      begin
7697
        tmp_len = i_length; // length of frame
7698
        tmp_bd_num = 0; // TX BD number
7699
        while (tmp_bd_num < 8) //
7700
        begin
7701
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7702
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7703
          if (tmp_len[0] == 0)
7704
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
7705
          else
7706
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
7707
          tmp_len = tmp_len + 1;
7708
          // set TX BD number
7709
          tmp_bd_num = tmp_bd_num + 1;
7710
        end
7711
        // set wrap bit
7712
        set_tx_bd_wrap(7);
7713
      end
7714
      #1;
7715
      // SET ready bit
7716
      if (num_of_frames < 10)
7717
        set_tx_bd_ready(0, 0);
7718
      else if (num_of_frames < 14)
7719
        set_tx_bd_ready((num_of_frames - 10), (num_of_frames - 10));
7720
      else if (num_of_frames < 18)
7721
        set_tx_bd_ready((num_of_frames - 14), (num_of_frames - 14));
7722
      else if (num_of_frames < 23)
7723
        set_tx_bd_ready((num_of_frames - 18), (num_of_frames - 18));
7724
      else if (num_of_frames < 28)
7725
        set_tx_bd_ready((num_of_frames - 23), (num_of_frames - 23));
7726
      else if (num_of_frames < 34)
7727
        set_tx_bd_ready((num_of_frames - 28), (num_of_frames - 28));
7728
      else if (num_of_frames < 40)
7729
        set_tx_bd_ready((num_of_frames - 34), (num_of_frames - 34));
7730
      else if (num_of_frames < 47)
7731
        set_tx_bd_ready((num_of_frames - 40), (num_of_frames - 40));
7732
      else if (num_of_frames < 54)
7733
        set_tx_bd_ready((num_of_frames - 47), (num_of_frames - 47));
7734
      else if (num_of_frames < 62)
7735
        set_tx_bd_ready((num_of_frames - 54), (num_of_frames - 54));
7736
      else if (num_of_frames < 70)
7737
        set_tx_bd_ready((num_of_frames - 62), (num_of_frames - 62));
7738
      // CHECK END OF TRANSMITION
7739
      frame_started = 0;
7740
      if (num_of_frames >= 5)
7741
        #1 check_tx_bd(num_of_bd, data);
7742
      fork
7743
      begin: fr_st3
7744
        wait (MTxEn === 1'b1); // start transmit
7745
        frame_started = 1;
7746
      end
7747
      begin
7748 279 mohor
        repeat (50) @(posedge mtx_clk);
7749
$display("(%0t) num_of_frames = 0x%0x", $time, num_of_frames);
7750 209 tadejm
        if (num_of_frames < 5)
7751
        begin
7752
          if (frame_started == 1)
7753
          begin
7754
            `TIME; $display("*E Frame should NOT start!");
7755
          end
7756
          disable fr_st3;
7757
        end
7758
        else
7759
        begin
7760
          if (frame_started == 0)
7761
          begin
7762
            `TIME; $display("*W Frame should start!");
7763 279 mohor
#500 $stop;
7764 209 tadejm
            disable fr_st3;
7765
          end
7766
        end
7767
      end
7768
      join
7769
      // check packets larger than 4 bytes
7770
      if (num_of_frames >= 5)
7771
      begin
7772
        wait (MTxEn === 1'b0); // end transmit
7773
        while (data[15] === 1)
7774
        begin
7775
          #1 check_tx_bd(num_of_bd, data);
7776
          @(posedge wb_clk);
7777
        end
7778
        repeat (1) @(posedge wb_clk);
7779
        // check length of a PACKET
7780 279 mohor
        if ((num_of_frames + 4) < 64)
7781
          begin
7782
            if (eth_phy.tx_len != 64)
7783
            begin
7784
              `TIME; $display("*E Wrong length of the packet out from MAC");
7785
              test_fail("Wrong length of the packet out from MAC");
7786
              fail = fail + 1;
7787
            end
7788
          end
7789
        else
7790
          begin
7791 209 tadejm
        if (eth_phy.tx_len != (i_length + 4))
7792
        begin
7793
          `TIME; $display("*E Wrong length of the packet out from MAC");
7794
          test_fail("Wrong length of the packet out from MAC");
7795
          fail = fail + 1;
7796
        end
7797 279 mohor
          end
7798 209 tadejm
        // check transmitted TX packet data
7799
        if (i_length[0] == 0)
7800
        begin
7801
          #1 check_tx_packet(`MEMORY_BASE, (num_of_frames * 16), i_length, tmp);
7802
        end
7803
        else
7804
        begin
7805
          #1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
7806
        end
7807
        if (tmp > 0)
7808
        begin
7809
          test_fail("Wrong data of the transmitted packet");
7810
          fail = fail + 1;
7811
        end
7812
        // check transmited TX packet CRC
7813
        #1 check_tx_crc((num_of_frames * 16), (eth_phy.tx_len - 4), 1'b0, tmp); // length without CRC
7814
        if (tmp > 0)
7815
        begin
7816
          test_fail("Wrong CRC of the transmitted packet");
7817
          fail = fail + 1;
7818
        end
7819
      end
7820
      // check WB INT signal
7821
      if ((i_length[1:0] == 2'h0) && (num_of_frames >= 5))
7822
      begin
7823
        if (wb_int !== 1'b1)
7824
        begin
7825
          `TIME; $display("*E WB INT signal should be set");
7826
          test_fail("WB INT signal should be set");
7827
          fail = fail + 1;
7828
        end
7829
      end
7830
      else
7831
      begin
7832
        if (wb_int !== 1'b0)
7833
        begin
7834
          `TIME; $display("*E WB INT signal should not be set");
7835
          test_fail("WB INT signal should not be set");
7836
          fail = fail + 1;
7837
        end
7838
      end
7839
      // check TX buffer descriptor of a packet
7840
      check_tx_bd(num_of_bd, data);
7841
      if (num_of_frames >= 5)
7842
      begin
7843
        if (i_length[1] == 1'b0) // interrupt enabled
7844
        begin
7845
          if ( (data[15:0] !== 16'h7800) && // wrap bit
7846
               (data[15:0] !== 16'h5800) ) // without wrap bit
7847
          begin
7848
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
7849
            test_fail("TX buffer descriptor status is not correct");
7850
            fail = fail + 1;
7851
          end
7852
        end
7853
        else // interrupt not enabled
7854
        begin
7855
          if ( (data[15:0] !== 16'h3800) && // wrap bit
7856
               (data[15:0] !== 16'h1800) ) // without wrap bit
7857
          begin
7858
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
7859
            test_fail("TX buffer descriptor status is not correct");
7860
            fail = fail + 1;
7861
          end
7862
        end
7863
      end
7864
      else
7865
      begin
7866
        if (data[15] !== 1'b1)
7867
        begin
7868
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
7869
          test_fail("TX buffer descriptor status is not correct");
7870
          fail = fail + 1;
7871
        end
7872
      end
7873
      // clear TX BD with wrap bit
7874
      if (num_of_frames == 63)
7875
        clear_tx_bd(16, 16);
7876
      // check interrupts
7877 274 tadejm
      wait (wbm_working == 0);
7878 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7879
      if ( ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1)) && (num_of_frames >= 5) )
7880
      begin
7881
        if ((data & `ETH_INT_TXB) !== 1'b1)
7882
        begin
7883
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
7884
          test_fail("Interrupt Transmit Buffer was not set");
7885
          fail = fail + 1;
7886
        end
7887
        if ((data & (~`ETH_INT_TXB)) !== 0)
7888
        begin
7889
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
7890
          test_fail("Other interrupts (except Transmit Buffer) were set");
7891
          fail = fail + 1;
7892
        end
7893
      end
7894
      else
7895
      begin
7896
        if (data !== 0)
7897
        begin
7898
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
7899
          test_fail("Any of interrupts (except Transmit Buffer) was set");
7900
          fail = fail + 1;
7901
        end
7902
      end
7903
      // clear interrupts
7904 274 tadejm
      wait (wbm_working == 0);
7905 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7906
      // check WB INT signal
7907
      if (wb_int !== 1'b0)
7908
      begin
7909
        test_fail("WB INT signal should not be set");
7910
        fail = fail + 1;
7911
      end
7912
      // INTERMEDIATE DISPLAYS
7913
      if (i_length == 3)
7914
      begin
7915
        $display("    pads appending to packets is selected");
7916
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
7917
        $display("    ->packets with lengths from %0d to %0d are not transmitted (length increasing by 1 byte)",
7918
                 0, 3);
7919
      end
7920
      else if (i_length == 9)
7921
      begin
7922
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
7923
        $display("    ->packet with length 4 is not transmitted (length increasing by 1 byte)");
7924
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7925
                 5, 9);
7926
      end
7927
      else if (i_length == 17)
7928
      begin
7929
        $display("    using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3)");
7930
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7931
                 10, 17);
7932
      end
7933
      else if (i_length == 27)
7934
      begin
7935
        $display("    using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4)");
7936
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7937
                 18, 27);
7938
      end
7939
      else if (i_length == 40)
7940
      begin
7941
        $display("    using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5)");
7942
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7943
                 28, 40);
7944
      end
7945
      else if (i_length == 54)
7946
      begin
7947
        $display("    using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6)");
7948
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7949
                 41, 54);
7950
      end
7951
      else if (i_length == 69)
7952
      begin
7953
        $display("    using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7)");
7954
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7955
                 55, 69);
7956
      end
7957
      // set length (loop variable)
7958
      i_length = i_length + 1;
7959
      // the number of frame transmitted
7960
      num_of_frames = num_of_frames + 1;
7961
      if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
7962
          (num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
7963
          (num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
7964
          (num_of_frames == 54) || (num_of_frames == 62))
7965
        num_of_bd = 0;
7966
      else
7967
        num_of_bd = num_of_bd + 1;
7968
    end
7969
    // disable TX
7970 274 tadejm
    wait (wbm_working == 0);
7971 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
7972
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7973
    @(posedge wb_clk);
7974
    if(fail == 0)
7975
      test_ok;
7976
    else
7977
      fail = 0;
7978
  end
7979
 
7980
 
7981
  ////////////////////////////////////////////////////////////////////
7982
  ////                                                            ////
7983
  ////  Test transmit packets across MAXFL value at               ////
7984
  ////  13 TX buffer decriptors ( 10Mbps ).                       ////
7985
  ////                                                            ////
7986
  ////////////////////////////////////////////////////////////////////
7987
  if (test_num == 10) // without and with padding
7988
  begin
7989
    // TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )
7990
    test_name = "TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )";
7991
    `TIME; $display("  TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )");
7992
 
7993
    // reset MAC registers
7994
    hard_reset;
7995
    // set wb slave response
7996
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
7997
 
7998
    max_tmp = 0;
7999
    min_tmp = 0;
8000
    num_of_frames = 0;
8001
    num_of_bd = 0;
8002
    // set 13 TX buffer descriptors - must be set before TX enable
8003 274 tadejm
    wait (wbm_working == 0);
8004 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'hD, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8005
    // enable TX, set full-duplex mode, NO padding and CRC appending
8006 274 tadejm
    wait (wbm_working == 0);
8007 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
8008
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8009
    // prepare a packet of MAXFL + 10 length
8010 274 tadejm
    wait (wbm_working == 0);
8011 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8012
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
8013
    min_tmp = tmp[31:16];
8014
    st_data = 8'hA3;
8015
    set_tx_packet(`MEMORY_BASE, (max_tmp + 10), st_data); // length without CRC
8016
    // check WB INT signal
8017
    if (wb_int !== 1'b0)
8018
    begin
8019
      test_fail("WB INT signal should not be set");
8020
      fail = fail + 1;
8021
    end
8022
 
8023
    // write to phy's control register for 10Mbps
8024
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
8025
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
8026
    speed = 10;
8027
 
8028
    i_length = (max_tmp - 5);
8029 279 mohor
    while (num_of_bd <= 3)
8030 209 tadejm
    begin
8031 279 mohor
      // unmask interrupts
8032
      wait (wbm_working == 0);
8033
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
8034
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8035
      // not detect carrier sense in FD and no collision
8036
      eth_phy.carrier_sense_tx_fd_detect(0);
8037
      eth_phy.collision(0);
8038 209 tadejm
      // first destination address on ethernet PHY
8039
      eth_phy.set_tx_mem_addr(0);
8040
 
8041 279 mohor
      if (num_of_bd == 0)
8042
      begin
8043
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8044
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8045
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8046
        set_tx_bd_wrap(2);
8047
        set_tx_bd_ready(0, 0);
8048
      end
8049
      else if (num_of_bd == 1)
8050
        set_tx_bd_ready(1, 1);
8051
      else if (num_of_bd == 2)
8052
        set_tx_bd_ready(2, 2);
8053
      else if (num_of_bd == 3)
8054
      begin
8055
        set_tx_bd(0, 0, 100, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8056
        set_tx_bd_wrap(2);
8057
        set_tx_bd_ready(0, 0);
8058
        i_length = 96;
8059
      end
8060
 
8061 209 tadejm
 
8062
      // CHECK END OF TRANSMITION
8063 279 mohor
      check_tx_bd(num_of_bd, data);
8064
      wait (MTxEn === 1'b1); // start transmit
8065
      check_tx_bd(num_of_bd, data);
8066
      if (data[15] !== 1)
8067
      begin
8068
        test_fail("Wrong buffer descriptor's ready bit read out from MAC");
8069
        fail = fail + 1;
8070
      end
8071
      wait (MTxEn === 1'b0); // end transmit
8072
      while (data[15] === 1)
8073
      begin
8074
        check_tx_bd(num_of_bd, data);
8075
        @(posedge wb_clk);
8076
      end
8077
      repeat (1) @(posedge wb_clk);
8078 209 tadejm
      // check length of a PACKET
8079 279 mohor
      tmp_len = eth_phy.tx_len;
8080
      #1;
8081
      if (tmp_len != (i_length + 4))
8082 209 tadejm
      begin
8083
        test_fail("Wrong length of the packet out from MAC");
8084
        fail = fail + 1;
8085
      end
8086 279 mohor
 
8087
      // check transmitted TX packet data
8088
      if ((i_length + 4) == 100)
8089
        check_tx_packet(`MEMORY_BASE, 0, 100 - 4, tmp);
8090
      else if ((i_length + 4) <= max_tmp)
8091
        check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
8092
      else
8093
        check_tx_packet(`MEMORY_BASE, 0, max_tmp - 4, tmp);
8094
 
8095
      if (tmp > 0)
8096
      begin
8097
        test_fail("Wrong data of the transmitted packet");
8098
        fail = fail + 1;
8099
      end
8100
 
8101
      // check transmited TX packet CRC
8102
      if ((i_length + 4) == 100)
8103
        check_tx_crc(0, 100, 1'b0, tmp); // length without CRC
8104
      else if ((i_length + 4) <= max_tmp)
8105
        check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
8106
 
8107
      if (tmp > 0)
8108
      begin
8109
        test_fail("Wrong CRC of the transmitted packet");
8110
        fail = fail + 1;
8111
      end
8112
 
8113
      if (wb_int !== 1'b1)
8114
      begin
8115
        `TIME; $display("*E WB INT signal should be set");
8116
        test_fail("WB INT signal should be set");
8117
        fail = fail + 1;
8118
      end
8119
 
8120
      check_tx_bd(num_of_bd, data);
8121
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
8122
           ((data[15:0] !== 16'h5800) && (num_of_bd < 2)) )   // without wrap bit
8123
      begin
8124
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
8125
        test_fail("TX buffer descriptor status is not correct");
8126
        fail = fail + 1;
8127
      end
8128
 
8129 209 tadejm
      // check interrupts
8130 274 tadejm
      wait (wbm_working == 0);
8131 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8132 279 mohor
      if ((data & `ETH_INT_TXB) !== `ETH_INT_TXB)
8133
      begin
8134
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
8135
        test_fail("Interrupt Transmit Buffer was not set");
8136
        fail = fail + 1;
8137
      end
8138
      if ((data & (~`ETH_INT_TXB)) !== 0)
8139
      begin
8140
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
8141
        test_fail("Other interrupts (except Transmit Buffer) were set");
8142
        fail = fail + 1;
8143
      end
8144
 
8145 209 tadejm
      // clear interrupts
8146 274 tadejm
      wait (wbm_working == 0);
8147 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8148
      // check WB INT signal
8149
      if (wb_int !== 1'b0)
8150
      begin
8151
        test_fail("WB INT signal should not be set");
8152
        fail = fail + 1;
8153
      end
8154 279 mohor
 
8155 209 tadejm
      // INTERMEDIATE DISPLAYS
8156 279 mohor
      if (num_of_bd == 0)
8157
        $display("    ->packet with length %0d sent", (i_length + 4));
8158
      else if (num_of_bd == 1)
8159
        $display("    ->packet with length %0d sent", (i_length + 4));
8160
      else if (num_of_bd == 2)
8161
        $display("    ->packet with length %0d sent", (i_length + 4));
8162
      else if (num_of_bd == 3)
8163
        $display("    ->packet with length %0d sent", (104));
8164 209 tadejm
      // set length (loop variable)
8165
      i_length = i_length + 1;
8166
      // the number of frame transmitted
8167
      num_of_frames = num_of_frames + 1;
8168
      num_of_bd = num_of_bd + 1;
8169
      @(posedge wb_clk);
8170
    end
8171
    // disable TX
8172 274 tadejm
    wait (wbm_working == 0);
8173 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
8174
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8175
    @(posedge wb_clk);
8176
    if(fail == 0)
8177
      test_ok;
8178
    else
8179
      fail = 0;
8180
  end
8181
 
8182
 
8183
  ////////////////////////////////////////////////////////////////////
8184
  ////                                                            ////
8185
  ////  Test transmit packets across MAXFL value at               ////
8186 279 mohor
  ////  13 TX buffer decriptors ( 100Mbps ).                       ////
8187 209 tadejm
  ////                                                            ////
8188
  ////////////////////////////////////////////////////////////////////
8189
  if (test_num == 11) // without and with padding
8190
  begin
8191
    // TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )
8192
    test_name = "TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )";
8193
    `TIME; $display("  TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )");
8194 279 mohor
 
8195 209 tadejm
    // reset MAC registers
8196
    hard_reset;
8197
    // set wb slave response
8198
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
8199
 
8200
    max_tmp = 0;
8201
    min_tmp = 0;
8202
    num_of_frames = 0;
8203
    num_of_bd = 0;
8204
    // set 13 TX buffer descriptors - must be set before TX enable
8205 274 tadejm
    wait (wbm_working == 0);
8206 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'hD, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8207
    // enable TX, set full-duplex mode, NO padding and CRC appending
8208 274 tadejm
    wait (wbm_working == 0);
8209 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
8210
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8211
    // prepare a packet of MAXFL + 10 length
8212 274 tadejm
    wait (wbm_working == 0);
8213 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8214
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
8215
    min_tmp = tmp[31:16];
8216
    st_data = 8'hA3;
8217
    set_tx_packet(`MEMORY_BASE, (max_tmp + 10), st_data); // length without CRC
8218
    // check WB INT signal
8219
    if (wb_int !== 1'b0)
8220
    begin
8221
      test_fail("WB INT signal should not be set");
8222
      fail = fail + 1;
8223
    end
8224 279 mohor
 
8225
    // write to phy's control register for 10Mbps
8226
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 reset - speed 100
8227
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
8228 209 tadejm
    speed = 100;
8229
 
8230
    i_length = (max_tmp - 5);
8231 279 mohor
    while (num_of_bd <= 3)
8232 209 tadejm
    begin
8233
      // unmask interrupts
8234 274 tadejm
      wait (wbm_working == 0);
8235 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
8236
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8237
      // not detect carrier sense in FD and no collision
8238
      eth_phy.carrier_sense_tx_fd_detect(0);
8239
      eth_phy.collision(0);
8240
      // first destination address on ethernet PHY
8241
      eth_phy.set_tx_mem_addr(0);
8242 279 mohor
 
8243 209 tadejm
      if (num_of_bd == 0)
8244
      begin
8245
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8246
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8247
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8248
        set_tx_bd_wrap(2);
8249
        set_tx_bd_ready(0, 0);
8250
      end
8251
      else if (num_of_bd == 1)
8252
        set_tx_bd_ready(1, 1);
8253
      else if (num_of_bd == 2)
8254
        set_tx_bd_ready(2, 2);
8255 279 mohor
      else if (num_of_bd == 3)
8256
      begin
8257
        set_tx_bd(0, 0, 100, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8258
        set_tx_bd_wrap(2);
8259
        set_tx_bd_ready(0, 0);
8260
        i_length = 96;
8261
      end
8262
 
8263
 
8264 209 tadejm
      // CHECK END OF TRANSMITION
8265
      check_tx_bd(num_of_bd, data);
8266 279 mohor
      wait (MTxEn === 1'b1); // start transmit
8267 209 tadejm
      check_tx_bd(num_of_bd, data);
8268 279 mohor
      if (data[15] !== 1)
8269
      begin
8270
        test_fail("Wrong buffer descriptor's ready bit read out from MAC");
8271
        fail = fail + 1;
8272
      end
8273
      wait (MTxEn === 1'b0); // end transmit
8274
      while (data[15] === 1)
8275
      begin
8276
        check_tx_bd(num_of_bd, data);
8277
        @(posedge wb_clk);
8278
      end
8279
      repeat (1) @(posedge wb_clk);
8280
      repeat (10) @(posedge mtx_clk);
8281 209 tadejm
      // check length of a PACKET
8282
      tmp_len = eth_phy.tx_len;
8283
      #1;
8284
      if (tmp_len != (i_length + 4))
8285
      begin
8286
        test_fail("Wrong length of the packet out from MAC");
8287
        fail = fail + 1;
8288
      end
8289 279 mohor
 
8290
      // check transmitted TX packet data
8291
      if ((i_length + 4) == 100)
8292
        check_tx_packet(`MEMORY_BASE, 0, 100 - 4, tmp);
8293
      else if ((i_length + 4) <= max_tmp)
8294
        check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
8295
      else
8296
        check_tx_packet(`MEMORY_BASE, 0, max_tmp - 4, tmp);
8297
 
8298 209 tadejm
      if (tmp > 0)
8299
      begin
8300
        test_fail("Wrong data of the transmitted packet");
8301
        fail = fail + 1;
8302
      end
8303 279 mohor
 
8304 209 tadejm
      // check transmited TX packet CRC
8305 279 mohor
      if ((i_length + 4) == 100)
8306
        check_tx_crc(0, 100, 1'b0, tmp); // length without CRC
8307
      else if ((i_length + 4) <= max_tmp)
8308
        check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
8309
 
8310 209 tadejm
      if (tmp > 0)
8311
      begin
8312
        test_fail("Wrong CRC of the transmitted packet");
8313
        fail = fail + 1;
8314
      end
8315 279 mohor
 
8316 209 tadejm
      if (wb_int !== 1'b1)
8317
      begin
8318
        `TIME; $display("*E WB INT signal should be set");
8319
        test_fail("WB INT signal should be set");
8320
        fail = fail + 1;
8321
      end
8322 279 mohor
 
8323 209 tadejm
      check_tx_bd(num_of_bd, data);
8324
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
8325
           ((data[15:0] !== 16'h5800) && (num_of_bd < 2)) )   // without wrap bit
8326
      begin
8327
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
8328
        test_fail("TX buffer descriptor status is not correct");
8329
        fail = fail + 1;
8330
      end
8331 279 mohor
 
8332 209 tadejm
      // check interrupts
8333 274 tadejm
      wait (wbm_working == 0);
8334 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8335 279 mohor
      if ((data & `ETH_INT_TXB) !== `ETH_INT_TXB)
8336 209 tadejm
      begin
8337
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
8338
        test_fail("Interrupt Transmit Buffer was not set");
8339
        fail = fail + 1;
8340
      end
8341
      if ((data & (~`ETH_INT_TXB)) !== 0)
8342
      begin
8343
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
8344
        test_fail("Other interrupts (except Transmit Buffer) were set");
8345
        fail = fail + 1;
8346
      end
8347 279 mohor
 
8348 209 tadejm
      // clear interrupts
8349 274 tadejm
      wait (wbm_working == 0);
8350 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8351
      // check WB INT signal
8352
      if (wb_int !== 1'b0)
8353
      begin
8354
        test_fail("WB INT signal should not be set");
8355
        fail = fail + 1;
8356
      end
8357 279 mohor
 
8358 209 tadejm
      // INTERMEDIATE DISPLAYS
8359
      if (num_of_bd == 0)
8360
        $display("    ->packet with length %0d sent", (i_length + 4));
8361
      else if (num_of_bd == 1)
8362
        $display("    ->packet with length %0d sent", (i_length + 4));
8363
      else if (num_of_bd == 2)
8364
        $display("    ->packet with length %0d sent", (i_length + 4));
8365 279 mohor
      else if (num_of_bd == 3)
8366
        $display("    ->packet with length %0d sent", (104));
8367 209 tadejm
      // set length (loop variable)
8368
      i_length = i_length + 1;
8369
      // the number of frame transmitted
8370
      num_of_frames = num_of_frames + 1;
8371
      num_of_bd = num_of_bd + 1;
8372
      @(posedge wb_clk);
8373
    end
8374
    // disable TX
8375 274 tadejm
    wait (wbm_working == 0);
8376 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
8377
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8378
    @(posedge wb_clk);
8379
    if(fail == 0)
8380
      test_ok;
8381
    else
8382
      fail = 0;
8383
  end
8384
 
8385
 
8386 279 mohor
 
8387
 
8388 209 tadejm
  ////////////////////////////////////////////////////////////////////
8389
  ////                                                            ////
8390
  ////  Test transmit packets across changed MAXFL value at       ////
8391
  ////  47 TX buffer decriptors ( 10Mbps ).                       ////
8392
  ////                                                            ////
8393
  ////////////////////////////////////////////////////////////////////
8394
  if (test_num == 12) // without and with padding
8395
  begin
8396
    // TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )
8397
    test_name = "TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )";
8398
    `TIME; $display("  TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )");
8399
 
8400
    // reset MAC registers
8401
    hard_reset;
8402
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
8403
 
8404
    max_tmp = 0;
8405
    min_tmp = 0;
8406
    num_of_frames = 0;
8407
    num_of_bd = 0;
8408
    // set 47 TX buffer descriptors - must be set before TX enable
8409 274 tadejm
    wait (wbm_working == 0);
8410 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h2F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8411
    // prepare a packet of MAXFL + 10 length
8412 274 tadejm
    wait (wbm_working == 0);
8413 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8414
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
8415
    min_tmp = tmp[31:16];
8416
    // change MAXFL value
8417
    max_tmp = min_tmp + 53;
8418 274 tadejm
    wait (wbm_working == 0);
8419 209 tadejm
    wbm_write(`ETH_PACKETLEN, {min_tmp, max_tmp}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8420
    st_data = 8'h62;
8421
    set_tx_packet(`MEMORY_BASE, max_tmp, st_data); // length with CRC
8422 274 tadejm
    wait (wbm_working == 0);
8423 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD,
8424
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8425
    // check WB INT signal
8426
    if (wb_int !== 1'b0)
8427
    begin
8428
      test_fail("WB INT signal should not be set");
8429
      fail = fail + 1;
8430
    end
8431
 
8432
    // write to phy's control register for 10Mbps
8433
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
8434
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
8435
    speed = 10;
8436
 
8437
    i_length = (max_tmp - 5); // (max_tmp - 1); // not (max_tmp - 5) because NO automatic CRC appending
8438
    while (i_length <= (max_tmp - 3)) // (max_tmp + 1)) // (max_tmp) is the limit
8439
    begin
8440 274 tadejm
      wait (wbm_working == 0);
8441 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
8442
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8443
      // not detect carrier sense in FD and no collision
8444
      eth_phy.carrier_sense_tx_fd_detect(0);
8445
      eth_phy.collision(0);
8446
      // first destination address on ethernet PHY
8447
      eth_phy.set_tx_mem_addr(0);
8448
      // prepare BDs
8449
      if (num_of_bd == 0)
8450
      begin
8451
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8452
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8453
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8454
        set_tx_bd_wrap(2);
8455
        set_tx_bd_ready(0, 0);
8456
      end
8457
      else if (num_of_bd == 1)
8458
        set_tx_bd_ready(1, 1);
8459
      else if (num_of_bd == 2)
8460
        set_tx_bd_ready(2, 2);
8461
      // CHECK END OF TRANSMITION
8462
      check_tx_bd(num_of_bd, data);
8463
        wait (MTxEn === 1'b1); // start transmit
8464
      check_tx_bd(num_of_bd, data);
8465
        if (data[15] !== 1)
8466
        begin
8467
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
8468
          fail = fail + 1;
8469
        end
8470
        wait (MTxEn === 1'b0); // end transmit
8471
        while (data[15] === 1)
8472
        begin
8473
      check_tx_bd(num_of_bd, data);
8474
          @(posedge wb_clk);
8475
        end
8476 279 mohor
        repeat (5) @(posedge mtx_clk);
8477 209 tadejm
      // check length of a PACKET
8478
      tmp_len = eth_phy.tx_len;
8479
      #1;
8480
      if (tmp_len != (i_length + 4))
8481
      begin
8482
        test_fail("Wrong length of the packet out from MAC");
8483
        fail = fail + 1;
8484
      end
8485
      // checking packet
8486
      check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
8487
      if (tmp > 0)
8488
      begin
8489
        test_fail("Wrong data of the transmitted packet");
8490
        fail = fail + 1;
8491
      end
8492
      // check transmited TX packet CRC
8493 279 mohor
      if (num_of_bd !== 2)
8494
        check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
8495 209 tadejm
      if (tmp > 0)
8496
      begin
8497
        test_fail("Wrong CRC of the transmitted packet");
8498
        fail = fail + 1;
8499
      end
8500
      // check WB INT signal
8501
      if (wb_int !== 1'b1)
8502
      begin
8503
        `TIME; $display("*E WB INT signal should be set");
8504
        test_fail("WB INT signal should be set");
8505
        fail = fail + 1;
8506
      end
8507
      // check TX buffer descriptor of a packet
8508
      check_tx_bd(num_of_bd, data);
8509
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
8510
           ((data[15:0] !== 16'h5800) && (num_of_bd < 2)) )   // without wrap bit
8511
      begin
8512
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
8513
        test_fail("TX buffer descriptor status is not correct");
8514
        fail = fail + 1;
8515
      end
8516
      // check interrupts
8517 274 tadejm
      wait (wbm_working == 0);
8518 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8519
      if ((data & `ETH_INT_TXB) !== 1'b1)
8520
      begin
8521
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
8522
        test_fail("Interrupt Transmit Buffer was not set");
8523
        fail = fail + 1;
8524
      end
8525
      if ((data & (~`ETH_INT_TXB)) !== 0)
8526
      begin
8527
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
8528
        test_fail("Other interrupts (except Transmit Buffer) were set");
8529
        fail = fail + 1;
8530
      end
8531
      // clear interrupts
8532 274 tadejm
      wait (wbm_working == 0);
8533 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8534
      // check WB INT signal
8535
      if (wb_int !== 1'b0)
8536
      begin
8537
        test_fail("WB INT signal should not be set");
8538
        fail = fail + 1;
8539
      end
8540
      // INTERMEDIATE DISPLAYS
8541
      if (num_of_bd == 0)
8542
        $display("    ->packet with length %0d sent", (i_length + 4));
8543
      else if (num_of_bd == 1)
8544
        $display("    ->packet with length %0d sent", (i_length + 4));
8545
      else if (num_of_bd == 2)
8546
        $display("    ->packet with length %0d sent", (i_length + 4));
8547
      // set length (loop variable)
8548
      i_length = i_length + 1;
8549
      // the number of frame transmitted
8550
      num_of_frames = num_of_frames + 1;
8551
      num_of_bd = num_of_bd + 1;
8552
      @(posedge wb_clk);
8553
    end
8554
    // disable TX
8555 274 tadejm
    wait (wbm_working == 0);
8556 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
8557
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8558
    @(posedge wb_clk);
8559
    if(fail == 0)
8560
      test_ok;
8561
    else
8562
      fail = 0;
8563
  end
8564
 
8565
 
8566
  ////////////////////////////////////////////////////////////////////
8567
  ////                                                            ////
8568
  ////  Test transmit packets across changed MAXFL value at       ////
8569
  ////  47 TX buffer decriptors ( 100Mbps ).                      ////
8570
  ////                                                            ////
8571
  ////////////////////////////////////////////////////////////////////
8572
  if (test_num == 13) // without and with padding
8573
  begin
8574
    // TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )
8575
    test_name = "TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )";
8576
    `TIME; $display("  TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )");
8577
 
8578
    // reset MAC registers
8579
    hard_reset;
8580
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
8581
 
8582
    max_tmp = 0;
8583
    min_tmp = 0;
8584
    num_of_frames = 0;
8585
    num_of_bd = 0;
8586
    // set 47 TX buffer descriptors - must be set before TX enable
8587 274 tadejm
    wait (wbm_working == 0);
8588 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h2F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8589
    // prepare a packet of MAXFL + 10 length
8590 274 tadejm
    wait (wbm_working == 0);
8591 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8592
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
8593
    min_tmp = tmp[31:16];
8594
    // change MAXFL value
8595
    max_tmp = min_tmp + 53;
8596 274 tadejm
    wait (wbm_working == 0);
8597 209 tadejm
    wbm_write(`ETH_PACKETLEN, {min_tmp, max_tmp}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8598
    st_data = 8'h62;
8599
    set_tx_packet(`MEMORY_BASE, max_tmp, st_data); // length with CRC
8600 274 tadejm
    wait (wbm_working == 0);
8601 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD,
8602
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8603
    // check WB INT signal
8604
    if (wb_int !== 1'b0)
8605
    begin
8606
      test_fail("WB INT signal should not be set");
8607
      fail = fail + 1;
8608
    end
8609
 
8610 279 mohor
    // write to phy's control register for 10Mbps
8611
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 reset - speed 100
8612
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
8613 209 tadejm
    speed = 100;
8614
 
8615
    i_length = (max_tmp - 5); // (max_tmp - 1); // not (max_tmp - 5) because NO automatic CRC appending
8616
    while (i_length <= (max_tmp - 3)) // (max_tmp + 1)) // (max_tmp) is the limit
8617
    begin
8618 274 tadejm
      wait (wbm_working == 0);
8619 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
8620
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8621
      // not detect carrier sense in FD and no collision
8622
      eth_phy.carrier_sense_tx_fd_detect(0);
8623
      eth_phy.collision(0);
8624
      // first destination address on ethernet PHY
8625
      eth_phy.set_tx_mem_addr(0);
8626
      // prepare BDs
8627
      if (num_of_bd == 0)
8628
      begin
8629
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8630
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8631
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8632
        set_tx_bd_wrap(2);
8633
        set_tx_bd_ready(0, 0);
8634
      end
8635
      else if (num_of_bd == 1)
8636
        set_tx_bd_ready(1, 1);
8637
      else if (num_of_bd == 2)
8638
        set_tx_bd_ready(2, 2);
8639
      // CHECK END OF TRANSMITION
8640
      check_tx_bd(num_of_bd, data);
8641
        wait (MTxEn === 1'b1); // start transmit
8642
      check_tx_bd(num_of_bd, data);
8643
        if (data[15] !== 1)
8644
        begin
8645
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
8646
          fail = fail + 1;
8647
        end
8648
        wait (MTxEn === 1'b0); // end transmit
8649
        while (data[15] === 1)
8650
        begin
8651
      check_tx_bd(num_of_bd, data);
8652
          @(posedge wb_clk);
8653
        end
8654 279 mohor
        repeat (5) @(posedge mtx_clk);
8655 209 tadejm
      // check length of a PACKET
8656
      tmp_len = eth_phy.tx_len;
8657
      #1;
8658
      if (tmp_len != (i_length + 4))
8659
      begin
8660
        test_fail("Wrong length of the packet out from MAC");
8661
        fail = fail + 1;
8662
      end
8663
      // checking packet
8664
      check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
8665
      if (tmp > 0)
8666
      begin
8667
        test_fail("Wrong data of the transmitted packet");
8668
        fail = fail + 1;
8669
      end
8670
      // check transmited TX packet CRC
8671 279 mohor
      if (num_of_bd !== 2)
8672
        check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
8673 209 tadejm
      if (tmp > 0)
8674
      begin
8675
        test_fail("Wrong CRC of the transmitted packet");
8676
        fail = fail + 1;
8677
      end
8678
      // check WB INT signal
8679
      if (wb_int !== 1'b1)
8680
      begin
8681
        `TIME; $display("*E WB INT signal should be set");
8682
        test_fail("WB INT signal should be set");
8683
        fail = fail + 1;
8684
      end
8685
      // check TX buffer descriptor of a packet
8686
      check_tx_bd(num_of_bd, data);
8687
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
8688
           ((data[15:0] !== 16'h5800) && (num_of_bd < 2)) )   // without wrap bit
8689
      begin
8690
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
8691
        test_fail("TX buffer descriptor status is not correct");
8692
        fail = fail + 1;
8693
      end
8694
      // check interrupts
8695 274 tadejm
      wait (wbm_working == 0);
8696 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8697
      if ((data & `ETH_INT_TXB) !== 1'b1)
8698
      begin
8699
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
8700
        test_fail("Interrupt Transmit Buffer was not set");
8701
        fail = fail + 1;
8702
      end
8703
      if ((data & (~`ETH_INT_TXB)) !== 0)
8704
      begin
8705
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
8706
        test_fail("Other interrupts (except Transmit Buffer) were set");
8707
        fail = fail + 1;
8708
      end
8709
      // clear interrupts
8710 274 tadejm
      wait (wbm_working == 0);
8711 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8712
      // check WB INT signal
8713
      if (wb_int !== 1'b0)
8714
      begin
8715
        test_fail("WB INT signal should not be set");
8716
        fail = fail + 1;
8717
      end
8718
      // INTERMEDIATE DISPLAYS
8719
      if (num_of_bd == 0)
8720
        $display("    ->packet with length %0d sent", (i_length + 4));
8721
      else if (num_of_bd == 1)
8722
        $display("    ->packet with length %0d sent", (i_length + 4));
8723
      else if (num_of_bd == 2)
8724
        $display("    ->packet with length %0d sent", (i_length + 4));
8725
      // set length (loop variable)
8726
      i_length = i_length + 1;
8727
      // the number of frame transmitted
8728
      num_of_frames = num_of_frames + 1;
8729
      num_of_bd = num_of_bd + 1;
8730
      @(posedge wb_clk);
8731
    end
8732
    // disable TX
8733 274 tadejm
    wait (wbm_working == 0);
8734 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
8735
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8736
    @(posedge wb_clk);
8737
    if(fail == 0)
8738
      test_ok;
8739
    else
8740
      fail = 0;
8741
  end
8742
 
8743
 
8744
  ////////////////////////////////////////////////////////////////////
8745
  ////                                                            ////
8746
  ////  Test transmit packets across changed MINFL value at       ////
8747
  ////  7 TX buffer decriptors ( 10Mbps ).                        ////
8748
  ////                                                            ////
8749
  ////////////////////////////////////////////////////////////////////
8750
  if (test_num == 14) // without and with padding
8751
  begin
8752
    // TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )
8753
    test_name = "TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )";
8754
    `TIME; $display("  TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )");
8755
 
8756
    // reset MAC registers
8757
    hard_reset;
8758 279 mohor
 
8759 209 tadejm
    // set wb slave response
8760
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
8761
 
8762
    max_tmp = 0;
8763
    min_tmp = 0;
8764
    num_of_frames = 0;
8765
    num_of_bd = 0;
8766
    // set 7 TX buffer descriptors - must be set before TX enable
8767 274 tadejm
    wait (wbm_working == 0);
8768 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h7, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8769
    // prepare a packet of MAXFL + 10 length
8770 274 tadejm
    wait (wbm_working == 0);
8771 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8772
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
8773
    min_tmp = tmp[31:16];
8774 279 mohor
 
8775 209 tadejm
    // change MINFL value
8776
    min_tmp = max_tmp - 177;
8777 274 tadejm
    wait (wbm_working == 0);
8778 209 tadejm
    wbm_write(`ETH_PACKETLEN, {min_tmp, max_tmp}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8779
    st_data = 8'h62;
8780
    set_tx_packet(`MEMORY_BASE, min_tmp, st_data); // length without CRC
8781
    // enable TX, set full-duplex mode, padding and CRC appending
8782 274 tadejm
    wait (wbm_working == 0);
8783 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
8784
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8785
    // check WB INT signal
8786
    if (wb_int !== 1'b0)
8787
    begin
8788
      test_fail("WB INT signal should not be set");
8789
      fail = fail + 1;
8790
    end
8791
 
8792
    // write to phy's control register for 10Mbps
8793
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
8794
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
8795
    speed = 10;
8796
 
8797
    i_length = (min_tmp - 5);
8798
    while (i_length <= (min_tmp - 3)) // (min_tmp - 4) is the limit
8799
    begin
8800
      // Reset_tx_bd nable interrupt generation
8801
      // unmask interrupts
8802 274 tadejm
      wait (wbm_working == 0);
8803 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
8804
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8805
      // not detect carrier sense in FD and no collision
8806
      eth_phy.carrier_sense_tx_fd_detect(0);
8807
      eth_phy.collision(0);
8808
      // first destination address on ethernet PHY
8809
      eth_phy.set_tx_mem_addr(0);
8810
      // prepare BDs
8811
      if (num_of_bd == 0)
8812
      begin
8813
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8814
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8815
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8816
        set_tx_bd_wrap(2);
8817
        set_tx_bd_ready(0, 0);
8818
      end
8819
      else if (num_of_bd == 1)
8820
        set_tx_bd_ready(1, 1);
8821
      else if (num_of_bd == 2)
8822
        set_tx_bd_ready(2, 2);
8823
      // CHECK END OF TRANSMITION
8824
      check_tx_bd(num_of_bd, data);
8825
        wait (MTxEn === 1'b1); // start transmit
8826
      check_tx_bd(num_of_bd, data);
8827
        if (data[15] !== 1)
8828
        begin
8829
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
8830
          fail = fail + 1;
8831
        end
8832
        wait (MTxEn === 1'b0); // end transmit
8833
        while (data[15] === 1)
8834
        begin
8835
      check_tx_bd(num_of_bd, data);
8836
          @(posedge wb_clk);
8837
        end
8838
        repeat (1) @(posedge wb_clk);
8839
      // check length of a PACKET
8840
      tmp_len = eth_phy.tx_len;
8841
      #1;
8842
      if (tmp_len != (i_length + 4))
8843
      begin
8844
        test_fail("Wrong length of the packet out from MAC");
8845
        fail = fail + 1;
8846
      end
8847
      // checking packet
8848
      check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
8849
      if (tmp > 0)
8850
      begin
8851
        test_fail("Wrong data of the transmitted packet");
8852
        fail = fail + 1;
8853
      end
8854
      // check transmited TX packet CRC
8855 279 mohor
      if (num_of_bd !== 0)  // First packet is padded and CRC does not match.
8856
        check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
8857
      else
8858
        tmp = 0;
8859 209 tadejm
      if (tmp > 0)
8860
      begin
8861
        test_fail("Wrong CRC of the transmitted packet");
8862
        fail = fail + 1;
8863
      end
8864
      // check WB INT signal
8865
      if (wb_int !== 1'b1)
8866
      begin
8867
        `TIME; $display("*E WB INT signal should be set");
8868
        test_fail("WB INT signal should be set");
8869
        fail = fail + 1;
8870
      end
8871
      // check TX buffer descriptor of a packet
8872
      check_tx_bd(num_of_bd, data);
8873
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
8874
           ((data[15:0] !== 16'h5800) && (num_of_bd < 2)) )   // without wrap bit
8875
      begin
8876
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
8877
        test_fail("TX buffer descriptor status is not correct");
8878
        fail = fail + 1;
8879
      end
8880
      // check interrupts
8881 274 tadejm
      wait (wbm_working == 0);
8882 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8883
      if ((data & `ETH_INT_TXB) !== 1'b1)
8884
      begin
8885
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
8886
        test_fail("Interrupt Transmit Buffer was not set");
8887
        fail = fail + 1;
8888
      end
8889
      if ((data & (~`ETH_INT_TXB)) !== 0)
8890
      begin
8891
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
8892
        test_fail("Other interrupts (except Transmit Buffer) were set");
8893
        fail = fail + 1;
8894
      end
8895
      // clear interrupts
8896 274 tadejm
      wait (wbm_working == 0);
8897 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8898
      // check WB INT signal
8899
      if (wb_int !== 1'b0)
8900
      begin
8901
        test_fail("WB INT signal should not be set");
8902
        fail = fail + 1;
8903
      end
8904
      // INTERMEDIATE DISPLAYS
8905
      if (num_of_bd == 0)
8906
        $display("    ->packet with length %0d sent", (i_length + 4));
8907
      else if (num_of_bd == 1)
8908
        $display("    ->packet with length %0d sent", (i_length + 4));
8909
      else if (num_of_bd == 2)
8910
        $display("    ->packet with length %0d sent", (i_length + 4));
8911
      // set length (loop variable)
8912
      i_length = i_length + 1;
8913
      // the number of frame transmitted
8914
      num_of_frames = num_of_frames + 1;
8915
      num_of_bd = num_of_bd + 1;
8916
      @(posedge wb_clk);
8917
    end
8918
    // disable TX
8919 274 tadejm
    wait (wbm_working == 0);
8920 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
8921
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8922
    @(posedge wb_clk);
8923
    if(fail == 0)
8924
      test_ok;
8925
    else
8926
      fail = 0;
8927
  end
8928
 
8929
 
8930
  ////////////////////////////////////////////////////////////////////
8931
  ////                                                            ////
8932
  ////  Test transmit packets across changed MINFL value at       ////
8933
  ////  7 TX buffer decriptors ( 100Mbps ).                       ////
8934
  ////                                                            ////
8935
  ////////////////////////////////////////////////////////////////////
8936
  if (test_num == 15) // without and with padding
8937
  begin
8938
    // TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )
8939
    test_name = "TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )";
8940
    `TIME; $display("  TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )");
8941
 
8942
    hard_reset;
8943 279 mohor
 
8944 209 tadejm
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
8945
 
8946
    max_tmp = 0;
8947
    min_tmp = 0;
8948
    num_of_frames = 0;
8949
    num_of_bd = 0;
8950
    // set 7 TX buffer descriptors - must be set before TX enable
8951 274 tadejm
    wait (wbm_working == 0);
8952 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h7, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8953
    // prepare a packet of MAXFL + 10 length
8954 274 tadejm
    wait (wbm_working == 0);
8955 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8956
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
8957
    min_tmp = tmp[31:16];
8958
    // change MINFL value
8959
    min_tmp = max_tmp - 177;
8960 274 tadejm
    wait (wbm_working == 0);
8961 209 tadejm
    wbm_write(`ETH_PACKETLEN, {min_tmp, max_tmp}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8962
    st_data = 8'h62;
8963
    set_tx_packet(`MEMORY_BASE, min_tmp, st_data); // length without CRC
8964
    // enable TX, set full-duplex mode, padding and CRC appending
8965 274 tadejm
    wait (wbm_working == 0);
8966 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
8967
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8968
    // check WB INT signal
8969
    if (wb_int !== 1'b0)
8970
    begin
8971
      test_fail("WB INT signal should not be set");
8972
      fail = fail + 1;
8973
    end
8974
 
8975
    // write to phy's control register for 100Mbps
8976
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
8977
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
8978
    speed = 100;
8979
 
8980
    i_length = (min_tmp - 5);
8981
    while (i_length <= (min_tmp - 3)) // (min_tmp - 4) is the limit
8982
    begin
8983
      // Reset_tx_bd nable interrupt generation
8984
      // unmask interrupts
8985 274 tadejm
      wait (wbm_working == 0);
8986 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
8987
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8988
      // not detect carrier sense in FD and no collision
8989
      eth_phy.carrier_sense_tx_fd_detect(0);
8990
      eth_phy.collision(0);
8991
      // first destination address on ethernet PHY
8992
      eth_phy.set_tx_mem_addr(0);
8993
      // prepare BDs
8994
      if (num_of_bd == 0)
8995
      begin
8996
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8997
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8998
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8999
        set_tx_bd_wrap(2);
9000
        set_tx_bd_ready(0, 0);
9001
      end
9002
      else if (num_of_bd == 1)
9003
        set_tx_bd_ready(1, 1);
9004
      else if (num_of_bd == 2)
9005
        set_tx_bd_ready(2, 2);
9006
      // CHECK END OF TRANSMITION
9007
      check_tx_bd(num_of_bd, data);
9008
        wait (MTxEn === 1'b1); // start transmit
9009
      check_tx_bd(num_of_bd, data);
9010
        if (data[15] !== 1)
9011
        begin
9012
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
9013
          fail = fail + 1;
9014
        end
9015
        wait (MTxEn === 1'b0); // end transmit
9016
        while (data[15] === 1)
9017
        begin
9018
      check_tx_bd(num_of_bd, data);
9019
          @(posedge wb_clk);
9020
        end
9021
        repeat (1) @(posedge wb_clk);
9022
      // check length of a PACKET
9023
      tmp_len = eth_phy.tx_len;
9024
      #1;
9025
      if (tmp_len != (i_length + 4))
9026
      begin
9027
        test_fail("Wrong length of the packet out from MAC");
9028
        fail = fail + 1;
9029
      end
9030
      // checking packet
9031
      check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
9032
      if (tmp > 0)
9033
      begin
9034
        test_fail("Wrong data of the transmitted packet");
9035
        fail = fail + 1;
9036
      end
9037
      // check transmited TX packet CRC
9038 279 mohor
      if (num_of_bd !== 0)
9039
        check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
9040
      else
9041
        tmp = 0;
9042
 
9043 209 tadejm
      if (tmp > 0)
9044
      begin
9045
        test_fail("Wrong CRC of the transmitted packet");
9046
        fail = fail + 1;
9047
      end
9048
      // check WB INT signal
9049
      if (wb_int !== 1'b1)
9050
      begin
9051
        `TIME; $display("*E WB INT signal should be set");
9052
        test_fail("WB INT signal should be set");
9053
        fail = fail + 1;
9054
      end
9055
      // check TX buffer descriptor of a packet
9056
      check_tx_bd(num_of_bd, data);
9057
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
9058
           ((data[15:0] !== 16'h5800) && (num_of_bd < 2)) )   // without wrap bit
9059
      begin
9060
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
9061
        test_fail("TX buffer descriptor status is not correct");
9062
        fail = fail + 1;
9063
      end
9064
      // check interrupts
9065 274 tadejm
      wait (wbm_working == 0);
9066 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9067
      if ((data & `ETH_INT_TXB) !== 1'b1)
9068
      begin
9069
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
9070
        test_fail("Interrupt Transmit Buffer was not set");
9071
        fail = fail + 1;
9072
      end
9073
      if ((data & (~`ETH_INT_TXB)) !== 0)
9074
      begin
9075
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
9076
        test_fail("Other interrupts (except Transmit Buffer) were set");
9077
        fail = fail + 1;
9078
      end
9079
      // clear interrupts
9080 274 tadejm
      wait (wbm_working == 0);
9081 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9082
      // check WB INT signal
9083
      if (wb_int !== 1'b0)
9084
      begin
9085
        test_fail("WB INT signal should not be set");
9086
        fail = fail + 1;
9087
      end
9088
      // INTERMEDIATE DISPLAYS
9089
      if (num_of_bd == 0)
9090
        $display("    ->packet with length %0d sent", (i_length + 4));
9091
      else if (num_of_bd == 1)
9092
        $display("    ->packet with length %0d sent", (i_length + 4));
9093
      else if (num_of_bd == 2)
9094
        $display("    ->packet with length %0d sent", (i_length + 4));
9095
      // set length (loop variable)
9096
      i_length = i_length + 1;
9097
      // the number of frame transmitted
9098
      num_of_frames = num_of_frames + 1;
9099
      num_of_bd = num_of_bd + 1;
9100
      @(posedge wb_clk);
9101
    end
9102
    // disable TX
9103 274 tadejm
    wait (wbm_working == 0);
9104 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
9105
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9106
    @(posedge wb_clk);
9107
    if(fail == 0)
9108
      test_ok;
9109
    else
9110
      fail = 0;
9111
  end
9112
 
9113
 
9114
  ////////////////////////////////////////////////////////////////////
9115
  ////                                                            ////
9116
  ////  Test transmit packets across MAXFL with HUGEN at          ////
9117
  ////  19 TX buffer decriptors ( 10Mbps ).                       ////
9118
  ////                                                            ////
9119
  ////////////////////////////////////////////////////////////////////
9120
  if (test_num == 16) // without and with padding
9121
  begin
9122
    // TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps )
9123
    test_name = "TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps )";
9124
    `TIME; $display("  TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps )");
9125
 
9126
    // reset MAC registers
9127
    hard_reset;
9128
    // reset MAC and MII LOGIC with soft reset
9129 274 tadejm
//    reset_mac;
9130
//    reset_mii;
9131 209 tadejm
    // set wb slave response
9132
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
9133
 
9134
    max_tmp = 0;
9135
    min_tmp = 0;
9136
    num_of_frames = 0;
9137
    num_of_bd = 0;
9138
    // set 19 TX buffer descriptors - must be set before TX enable
9139 274 tadejm
    wait (wbm_working == 0);
9140 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h13, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9141
    // prepare a packet of 64k - 1 length (16'hFFFF)
9142 274 tadejm
    wait (wbm_working == 0);
9143 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9144
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
9145
    min_tmp = tmp[31:16];
9146
    st_data = 8'h8D;
9147
    set_tx_packet(`MEMORY_BASE, 16'hFFFF, st_data); // length with CRC
9148
    // enable TX, set full-duplex mode, NO padding, CRC appending and huge enabled
9149 274 tadejm
    wait (wbm_working == 0);
9150 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN | `ETH_MODER_HUGEN,
9151
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9152
    // check WB INT signal
9153
    if (wb_int !== 1'b0)
9154
    begin
9155
      test_fail("WB INT signal should not be set");
9156
      fail = fail + 1;
9157
    end
9158
 
9159
    // write to phy's control register for 10Mbps
9160
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
9161
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
9162
    speed = 10;
9163
 
9164
    i_length = (max_tmp - 5); // (max_tmp - 4) is the MAXFL limit
9165
    while (i_length <= (16'hFFFF - 4)) // (16'hFFFF - 4) is the limit
9166
    begin
9167
      $display("   i_length = %0d", i_length);
9168
      // Reset_tx_bd nable interrupt generation
9169
      // unmask interrupts
9170 274 tadejm
      wait (wbm_working == 0);
9171 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
9172
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9173
      // not detect carrier sense in FD and no collision
9174
      eth_phy.carrier_sense_tx_fd_detect(0);
9175
      eth_phy.collision(0);
9176
      // first destination address on ethernet PHY
9177
      eth_phy.set_tx_mem_addr(0);
9178
      // prepare BDs
9179
      if (num_of_bd == 0)
9180
      begin
9181
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9182
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9183
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9184
        set_tx_bd(3, 3, (16'hFFFF - 5), 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9185
        set_tx_bd(4, 4, (16'hFFFF - 4), 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9186
        set_tx_bd_wrap(4);
9187
        set_tx_bd_ready(0, 0);
9188
      end
9189
      else if (num_of_bd == 1)
9190
        set_tx_bd_ready(1, 1);
9191
      else if (num_of_bd == 2)
9192
        set_tx_bd_ready(2, 2);
9193
      else if (num_of_bd == 3)
9194
        set_tx_bd_ready(3, 3);
9195
      else if (num_of_bd == 4)
9196
        set_tx_bd_ready(4, 4);
9197
      // CHECK END OF TRANSMITION
9198
      check_tx_bd(num_of_bd, data);
9199
        wait (MTxEn === 1'b1); // start transmit
9200
      check_tx_bd(num_of_bd, data);
9201
        if (data[15] !== 1)
9202
        begin
9203
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
9204
          fail = fail + 1;
9205
        end
9206
        wait (MTxEn === 1'b0); // end transmit
9207
        while (data[15] === 1)
9208
        begin
9209
      check_tx_bd(num_of_bd, data);
9210
          @(posedge wb_clk);
9211
        end
9212
        repeat (1) @(posedge wb_clk);
9213
      // check length of a PACKET
9214
      $display("   eth_phy length = %0d", eth_phy.tx_len);
9215
      tmp_len = eth_phy.tx_len;
9216
      #1;
9217
      if (tmp_len != (i_length + 4))
9218
      begin
9219
        test_fail("Wrong length of the packet out from MAC");
9220
        fail = fail + 1;
9221
      end
9222
      // checking packet
9223
      check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
9224
      if (tmp > 0)
9225
      begin
9226
        test_fail("Wrong data of the transmitted packet");
9227
        fail = fail + 1;
9228
      end
9229
      // check transmited TX packet CRC
9230
      check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
9231
      if (tmp > 0)
9232
      begin
9233
        test_fail("Wrong CRC of the transmitted packet");
9234
        fail = fail + 1;
9235
      end
9236
      // check WB INT signal
9237
      if (wb_int !== 1'b1)
9238
      begin
9239
        `TIME; $display("*E WB INT signal should be set");
9240
        test_fail("WB INT signal should be set");
9241
        fail = fail + 1;
9242
      end
9243
      // check TX buffer descriptor of a packet
9244
      check_tx_bd(num_of_bd, data);
9245
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 4)) || // wrap bit
9246
           ((data[15:0] !== 16'h5800) && (num_of_bd < 4)) )   // without wrap bit
9247
      begin
9248
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
9249
        test_fail("TX buffer descriptor status is not correct");
9250
        fail = fail + 1;
9251
      end
9252
      // check interrupts
9253 274 tadejm
      wait (wbm_working == 0);
9254 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9255
      if ((data & `ETH_INT_TXB) !== 1'b1)
9256
      begin
9257
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
9258
        test_fail("Interrupt Transmit Buffer was not set");
9259
        fail = fail + 1;
9260
      end
9261
      if ((data & (~`ETH_INT_TXB)) !== 0)
9262
      begin
9263
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
9264
        test_fail("Other interrupts (except Transmit Buffer) were set");
9265
        fail = fail + 1;
9266
      end
9267
      // clear interrupts
9268 274 tadejm
      wait (wbm_working == 0);
9269 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9270
      // check WB INT signal
9271
      if (wb_int !== 1'b0)
9272
      begin
9273
        test_fail("WB INT signal should not be set");
9274
        fail = fail + 1;
9275
      end
9276
      // INTERMEDIATE DISPLAYS
9277
      $display("    ->packet with length %0d sent", (i_length + 4));
9278
      // set length (loop variable)
9279
      if ((num_of_bd < 2) || (num_of_bd >= 3))
9280
        i_length = i_length + 1;
9281
      else if (num_of_bd == 2)
9282
        i_length = (16'hFFFF - 5);
9283
      // the number of frame transmitted
9284
      num_of_frames = num_of_frames + 1;
9285
      num_of_bd = num_of_bd + 1;
9286
      @(posedge wb_clk);
9287
    end
9288
    // disable TX
9289 274 tadejm
    wait (wbm_working == 0);
9290 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
9291
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9292
    @(posedge wb_clk);
9293
    if(fail == 0)
9294
      test_ok;
9295
    else
9296
      fail = 0;
9297
  end
9298
 
9299
 
9300
  ////////////////////////////////////////////////////////////////////
9301
  ////                                                            ////
9302
  ////  Test transmit packets across MAXFL with HUGEN at          ////
9303
  ////  19 TX buffer decriptors ( 100Mbps ).                      ////
9304
  ////                                                            ////
9305
  ////////////////////////////////////////////////////////////////////
9306
  if (test_num == 17) // without and with padding
9307
  begin
9308
    // TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps )
9309
    test_name = "TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps )";
9310
    `TIME; $display("  TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps )");
9311
 
9312
    // reset MAC registers
9313
    hard_reset;
9314
    // reset MAC and MII LOGIC with soft reset
9315 274 tadejm
//    reset_mac;
9316
//    reset_mii;
9317 209 tadejm
    // set wb slave response
9318
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
9319
 
9320
    max_tmp = 0;
9321
    min_tmp = 0;
9322
    num_of_frames = 0;
9323
    num_of_bd = 0;
9324
    // set 19 TX buffer descriptors - must be set before TX enable
9325 274 tadejm
    wait (wbm_working == 0);
9326 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h13, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9327
    // prepare a packet of 64k - 1 length (16'hFFFF)
9328 274 tadejm
    wait (wbm_working == 0);
9329 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9330
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
9331
    min_tmp = tmp[31:16];
9332
    st_data = 8'h8D;
9333
    set_tx_packet(`MEMORY_BASE, 16'hFFFF, st_data); // length with CRC
9334
    // enable TX, set full-duplex mode, NO padding, CRC appending and huge enabled
9335 274 tadejm
    wait (wbm_working == 0);
9336 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN | `ETH_MODER_HUGEN,
9337
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9338
    // check WB INT signal
9339
    if (wb_int !== 1'b0)
9340
    begin
9341
      test_fail("WB INT signal should not be set");
9342
      fail = fail + 1;
9343
    end
9344
 
9345
    // write to phy's control register for 100Mbps
9346
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
9347
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
9348
    speed = 100;
9349
 
9350
    i_length = (max_tmp - 5); // (max_tmp - 4) is the MAXFL limit
9351
    while (i_length <= (16'hFFFF - 4)) // (16'hFFFF - 4) is the limit
9352
    begin
9353
      $display("   i_length = %0d", i_length);
9354
      // Reset_tx_bd nable interrupt generation
9355
      // unmask interrupts
9356 274 tadejm
      wait (wbm_working == 0);
9357 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
9358
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9359
      // not detect carrier sense in FD and no collision
9360
      eth_phy.carrier_sense_tx_fd_detect(0);
9361
      eth_phy.collision(0);
9362
      // first destination address on ethernet PHY
9363
      eth_phy.set_tx_mem_addr(0);
9364
      // prepare BDs
9365
      if (num_of_bd == 0)
9366
      begin
9367
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9368
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9369
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9370
        set_tx_bd(3, 3, (16'hFFFF - 5), 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9371
        set_tx_bd(4, 4, (16'hFFFF - 4), 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9372
        set_tx_bd_wrap(4);
9373
        set_tx_bd_ready(0, 0);
9374
      end
9375
      else if (num_of_bd == 1)
9376
        set_tx_bd_ready(1, 1);
9377
      else if (num_of_bd == 2)
9378
        set_tx_bd_ready(2, 2);
9379
      else if (num_of_bd == 3)
9380
        set_tx_bd_ready(3, 3);
9381
      else if (num_of_bd == 4)
9382
        set_tx_bd_ready(4, 4);
9383
      // CHECK END OF TRANSMITION
9384
      check_tx_bd(num_of_bd, data);
9385
        wait (MTxEn === 1'b1); // start transmit
9386
      check_tx_bd(num_of_bd, data);
9387
        if (data[15] !== 1)
9388
        begin
9389
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
9390
          fail = fail + 1;
9391
        end
9392
        wait (MTxEn === 1'b0); // end transmit
9393
        while (data[15] === 1)
9394
        begin
9395
      check_tx_bd(num_of_bd, data);
9396
          @(posedge wb_clk);
9397
        end
9398
        repeat (1) @(posedge wb_clk);
9399
      // check length of a PACKET
9400
      $display("   eth_phy length = %0d", eth_phy.tx_len);
9401
      tmp_len = eth_phy.tx_len;
9402
      #1;
9403
      if (tmp_len != (i_length + 4))
9404
      begin
9405
        test_fail("Wrong length of the packet out from MAC");
9406
        fail = fail + 1;
9407
      end
9408
      // checking packet
9409
      check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
9410
      if (tmp > 0)
9411
      begin
9412
        test_fail("Wrong data of the transmitted packet");
9413
        fail = fail + 1;
9414
      end
9415
      // check transmited TX packet CRC
9416
      check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
9417
      if (tmp > 0)
9418
      begin
9419
        test_fail("Wrong CRC of the transmitted packet");
9420
        fail = fail + 1;
9421
      end
9422
      // check WB INT signal
9423
      if (wb_int !== 1'b1)
9424
      begin
9425
        `TIME; $display("*E WB INT signal should be set");
9426
        test_fail("WB INT signal should be set");
9427
        fail = fail + 1;
9428
      end
9429
      // check TX buffer descriptor of a packet
9430
      check_tx_bd(num_of_bd, data);
9431
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 4)) || // wrap bit
9432
           ((data[15:0] !== 16'h5800) && (num_of_bd < 4)) )   // without wrap bit
9433
      begin
9434
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
9435
        test_fail("TX buffer descriptor status is not correct");
9436
        fail = fail + 1;
9437
      end
9438
      // check interrupts
9439 274 tadejm
      wait (wbm_working == 0);
9440 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9441
      if ((data & `ETH_INT_TXB) !== 1'b1)
9442
      begin
9443
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
9444
        test_fail("Interrupt Transmit Buffer was not set");
9445
        fail = fail + 1;
9446
      end
9447
      if ((data & (~`ETH_INT_TXB)) !== 0)
9448
      begin
9449
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
9450
        test_fail("Other interrupts (except Transmit Buffer) were set");
9451
        fail = fail + 1;
9452
      end
9453
      // clear interrupts
9454 274 tadejm
      wait (wbm_working == 0);
9455 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9456
      // check WB INT signal
9457
      if (wb_int !== 1'b0)
9458
      begin
9459
        test_fail("WB INT signal should not be set");
9460
        fail = fail + 1;
9461
      end
9462
      // INTERMEDIATE DISPLAYS
9463
      $display("    ->packet with length %0d sent", (i_length + 4));
9464
      // set length (loop variable)
9465
      if ((num_of_bd < 2) || (num_of_bd >= 3))
9466
        i_length = i_length + 1;
9467
      else if (num_of_bd == 2)
9468
        i_length = (16'hFFFF - 5);
9469
      // the number of frame transmitted
9470
      num_of_frames = num_of_frames + 1;
9471
      num_of_bd = num_of_bd + 1;
9472
      @(posedge wb_clk);
9473
    end
9474
    // disable TX
9475 274 tadejm
    wait (wbm_working == 0);
9476 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
9477
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9478
    @(posedge wb_clk);
9479
    if(fail == 0)
9480
      test_ok;
9481
    else
9482
      fail = 0;
9483
  end
9484
 
9485
 
9486
  ////////////////////////////////////////////////////////////////////
9487
  ////                                                            ////
9488
  ////  Test IPG during Back-to-Back transmit at                  ////
9489
  ////  88 TX buffer decriptors ( 10Mbps ).                       ////
9490
  ////                                                            ////
9491
  ////////////////////////////////////////////////////////////////////
9492
  if (test_num == 18) // without and with padding
9493
  begin
9494
    // TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps )
9495
    test_name = "TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps )";
9496
    `TIME; $display("  TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps )");
9497
 
9498
    // reset MAC registers
9499
    hard_reset;
9500
    // reset MAC and MII LOGIC with soft reset
9501 274 tadejm
//    reset_mac;
9502
//    reset_mii;
9503 209 tadejm
    // set wb slave response
9504
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
9505
 
9506
    max_tmp = 0;
9507
    min_tmp = 0;
9508
    num_of_frames = 0;
9509
    num_of_bd = 0;
9510
    tmp_ipgt = 0;
9511
    // set 88 TX buffer descriptors - must be set before TX enable
9512 274 tadejm
    wait (wbm_working == 0);
9513 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h58, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9514
    // enable TX, set full-duplex mode, NO padding and CRC appending
9515 274 tadejm
    wait (wbm_working == 0);
9516 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
9517
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9518
    // prepare two packets of MAXFL length
9519 274 tadejm
    wait (wbm_working == 0);
9520 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9521
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
9522
    min_tmp = tmp[31:16];
9523
    st_data = 8'h29;
9524
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
9525
    // check WB INT signal
9526
    if (wb_int !== 1'b0)
9527
    begin
9528
      test_fail("WB INT signal should not be set");
9529
      fail = fail + 1;
9530
    end
9531
 
9532
    // write to phy's control register for 10Mbps
9533
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
9534
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
9535
    speed = 10;
9536
 
9537
    i_length = (min_tmp - 4);
9538
    while (i_length < (max_tmp - 4))
9539
    begin
9540
      // disable TX, set full-duplex mode, NO padding and CRC appending
9541 274 tadejm
      wait (wbm_working == 0);
9542 209 tadejm
      wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
9543
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9544
      // set IPGT register
9545 274 tadejm
      wait (wbm_working == 0);
9546 209 tadejm
      wbm_write(`ETH_IPGT, tmp_ipgt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9547
      // enable TX, set full-duplex mode, NO padding and CRC appending
9548 274 tadejm
      wait (wbm_working == 0);
9549 209 tadejm
      wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
9550
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9551
      // Reset_tx_bd enable interrupt generation
9552
      // unmask interrupts
9553 274 tadejm
      wait (wbm_working == 0);
9554 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
9555
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9556
      // not detect carrier sense in FD and no collision
9557
      eth_phy.carrier_sense_tx_fd_detect(0);
9558
      eth_phy.collision(0);
9559
      // first destination address on ethernet PHY
9560
      eth_phy.set_tx_mem_addr(0);
9561
      // prepare BDs
9562
      if (num_of_bd == 0)
9563
      begin
9564
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9565
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9566
        set_tx_bd_wrap(1);
9567
        set_tx_bd_ready(0, 0);
9568
        set_tx_bd_ready(1, 1);
9569
      end
9570
      // CHECK END OF TWO TRANSMITIONs
9571
      // wait for first transmit to end
9572
      check_tx_bd(num_of_bd, data);
9573
      wait (MTxEn === 1'b1); // start transmit
9574
      if (data[15] !== 1)
9575
      begin
9576
        test_fail("Wrong buffer descriptor's ready bit read out from MAC");
9577
        fail = fail + 1;
9578
      end
9579
      wait (MTxEn === 1'b0); // end transmit
9580
      num_of_frames = num_of_frames + 1;
9581
      num_of_bd = num_of_bd + 1;
9582
      #Tp;
9583
      // destination address on ethernet PHY
9584
      eth_phy.set_tx_mem_addr(0);
9585
      i1 = 0;
9586
      i2 = 0;
9587
      // count IPG clock periods
9588
      fork
9589
        begin
9590
          wait (MTxEn === 1'b1); // start second transmit
9591
          #Tp;
9592
          disable count_rising;
9593
          disable count_falling;
9594
        end
9595
        begin: count_rising
9596
          forever
9597
          begin
9598
            @(posedge mtx_clk);
9599
            i1 = i1 + 1;
9600
            #Tp;
9601
          end
9602
        end
9603
        begin: count_falling
9604
          forever
9605
          begin
9606
            @(negedge mtx_clk);
9607
            i2 = i2 + 1;
9608
            #Tp;
9609
          end
9610
        end
9611
      join
9612
      // check IPG length - INTERMEDIATE DISPLAYS
9613
      if((i1 == i2) && (i1 >= (tmp_ipgt + 3)))
9614
      begin
9615
        $display("    ->IPG with %0d mtx_clk periods (min %0d) between packets with lengths %0d and %0d checked",
9616
                  i1, (tmp_ipgt + 3), (i_length + 4), (i_length + 4 + 1));
9617
      end
9618
      else
9619
      begin
9620
        `TIME; $display("*E IPG is not correct: (%0d + %0d) / 2, requested: %d", i1, i2, (tmp_ipgt + 3));
9621
        fail = fail + 1;
9622
        test_fail("IPG is not correct");
9623
      end
9624
      // wait for second transmit to end
9625
      wait (MTxEn === 1'b0); // end second transmit
9626
      while (data[15] === 1)
9627
      begin
9628
        check_tx_bd(num_of_bd, data);
9629
        @(posedge wb_clk);
9630
      end
9631
      repeat (1) @(posedge wb_clk);
9632
      // check length of a second PACKET
9633
      tmp_len = eth_phy.tx_len;
9634
      #1;
9635
      if (tmp_len != (i_length + 4 + 1))
9636
      begin
9637
        test_fail("Wrong length of second packet out from MAC");
9638
        fail = fail + 1;
9639
      end
9640
      // checking second packet
9641
      check_tx_packet(`MEMORY_BASE, 0, (i_length + 1), tmp);
9642
      if (tmp > 0)
9643
      begin
9644
        test_fail("Wrong data of second transmitted packet");
9645
        fail = fail + 1;
9646
      end
9647
      // check second transmited TX packet CRC
9648
      check_tx_crc(0, (i_length + 1), 1'b0, tmp); // length without CRC
9649
      if (tmp > 0)
9650
      begin
9651
        test_fail("Wrong CRC of second transmitted packet");
9652
        fail = fail + 1;
9653
      end
9654
      // check WB INT signal
9655
      if (wb_int !== 1'b1)
9656
      begin
9657
        `TIME; $display("*E WB INT signal should be set");
9658
        test_fail("WB INT signal should be set");
9659
        fail = fail + 1;
9660
      end
9661
      // check TX buffer descriptor of a packet
9662
      check_tx_bd(num_of_bd, data);
9663
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // wrap bit
9664
           ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // without wrap bit
9665
      begin
9666
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
9667
        test_fail("TX buffer descriptor status is not correct");
9668
        fail = fail + 1;
9669
      end
9670
      // check interrupts
9671 274 tadejm
      wait (wbm_working == 0);
9672 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9673
      if ((data & `ETH_INT_TXB) !== 1'b1)
9674
      begin
9675
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
9676
        test_fail("Interrupt Transmit Buffer was not set");
9677
        fail = fail + 1;
9678
      end
9679
      if ((data & (~`ETH_INT_TXB)) !== 0)
9680
      begin
9681
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
9682
        test_fail("Other interrupts (except Transmit Buffer) were set");
9683
        fail = fail + 1;
9684
      end
9685
      // clear interrupts
9686 274 tadejm
      wait (wbm_working == 0);
9687 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9688
      // check WB INT signal
9689
      if (wb_int !== 1'b0)
9690
      begin
9691
        test_fail("WB INT signal should not be set");
9692
        fail = fail + 1;
9693
      end
9694
      // set length (LOOP variable)
9695
      if ((tmp_ipgt + 3) < 130) // tmp_ipgt < 124
9696
        i_length = i_length + 2;
9697
      else
9698
        i_length = (max_tmp - 4);
9699
      // set IPGT
9700
      if ((tmp_ipgt + 3) < 10)
9701
        tmp_ipgt = tmp_ipgt + 1;
9702
      else if ((tmp_ipgt + 3) < 24)
9703
        tmp_ipgt = tmp_ipgt + 7;
9704
      else if ((tmp_ipgt + 3) == 24)
9705
        tmp_ipgt = 38 - 3;
9706
      else if ((tmp_ipgt + 3) == 38)
9707
        tmp_ipgt = 72 - 3;
9708
      else if ((tmp_ipgt + 3) == 72)
9709
        tmp_ipgt = 130 - 3; // 124 - 3
9710
      // the number of frame transmitted
9711
      num_of_frames = num_of_frames + 1;
9712
      num_of_bd = 0;
9713
      @(posedge wb_clk);
9714
    end
9715
    // disable TX
9716 274 tadejm
    wait (wbm_working == 0);
9717 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
9718
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9719
    @(posedge wb_clk);
9720
    if(fail == 0)
9721
      test_ok;
9722
    else
9723
      fail = 0;
9724
  end
9725
 
9726
 
9727
  ////////////////////////////////////////////////////////////////////
9728
  ////                                                            ////
9729
  ////  Test IPG during Back-to-Back transmit at                  ////
9730
  ////  88 TX buffer decriptors ( 100Mbps ).                      ////
9731
  ////                                                            ////
9732
  ////////////////////////////////////////////////////////////////////
9733
  if (test_num == 19) // without and with padding
9734
  begin
9735
    // TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps )
9736
    test_name = "TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps )";
9737
    `TIME; $display("  TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps )");
9738
 
9739
    // reset MAC registers
9740
    hard_reset;
9741
    // reset MAC and MII LOGIC with soft reset
9742 274 tadejm
//    reset_mac;
9743
//    reset_mii;
9744 209 tadejm
    // set wb slave response
9745
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
9746
 
9747
    max_tmp = 0;
9748
    min_tmp = 0;
9749
    num_of_frames = 0;
9750
    num_of_bd = 0;
9751
    tmp_ipgt = 0;
9752
    // set 88 TX buffer descriptors - must be set before TX enable
9753 274 tadejm
    wait (wbm_working == 0);
9754 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h58, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9755
    // enable TX, set full-duplex mode, NO padding and CRC appending
9756 274 tadejm
    wait (wbm_working == 0);
9757 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
9758
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9759
    // prepare two packets of MAXFL length
9760 274 tadejm
    wait (wbm_working == 0);
9761 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9762
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
9763
    min_tmp = tmp[31:16];
9764
    st_data = 8'h29;
9765
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
9766
    // check WB INT signal
9767
    if (wb_int !== 1'b0)
9768
    begin
9769
      test_fail("WB INT signal should not be set");
9770
      fail = fail + 1;
9771
    end
9772
 
9773
    // write to phy's control register for 100Mbps
9774
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
9775
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
9776
    speed = 100;
9777
 
9778
    i_length = (min_tmp - 4);
9779
    while (i_length < (max_tmp - 4))
9780
    begin
9781
      // disable TX, set full-duplex mode, NO padding and CRC appending
9782 274 tadejm
      wait (wbm_working == 0);
9783 209 tadejm
      wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
9784
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9785
      // set IPGT register
9786 274 tadejm
      wait (wbm_working == 0);
9787 209 tadejm
      wbm_write(`ETH_IPGT, tmp_ipgt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9788
      // enable TX, set full-duplex mode, NO padding and CRC appending
9789 274 tadejm
      wait (wbm_working == 0);
9790 209 tadejm
      wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
9791
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9792
      // Reset_tx_bd enable interrupt generation
9793
      // unmask interrupts
9794 274 tadejm
      wait (wbm_working == 0);
9795 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
9796
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9797
      // not detect carrier sense in FD and no collision
9798
      eth_phy.carrier_sense_tx_fd_detect(0);
9799
      eth_phy.collision(0);
9800
      // first destination address on ethernet PHY
9801
      eth_phy.set_tx_mem_addr(0);
9802
      // prepare BDs
9803
      if (num_of_bd == 0)
9804
      begin
9805
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9806
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9807
        set_tx_bd_wrap(1);
9808
        set_tx_bd_ready(0, 0);
9809
        set_tx_bd_ready(1, 1);
9810
      end
9811
      // CHECK END OF TWO TRANSMITIONs
9812
      // wait for first transmit to end
9813
      check_tx_bd(num_of_bd, data);
9814
      wait (MTxEn === 1'b1); // start transmit
9815
      if (data[15] !== 1)
9816
      begin
9817
        test_fail("Wrong buffer descriptor's ready bit read out from MAC");
9818
        fail = fail + 1;
9819
      end
9820
      wait (MTxEn === 1'b0); // end transmit
9821
      num_of_frames = num_of_frames + 1;
9822
      num_of_bd = num_of_bd + 1;
9823
      #Tp;
9824
      // destination address on ethernet PHY
9825
      eth_phy.set_tx_mem_addr(0);
9826
      i1 = 0;
9827
      i2 = 0;
9828
      // count IPG clock periods
9829
      fork
9830
        begin
9831
          wait (MTxEn === 1'b1); // start second transmit
9832
          #Tp;
9833
          disable count_rising1;
9834
          disable count_falling1;
9835
        end
9836
        begin: count_rising1
9837
          forever
9838
          begin
9839
            @(posedge mtx_clk);
9840
            i1 = i1 + 1;
9841
            #Tp;
9842
          end
9843
        end
9844
        begin: count_falling1
9845
          forever
9846
          begin
9847
            @(negedge mtx_clk);
9848
            i2 = i2 + 1;
9849
            #Tp;
9850
          end
9851
        end
9852
      join
9853
      // check IPG length - INTERMEDIATE DISPLAYS
9854
      if((i1 == i2) && (i1 >= (tmp_ipgt + 3)))
9855
      begin
9856
        $display("    ->IPG with %0d mtx_clk periods (min %0d) between packets with lengths %0d and %0d checked",
9857
                  i1, (tmp_ipgt + 3), (i_length + 4), (i_length + 4 + 1));
9858
      end
9859
      else
9860
      begin
9861
        `TIME; $display("*E IPG is not correct: (%0d + %0d) / 2, requested: %d", i1, i2, (tmp_ipgt + 3));
9862
        fail = fail + 1;
9863
        test_fail("IPG is not correct");
9864
      end
9865
      // wait for second transmit to end
9866
      wait (MTxEn === 1'b0); // end second transmit
9867
      while (data[15] === 1)
9868
      begin
9869
        check_tx_bd(num_of_bd, data);
9870
        @(posedge wb_clk);
9871
      end
9872
      repeat (1) @(posedge wb_clk);
9873
      // check length of a second PACKET
9874
      tmp_len = eth_phy.tx_len;
9875
      #1;
9876
      if (tmp_len != (i_length + 4 + 1))
9877
      begin
9878
        test_fail("Wrong length of second packet out from MAC");
9879
        fail = fail + 1;
9880
      end
9881
      // checking second packet
9882
      check_tx_packet(`MEMORY_BASE, 0, (i_length + 1), tmp);
9883
      if (tmp > 0)
9884
      begin
9885
        test_fail("Wrong data of second transmitted packet");
9886
        fail = fail + 1;
9887
      end
9888
      // check second transmited TX packet CRC
9889
      check_tx_crc(0, (i_length + 1), 1'b0, tmp); // length without CRC
9890
      if (tmp > 0)
9891
      begin
9892
        test_fail("Wrong CRC of second transmitted packet");
9893
        fail = fail + 1;
9894
      end
9895
      // check WB INT signal
9896
      if (wb_int !== 1'b1)
9897
      begin
9898
        `TIME; $display("*E WB INT signal should be set");
9899
        test_fail("WB INT signal should be set");
9900
        fail = fail + 1;
9901
      end
9902
      // check TX buffer descriptor of a packet
9903
      check_tx_bd(num_of_bd, data);
9904
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // wrap bit
9905
           ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // without wrap bit
9906
      begin
9907
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
9908
        test_fail("TX buffer descriptor status is not correct");
9909
        fail = fail + 1;
9910
      end
9911
      // check interrupts
9912 274 tadejm
      wait (wbm_working == 0);
9913 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9914
      if ((data & `ETH_INT_TXB) !== 1'b1)
9915
      begin
9916
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
9917
        test_fail("Interrupt Transmit Buffer was not set");
9918
        fail = fail + 1;
9919
      end
9920
      if ((data & (~`ETH_INT_TXB)) !== 0)
9921
      begin
9922
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
9923
        test_fail("Other interrupts (except Transmit Buffer) were set");
9924
        fail = fail + 1;
9925
      end
9926
      // clear interrupts
9927 274 tadejm
      wait (wbm_working == 0);
9928 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9929
      // check WB INT signal
9930
      if (wb_int !== 1'b0)
9931
      begin
9932
        test_fail("WB INT signal should not be set");
9933
        fail = fail + 1;
9934
      end
9935
      // set length (LOOP variable)
9936
      if ((tmp_ipgt + 3) < 130) // tmp_ipgt < 124
9937
        i_length = i_length + 2;
9938
      else
9939
        i_length = (max_tmp - 4);
9940
      // set IPGT
9941
      if ((tmp_ipgt + 3) < 10)
9942
        tmp_ipgt = tmp_ipgt + 1;
9943
      else if ((tmp_ipgt + 3) < 24)
9944
        tmp_ipgt = tmp_ipgt + 7;
9945
      else if ((tmp_ipgt + 3) == 24)
9946
        tmp_ipgt = 38 - 3;
9947
      else if ((tmp_ipgt + 3) == 38)
9948
        tmp_ipgt = 72 - 3;
9949
      else if ((tmp_ipgt + 3) == 72)
9950
        tmp_ipgt = 130 - 3; // 124 - 3
9951
      // the number of frame transmitted
9952
      num_of_frames = num_of_frames + 1;
9953
      num_of_bd = 0;
9954
      @(posedge wb_clk);
9955
    end
9956
    // disable TX
9957 274 tadejm
    wait (wbm_working == 0);
9958 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
9959
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9960
    @(posedge wb_clk);
9961
    if(fail == 0)
9962
      test_ok;
9963
    else
9964
      fail = 0;
9965
  end
9966
 
9967
 
9968
  ////////////////////////////////////////////////////////////////////
9969
  ////                                                            ////
9970
  ////  Test transmit packets after TX under-run on each packet's ////
9971
  ////  byte at 2 TX buffer decriptors ( 10Mbps ).                ////
9972
  ////                                                            ////
9973
  ////////////////////////////////////////////////////////////////////
9974
  if (test_num == 20) // without padding
9975
  begin
9976
    // TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps )
9977
    test_name = "TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps )";
9978
    `TIME;
9979
    $display("  TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps )");
9980
 
9981
    // reset MAC registers
9982
    hard_reset;
9983
    // set wb slave response
9984
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
9985
 
9986
    max_tmp = 0;
9987
    min_tmp = 0;
9988
    // set 2 TX buffer descriptors - must be set before TX enable
9989 274 tadejm
    wait (wbm_working == 0);
9990 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h2, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9991
    // enable TX, set full-duplex mode, NO padding and CRC appending
9992 274 tadejm
    wait (wbm_working == 0);
9993 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN |/* `ETH_MODER_PAD |*/ `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
9994
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9995
    // prepare a packet of MAXFL length
9996 274 tadejm
    wait (wbm_working == 0);
9997 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9998
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
9999
    min_tmp = tmp[31:16];
10000
    st_data = 8'h99;
10001
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
10002
    // read IPG value
10003 274 tadejm
    wait (wbm_working == 0);
10004 209 tadejm
    wbm_read(`ETH_IPGT, tmp_ipgt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10005
    // check WB INT signal
10006
    if (wb_int !== 1'b0)
10007
    begin
10008
      test_fail("WB INT signal should not be set");
10009
      fail = fail + 1;
10010
    end
10011
 
10012
    // write to phy's control register for 10Mbps
10013
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
10014
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
10015
    speed = 10;
10016
 
10017 279 mohor
    num_of_frames = 60; // (0..3) => start under-run on first word
10018 209 tadejm
    num_of_bd = 0;
10019
    i_data = 3; // (3) => one BYTE read in first word - FIRST byte
10020 279 mohor
    i_length = 80;
10021 209 tadejm
    while (i_length < (max_tmp - 4))
10022
    begin
10023
      // Reset_tx_bd enable interrupt generation
10024
      // unmask interrupts
10025 274 tadejm
      wait (wbm_working == 0);
10026 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
10027
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10028
      // not detect carrier sense in FD and no collision
10029
      eth_phy.carrier_sense_tx_fd_detect(0);
10030
      eth_phy.collision(0);
10031
      // first destination address on ethernet PHY
10032
      eth_phy.set_tx_mem_addr(0);
10033
      // prepare BDs
10034
      if (num_of_bd == 0)
10035
      begin
10036
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_data[1:0]));
10037
        set_tx_bd(1, 1, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
10038
        set_tx_bd_wrap(1);
10039
        // set wb slave response: ACK (response), wbs_waits[2:0] (waits before response), 
10040
        //                       wbs_retries[7:0] (RTYs before ACK if RTY response selected)
10041 223 tadejm
        #1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
10042 209 tadejm
        set_tx_bd_ready(1, 1);
10043
        set_tx_bd_ready(0, 0);
10044
      end
10045
      // frame under-run checking
10046
      frame_started = 0;
10047
      frame_ended = 0;
10048
      wait_for_frame = 0;
10049 279 mohor
      no_underrun = 0;
10050 209 tadejm
      fork
10051
        begin
10052
          // for every 4 frames bytes 1, 2, 3 and 4 respectively are read in first word => 1 ACK
10053
          // in other words 4 bytes are read, since length is MINFL => num_of_frames[31:2] ACKs
10054 279 mohor
          i = 0;
10055
          while (i <= (num_of_frames[31:2] + 1))
10056
          begin
10057
            @(negedge wb_clk);
10058
            if (eth_ma_wb_ack_i)
10059
            begin
10060
              i = i + 1;
10061
            end
10062
          end
10063 209 tadejm
          // set wb slave response: ACK (response), wbs_waits[2:0] (waits before response), 
10064
          //                       wbs_retries[7:0] (RTYs before ACK if RTY response selected)
10065 223 tadejm
          #1 wb_slave.cycle_response(`NO_RESPONSE, 3'h0, 8'hFF);
10066 209 tadejm
          // wait for synchronization and some additional clocks
10067
          wait_for_frame = 1;
10068
          // wait for frame
10069
          wait ((wait_for_frame == 0) || (frame_started == 1))
10070
          if ((wait_for_frame == 0) && (frame_started == 0)) // frame didn't start
10071
          begin
10072
            disable check_fr;
10073
          end
10074
          else if ((wait_for_frame == 1) && (frame_started == 1)) // frame started
10075
          begin
10076
            disable wait_fr;
10077 279 mohor
            if (frame_ended == 1)
10078
            begin
10079
              $display("(%0t) no under-run on %0d. byte, since length of frame (without CRC) is only %0d bytes",
10080
                        $time, ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])), i_length);
10081
              no_underrun = 1;
10082
            end
10083
            else
10084
            begin
10085
              wait (frame_ended == 1);
10086
              $display("(%0t) under-run on %0d. byte",
10087
                        $time, ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])));
10088
              no_underrun = 0;
10089
            end
10090 209 tadejm
          end
10091
          repeat (2) @(posedge wb_clk);
10092
          // set wb slave response: ACK (response), wbs_waits[2:0] (waits before response), 
10093
          //                       wbs_retries[7:0] (RTYs before ACK if RTY response selected)
10094 223 tadejm
          wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
10095 209 tadejm
        end
10096
        begin: wait_fr
10097
          wait (wait_for_frame == 1)
10098
          begin
10099
            // wait for synchronization and some additional clocks
10100
            repeat (3) @(posedge wb_clk);
10101
            repeat (2 * tmp_ipgt) @(posedge mtx_clk);
10102
            repeat (2) @(posedge wb_clk);
10103
            repeat (2) @(posedge mtx_clk);
10104
            wait_for_frame = 0;
10105
          end
10106
        end
10107
        begin: check_fr
10108
          // wait for frame to start
10109
          @(posedge MTxEn);
10110
          frame_started = 1;
10111
          // wait for frame to end due to under-run
10112
          @(negedge MTxEn);
10113
          frame_ended = 1;
10114
        end
10115
      join
10116 279 mohor
 
10117
      repeat (5) @ (posedge mtx_clk);
10118
 
10119 209 tadejm
      // wait for first transmit to end, if under-run didn't happen
10120
      if (frame_ended == 0)
10121
      begin
10122
        // WAIT FOR FIRST TRANSMIT
10123
        check_tx_bd(num_of_bd, data);
10124
        wait (MTxEn === 1'b1); // start first transmit
10125
        if (data[15] !== 1)
10126
        begin
10127
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
10128
          fail = fail + 1;
10129
        end
10130
        wait (MTxEn === 1'b0); // end first transmit
10131
        while (data[15] === 1)
10132
        begin
10133
          check_tx_bd(num_of_bd, data);
10134
          @(posedge wb_clk);
10135
        end
10136
        repeat (1) @(posedge wb_clk);
10137
        // CHECK FIRST FRAME
10138
        // check length of a first PACKET
10139
        tmp_len = eth_phy.tx_len;
10140 279 mohor
 
10141 209 tadejm
        #1;
10142
        if (tmp_len != (i_length + 4))
10143
        begin
10144 223 tadejm
          `TIME; $display("*E Wrong length of first packet out from MAC");
10145
          test_fail("Wrong length of first packet out from MAC");
10146 209 tadejm
          fail = fail + 1;
10147
        end
10148
        // checking first packet
10149
        check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (i_length), tmp);
10150
        if (tmp > 0)
10151
        begin
10152 223 tadejm
          `TIME; $display("*E Wrong data of first transmitted packet");
10153
          test_fail("Wrong data of first transmitted packet");
10154 209 tadejm
          fail = fail + 1;
10155
        end
10156
        // check first transmited TX packet CRC
10157
        check_tx_crc(0, (i_length), 1'b0, tmp); // length without CRC
10158
        if (tmp > 0)
10159
        begin
10160 223 tadejm
          `TIME; $display("*E Wrong CRC of first transmitted packet");
10161
          test_fail("Wrong CRC of first transmitted packet");
10162 209 tadejm
          fail = fail + 1;
10163
        end
10164
        // check WB INT signal
10165
        if (wb_int !== 1'b1)
10166
        begin
10167
          `TIME; $display("*E WB INT signal should be set");
10168
          test_fail("WB INT signal should be set");
10169
          fail = fail + 1;
10170
        end
10171
        // check TX buffer descriptor of a packet
10172
        check_tx_bd(num_of_bd, data);
10173
        if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // wrap bit
10174
             ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // without wrap bit
10175
        begin
10176
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
10177
          test_fail("TX buffer descriptor status is not correct");
10178
          fail = fail + 1;
10179
        end
10180
        // check interrupts
10181 274 tadejm
        wait (wbm_working == 0);
10182 209 tadejm
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10183
        if ((data & `ETH_INT_TXB) !== 1'b1)
10184
        begin
10185
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
10186
          test_fail("Interrupt Transmit Buffer was not set");
10187
          fail = fail + 1;
10188
        end
10189
        if ((data & (~`ETH_INT_TXB)) !== 0)
10190
        begin
10191
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
10192
          test_fail("Other interrupts (except Transmit Buffer) were set");
10193
          fail = fail + 1;
10194
        end
10195
        // clear interrupts
10196 274 tadejm
        wait (wbm_working == 0);
10197 209 tadejm
        wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10198
        // check WB INT signal
10199
        if (wb_int !== 1'b0)
10200
        begin
10201
          test_fail("WB INT signal should not be set");
10202
          fail = fail + 1;
10203
        end
10204
      end
10205 279 mohor
      else // if (frame_ended == 1)
10206 223 tadejm
      begin
10207
        // CHECK FIRST FRAME
10208
        // check length of a first PACKET
10209 279 mohor
 
10210
        if (no_underrun)
10211 223 tadejm
        begin
10212 279 mohor
          // CHECK FIRST FRAME, without under-run !!!
10213
          // check length of a first PACKET
10214
          tmp_len = eth_phy.tx_len;
10215
          #1;
10216
          if (tmp_len != (i_length + 4))
10217
          begin
10218
            `TIME; $display("*E Wrong length of first packet out from MAC (no under-run)");
10219
            test_fail("Wrong length of first packet out from MAC (no under-run)");
10220
            fail = fail + 1;
10221
          end
10222 223 tadejm
        end
10223 279 mohor
        else
10224
        begin
10225
          // CHECK FIRST FRAME, on which under-run occure !!!
10226
          // check length of a first PACKET
10227
          tmp_len = eth_phy.tx_len_err;
10228
          #1;
10229
          if (tmp_len != ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])))
10230
          begin
10231
            `TIME; $display("*E Wrong length of first packet out from MAC");
10232
            test_fail("Wrong length of first packet out from MAC");
10233
            fail = fail + 1;
10234
          end
10235
        end
10236 223 tadejm
        // checking first packet
10237 279 mohor
        if (no_underrun)
10238
          check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (i_length), tmp);    // only received are checked
10239
        else
10240
          check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (num_of_frames), tmp);
10241 223 tadejm
        if (tmp > 0)
10242
        begin
10243
          `TIME; $display("*E Wrong data of first transmitted packet");
10244
          test_fail("Wrong data of first transmitted packet");
10245
          fail = fail + 1;
10246
        end
10247
        // check WB INT signal
10248
        if (wb_int !== 1'b1)
10249
        begin
10250
          `TIME; $display("*E WB INT signal should be set");
10251
          test_fail("WB INT signal should be set");
10252
          fail = fail + 1;
10253
        end
10254 279 mohor
 
10255 223 tadejm
        // check TX buffer descriptor of a packet
10256
        check_tx_bd(num_of_bd, data);
10257 279 mohor
        if (no_underrun)
10258 223 tadejm
        begin
10259 279 mohor
          if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // under-run, wrap bit
10260
               ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // under-run, without wrap bit
10261
          begin
10262
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
10263
            test_fail("TX buffer descriptor status is not correct");
10264
            fail = fail + 1;
10265
          end
10266 223 tadejm
        end
10267 279 mohor
        else
10268
          if ( ((data[15:0] !== 16'h7900) && (num_of_bd == 1)) || // under-run, wrap bit
10269
               ((data[15:0] !== 16'h5900) && (num_of_bd < 1)) )   // under-run, without wrap bit
10270
          begin
10271
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
10272
            test_fail("TX buffer descriptor status is not correct");
10273
            fail = fail + 1;
10274
          end
10275
 
10276 223 tadejm
        // check interrupts
10277 274 tadejm
        wait (wbm_working == 0);
10278 223 tadejm
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10279 279 mohor
 
10280
        if (no_underrun)
10281 223 tadejm
        begin
10282 279 mohor
          if ((data & `ETH_INT_TXB) !== 2'b01)
10283
          begin
10284
            `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
10285
            test_fail("Interrupt Transmit Buffer was not set");
10286
            fail = fail + 1;
10287
          end
10288
          if ((data & (~`ETH_INT_TXB)) !== 0)
10289
          begin
10290
            `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
10291
            test_fail("Other interrupts (except Transmit Buffer) were set");
10292
            fail = fail + 1;
10293
          end
10294 223 tadejm
        end
10295 279 mohor
        else
10296 223 tadejm
        begin
10297 279 mohor
          if ((data & `ETH_INT_TXE) !== 2'b10)
10298
          begin
10299
            `TIME; $display("*E Interrupt Transmit Error was not set, interrupt reg: %0h", data);
10300
            test_fail("Interrupt Transmit Error was not set");
10301
            fail = fail + 1;
10302
          end
10303
          if ((data & (~`ETH_INT_TXE)) !== 0)
10304
          begin
10305
            `TIME; $display("*E Other interrupts (except Transmit Error) were set, interrupt reg: %0h", data);
10306
            test_fail("Other interrupts (except Transmit Buffer) were set");
10307
            fail = fail + 1;
10308
          end
10309 223 tadejm
        end
10310 279 mohor
 
10311 223 tadejm
        // clear interrupts
10312 274 tadejm
        wait (wbm_working == 0);
10313 223 tadejm
        wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10314
        // check WB INT signal
10315
        if (wb_int !== 1'b0)
10316
        begin
10317
          test_fail("WB INT signal should not be set");
10318
          fail = fail + 1;
10319
        end
10320
      end
10321 209 tadejm
      num_of_bd = num_of_bd + 1;
10322
      // destination address on ethernet PHY
10323
      eth_phy.set_tx_mem_addr(0);
10324 223 tadejm
      // WAIT FOR SECOND TRANSMIT
10325 209 tadejm
      check_tx_bd(num_of_bd, data);
10326
      wait (MTxEn === 1'b1); // start first transmit
10327
      if (data[15] !== 1)
10328
      begin
10329
        test_fail("Wrong buffer descriptor's ready bit read out from MAC");
10330
        fail = fail + 1;
10331
      end
10332
      wait (MTxEn === 1'b0); // end first transmit
10333
      while (data[15] === 1)
10334
      begin
10335
        check_tx_bd(num_of_bd, data);
10336
        @(posedge wb_clk);
10337
      end
10338
      repeat (1) @(posedge wb_clk);
10339
      // CHECK SECOND FRAME
10340
      // check length of a second PACKET
10341
      tmp_len = eth_phy.tx_len;
10342
      #1;
10343
      if (tmp_len != (i_length + 4))
10344
      begin
10345 223 tadejm
        `TIME; $display("*E Wrong length of second packet out from MAC");
10346 209 tadejm
        test_fail("Wrong length of second packet out from MAC");
10347
        fail = fail + 1;
10348
      end
10349
      // checking second packet
10350
      check_tx_packet(`MEMORY_BASE, 0, (i_length), tmp);
10351
      if (tmp > 0)
10352
      begin
10353 223 tadejm
        `TIME; $display("*E Wrong data of second transmitted packet");
10354 209 tadejm
        test_fail("Wrong data of second transmitted packet");
10355
        fail = fail + 1;
10356
      end
10357
      // check second transmited TX packet CRC
10358
      check_tx_crc(0, (i_length), 1'b0, tmp); // length without CRC
10359
      if (tmp > 0)
10360
      begin
10361 223 tadejm
        `TIME; $display("*E Wrong CRC of second transmitted packet");
10362 209 tadejm
        test_fail("Wrong CRC of second transmitted packet");
10363
        fail = fail + 1;
10364
      end
10365
      // check WB INT signal
10366
      if (wb_int !== 1'b1)
10367
      begin
10368
        `TIME; $display("*E WB INT signal should be set");
10369
        test_fail("WB INT signal should be set");
10370
        fail = fail + 1;
10371
      end
10372
      // check TX buffer descriptor of a packet
10373
      check_tx_bd(num_of_bd, data);
10374
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // wrap bit
10375
           ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // without wrap bit
10376
      begin
10377
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
10378
        test_fail("TX buffer descriptor status is not correct");
10379
        fail = fail + 1;
10380
      end
10381
      // check interrupts
10382 274 tadejm
      wait (wbm_working == 0);
10383 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10384
      if ((data & `ETH_INT_TXB) !== 1'b1)
10385
      begin
10386
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
10387
        test_fail("Interrupt Transmit Buffer was not set");
10388
        fail = fail + 1;
10389
      end
10390
      if ((data & (~`ETH_INT_TXB)) !== 0)
10391
      begin
10392
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
10393
        test_fail("Other interrupts (except Transmit Buffer) were set");
10394
        fail = fail + 1;
10395
      end
10396
      // clear interrupts
10397 274 tadejm
      wait (wbm_working == 0);
10398 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10399
      // check WB INT signal
10400
      if (wb_int !== 1'b0)
10401
      begin
10402
        test_fail("WB INT signal should not be set");
10403
        fail = fail + 1;
10404
      end
10405
      // set initial value
10406
      i_data = i_data - 1;
10407 279 mohor
      // the number of frames transmitted
10408 209 tadejm
      num_of_frames = num_of_frames + 1;
10409
      num_of_bd = 0;
10410
      // set length (LOOP variable)
10411 223 tadejm
      if (num_of_frames == i_length + 4) // 64 => this was last Byte (1st .. 64th) when i_length = min_tmp - 4
10412 209 tadejm
        i_length = (max_tmp - 4);
10413
      @(posedge wb_clk);
10414
    end
10415
    // disable TX
10416 274 tadejm
    wait (wbm_working == 0);
10417 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
10418
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10419
    @(posedge wb_clk);
10420
    if(fail == 0)
10421
      test_ok;
10422
    else
10423
      fail = 0;
10424
  end
10425
 
10426
 
10427
  ////////////////////////////////////////////////////////////////////
10428
  ////                                                            ////
10429
  ////  Test transmit packets after TX under-run on each packet's ////
10430
  ////  byte at 2 TX buffer decriptors ( 100Mbps ).               ////
10431
  ////                                                            ////
10432
  ////////////////////////////////////////////////////////////////////
10433
  if (test_num == 21) // without padding
10434
  begin
10435
    // TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps )
10436
    test_name = "TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps )";
10437
    `TIME;
10438
    $display("  TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps )");
10439
 
10440
    // reset MAC registers
10441
    hard_reset;
10442
    // set wb slave response
10443
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
10444
 
10445
    max_tmp = 0;
10446
    min_tmp = 0;
10447
    // set 2 TX buffer descriptors - must be set before TX enable
10448 274 tadejm
    wait (wbm_working == 0);
10449 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h2, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10450
    // enable TX, set full-duplex mode, NO padding and CRC appending
10451 274 tadejm
    wait (wbm_working == 0);
10452 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN |/* `ETH_MODER_PAD |*/ `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
10453
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10454
    // prepare a packet of MAXFL length
10455 274 tadejm
    wait (wbm_working == 0);
10456 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10457
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
10458
    min_tmp = tmp[31:16];
10459
    st_data = 8'h99;
10460
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
10461
    // read IPG value
10462 274 tadejm
    wait (wbm_working == 0);
10463 209 tadejm
    wbm_read(`ETH_IPGT, tmp_ipgt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10464
    // check WB INT signal
10465
    if (wb_int !== 1'b0)
10466
    begin
10467
      test_fail("WB INT signal should not be set");
10468
      fail = fail + 1;
10469
    end
10470
 
10471
    // write to phy's control register for 100Mbps
10472
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
10473 279 mohor
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
10474 209 tadejm
    speed = 100;
10475
 
10476 279 mohor
    num_of_frames = 60; // (0..3) => start under-run on first word
10477 209 tadejm
    num_of_bd = 0;
10478
    i_data = 3; // (3) => one BYTE read in first word - FIRST byte
10479 279 mohor
    i_length = 80;
10480 209 tadejm
    while (i_length < (max_tmp - 4))
10481
    begin
10482
      // Reset_tx_bd enable interrupt generation
10483
      // unmask interrupts
10484 274 tadejm
      wait (wbm_working == 0);
10485 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
10486
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10487
      // not detect carrier sense in FD and no collision
10488
      eth_phy.carrier_sense_tx_fd_detect(0);
10489
      eth_phy.collision(0);
10490
      // first destination address on ethernet PHY
10491
      eth_phy.set_tx_mem_addr(0);
10492
      // prepare BDs
10493
      if (num_of_bd == 0)
10494
      begin
10495
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_data[1:0]));
10496
        set_tx_bd(1, 1, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
10497
        set_tx_bd_wrap(1);
10498
        // set wb slave response: ACK (response), wbs_waits[2:0] (waits before response), 
10499
        //                       wbs_retries[7:0] (RTYs before ACK if RTY response selected)
10500 279 mohor
        #1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
10501 209 tadejm
        set_tx_bd_ready(1, 1);
10502
        set_tx_bd_ready(0, 0);
10503
      end
10504
      // frame under-run checking
10505
      frame_started = 0;
10506
      frame_ended = 0;
10507
      wait_for_frame = 0;
10508 279 mohor
      no_underrun = 0;
10509 209 tadejm
      fork
10510
        begin
10511
          // for every 4 frames bytes 1, 2, 3 and 4 respectively are read in first word => 1 ACK
10512
          // in other words 4 bytes are read, since length is MINFL => num_of_frames[31:2] ACKs
10513 279 mohor
          i = 0;
10514
          while (i <= (num_of_frames[31:2] + 1))
10515
          begin
10516
            @(negedge wb_clk);
10517
            if (eth_ma_wb_ack_i)
10518
            begin
10519
              i = i + 1;
10520
            end
10521
          end
10522 209 tadejm
          // set wb slave response: ACK (response), wbs_waits[2:0] (waits before response), 
10523
          //                       wbs_retries[7:0] (RTYs before ACK if RTY response selected)
10524 279 mohor
          #1 wb_slave.cycle_response(`NO_RESPONSE, 3'h0, 8'hFF);
10525 209 tadejm
          // wait for synchronization and some additional clocks
10526
          wait_for_frame = 1;
10527
          // wait for frame
10528
          wait ((wait_for_frame == 0) || (frame_started == 1))
10529
          if ((wait_for_frame == 0) && (frame_started == 0)) // frame didn't start
10530
          begin
10531
            disable check_fr1;
10532
          end
10533
          else if ((wait_for_frame == 1) && (frame_started == 1)) // frame started
10534
          begin
10535
            disable wait_fr1;
10536 279 mohor
            if (frame_ended == 1)
10537
            begin
10538
              $display("(%0t) no under-run on %0d. byte, since length of frame (without CRC) is only %0d bytes",
10539
                        $time, ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])), i_length);
10540
              no_underrun = 1;
10541
            end
10542
            else
10543
            begin
10544
              wait (frame_ended == 1);
10545
              $display("(%0t) under-run on %0d. byte",
10546
                        $time, ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])));
10547
              no_underrun = 0;
10548
            end
10549 209 tadejm
          end
10550
          repeat (2) @(posedge wb_clk);
10551
          // set wb slave response: ACK (response), wbs_waits[2:0] (waits before response), 
10552
          //                       wbs_retries[7:0] (RTYs before ACK if RTY response selected)
10553 279 mohor
          wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
10554 209 tadejm
        end
10555
        begin: wait_fr1
10556
          wait (wait_for_frame == 1)
10557
          begin
10558
            // wait for synchronization and some additional clocks
10559
            repeat (3) @(posedge wb_clk);
10560
            repeat (2 * tmp_ipgt) @(posedge mtx_clk);
10561
            repeat (2) @(posedge wb_clk);
10562
            repeat (2) @(posedge mtx_clk);
10563
            wait_for_frame = 0;
10564
          end
10565
        end
10566
        begin: check_fr1
10567
          // wait for frame to start
10568
          @(posedge MTxEn);
10569
          frame_started = 1;
10570
          // wait for frame to end due to under-run
10571
          @(negedge MTxEn);
10572
          frame_ended = 1;
10573
        end
10574
      join
10575 279 mohor
 
10576
      repeat (5) @ (posedge mtx_clk);
10577
 
10578 209 tadejm
      // wait for first transmit to end, if under-run didn't happen
10579
      if (frame_ended == 0)
10580
      begin
10581
        // WAIT FOR FIRST TRANSMIT
10582
        check_tx_bd(num_of_bd, data);
10583
        wait (MTxEn === 1'b1); // start first transmit
10584
        if (data[15] !== 1)
10585
        begin
10586
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
10587
          fail = fail + 1;
10588
        end
10589
        wait (MTxEn === 1'b0); // end first transmit
10590
        while (data[15] === 1)
10591
        begin
10592
          check_tx_bd(num_of_bd, data);
10593
          @(posedge wb_clk);
10594
        end
10595 279 mohor
        repeat (10) @(posedge wb_clk);
10596 209 tadejm
        // CHECK FIRST FRAME
10597
        // check length of a first PACKET
10598
        tmp_len = eth_phy.tx_len;
10599 279 mohor
 
10600 209 tadejm
        #1;
10601
        if (tmp_len != (i_length + 4))
10602
        begin
10603 279 mohor
          `TIME; $display("*E Wrong length of first packet out from MAC");
10604
          test_fail("Wrong length of first packet out from MAC");
10605 209 tadejm
          fail = fail + 1;
10606
        end
10607
        // checking first packet
10608
        check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (i_length), tmp);
10609
        if (tmp > 0)
10610
        begin
10611 279 mohor
          `TIME; $display("*E Wrong data of first transmitted packet");
10612
          test_fail("Wrong data of first transmitted packet");
10613 209 tadejm
          fail = fail + 1;
10614
        end
10615
        // check first transmited TX packet CRC
10616
        check_tx_crc(0, (i_length), 1'b0, tmp); // length without CRC
10617
        if (tmp > 0)
10618
        begin
10619 279 mohor
          `TIME; $display("*E Wrong CRC of first transmitted packet");
10620
          test_fail("Wrong CRC of first transmitted packet");
10621 209 tadejm
          fail = fail + 1;
10622
        end
10623
        // check WB INT signal
10624
        if (wb_int !== 1'b1)
10625
        begin
10626
          `TIME; $display("*E WB INT signal should be set");
10627
          test_fail("WB INT signal should be set");
10628
          fail = fail + 1;
10629
        end
10630
        // check TX buffer descriptor of a packet
10631
        check_tx_bd(num_of_bd, data);
10632
        if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // wrap bit
10633
             ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // without wrap bit
10634
        begin
10635
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
10636
          test_fail("TX buffer descriptor status is not correct");
10637
          fail = fail + 1;
10638
        end
10639
        // check interrupts
10640 274 tadejm
        wait (wbm_working == 0);
10641 209 tadejm
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10642
        if ((data & `ETH_INT_TXB) !== 1'b1)
10643
        begin
10644
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
10645
          test_fail("Interrupt Transmit Buffer was not set");
10646
          fail = fail + 1;
10647
        end
10648
        if ((data & (~`ETH_INT_TXB)) !== 0)
10649
        begin
10650
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
10651
          test_fail("Other interrupts (except Transmit Buffer) were set");
10652
          fail = fail + 1;
10653
        end
10654
        // clear interrupts
10655 274 tadejm
        wait (wbm_working == 0);
10656 209 tadejm
        wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10657
        // check WB INT signal
10658
        if (wb_int !== 1'b0)
10659
        begin
10660
          test_fail("WB INT signal should not be set");
10661
          fail = fail + 1;
10662
        end
10663
      end
10664 279 mohor
      else // if (frame_ended == 1)
10665
      begin
10666
        // CHECK FIRST FRAME
10667
        // check length of a first PACKET
10668
 
10669
        if (no_underrun)
10670
        begin
10671
          // CHECK FIRST FRAME, without under-run !!!
10672
          // check length of a first PACKET
10673
          tmp_len = eth_phy.tx_len;
10674
          #1;
10675
          if (tmp_len != (i_length + 4))
10676
          begin
10677
            `TIME; $display("*E Wrong length of first packet out from MAC (no under-run)");
10678
            test_fail("Wrong length of first packet out from MAC (no under-run)");
10679
            fail = fail + 1;
10680
          end
10681
        end
10682
        else
10683
        begin
10684
          // CHECK FIRST FRAME, on which under-run occure !!!
10685
          // check length of a first PACKET
10686
          tmp_len = eth_phy.tx_len_err-1;   // -1 because synchronization at 100 Mbps is slover then at 10 Mbps (wb_clk remains the same)
10687
          #1;
10688
          if (tmp_len != ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])))
10689
          begin
10690
            `TIME; $display("*E Wrong length of first packet out from MAC");
10691
            test_fail("Wrong length of first packet out from MAC");
10692
            fail = fail + 1;
10693
          end
10694
        end
10695
        // checking first packet
10696
        if (no_underrun)
10697
          check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (i_length), tmp);    // only received are checked
10698
        else
10699
          check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (num_of_frames), tmp);
10700
        if (tmp > 0)
10701
        begin
10702
          `TIME; $display("*E Wrong data of first transmitted packet");
10703
          test_fail("Wrong data of first transmitted packet");
10704
          fail = fail + 1;
10705
        end
10706
        // check WB INT signal
10707
        if (wb_int !== 1'b1)
10708
        begin
10709
          `TIME; $display("*E WB INT signal should be set");
10710
          test_fail("WB INT signal should be set");
10711
          fail = fail + 1;
10712
        end
10713
 
10714
        // check TX buffer descriptor of a packet
10715
        check_tx_bd(num_of_bd, data);
10716
        if (no_underrun)
10717
        begin
10718
          if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // under-run, wrap bit
10719
               ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // under-run, without wrap bit
10720
          begin
10721
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
10722
            test_fail("TX buffer descriptor status is not correct");
10723
            fail = fail + 1;
10724
          end
10725
        end
10726
        else
10727
          if ( ((data[15:0] !== 16'h7900) && (num_of_bd == 1)) || // under-run, wrap bit
10728
               ((data[15:0] !== 16'h5900) && (num_of_bd < 1)) )   // under-run, without wrap bit
10729
          begin
10730
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
10731
            test_fail("TX buffer descriptor status is not correct");
10732
            fail = fail + 1;
10733
          end
10734
 
10735
        // check interrupts
10736
        wait (wbm_working == 0);
10737
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10738
 
10739
        if (no_underrun)
10740
        begin
10741
          if ((data & `ETH_INT_TXB) !== 2'b01)
10742
          begin
10743
            `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
10744
            test_fail("Interrupt Transmit Buffer was not set");
10745
            fail = fail + 1;
10746
          end
10747
          if ((data & (~`ETH_INT_TXB)) !== 0)
10748
          begin
10749
            `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
10750
            test_fail("Other interrupts (except Transmit Buffer) were set");
10751
            fail = fail + 1;
10752
          end
10753
        end
10754
        else
10755
        begin
10756
          if ((data & `ETH_INT_TXE) !== 2'b10)
10757
          begin
10758
            `TIME; $display("*E Interrupt Transmit Error was not set, interrupt reg: %0h", data);
10759
            test_fail("Interrupt Transmit Error was not set");
10760
            fail = fail + 1;
10761
          end
10762
          if ((data & (~`ETH_INT_TXE)) !== 0)
10763
          begin
10764
            `TIME; $display("*E Other interrupts (except Transmit Error) were set, interrupt reg: %0h", data);
10765
            test_fail("Other interrupts (except Transmit Buffer) were set");
10766
            fail = fail + 1;
10767
          end
10768
        end
10769
 
10770
        // clear interrupts
10771
        wait (wbm_working == 0);
10772
        wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10773
        // check WB INT signal
10774
        if (wb_int !== 1'b0)
10775
        begin
10776
          test_fail("WB INT signal should not be set");
10777
          fail = fail + 1;
10778
        end
10779
      end
10780 209 tadejm
      num_of_bd = num_of_bd + 1;
10781
      // destination address on ethernet PHY
10782
      eth_phy.set_tx_mem_addr(0);
10783 279 mohor
      // WAIT FOR SECOND TRANSMIT
10784 209 tadejm
      check_tx_bd(num_of_bd, data);
10785
      wait (MTxEn === 1'b1); // start first transmit
10786
      if (data[15] !== 1)
10787
      begin
10788
        test_fail("Wrong buffer descriptor's ready bit read out from MAC");
10789
        fail = fail + 1;
10790
      end
10791
      wait (MTxEn === 1'b0); // end first transmit
10792
      while (data[15] === 1)
10793
      begin
10794
        check_tx_bd(num_of_bd, data);
10795
        @(posedge wb_clk);
10796
      end
10797
      repeat (1) @(posedge wb_clk);
10798
      // CHECK SECOND FRAME
10799
      // check length of a second PACKET
10800
      tmp_len = eth_phy.tx_len;
10801
      #1;
10802
      if (tmp_len != (i_length + 4))
10803
      begin
10804 279 mohor
        `TIME; $display("*E Wrong length of second packet out from MAC");
10805 209 tadejm
        test_fail("Wrong length of second packet out from MAC");
10806
        fail = fail + 1;
10807
      end
10808
      // checking second packet
10809
      check_tx_packet(`MEMORY_BASE, 0, (i_length), tmp);
10810
      if (tmp > 0)
10811
      begin
10812 279 mohor
        `TIME; $display("*E Wrong data of second transmitted packet");
10813 209 tadejm
        test_fail("Wrong data of second transmitted packet");
10814
        fail = fail + 1;
10815
      end
10816
      // check second transmited TX packet CRC
10817
      check_tx_crc(0, (i_length), 1'b0, tmp); // length without CRC
10818
      if (tmp > 0)
10819
      begin
10820 279 mohor
        `TIME; $display("*E Wrong CRC of second transmitted packet");
10821 209 tadejm
        test_fail("Wrong CRC of second transmitted packet");
10822
        fail = fail + 1;
10823
      end
10824
      // check WB INT signal
10825
      if (wb_int !== 1'b1)
10826
      begin
10827
        `TIME; $display("*E WB INT signal should be set");
10828
        test_fail("WB INT signal should be set");
10829
        fail = fail + 1;
10830
      end
10831
      // check TX buffer descriptor of a packet
10832
      check_tx_bd(num_of_bd, data);
10833
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // wrap bit
10834
           ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // without wrap bit
10835
      begin
10836
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
10837
        test_fail("TX buffer descriptor status is not correct");
10838
        fail = fail + 1;
10839
      end
10840
      // check interrupts
10841 274 tadejm
      wait (wbm_working == 0);
10842 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10843
      if ((data & `ETH_INT_TXB) !== 1'b1)
10844
      begin
10845
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
10846
        test_fail("Interrupt Transmit Buffer was not set");
10847
        fail = fail + 1;
10848
      end
10849
      if ((data & (~`ETH_INT_TXB)) !== 0)
10850
      begin
10851
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
10852
        test_fail("Other interrupts (except Transmit Buffer) were set");
10853
        fail = fail + 1;
10854
      end
10855
      // clear interrupts
10856 274 tadejm
      wait (wbm_working == 0);
10857 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10858
      // check WB INT signal
10859
      if (wb_int !== 1'b0)
10860
      begin
10861
        test_fail("WB INT signal should not be set");
10862
        fail = fail + 1;
10863
      end
10864
      // set initial value
10865
      i_data = i_data - 1;
10866 279 mohor
      // the number of frames transmitted
10867 209 tadejm
      num_of_frames = num_of_frames + 1;
10868
      num_of_bd = 0;
10869
      // set length (LOOP variable)
10870 279 mohor
      if (num_of_frames == i_length + 4) // 64 => this was last Byte (1st .. 64th) when i_length = min_tmp - 4
10871 209 tadejm
        i_length = (max_tmp - 4);
10872
      @(posedge wb_clk);
10873
    end
10874
    // disable TX
10875 274 tadejm
    wait (wbm_working == 0);
10876 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
10877
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10878
    @(posedge wb_clk);
10879
    if(fail == 0)
10880
      test_ok;
10881
    else
10882
      fail = 0;
10883
  end
10884
 
10885 194 tadej
end   //  for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
10886 169 mohor
 
10887
end
10888
endtask // test_mac_full_duplex_transmit
10889
 
10890
 
10891 209 tadejm
task test_mac_full_duplex_receive;
10892
  input  [31:0]  start_task;
10893
  input  [31:0]  end_task;
10894
  integer        bit_start_1;
10895
  integer        bit_end_1;
10896
  integer        bit_start_2;
10897
  integer        bit_end_2;
10898
  integer        num_of_reg;
10899
  integer        num_of_frames;
10900
  integer        num_of_bd;
10901
  integer        i_addr;
10902
  integer        i_data;
10903
  integer        i_length;
10904
  integer        tmp_len;
10905
  integer        tmp_bd;
10906
  integer        tmp_bd_num;
10907
  integer        tmp_data;
10908
  integer        tmp_ipgt;
10909
  integer        test_num;
10910
  reg    [31:0]  tx_bd_num;
10911
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
10912
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
10913
  integer        i;
10914
  integer        i1;
10915
  integer        i2;
10916
  integer        i3;
10917
  integer        fail;
10918
  integer        speed;
10919
  reg            frame_started;
10920
  reg            frame_ended;
10921
  reg            wait_for_frame;
10922 243 tadejm
  reg            check_frame;
10923
  reg            stop_checking_frame;
10924
  reg            first_fr_received;
10925 209 tadejm
  reg    [31:0]  addr;
10926
  reg    [31:0]  data;
10927
  reg    [31:0]  tmp;
10928
  reg    [ 7:0]  st_data;
10929
  reg    [15:0]  max_tmp;
10930
  reg    [15:0]  min_tmp;
10931
begin
10932
// MAC FULL DUPLEX RECEIVE TEST
10933
test_heading("MAC FULL DUPLEX RECEIVE TEST");
10934
$display(" ");
10935
$display("MAC FULL DUPLEX RECEIVE TEST");
10936
fail = 0;
10937
 
10938
// reset MAC registers
10939
hard_reset;
10940
// reset MAC and MII LOGIC with soft reset
10941 274 tadejm
//reset_mac;
10942
//reset_mii;
10943 209 tadejm
// set wb slave response
10944
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
10945
 
10946
  /*
10947
  TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
10948
  -------------------------------------------------------------------------------------
10949
  set_tx_bd
10950
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0], len[15:0], irq, pad, crc, txpnt[31:0]);
10951
  set_tx_bd_wrap
10952
    (tx_bd_num_end[6:0]);
10953
  set_tx_bd_ready
10954
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
10955
  check_tx_bd
10956
    (tx_bd_num_start[6:0], tx_bd_status[31:0]);
10957
  clear_tx_bd
10958
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
10959
 
10960
  TASKS for set and control RX buffer descriptors:
10961
  ------------------------------------------------
10962
  set_rx_bd
10963
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0], irq, rxpnt[31:0]);
10964
  set_rx_bd_wrap
10965
    (rx_bd_num_end[6:0]);
10966
  set_rx_bd_empty
10967
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
10968
  check_rx_bd
10969
    (rx_bd_num_end[6:0], rx_bd_status);
10970
  clear_rx_bd
10971
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
10972
 
10973
  TASKS for set and check TX packets:
10974
  -----------------------------------
10975
  set_tx_packet
10976
    (txpnt[31:0], len[15:0], eth_start_data[7:0]);
10977
  check_tx_packet
10978
    (txpnt_wb[31:0], txpnt_phy[31:0], len[15:0], failure[31:0]);
10979
 
10980
  TASKS for set and check RX packets:
10981
  -----------------------------------
10982
  set_rx_packet
10983
    (rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
10984
  check_rx_packet
10985
    (rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
10986
 
10987
  TASKS for append and check CRC to/of TX packet:
10988
  -----------------------------------------------
10989
  append_tx_crc
10990
    (txpnt_wb[31:0], len[15:0], negated_crc);
10991
  check_tx_crc
10992
    (txpnt_phy[31:0], len[15:0], negated_crc, failure[31:0]);
10993
 
10994
  TASK for append CRC to RX packet (CRC is checked together with check_rx_packet):
10995
  --------------------------------------------------------------------------------
10996
  append_rx_crc
10997
    (rxpnt_phy[31:0], len[15:0], plus_nibble, negated_crc);
10998
  */
10999
 
11000
//////////////////////////////////////////////////////////////////////
11001
////                                                              ////
11002
////  test_mac_full_duplex_receive:                               ////
11003
////                                                              ////
11004
////  0: Test no receive when all buffers are TX ( 10Mbps ).      ////
11005
////  1: Test no receive when all buffers are TX ( 100Mbps ).     ////
11006 243 tadejm
////  2: Test receive packet synchronization with receive         ////
11007
////     disable/enable ( 10Mbps ).                               ////
11008
////  3: Test receive packet synchronization with receive         ////
11009
////     disable/enable ( 100Mbps ).                              ////
11010
////  4: Test receive packets form MINFL to MAXFL sizes at        ////
11011 209 tadejm
////     one RX buffer decriptor ( 10Mbps ).                      ////
11012 243 tadejm
////  5: Test receive packets form MINFL to MAXFL sizes at        ////
11013 209 tadejm
////     one RX buffer decriptor ( 100Mbps ).                     ////
11014
////                                                              ////
11015
//////////////////////////////////////////////////////////////////////
11016
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
11017
begin
11018
 
11019
  ////////////////////////////////////////////////////////////////////
11020
  ////                                                            ////
11021
  ////  Test no receive when all buffers are TX ( 10Mbps ).       ////
11022
  ////                                                            ////
11023
  ////////////////////////////////////////////////////////////////////
11024
  if (test_num == 0) // Test no receive when all buffers are TX ( 10Mbps ).
11025
  begin
11026
    // TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )
11027
    test_name   = "TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )";
11028
    `TIME; $display("  TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )");
11029
 
11030
    // unmask interrupts
11031 274 tadejm
    wait (wbm_working == 0);
11032 209 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
11033
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11034
    // set all buffer descriptors to TX - must be set before RX enable
11035 274 tadejm
    wait (wbm_working == 0);
11036 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11037 223 tadejm
    // enable RX, set full-duplex mode, receive small, NO correct IFG
11038 274 tadejm
    wait (wbm_working == 0);
11039 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
11040
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11041
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11042
 
11043
    // write to phy's control register for 10Mbps
11044
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
11045
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
11046
    speed = 10;
11047
 
11048
    i = 0;
11049
    while (i < 128)
11050
    begin
11051
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
11052
      begin
11053
        set_rx_packet((i1 * 50), 10, 1'b0, 48'h1234_5678_8765, 48'h0011_2233_4455, 16'h0101, 8'h0);
11054
        append_rx_crc((i1 * 50), 10, 1'b0, 1'b0);
11055
        set_rx_bd(i1, i1, 1'b1, (`MEMORY_BASE + (i1 * 50)));
11056
      end
11057
      set_rx_bd_wrap(i);
11058
      set_rx_bd_empty(0, i);
11059
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
11060
      begin
11061
        #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, (i1 * 50), 14, 1'b0);
11062
        repeat(10) @(posedge mrx_clk);
11063
      end
11064
      @(posedge mrx_clk);
11065
      for (i2 = 0; i2 < 20; i2 = i2 + 1)
11066
      begin
11067
        check_rx_bd(0, tmp);
11068
        #1;
11069
        if (tmp[15] === 1'b0)
11070
        begin
11071
          test_fail("Receive should not start at all");
11072
          fail = fail + 1;
11073
          `TIME; $display("*E Receive of %d packets should not start at all - empty is 0", i);
11074
        end
11075
        if (tmp[7:0] !== 0)
11076
        begin
11077
          test_fail("Receive should not be finished since it should not start at all");
11078
          fail = fail + 1;
11079
          `TIME; $display("*E Receive of should not be finished since it should not start at all");
11080
        end
11081
        @(posedge wb_clk);
11082
      end
11083 274 tadejm
      wait (wbm_working == 0);
11084 209 tadejm
      wbm_read(`ETH_INT, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11085
      if (tmp[6:0] !== 0)
11086
      begin
11087
        test_fail("Receive should not get INT since it should not start at all");
11088
        fail = fail + 1;
11089
        `TIME; $display("*E Receive of should not get INT since it should not start at all");
11090
      end
11091
      clear_rx_bd(0, i);
11092
      if ((i < 5) || (i > 124))
11093
        i = i + 1;
11094
      else
11095
        i = i + 120;
11096
    end
11097
    // disable RX
11098 274 tadejm
    wait (wbm_working == 0);
11099 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
11100
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11101
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11102
    if(fail == 0)
11103
      test_ok;
11104
    else
11105
      fail = 0;
11106
  end
11107
 
11108
 
11109
  ////////////////////////////////////////////////////////////////////
11110
  ////                                                            ////
11111
  ////  Test no receive when all buffers are TX ( 100Mbps ).      ////
11112
  ////                                                            ////
11113
  ////////////////////////////////////////////////////////////////////
11114
  if (test_num == 1) // Test no receive when all buffers are TX ( 100Mbps ).
11115
  begin
11116
    // TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )
11117
    test_name   = "TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )";
11118
    `TIME; $display("  TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )");
11119
 
11120
    // unmask interrupts
11121 274 tadejm
    wait (wbm_working == 0);
11122 209 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
11123
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11124
    // set all buffer descriptors to TX - must be set before RX enable
11125 274 tadejm
    wait (wbm_working == 0);
11126 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11127 223 tadejm
    // enable RX, set full-duplex mode, receive small, NO correct IFG
11128 274 tadejm
    wait (wbm_working == 0);
11129 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
11130
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11131
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11132
 
11133
    // write to phy's control register for 100Mbps
11134
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
11135
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
11136
    speed = 100;
11137
 
11138
    i = 0;
11139
    while (i < 128)
11140
    begin
11141
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
11142
      begin
11143
        set_rx_packet((i1 * 50), 10, 1'b0, 48'h1234_5678_8765, 48'h0011_2233_4455, 16'h0101, 8'h0);
11144
        append_rx_crc((i1 * 50), 10, 1'b0, 1'b0);
11145
        set_rx_bd(i1, i1, 1'b1, (`MEMORY_BASE + (i1 * 50)));
11146
      end
11147
      set_rx_bd_wrap(i);
11148
      set_rx_bd_empty(0, i);
11149
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
11150
      begin
11151
        #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, (i1 * 50), 14, 1'b0);
11152
        repeat(10) @(posedge mrx_clk);
11153
      end
11154
      @(posedge mrx_clk);
11155
      for (i2 = 0; i2 < 20; i2 = i2 + 1)
11156
      begin
11157
        check_rx_bd(0, tmp);
11158
        #1;
11159
        if (tmp[15] === 1'b0)
11160
        begin
11161
          test_fail("Receive should not start at all");
11162
          fail = fail + 1;
11163
          `TIME; $display("*E Receive of %d packets should not start at all - empty is 0", i);
11164
        end
11165
        if (tmp[7:0] !== 0)
11166
        begin
11167
          test_fail("Receive should not be finished since it should not start at all");
11168
          fail = fail + 1;
11169
          `TIME; $display("*E Receive of should not be finished since it should not start at all");
11170
        end
11171
        @(posedge wb_clk);
11172
      end
11173 274 tadejm
      wait (wbm_working == 0);
11174 209 tadejm
      wbm_read(`ETH_INT, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11175
      if (tmp[6:0] !== 0)
11176
      begin
11177
        test_fail("Receive should not get INT since it should not start at all");
11178
        fail = fail + 1;
11179
        `TIME; $display("*E Receive of should not get INT since it should not start at all");
11180
      end
11181
      clear_rx_bd(0, i);
11182
      if ((i < 5) || (i > 124))
11183
        i = i + 1;
11184
      else
11185
        i = i + 120;
11186
    end
11187
    // disable RX
11188 274 tadejm
    wait (wbm_working == 0);
11189 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
11190
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11191
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11192
    if(fail == 0)
11193
      test_ok;
11194
    else
11195
      fail = 0;
11196
  end
11197
 
11198
 
11199
  ////////////////////////////////////////////////////////////////////
11200
  ////                                                            ////
11201 243 tadejm
  ////  Test receive packet synchronization with receive          ////
11202
  ////  disable/enable ( 10Mbps ).                                ////
11203
  ////                                                            ////
11204
  ////////////////////////////////////////////////////////////////////
11205
  if (test_num == 2) // Test no receive when all buffers are TX ( 10Mbps ).
11206
  begin
11207
    // TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
11208
    test_name   = "TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
11209
    `TIME; $display("  TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
11210
 
11211
    // unmask interrupts
11212 274 tadejm
    wait (wbm_working == 0);
11213 243 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
11214
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11215
    // set 10 RX buffer descriptor (8'h80 - 8'hA) - must be set before RX enable
11216 274 tadejm
    wait (wbm_working == 0);
11217 243 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h76, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11218
    // disable RX, set full-duplex mode, NO receive small, NO correct IFG
11219 274 tadejm
    wait (wbm_working == 0);
11220 243 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
11221
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11222
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11223
    // prepare two packets of MAXFL length
11224 274 tadejm
    wait (wbm_working == 0);
11225 243 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11226
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
11227
    min_tmp = tmp[31:16];
11228
    st_data = 8'h0F;
11229
    set_rx_packet(0, (min_tmp + 1), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
11230
    append_rx_crc(0, (min_tmp + 1), 1'b0, 1'b0);
11231
    st_data = 8'h1A;
11232
    set_rx_packet(max_tmp, (min_tmp + 1), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
11233
    append_rx_crc(max_tmp, (min_tmp + 1), 1'b0, 1'b0);
11234
    // check WB INT signal
11235
    if (wb_int !== 1'b0)
11236
    begin
11237
      test_fail("WB INT signal should not be set");
11238
      fail = fail + 1;
11239
    end
11240
 
11241
    // write to phy's control register for 10Mbps
11242
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
11243
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
11244
    speed = 10;
11245
 
11246
    frame_started = 0;
11247
    frame_ended = 0;
11248
    wait_for_frame = 0;
11249
    check_frame = 0;
11250
    stop_checking_frame = 0;
11251
    first_fr_received = 1; // at the beginning the first frame of each two will be received!
11252
 
11253
    num_of_frames = 0; // 
11254
    num_of_bd = 0;
11255
    i_length = (min_tmp + 1); // 5 bytes longer than MINFL
11256
    while (i_length < (max_tmp - 4))
11257
    begin
11258
      // choose generating carrier sense and collision 
11259
      case (num_of_frames[1:0])
11260
      2'h0: // Interrupt is generated
11261
      begin
11262
        // enable interrupt generation
11263
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
11264
        // not detect carrier sense in FD and no collision
11265
        eth_phy.no_carrier_sense_rx_fd_detect(0);
11266
        eth_phy.collision(0);
11267
      end
11268
      2'h1: // Interrupt is generated
11269
      begin
11270
        // enable interrupt generation
11271
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
11272
        // detect carrier sense in FD and no collision
11273
        eth_phy.no_carrier_sense_rx_fd_detect(1);
11274
        eth_phy.collision(0);
11275
      end
11276
      2'h2: // Interrupt is generated
11277
      begin
11278
        // disable interrupt generation
11279
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
11280
        // not detect carrier sense in FD and set collision
11281
        eth_phy.no_carrier_sense_rx_fd_detect(0);
11282
        eth_phy.collision(1);
11283
      end
11284
      default: // 2'h3: // Interrupt is generated
11285
      begin
11286
        // disable interrupt generation
11287
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
11288
        // detect carrier sense in FD and set collision
11289
        eth_phy.no_carrier_sense_rx_fd_detect(1);
11290
        eth_phy.collision(1);
11291
      end
11292
      endcase
11293
      // set wrap bit
11294
      set_rx_bd_wrap(118);
11295
      set_rx_bd_empty(118, 118);
11296
      check_frame = 0;
11297
      stop_checking_frame = 0;
11298
      tmp_data = 0;
11299
      fork
11300
        begin // enable RX MAC on first of each two packets - every second should be recived normaly
11301
          if (num_of_frames[0] == 1'b0)
11302
          begin
11303
            repeat(1) @(posedge wb_clk);
11304
            if (num_of_frames[1] == 1'b0)
11305
            begin
11306
              repeat (num_of_frames[31:2]) @(posedge mrx_clk); // for every (second) frame enable receiver one clock later
11307
            end
11308
            else
11309
            begin
11310
              @(posedge mrx_clk);
11311
              repeat (num_of_frames[31:2]) @(negedge mrx_clk); // for every (second) frame enable receiver one clock later
11312
            end
11313
            // enable RX, set full-duplex mode, NO receive small, NO correct IFG
11314
            wbm_init_waits = 4'h0;
11315
            wbm_subseq_waits = 4'h0;
11316 274 tadejm
            #1 wait (wbm_working == 0);
11317
            wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
11318 243 tadejm
                      `ETH_MODER_PRO | `ETH_MODER_BRO,
11319
                      4'hF, 1, wbm_init_waits, wbm_subseq_waits); // write ASAP
11320
          end
11321
        end
11322
        begin // send a packet from PHY RX
11323
          repeat(1) @(posedge wb_clk); // wait for WB write when it is without delays
11324
          if (num_of_frames[1] == 1'b0)
11325
          begin
11326
            set_rx_addr_type(0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E);
11327
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
11328
          end
11329
          else
11330
          begin
11331
            set_rx_addr_type((max_tmp), 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E);
11332
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
11333
          end
11334
        end
11335
        begin: send_packet0
11336
          wait (MRxDV === 1'b1); // start transmit
11337
          wait (MRxDV === 1'b0); // end transmit
11338
          check_frame = 1;
11339
          repeat(10) @(posedge mrx_clk);
11340
          repeat(15) @(posedge wb_clk);
11341
          stop_checking_frame = 1;
11342
        end
11343
        begin // count WB clocks between ACK (negedge) and RX_DV (posedge) or vice-versa
11344
          @(posedge eth_sl_wb_ack_o or posedge MRxDV);
11345
          if ((eth_sl_wb_ack_o === 1'b1) && (MRxDV === 1'b1))
11346
          begin
11347
            tmp_data = 32'h8000_0001; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
11348
          end
11349
          else if (MRxDV === 1'b1)
11350
          begin
11351
            while (eth_sl_wb_ack_o === 1'b0)
11352
            begin
11353
              @(posedge wb_clk);
11354
              tmp_data = tmp_data + 1;
11355
            end
11356
            tmp_data = tmp_data | 32'h8000_0000; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
11357
          end
11358
          else if (eth_sl_wb_ack_o === 1'b1)
11359
          begin
11360
            @(posedge wb_clk); // wait for one clock => tmp_data 'becomes' 0
11361
            while (MRxDV === 1'b0)
11362
            begin
11363
              @(posedge wb_clk);
11364
              tmp_data = tmp_data + 1; // bit[31]==0 => 'negedge eth_sl_wb_ack_o' was equal or before 'posedge MRxDV'
11365
            end
11366
          end
11367
        end
11368
        begin // check packet
11369
          wait (check_frame == 1);
11370
          check_rx_bd(118, tmp_bd);
11371
          while ((tmp_bd[15] === 1) && (stop_checking_frame == 0))
11372
          begin
11373
            #1 check_rx_bd(118, tmp_bd);
11374
            @(posedge wb_clk);
11375
          end
11376
          if (num_of_frames[0] == 1'b0)
11377
          begin
11378
            if (tmp_bd[15] === 1)
11379
            begin
11380
              if (first_fr_received == 1)
11381
              begin
11382
                first_fr_received = 0;
11383
                $display("    %0d packets (without this one) are checked - packets are received by two in a set",
11384
                         num_of_frames); // +1 due to start with 0 AND -1 because this packet is excluded
11385
                $display("    From this moment:");
11386
                $display("    first one of two packets (including this one) is not accepted due to late RX enable");
11387
                if (tmp_data[31])
11388
                  $display("    ->RX enable set %0d WB clks after RX_DV", tmp_data[30:0]);
11389
                else
11390
                  $display("    ->RX enable set %0d WB clks before RX_DV", tmp_data[30:0]);
11391
              end
11392
            end
11393
          end
11394
          if (stop_checking_frame == 0)
11395
            disable send_packet0;
11396
        end
11397
      join
11398
      // ONLY IF packet was received!
11399
      if (tmp_bd[15] === 0)
11400
      begin
11401
        // check length of a PACKET
11402
        if (tmp_bd[31:16] != (i_length + 4))
11403
        begin
11404
          `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
11405
                          tmp_bd[31:16], (i_length + 4));
11406
          test_fail("Wrong length of the packet out from PHY");
11407
          fail = fail + 1;
11408
        end
11409
        // check received RX packet data and CRC
11410
        if (first_fr_received == 0) // if PREVIOUS RX buffer descriptor was not ready, pointer address is -1
11411
        begin
11412
          if (num_of_frames[1] == 1'b0)
11413
          begin
11414
            check_rx_packet(0, (`MEMORY_BASE + num_of_frames[1:0] - 1'b1), (i_length + 4), 1'b0, 1'b0, tmp);
11415
          end
11416
          else
11417
          begin
11418
            check_rx_packet(max_tmp, (`MEMORY_BASE + num_of_frames[1:0] - 1'b1), (i_length + 4), 1'b0, 1'b0, tmp);
11419
          end
11420
          if (tmp > 0)
11421
          begin
11422
            `TIME; $display("*E Wrong data of the received packet");
11423
            test_fail("Wrong data of the received packet");
11424
            fail = fail + 1;
11425
          end
11426
        end
11427
        else // if PREVIOUS RX buffer descriptor was ready
11428
        begin
11429
          if (num_of_frames[1] == 1'b0)
11430
          begin
11431
            check_rx_packet(0, (`MEMORY_BASE + num_of_frames[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
11432
          end
11433
          else
11434
          begin
11435
            check_rx_packet(max_tmp, (`MEMORY_BASE + num_of_frames[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
11436
          end
11437
          if (tmp > 0)
11438
          begin
11439
            `TIME; $display("*E Wrong data of the received packet");
11440
            test_fail("Wrong data of the received packet");
11441
            fail = fail + 1;
11442
          end
11443
        end
11444
      end
11445
      // check WB INT signal
11446
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
11447
      begin
11448
        if (wb_int !== 1'b0)
11449
        begin
11450
          `TIME; $display("*E WB INT signal should not be set");
11451
          test_fail("WB INT signal should not be set");
11452
          fail = fail + 1;
11453
        end
11454
      end
11455
      else
11456
      begin
11457
        if (wb_int !== 1'b1)
11458
        begin
11459
          `TIME; $display("*E WB INT signal should be set");
11460
          test_fail("WB INT signal should be set");
11461
          fail = fail + 1;
11462
        end
11463
      end
11464
      // check RX buffer descriptor of a packet - only 15 LSBits
11465
      check_rx_bd(118, data);
11466
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
11467
      begin
11468
        if (data[15:0] !== 16'hE000)
11469
        begin
11470
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
11471
          test_fail("RX buffer descriptor status is not correct");
11472
          fail = fail + 1;
11473
        end
11474
      end
11475
      else // interrupt enabled
11476
      begin
11477 279 mohor
        if ((data[15:0] !== 16'h6000) && (data[15:0] !== 16'h6080)) // because of promiscuous
11478 243 tadejm
        begin
11479
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
11480
          test_fail("RX buffer descriptor status is not correct");
11481
          fail = fail + 1;
11482
        end
11483
      end
11484
      // check interrupts
11485 274 tadejm
      wait (wbm_working == 0);
11486 243 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11487
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
11488
      begin
11489
        if (data !== 0)
11490
        begin
11491
          `TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, num_of_frames[1:0]);
11492
          test_fail("Any of interrupts was set");
11493
          fail = fail + 1;
11494
        end
11495
      end
11496
      else
11497
      begin
11498
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
11499
        begin
11500
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
11501
          test_fail("Interrupt Receive Buffer was not set");
11502
          fail = fail + 1;
11503
        end
11504
        if ((data & (~`ETH_INT_RXB)) !== 0)
11505
        begin
11506
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
11507
          test_fail("Other interrupts (except Receive Buffer) were set");
11508
          fail = fail + 1;
11509
        end
11510
      end
11511
      // clear interrupts
11512 274 tadejm
      wait (wbm_working == 0);
11513 243 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11514
      // check WB INT signal
11515
      if (wb_int !== 1'b0)
11516
      begin
11517
        test_fail("WB INT signal should not be set");
11518
        fail = fail + 1;
11519
      end
11520
      // disable RX after two packets
11521
      if (num_of_frames[0] == 1'b1)
11522
      begin
11523
        // disable RX, set full-duplex mode, NO receive small, NO correct IFG
11524 274 tadejm
        wait (wbm_working == 0);
11525 243 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
11526
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
11527
                  4'hF, 1, 4'h0, 4'h0); // write ASAP
11528
      end
11529
      // the number of frame transmitted
11530
      num_of_frames = num_of_frames + 1;
11531
      num_of_bd = 0;
11532
      // set length (LOOP variable)
11533
      if (num_of_frames[31:2] == (i_length * 2 + 16)) // 64 => this vas last Byte (1st .. 64th) when i_length = min_tmp - 4
11534
        i_length = (max_tmp - 4);
11535
      @(posedge wb_clk);
11536
    end
11537
    // disable RX
11538 274 tadejm
    wait (wbm_working == 0);
11539 243 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
11540
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11541
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11542
    if(fail == 0)
11543
      test_ok;
11544
    else
11545
      fail = 0;
11546
  end
11547
 
11548
 
11549
  ////////////////////////////////////////////////////////////////////
11550
  ////                                                            ////
11551
  ////  Test receive packet synchronization with receive          ////
11552
  ////  disable/enable ( 100Mbps ).                               ////
11553
  ////                                                            ////
11554
  ////////////////////////////////////////////////////////////////////
11555
  if (test_num == 3) // Test no receive when all buffers are TX ( 100Mbps ).
11556
  begin
11557
    // TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )
11558
    test_name   = "TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )";
11559
    `TIME; $display("  TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )");
11560
 
11561
    // unmask interrupts
11562 274 tadejm
    wait (wbm_working == 0);
11563 243 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
11564
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11565
    // set 10 RX buffer descriptor (8'h80 - 8'hA) - must be set before RX enable
11566 274 tadejm
    wait (wbm_working == 0);
11567 243 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h76, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11568
    // disable RX, set full-duplex mode, NO receive small, NO correct IFG
11569 274 tadejm
    wait (wbm_working == 0);
11570 243 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
11571
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11572
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11573
    // prepare two packets of MAXFL length
11574 274 tadejm
    wait (wbm_working == 0);
11575 243 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11576
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
11577
    min_tmp = tmp[31:16];
11578
    st_data = 8'h0F;
11579
    set_rx_packet(0, (min_tmp + 1), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
11580
    append_rx_crc(0, (min_tmp + 1), 1'b0, 1'b0);
11581
    st_data = 8'h1A;
11582
    set_rx_packet(max_tmp, (min_tmp + 1), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
11583
    append_rx_crc(max_tmp, (min_tmp + 1), 1'b0, 1'b0);
11584
    // check WB INT signal
11585
    if (wb_int !== 1'b0)
11586
    begin
11587
      test_fail("WB INT signal should not be set");
11588
      fail = fail + 1;
11589
    end
11590
 
11591
    // write to phy's control register for 100Mbps
11592
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
11593
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
11594
    speed = 100;
11595
 
11596
    frame_started = 0;
11597
    frame_ended = 0;
11598
    wait_for_frame = 0;
11599
    check_frame = 0;
11600
    stop_checking_frame = 0;
11601
    first_fr_received = 1; // at the beginning the first frame of each two will be received!
11602
 
11603
    num_of_frames = 0; // 
11604
    num_of_bd = 0;
11605
    i_length = (min_tmp + 1); // 5 bytes longer than MINFL
11606
    while (i_length < (max_tmp - 4))
11607
    begin
11608
      // choose generating carrier sense and collision 
11609
      case (num_of_frames[1:0])
11610
      2'h0: // Interrupt is generated
11611
      begin
11612
        // enable interrupt generation
11613
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
11614
        // not detect carrier sense in FD and no collision
11615
        eth_phy.no_carrier_sense_rx_fd_detect(0);
11616
        eth_phy.collision(0);
11617
      end
11618
      2'h1: // Interrupt is generated
11619
      begin
11620
        // enable interrupt generation
11621
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
11622
        // detect carrier sense in FD and no collision
11623
        eth_phy.no_carrier_sense_rx_fd_detect(1);
11624
        eth_phy.collision(0);
11625
      end
11626
      2'h2: // Interrupt is generated
11627
      begin
11628
        // disable interrupt generation
11629
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
11630
        // not detect carrier sense in FD and set collision
11631
        eth_phy.no_carrier_sense_rx_fd_detect(0);
11632
        eth_phy.collision(1);
11633
      end
11634
      default: // 2'h3: // Interrupt is generated
11635
      begin
11636
        // disable interrupt generation
11637
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
11638
        // detect carrier sense in FD and set collision
11639
        eth_phy.no_carrier_sense_rx_fd_detect(1);
11640
        eth_phy.collision(1);
11641
      end
11642
      endcase
11643
//if (first_fr_received == 0)
11644
//begin
11645
//  check_rx_bd(118, data);
11646 274 tadejm
//  wait (wbm_working == 0);
11647 243 tadejm
//  wbm_read((`TX_BD_BASE + (118 * 8) + 4), tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11648
//  $display("RX BD set : %h, %h", data, tmp);
11649
//end
11650
      // set wrap bit
11651
      set_rx_bd_wrap(118);
11652
      set_rx_bd_empty(118, 118);
11653
      check_frame = 0;
11654
      stop_checking_frame = 0;
11655
      tmp_data = 0;
11656
      fork
11657
        begin // enable RX MAC on first of each two packets - every second should be recived normaly
11658
          if (num_of_frames[0] == 1'b0)
11659
          begin
11660
            repeat(1) @(posedge wb_clk);
11661
            if (num_of_frames[1] == 1'b0)
11662
            begin
11663
              repeat (num_of_frames[31:2]) @(posedge mrx_clk); // for every (second) frame enable receiver one clock later
11664
            end
11665
            else
11666
            begin
11667
              @(posedge mrx_clk);
11668
              repeat (num_of_frames[31:2]) @(negedge mrx_clk); // for every (second) frame enable receiver one clock later
11669
            end
11670
            // enable RX, set full-duplex mode, NO receive small, NO correct IFG
11671
            wbm_init_waits = 4'h0;
11672
            wbm_subseq_waits = 4'h0;
11673 274 tadejm
            #1 wait (wbm_working == 0);
11674
            wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
11675 243 tadejm
                      `ETH_MODER_PRO | `ETH_MODER_BRO,
11676
                      4'hF, 1, wbm_init_waits, wbm_subseq_waits); // write ASAP
11677
$display("mama 2, num_of_frames=%0h", num_of_frames);
11678
          end
11679
        end
11680
        begin // send a packet from PHY RX
11681
          repeat(1) @(posedge wb_clk); // wait for WB write when it is without delays
11682
          if (num_of_frames[1] == 1'b0)
11683
          begin
11684
            set_rx_addr_type(0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E);
11685
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
11686
          end
11687
          else
11688
          begin
11689
            set_rx_addr_type((max_tmp), 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E);
11690
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
11691
          end
11692
        end
11693
        begin: send_packet1
11694
          wait (MRxDV === 1'b1); // start transmit
11695
          wait (MRxDV === 1'b0); // end transmit
11696
          check_frame = 1;
11697
$display("mama 3");
11698
          repeat(10) @(posedge mrx_clk);
11699
          repeat(15) @(posedge wb_clk);
11700
          stop_checking_frame = 1;
11701
        end
11702
        begin // count WB clocks between ACK (negedge) and RX_DV (posedge) or vice-versa
11703
          @(posedge eth_sl_wb_ack_o or posedge MRxDV);
11704
$display("mama 4");
11705
          if ((eth_sl_wb_ack_o === 1'b1) && (MRxDV === 1'b1))
11706
          begin
11707
            tmp_data = 32'h8000_0001; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
11708
$display("mama 4_1");
11709
          end
11710
          else if (MRxDV === 1'b1)
11711
          begin
11712
            while (eth_sl_wb_ack_o === 1'b0)
11713
            begin
11714
              @(posedge wb_clk);
11715
              tmp_data = tmp_data + 1;
11716
            end
11717
            tmp_data = tmp_data | 32'h8000_0000; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
11718
$display("mama 4_2");
11719
          end
11720
          else if (eth_sl_wb_ack_o === 1'b1)
11721
          begin
11722
            @(posedge wb_clk); // wait for one clock => tmp_data 'becomes' 0
11723
            while (MRxDV === 1'b0)
11724
            begin
11725
              @(posedge wb_clk);
11726
              tmp_data = tmp_data + 1; // bit[31]==0 => 'negedge eth_sl_wb_ack_o' was equal or before 'posedge MRxDV'
11727
            end
11728
$display("mama 4_3");
11729
          end
11730
        end
11731
        begin // check packet
11732
          wait (check_frame == 1);
11733
          check_rx_bd(118, tmp_bd);
11734
          while ((tmp_bd[15] === 1) && (stop_checking_frame == 0))
11735
          begin
11736
            #1 check_rx_bd(118, tmp_bd);
11737
            @(posedge wb_clk);
11738
          end
11739
$display("mama 5, tmp_bd=%0h", tmp_bd);
11740
          if (num_of_frames[0] == 1'b0)
11741
          begin
11742
            if (tmp_bd[15] === 1)
11743
            begin
11744
              if (first_fr_received == 1)
11745
              begin
11746
                first_fr_received = 0;
11747
                $display("    %0d packets (without this one) are checked - packets are received by two in a set",
11748
                         num_of_frames); // +1 due to start with 0 AND -1 because this packet is excluded
11749
                $display("    From this moment:");
11750
                $display("    first one of two packets (including this one) is not accepted due to late RX enable");
11751
                if (tmp_data[31])
11752
                  $display("    ->RX enable set %0d WB clks after RX_DV", tmp_data[30:0]);
11753
                else
11754
                  $display("    ->RX enable set %0d WB clks before RX_DV", tmp_data[30:0]);
11755
              end
11756
              // check FB, etc.
11757
 
11758
            end
11759
            else // (tmp_bd[15] === 0)
11760
            begin // check FB, packet, etc.
11761
 
11762
            end
11763
$display("mama 5_1");
11764
          end
11765
          else // (num_of_frames[0] == 1'b1)
11766
          begin
11767
            if (tmp_bd[15] === 1) // ERROR, because second packet of each two frames should be received
11768
            begin // check NOTHING
11769
 
11770
            end
11771
            else // (tmp_bd[15] === 0)
11772
            begin // check FB, packet, etc.
11773
 
11774
            end
11775
$display("mama 5_2");
11776
          end
11777
          if (stop_checking_frame == 0)
11778
            disable send_packet1;
11779
        end
11780
      join
11781
      // ONLY IF packet was received!
11782
$display("mama 6");
11783
      if (tmp_bd[15] === 0)
11784
      begin
11785
        // check length of a PACKET
11786
        if (tmp_bd[31:16] != (i_length + 4))
11787
        begin
11788
          `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
11789
                          tmp_bd[31:16], (i_length + 4));
11790
          test_fail("Wrong length of the packet out from PHY");
11791
          fail = fail + 1;
11792
        end
11793
        // check received RX packet data and CRC
11794
        if (first_fr_received == 0) // if PREVIOUS RX buffer descriptor was not ready, pointer address is -1
11795
        begin
11796
          if (num_of_frames[1] == 1'b0)
11797
          begin
11798
            check_rx_packet(0, (`MEMORY_BASE + num_of_frames[1:0] - 1'b1), (i_length + 4), 1'b0, 1'b0, tmp);
11799
          end
11800
          else
11801
          begin
11802
            check_rx_packet(max_tmp, (`MEMORY_BASE + num_of_frames[1:0] - 1'b1), (i_length + 4), 1'b0, 1'b0, tmp);
11803
          end
11804
          if (tmp > 0)
11805
          begin
11806
            `TIME; $display("*E Wrong data of the received packet");
11807
            test_fail("Wrong data of the received packet");
11808
            fail = fail + 1;
11809
          end
11810
        end
11811
        else // if PREVIOUS RX buffer descriptor was ready
11812
        begin
11813
          if (num_of_frames[1] == 1'b0)
11814
          begin
11815
            check_rx_packet(0, (`MEMORY_BASE + num_of_frames[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
11816
          end
11817
          else
11818
          begin
11819
            check_rx_packet(max_tmp, (`MEMORY_BASE + num_of_frames[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
11820
          end
11821
          if (tmp > 0)
11822
          begin
11823
            `TIME; $display("*E Wrong data of the received packet");
11824
            test_fail("Wrong data of the received packet");
11825
            fail = fail + 1;
11826
          end
11827
        end
11828
      end
11829
      // check WB INT signal
11830
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
11831
      begin
11832
        if (wb_int !== 1'b0)
11833
        begin
11834
          `TIME; $display("*E WB INT signal should not be set");
11835
          test_fail("WB INT signal should not be set");
11836
          fail = fail + 1;
11837
        end
11838
      end
11839
      else
11840
      begin
11841
        if (wb_int !== 1'b1)
11842
        begin
11843
          `TIME; $display("*E WB INT signal should be set");
11844
          test_fail("WB INT signal should be set");
11845
          fail = fail + 1;
11846
        end
11847
      end
11848
      // check RX buffer descriptor of a packet - only 15 LSBits
11849
      check_rx_bd(118, data);
11850
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
11851
      begin
11852
        if (data[15:0] !== 16'hE000)
11853
        begin
11854
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
11855
          test_fail("RX buffer descriptor status is not correct");
11856
          fail = fail + 1;
11857
        end
11858
      end
11859
      else // interrupt enabled
11860
      begin
11861 279 mohor
        if ((data[15:0] !== 16'h6000) && (data[15:0] !== 16'h6080)) // because of promiscuous
11862 243 tadejm
        begin
11863
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
11864
          test_fail("RX buffer descriptor status is not correct");
11865
          fail = fail + 1;
11866
        end
11867
      end
11868
      // check interrupts
11869 274 tadejm
      wait (wbm_working == 0);
11870 243 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11871
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
11872
      begin
11873
        if (data !== 0)
11874
        begin
11875
          `TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, num_of_frames[1:0]);
11876
          test_fail("Any of interrupts was set");
11877
          fail = fail + 1;
11878
        end
11879
      end
11880
      else
11881
      begin
11882
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
11883
        begin
11884
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
11885
          test_fail("Interrupt Receive Buffer was not set");
11886
          fail = fail + 1;
11887
        end
11888
        if ((data & (~`ETH_INT_RXB)) !== 0)
11889
        begin
11890
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
11891
          test_fail("Other interrupts (except Receive Buffer) were set");
11892
          fail = fail + 1;
11893
        end
11894
      end
11895
      // clear interrupts
11896 274 tadejm
      wait (wbm_working == 0);
11897 243 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11898
      // check WB INT signal
11899
      if (wb_int !== 1'b0)
11900
      begin
11901
        test_fail("WB INT signal should not be set");
11902
        fail = fail + 1;
11903
      end
11904
      // disable RX after two packets
11905
      if (num_of_frames[0] == 1'b1)
11906
      begin
11907
        // disable RX, set full-duplex mode, NO receive small, NO correct IFG
11908 274 tadejm
        wait (wbm_working == 0);
11909 243 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
11910
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
11911
                  4'hF, 1, 4'h0, 4'h0); // write ASAP
11912
      end
11913
      // the number of frame transmitted
11914
      num_of_frames = num_of_frames + 1;
11915
      num_of_bd = 0;
11916
      // set length (LOOP variable)
11917
      if (num_of_frames[31:2] == (i_length * 2 + 16)) // 64 => this vas last Byte (1st .. 64th) when i_length = min_tmp - 4
11918
        i_length = (max_tmp - 4);
11919
      @(posedge wb_clk);
11920
    end
11921
    // disable RX
11922 274 tadejm
    wait (wbm_working == 0);
11923 243 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
11924
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11925
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11926
    if(fail == 0)
11927
      test_ok;
11928
    else
11929
      fail = 0;
11930
  end
11931
 
11932
 
11933
  ////////////////////////////////////////////////////////////////////
11934
  ////                                                            ////
11935 209 tadejm
  ////  Test receive packets form MINFL to MAXFL sizes at         ////
11936
  ////  one RX buffer decriptor ( 10Mbps ).                       ////
11937
  ////                                                            ////
11938
  ////////////////////////////////////////////////////////////////////
11939 243 tadejm
  if (test_num == 4) // 
11940 209 tadejm
  begin
11941 243 tadejm
    // TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )
11942
    test_name   = "TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )";
11943
    `TIME; $display("  TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )");
11944 209 tadejm
 
11945
    // unmask interrupts
11946 274 tadejm
    wait (wbm_working == 0);
11947 209 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
11948
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11949
    // set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
11950 274 tadejm
    wait (wbm_working == 0);
11951 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11952
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
11953 274 tadejm
    wait (wbm_working == 0);
11954 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
11955
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11956
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11957
    // prepare two packets of MAXFL length
11958 274 tadejm
    wait (wbm_working == 0);
11959 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11960
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
11961
    min_tmp = tmp[31:16];
11962
    st_data = 8'h0F;
11963
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
11964
    st_data = 8'h1A;
11965
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
11966
    // check WB INT signal
11967
    if (wb_int !== 1'b0)
11968
    begin
11969
      test_fail("WB INT signal should not be set");
11970
      fail = fail + 1;
11971
    end
11972
 
11973
    // write to phy's control register for 10Mbps
11974
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
11975
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
11976
    speed = 10;
11977
 
11978
    i_length = (min_tmp - 4);
11979
    while (i_length <= (max_tmp - 4))
11980
    begin
11981
      // choose generating carrier sense and collision for first and last 64 lengths of frames
11982
      case (i_length[1:0])
11983
      2'h0: // Interrupt is generated
11984
      begin
11985
        // enable interrupt generation
11986
        set_rx_bd(127, 127, 1'b1, (`MEMORY_BASE + i_length[1:0]));
11987
        // unmask interrupts
11988 274 tadejm
        wait (wbm_working == 0);
11989 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
11990
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11991
        // not detect carrier sense in FD and no collision
11992
        eth_phy.no_carrier_sense_rx_fd_detect(0);
11993
        eth_phy.collision(0);
11994
      end
11995
      2'h1: // Interrupt is not generated
11996
      begin
11997
        // enable interrupt generation
11998
        set_rx_bd(127, 127, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
11999
        // mask interrupts
12000 274 tadejm
        wait (wbm_working == 0);
12001 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12002
        // detect carrier sense in FD and no collision
12003
        eth_phy.no_carrier_sense_rx_fd_detect(1);
12004
        eth_phy.collision(0);
12005
      end
12006
      2'h2: // Interrupt is not generated
12007
      begin
12008
        // disable interrupt generation
12009
        set_rx_bd(127, 127, 1'b0, (`MEMORY_BASE + i_length[1:0]));
12010
        // unmask interrupts
12011 274 tadejm
        wait (wbm_working == 0);
12012 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
12013
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12014
        // not detect carrier sense in FD and set collision
12015
        eth_phy.no_carrier_sense_rx_fd_detect(0);
12016
        eth_phy.collision(1);
12017
      end
12018
      default: // 2'h3: // Interrupt is not generated
12019
      begin
12020
        // disable interrupt generation
12021
        set_rx_bd(127, 127, 1'b0, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
12022
        // mask interrupts
12023 274 tadejm
        wait (wbm_working == 0);
12024 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12025
        // detect carrier sense in FD and set collision
12026
        eth_phy.no_carrier_sense_rx_fd_detect(1);
12027
        eth_phy.collision(1);
12028
      end
12029
      endcase
12030
      if (i_length[0] == 1'b0)
12031
        append_rx_crc (0, i_length, 1'b0, 1'b0);
12032
      else
12033
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
12034
      // set wrap bit
12035
      set_rx_bd_wrap(127);
12036
      set_rx_bd_empty(127, 127);
12037
      fork
12038
        begin
12039
          if (i_length[0] == 1'b0)
12040
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
12041
          else
12042
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
12043
          repeat(10) @(posedge mrx_clk);
12044
        end
12045
        begin
12046
          #1 check_rx_bd(127, data);
12047
          if (i_length < min_tmp) // just first four
12048
          begin
12049
            while (data[15] === 1)
12050
            begin
12051
              #1 check_rx_bd(127, data);
12052
              @(posedge wb_clk);
12053
            end
12054
            repeat (1) @(posedge wb_clk);
12055
          end
12056
          else
12057
          begin
12058
            wait (MRxDV === 1'b1); // start transmit
12059
            #1 check_rx_bd(127, data);
12060
            if (data[15] !== 1)
12061
            begin
12062
              test_fail("Wrong buffer descriptor's ready bit read out from MAC");
12063
              fail = fail + 1;
12064
            end
12065
            wait (MRxDV === 1'b0); // end transmit
12066
            while (data[15] === 1)
12067
            begin
12068
              #1 check_rx_bd(127, data);
12069
              @(posedge wb_clk);
12070
            end
12071
            repeat (1) @(posedge wb_clk);
12072
          end
12073
        end
12074
      join
12075
      // check length of a PACKET
12076
      if (data[31:16] != (i_length + 4))
12077
      begin
12078
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
12079
                        data[31:16], (i_length + 4));
12080
        test_fail("Wrong length of the packet out from PHY");
12081
        fail = fail + 1;
12082
      end
12083
      // checking in the following if statement is performed only for first and last 64 lengths
12084
      // check received RX packet data and CRC
12085
      if (i_length[0] == 1'b0)
12086
      begin
12087
        check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
12088
      end
12089
      else
12090
      begin
12091
        check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
12092
      end
12093
      if (tmp > 0)
12094
      begin
12095
        `TIME; $display("*E Wrong data of the received packet");
12096
        test_fail("Wrong data of the received packet");
12097
        fail = fail + 1;
12098
      end
12099
      // check WB INT signal
12100
      if (i_length[1:0] == 2'h0)
12101
      begin
12102
        if (wb_int !== 1'b1)
12103
        begin
12104
          `TIME; $display("*E WB INT signal should be set");
12105
          test_fail("WB INT signal should be set");
12106
          fail = fail + 1;
12107
        end
12108
      end
12109
      else
12110
      begin
12111
        if (wb_int !== 1'b0)
12112
        begin
12113
          `TIME; $display("*E WB INT signal should not be set");
12114
          test_fail("WB INT signal should not be set");
12115
          fail = fail + 1;
12116
        end
12117
      end
12118
      // check RX buffer descriptor of a packet
12119
      check_rx_bd(127, data);
12120
      if (i_length[1] == 1'b0) // interrupt enabled no_carrier_sense_rx_fd_detect
12121
      begin
12122
        if ( ((data[15:0] !== 16'h6000) && (i_length[0] == 1'b0)) ||
12123
             ((data[15:0] !== 16'h6000) && (i_length[0] == 1'b1)) )
12124
        begin
12125
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
12126
          test_fail("RX buffer descriptor status is not correct");
12127
          fail = fail + 1;
12128
        end
12129
      end
12130
      else // interrupt not enabled
12131
      begin
12132
        if ( ((data[15:0] !== 16'h2000) && (i_length[0] == 1'b0)) ||
12133
             ((data[15:0] !== 16'h2000) && (i_length[0] == 1'b1)) )
12134
        begin
12135
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
12136
          test_fail("RX buffer descriptor status is not correct");
12137
          fail = fail + 1;
12138
        end
12139
      end
12140
      // clear RX buffer descriptor for first 4 frames
12141
      if (i_length < min_tmp)
12142
        clear_rx_bd(127, 127);
12143
      // check interrupts
12144 274 tadejm
      wait (wbm_working == 0);
12145 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12146
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
12147
      begin
12148
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
12149
        begin
12150
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
12151
          test_fail("Interrupt Receive Buffer was not set");
12152
          fail = fail + 1;
12153
        end
12154
        if ((data & (~`ETH_INT_RXB)) !== 0)
12155
        begin
12156
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
12157
          test_fail("Other interrupts (except Receive Buffer) were set");
12158
          fail = fail + 1;
12159
        end
12160
      end
12161
      else
12162
      begin
12163
        if (data !== 0)
12164
        begin
12165
          `TIME; $display("*E Any of interrupts (except Receive Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
12166
          test_fail("Any of interrupts (except Receive Buffer) was set");
12167
          fail = fail + 1;
12168
        end
12169
      end
12170
      // clear interrupts
12171 274 tadejm
      wait (wbm_working == 0);
12172 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12173
      // check WB INT signal
12174
      if (wb_int !== 1'b0)
12175
      begin
12176
        test_fail("WB INT signal should not be set");
12177
        fail = fail + 1;
12178
      end
12179
      // INTERMEDIATE DISPLAYS
12180
      if ((i_length + 4) == (min_tmp + 64))
12181
      begin
12182
        // starting length is min_tmp, ending length is (min_tmp + 64)
12183
        $display("    receive small packets is NOT selected");
12184
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
12185
                 min_tmp, (min_tmp + 64));
12186
        // set receive small, remain the rest
12187 274 tadejm
        wait (wbm_working == 0);
12188 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
12189
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12190
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12191
      end
12192
      else if ((i_length + 4) == (max_tmp - 16))
12193
      begin
12194
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
12195
        $display("    receive small packets is selected");
12196
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
12197
                 (min_tmp + 64 + 128), tmp_data);
12198
        // reset receive small, remain the rest
12199 274 tadejm
        wait (wbm_working == 0);
12200 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
12201
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12202
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12203
      end
12204
      else if ((i_length + 4) == max_tmp)
12205
      begin
12206
        $display("    receive small packets is NOT selected");
12207
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
12208
                 (max_tmp - (4 + 16)), max_tmp);
12209
      end
12210
      // set length (loop variable)
12211
      if ((i_length + 4) < (min_tmp + 64))
12212
        i_length = i_length + 1;
12213
      else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
12214
      begin
12215
        i_length = i_length + 128;
12216
        tmp_data = i_length + 4; // last tmp_data is ending length
12217
      end
12218
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
12219
        i_length = max_tmp - (4 + 16);
12220
      else if ((i_length + 4) >= (max_tmp - 16))
12221
        i_length = i_length + 1;
12222
      else
12223
      begin
12224
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
12225
        #10 $stop;
12226
      end
12227
    end
12228
    // disable RX
12229 274 tadejm
    wait (wbm_working == 0);
12230 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
12231
              `ETH_MODER_PRO | `ETH_MODER_BRO,
12232
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12233
    if(fail == 0)
12234
      test_ok;
12235
    else
12236
      fail = 0;
12237
  end
12238
 
12239
 
12240
  ////////////////////////////////////////////////////////////////////
12241
  ////                                                            ////
12242
  ////  Test receive packets form MINFL to MAXFL sizes at         ////
12243
  ////  one RX buffer decriptor ( 100Mbps ).                      ////
12244
  ////                                                            ////
12245
  ////////////////////////////////////////////////////////////////////
12246 243 tadejm
  if (test_num == 5) // Test no receive when all buffers are TX ( 100Mbps ).
12247 209 tadejm
  begin
12248 243 tadejm
    // TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )
12249
    test_name   = "TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )";
12250
    `TIME; $display("  TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )");
12251 209 tadejm
 
12252
    // unmask interrupts
12253 274 tadejm
    wait (wbm_working == 0);
12254 209 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
12255
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12256
    // set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
12257 274 tadejm
    wait (wbm_working == 0);
12258 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12259
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
12260 274 tadejm
    wait (wbm_working == 0);
12261 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
12262
              `ETH_MODER_PRO | `ETH_MODER_BRO,
12263
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12264
    // prepare two packets of MAXFL length
12265 274 tadejm
    wait (wbm_working == 0);
12266 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12267
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
12268
    min_tmp = tmp[31:16];
12269
    st_data = 8'h0F;
12270
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
12271
    st_data = 8'h1A;
12272
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
12273
    // check WB INT signal
12274
    if (wb_int !== 1'b0)
12275
    begin
12276
      test_fail("WB INT signal should not be set");
12277
      fail = fail + 1;
12278
    end
12279
 
12280
    // write to phy's control register for 100Mbps
12281
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
12282
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
12283
    speed = 100;
12284
 
12285
    i_length = (min_tmp - 4);
12286
    while (i_length <= (max_tmp - 4))
12287
    begin
12288
      // choose generating carrier sense and collision for first and last 64 lengths of frames
12289
      case (i_length[1:0])
12290
      2'h0: // Interrupt is generated
12291
      begin
12292
        // enable interrupt generation
12293
        set_rx_bd(127, 127, 1'b1, (`MEMORY_BASE + i_length[1:0]));
12294
        // unmask interrupts
12295 274 tadejm
        wait (wbm_working == 0);
12296 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
12297
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12298
        // not detect carrier sense in FD and no collision
12299
        eth_phy.no_carrier_sense_rx_fd_detect(0);
12300
        eth_phy.collision(0);
12301
      end
12302
      2'h1: // Interrupt is not generated
12303
      begin
12304
        // enable interrupt generation
12305
        set_rx_bd(127, 127, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
12306
        // mask interrupts
12307 274 tadejm
        wait (wbm_working == 0);
12308 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12309
        // detect carrier sense in FD and no collision
12310
        eth_phy.no_carrier_sense_rx_fd_detect(1);
12311
        eth_phy.collision(0);
12312
      end
12313
      2'h2: // Interrupt is not generated
12314
      begin
12315
        // disable interrupt generation
12316
        set_rx_bd(127, 127, 1'b0, (`MEMORY_BASE + i_length[1:0]));
12317
        // unmask interrupts
12318 274 tadejm
        wait (wbm_working == 0);
12319 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
12320
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12321
        // not detect carrier sense in FD and set collision
12322
        eth_phy.no_carrier_sense_rx_fd_detect(0);
12323
        eth_phy.collision(1);
12324
      end
12325
      default: // 2'h3: // Interrupt is not generated
12326
      begin
12327
        // disable interrupt generation
12328
        set_rx_bd(127, 127, 1'b0, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
12329
        // mask interrupts
12330 274 tadejm
        wait (wbm_working == 0);
12331 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12332
        // detect carrier sense in FD and set collision
12333
        eth_phy.no_carrier_sense_rx_fd_detect(1);
12334
        eth_phy.collision(1);
12335
      end
12336
      endcase
12337
      if (i_length[0] == 1'b0)
12338
        append_rx_crc (0, i_length, 1'b0, 1'b0);
12339
      else
12340
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
12341
      // set wrap bit
12342
      set_rx_bd_wrap(127);
12343
      set_rx_bd_empty(127, 127);
12344
      fork
12345
        begin
12346
          if (i_length[0] == 1'b0)
12347
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
12348
          else
12349
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
12350
          repeat(10) @(posedge mrx_clk);
12351
        end
12352
        begin
12353
          #1 check_rx_bd(127, data);
12354
          if (i_length < min_tmp) // just first four
12355
          begin
12356
            while (data[15] === 1)
12357
            begin
12358
              #1 check_rx_bd(127, data);
12359
              @(posedge wb_clk);
12360
            end
12361
            repeat (1) @(posedge wb_clk);
12362
          end
12363
          else
12364
          begin
12365
            wait (MRxDV === 1'b1); // start transmit
12366
            #1 check_rx_bd(127, data);
12367
            if (data[15] !== 1)
12368
            begin
12369
              test_fail("Wrong buffer descriptor's ready bit read out from MAC");
12370
              fail = fail + 1;
12371
            end
12372
            wait (MRxDV === 1'b0); // end transmit
12373
            while (data[15] === 1)
12374
            begin
12375
              #1 check_rx_bd(127, data);
12376
              @(posedge wb_clk);
12377
            end
12378
            repeat (1) @(posedge wb_clk);
12379
          end
12380
        end
12381
      join
12382
      // check length of a PACKET
12383
      if (data[31:16] != (i_length + 4))
12384
      begin
12385
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
12386
                        data[31:16], (i_length + 4));
12387
        test_fail("Wrong length of the packet out from PHY");
12388
        fail = fail + 1;
12389
      end
12390
      // checking in the following if statement is performed only for first and last 64 lengths
12391
      // check received RX packet data and CRC
12392
      if (i_length[0] == 1'b0)
12393
      begin
12394
        check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
12395
      end
12396
      else
12397
      begin
12398
        check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
12399
      end
12400
      if (tmp > 0)
12401
      begin
12402
        `TIME; $display("*E Wrong data of the received packet");
12403
        test_fail("Wrong data of the received packet");
12404
        fail = fail + 1;
12405
      end
12406
      // check WB INT signal
12407
      if (i_length[1:0] == 2'h0)
12408
      begin
12409
        if (wb_int !== 1'b1)
12410
        begin
12411
          `TIME; $display("*E WB INT signal should be set");
12412
          test_fail("WB INT signal should be set");
12413
          fail = fail + 1;
12414
        end
12415
      end
12416
      else
12417
      begin
12418
        if (wb_int !== 1'b0)
12419
        begin
12420
          `TIME; $display("*E WB INT signal should not be set");
12421
          test_fail("WB INT signal should not be set");
12422
          fail = fail + 1;
12423
        end
12424
      end
12425
      // check RX buffer descriptor of a packet
12426
      check_rx_bd(127, data);
12427
      if (i_length[1] == 1'b0) // interrupt enabled 
12428
      begin
12429
        if ( ((data[15:0] !== 16'h6000) && (i_length[0] == 1'b0)) ||
12430
             ((data[15:0] !== 16'h6000) && (i_length[0] == 1'b1)) )
12431
        begin
12432
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
12433
          test_fail("RX buffer descriptor status is not correct");
12434
          fail = fail + 1;
12435
        end
12436
      end
12437
      else // interrupt not enabled
12438
      begin
12439
        if ( ((data[15:0] !== 16'h2000) && (i_length[0] == 1'b0)) ||
12440
             ((data[15:0] !== 16'h2000) && (i_length[0] == 1'b1)) )
12441
        begin
12442
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
12443
          test_fail("RX buffer descriptor status is not correct");
12444
          fail = fail + 1;
12445
        end
12446
      end
12447
      // clear RX buffer descriptor for first 4 frames
12448
      if (i_length < min_tmp)
12449
        clear_rx_bd(127, 127);
12450
      // check interrupts
12451 274 tadejm
      wait (wbm_working == 0);
12452 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12453
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
12454
      begin
12455
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
12456
        begin
12457
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
12458
          test_fail("Interrupt Receive Buffer was not set");
12459
          fail = fail + 1;
12460
        end
12461
        if ((data & (~`ETH_INT_RXB)) !== 0)
12462
        begin
12463
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
12464
          test_fail("Other interrupts (except Receive Buffer) were set");
12465
          fail = fail + 1;
12466
        end
12467
      end
12468
      else
12469
      begin
12470
        if (data !== 0)
12471
        begin
12472
          `TIME; $display("*E Any of interrupts (except Receive Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
12473
          test_fail("Any of interrupts (except Receive Buffer) was set");
12474
          fail = fail + 1;
12475
        end
12476
      end
12477
      // clear interrupts
12478 274 tadejm
      wait (wbm_working == 0);
12479 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12480
      // check WB INT signal
12481
      if (wb_int !== 1'b0)
12482
      begin
12483
        test_fail("WB INT signal should not be set");
12484
        fail = fail + 1;
12485
      end
12486
      // INTERMEDIATE DISPLAYS
12487
      if ((i_length + 4) == (min_tmp + 64))
12488
      begin
12489
        // starting length is min_tmp, ending length is (min_tmp + 64)
12490
        $display("    receive small packets is NOT selected");
12491
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
12492
                 min_tmp, (min_tmp + 64));
12493
        // set receive small, remain the rest
12494 274 tadejm
        wait (wbm_working == 0);
12495 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
12496
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12497
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12498
      end
12499
      else if ((i_length + 4) == (max_tmp - 16))
12500
      begin
12501
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
12502
        $display("    receive small packets is selected");
12503
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
12504
                 (min_tmp + 64 + 128), tmp_data);
12505
        // reset receive small, remain the rest
12506 274 tadejm
        wait (wbm_working == 0);
12507 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
12508
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12509
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12510
      end
12511
      else if ((i_length + 4) == max_tmp)
12512
      begin
12513
        $display("    receive small packets is NOT selected");
12514
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
12515
                 (max_tmp - (4 + 16)), max_tmp);
12516
      end
12517
      // set length (loop variable)
12518
      if ((i_length + 4) < (min_tmp + 64))
12519
        i_length = i_length + 1;
12520
      else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
12521
      begin
12522
        i_length = i_length + 128;
12523
        tmp_data = i_length + 4; // last tmp_data is ending length
12524
      end
12525
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
12526
        i_length = max_tmp - (4 + 16);
12527
      else if ((i_length + 4) >= (max_tmp - 16))
12528
        i_length = i_length + 1;
12529
      else
12530
      begin
12531
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
12532
        #10 $stop;
12533
      end
12534
    end
12535
    // disable RX
12536 274 tadejm
    wait (wbm_working == 0);
12537 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
12538
              `ETH_MODER_PRO | `ETH_MODER_BRO,
12539
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12540
    if(fail == 0)
12541
      test_ok;
12542
    else
12543
      fail = 0;
12544
  end
12545
 
12546
 
12547
  ////////////////////////////////////////////////////////////////////
12548
  ////                                                            ////
12549
  ////  Test receive packets form MINFL to MAXFL sizes at         ////
12550
  ////  maximum RX buffer decriptors ( 10Mbps ).                  ////
12551
  ////                                                            ////
12552
  ////////////////////////////////////////////////////////////////////
12553 243 tadejm
  if (test_num == 6) // 
12554 209 tadejm
  begin
12555 243 tadejm
    // TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )
12556
    test_name = "TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )";
12557
    `TIME; $display("  TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )");
12558 209 tadejm
 
12559
    // reset MAC registers
12560
    hard_reset;
12561
    // reset MAC and MII LOGIC with soft reset
12562 274 tadejm
//    reset_mac;
12563
//    reset_mii;
12564 209 tadejm
    // set wb slave response
12565
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
12566
 
12567
    max_tmp = 0;
12568
    min_tmp = 0;
12569
    num_of_frames = 0;
12570
    num_of_bd = 0;
12571
    // set maximum RX buffer descriptors (128) - must be set before RX enable
12572 274 tadejm
    wait (wbm_working == 0);
12573 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12574
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
12575 274 tadejm
    wait (wbm_working == 0);
12576 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
12577
              `ETH_MODER_PRO | `ETH_MODER_BRO,
12578
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12579
    // prepare two packets of MAXFL length
12580 274 tadejm
    wait (wbm_working == 0);
12581 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12582
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
12583
    min_tmp = tmp[31:16];
12584
    st_data = 8'hAC;
12585
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
12586
    st_data = 8'h35;
12587
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
12588
    // check WB INT signal
12589
    if (wb_int !== 1'b0)
12590
    begin
12591
      test_fail("WB INT signal should not be set");
12592
      fail = fail + 1;
12593
    end
12594
 
12595
    // write to phy's control register for 10Mbps
12596
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
12597
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
12598
    speed = 10;
12599
 
12600
    i_length = (min_tmp - 4);
12601
    while (i_length <= (max_tmp - 4))
12602
    begin
12603
      // append CRC to packet
12604
      if (i_length[0] == 1'b0)
12605
        append_rx_crc (0, i_length, 1'b0, 1'b0);
12606
      else
12607
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
12608
      // choose generating carrier sense and collision
12609
      case (i_length[1:0])
12610
      2'h0: // Interrupt is generated
12611
      begin
12612
        // Reset_tx_bd nable interrupt generation
12613
        // unmask interrupts
12614 274 tadejm
        wait (wbm_working == 0);
12615 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
12616
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12617
        // not detect carrier sense in FD and no collision
12618
        eth_phy.no_carrier_sense_rx_fd_detect(0);
12619
        eth_phy.collision(0);
12620
      end
12621
      2'h1: // Interrupt is not generated
12622
      begin
12623
        // set_tx_bd enable interrupt generation
12624
        // mask interrupts
12625 274 tadejm
        wait (wbm_working == 0);
12626 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12627
        // detect carrier sense in FD and no collision
12628
        eth_phy.no_carrier_sense_rx_fd_detect(1);
12629
        eth_phy.collision(0);
12630
      end
12631
      2'h2: // Interrupt is not generated
12632
      begin
12633
        // set_tx_bd disable the interrupt generation
12634
        // unmask interrupts
12635 274 tadejm
        wait (wbm_working == 0);
12636 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
12637
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12638
        // not detect carrier sense in FD and set collision
12639
        eth_phy.no_carrier_sense_rx_fd_detect(0);
12640
        eth_phy.collision(1);
12641
      end
12642
      default: // 2'h3: // Interrupt is not generated
12643
      begin
12644
        // set_tx_bd disable the interrupt generation
12645
        // mask interrupts
12646 274 tadejm
        wait (wbm_working == 0);
12647 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12648
        // detect carrier sense in FD and set collision
12649
        eth_phy.no_carrier_sense_rx_fd_detect(1);
12650
        eth_phy.collision(1);
12651
      end
12652
      endcase
12653
      // first 8 frames are received with RX BD 0 (wrap bit on RX BD 0)
12654
      // number of all frames is 154 (146 without first 8)
12655
      if (num_of_frames < 8)
12656
      begin
12657
        case (i_length[1:0])
12658
        2'h0: // Interrupt is generated
12659
        begin
12660
          // enable interrupt generation
12661
          set_rx_bd(0, 0, 1'b1, (`MEMORY_BASE + i_length[1:0]));
12662
          // interrupts are unmasked
12663
        end
12664
        2'h1: // Interrupt is not generated
12665
        begin
12666
          // enable interrupt generation
12667
          set_rx_bd(0, 0, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
12668
          // interrupts are masked
12669
        end
12670
        2'h2: // Interrupt is not generated
12671
        begin
12672
          // disable interrupt generation
12673
          set_rx_bd(0, 0, 1'b0, (`MEMORY_BASE + i_length[1:0]));
12674
          // interrupts are unmasked
12675
        end
12676
        default: // 2'h3: // Interrupt is not generated
12677
        begin
12678
          // disable interrupt generation
12679
          set_rx_bd(0, 0, 1'b0, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
12680
          // interrupts are masked
12681
        end
12682
        endcase
12683
        // set wrap bit
12684
        set_rx_bd_wrap(0);
12685
      end
12686
      // after first 8 number of frames, 128 frames form RX BD 0 to 127 will be received
12687
      else if ((num_of_frames - 8) == 0)
12688
      begin
12689
        tmp_len = i_length; // length of frame
12690
        tmp_bd_num = 0; // RX BD number
12691
        while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
12692
        begin
12693
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
12694
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
12695
          if (tmp_len[0] == 0)
12696
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], (`MEMORY_BASE + tmp_len[1:0]));
12697
          else
12698
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
12699
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
12700
          if ((tmp_len + 4) < (min_tmp + 128))
12701
            tmp_len = tmp_len + 1;
12702
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
12703
            tmp_len = 256;
12704
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
12705
            tmp_len = tmp_len + 128;
12706
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
12707
            tmp_len = max_tmp - (4 + 16);
12708
          else if ((tmp_len + 4) >= (max_tmp - 16))
12709
            tmp_len = tmp_len + 1;
12710
          // set RX BD number
12711
          tmp_bd_num = tmp_bd_num + 1;
12712
        end
12713
        // set wrap bit
12714
        set_rx_bd_wrap(127);
12715
      end
12716
      // after 128 + first 8 number of frames, 19 frames form RX BD 0 to 18 will be received
12717
      else if ((num_of_frames - 8) == 20) // 128
12718
      begin
12719
        tmp_len = tmp_len; // length of frame remaines from previous settings
12720
        tmp_bd_num = 0; // TX BD number
12721
        while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
12722
        begin
12723
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
12724
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
12725
          if (tmp_len[0] == 0)
12726
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], (`MEMORY_BASE + tmp_len[1:0]));
12727
          else
12728
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
12729
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
12730
          if ((tmp_len + 4) < (min_tmp + 128))
12731
            tmp_len = tmp_len + 1;
12732
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
12733
            tmp_len = 256;
12734
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
12735
            tmp_len = tmp_len + 128;
12736
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
12737
            tmp_len = max_tmp - (4 + 16);
12738
          else if ((tmp_len + 4) >= (max_tmp - 16))
12739
            tmp_len = tmp_len + 1;
12740
          // set TX BD number
12741
          tmp_bd_num = tmp_bd_num + 1;
12742
        end
12743
      end
12744
      // set empty bit
12745
      if (num_of_frames < 8)
12746
        set_rx_bd_empty(0, 0);
12747
      else if ((num_of_frames - 8) < 128)
12748
        set_rx_bd_empty((num_of_frames - 8), (num_of_frames - 8));
12749
      else if ((num_of_frames - 136) < 19)
12750
        set_rx_bd_empty((num_of_frames - 136), (num_of_frames - 136));
12751
      // CHECK END OF RECEIVE
12752
      fork
12753
        begin
12754
          if (i_length[0] == 1'b0)
12755
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
12756
          else
12757
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
12758
          repeat(10) @(posedge mrx_clk);
12759
        end
12760
        begin
12761
          #1 check_rx_bd(num_of_bd, data);
12762
          if (i_length < min_tmp) // just first four
12763
          begin
12764
            while (data[15] === 1)
12765
            begin
12766
              #1 check_rx_bd(num_of_bd, data);
12767
              @(posedge wb_clk);
12768
            end
12769
            repeat (1) @(posedge wb_clk);
12770
          end
12771
          else
12772
          begin
12773
            wait (MRxDV === 1'b1); // start transmit
12774
            #1 check_rx_bd(num_of_bd, data);
12775
            if (data[15] !== 1)
12776
            begin
12777
              test_fail("Wrong buffer descriptor's ready bit read out from MAC");
12778
              fail = fail + 1;
12779
            end
12780
            wait (MRxDV === 1'b0); // end transmit
12781
            while (data[15] === 1)
12782
            begin
12783
              #1 check_rx_bd(num_of_bd, data);
12784
              @(posedge wb_clk);
12785
            end
12786
            repeat (1) @(posedge wb_clk);
12787
          end
12788
        end
12789
      join
12790
      // check length of a PACKET
12791
      if (data[31:16] != (i_length + 4))
12792
      begin
12793
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
12794
                        data[31:16], (i_length + 4));
12795
        test_fail("Wrong length of the packet out from PHY");
12796
        fail = fail + 1;
12797
      end
12798
      // checking in the following if statement is performed only for first and last 64 lengths
12799
      // check received RX packet data and CRC
12800
      if (i_length[0] == 1'b0)
12801
      begin
12802
        check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
12803
      end
12804
      else
12805
      begin
12806
        check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
12807
      end
12808
      if (tmp > 0)
12809
      begin
12810
        `TIME; $display("*E Wrong data of the received packet");
12811
        test_fail("Wrong data of the received packet");
12812
        fail = fail + 1;
12813
      end
12814
      // check WB INT signal
12815
      if (i_length[1:0] == 2'h0)
12816
      begin
12817
        if (wb_int !== 1'b1)
12818
        begin
12819
          `TIME; $display("*E WB INT signal should be set");
12820
          test_fail("WB INT signal should be set");
12821
          fail = fail + 1;
12822
        end
12823
      end
12824
      else
12825
      begin
12826
        if (wb_int !== 1'b0)
12827
        begin
12828
          `TIME; $display("*E WB INT signal should not be set");
12829
          test_fail("WB INT signal should not be set");
12830
          fail = fail + 1;
12831
        end
12832
      end
12833
      // check RX buffer descriptor of a packet
12834
      check_rx_bd(num_of_bd, data);
12835
      if (i_length[1] == 1'b0) // interrupt enabled
12836
      begin
12837
        if ( ((data[15:0] !== 16'h6000) && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
12838
             ((data[15:0] !== 16'h4000) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
12839
        begin
12840
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
12841
          test_fail("RX buffer descriptor status is not correct");
12842
          fail = fail + 1;
12843
        end
12844
      end
12845
      else // interrupt not enabled
12846
      begin
12847
        if ( ((data[15:0] !== 16'h2000)  && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
12848
             ((data[15:0] !== 16'h0000) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
12849
        begin
12850
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
12851
          test_fail("RX buffer descriptor status is not correct");
12852
          fail = fail + 1;
12853
        end
12854
      end
12855
      // clear first half of 8 frames from RX buffer descriptor 0
12856
      if (num_of_frames < 4)
12857
        clear_rx_bd(num_of_bd, num_of_bd);
12858
      // clear BD with wrap bit
12859
      if (num_of_frames == 140)
12860
        clear_rx_bd(127, 127);
12861
      // check interrupts
12862 274 tadejm
      wait (wbm_working == 0);
12863 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12864
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
12865
      begin
12866
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
12867
        begin
12868
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
12869
          test_fail("Interrupt Receive Buffer was not set");
12870
          fail = fail + 1;
12871
        end
12872
        if ((data & (~`ETH_INT_RXB)) !== 0)
12873
        begin
12874
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
12875
          test_fail("Other interrupts (except Receive Buffer) were set");
12876
          fail = fail + 1;
12877
        end
12878
      end
12879
      else
12880
      begin
12881
        if (data !== 0)
12882
        begin
12883
          `TIME; $display("*E Any of interrupts (except Receive Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
12884
          test_fail("Any of interrupts (except Receive Buffer) was set");
12885
          fail = fail + 1;
12886
        end
12887
      end
12888
      // clear interrupts
12889 274 tadejm
      wait (wbm_working == 0);
12890 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12891
      // check WB INT signal
12892
      if (wb_int !== 1'b0)
12893
      begin
12894
        test_fail("WB INT signal should not be set");
12895
        fail = fail + 1;
12896
      end
12897
      // INTERMEDIATE DISPLAYS
12898
      if ((i_length + 4) == (min_tmp + 7))
12899
      begin
12900
        // starting length is min_tmp, ending length is (min_tmp + 128)
12901
        $display("    receive small packets is NOT selected");
12902
        $display("    using only RX BD 0 out of 128 BDs assigned to RX (wrap at first BD - RX BD 0)");
12903
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
12904
                 min_tmp, (min_tmp + 7));
12905
        $display("    ->all packets were received on RX BD 0");
12906
        // reset receive small, remain the rest
12907 274 tadejm
        wait (wbm_working == 0);
12908 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
12909
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12910
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12911
      end
12912
      else if ((i_length + 4) == (min_tmp + 128))
12913
      begin
12914
        // starting length is min_tmp, ending length is (min_tmp + 128)
12915
        $display("    receive small packets is NOT selected");
12916
        $display("    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
12917
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
12918
                 (min_tmp + 8), (min_tmp + 128));
12919
        $display("    ->packets were received on RX BD %0d to RX BD %0d respectively",
12920
                 1'b0, num_of_bd);
12921
        tmp_bd = num_of_bd + 1;
12922
        // set receive small, remain the rest
12923 274 tadejm
        wait (wbm_working == 0);
12924 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
12925
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12926
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12927
      end
12928
      else if ((i_length + 4) == (max_tmp - 16))
12929
      begin
12930
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
12931
        $display("    receive small packets is selected");
12932
        $display("    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
12933
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
12934
                 (min_tmp + 64 + 128), tmp_data);
12935
        if (tmp_bd > num_of_bd)
12936
          $display("    ->packets were received from RX BD %0d to RX BD 127 and from RX BD 0 to RX BD %0d respectively",
12937
                   tmp_bd, num_of_bd);
12938
        else
12939
          $display("    ->packets were received from RX BD %0d to RX BD %0d respectively",
12940
                   tmp_bd, num_of_bd);
12941
        tmp_bd = num_of_bd + 1;
12942
        // reset receive small, remain the rest
12943 274 tadejm
        wait (wbm_working == 0);
12944 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
12945
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12946
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12947
      end
12948
      else if ((i_length + 4) == max_tmp)
12949
      begin
12950
        $display("    receive small packets is NOT selected");
12951
        $display("    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
12952
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
12953
                 (max_tmp - (4 + 16)), max_tmp);
12954
        if (tmp_bd > num_of_bd)
12955
          $display("    ->packets were received from RX BD %0d to RX BD 127 and from RX BD 0 to RX BD %0d respectively",
12956
                   tmp_bd, num_of_bd);
12957
        else
12958
          $display("    ->packets were received from RX BD %0d to RX BD %0d respectively",
12959
                   tmp_bd, num_of_bd);
12960
      end
12961
      // set length (loop variable)
12962
      if ((i_length + 4) < (min_tmp + 128))
12963
        i_length = i_length + 1;
12964
      else if ( ((i_length + 4) == (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
12965
        i_length = 256;
12966
      else if ( ((i_length + 4) > (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
12967
      begin
12968
        i_length = i_length + 128;
12969
        tmp_data = i_length + 4; // last tmp_data is ending length
12970
      end
12971
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
12972
        i_length = max_tmp - (4 + 16);
12973
      else if ((i_length + 4) >= (max_tmp - 16))
12974
        i_length = i_length + 1;
12975
      else
12976
      begin
12977
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
12978
        #10 $stop;
12979
      end
12980
      // the number of frame transmitted
12981
      num_of_frames = num_of_frames + 1;
12982
      if ((num_of_frames <= 8) || ((num_of_frames - 8) == 128))
12983
        num_of_bd = 0;
12984
      else
12985
        num_of_bd = num_of_bd + 1;
12986
    end
12987
    // disable RX
12988 274 tadejm
    wait (wbm_working == 0);
12989 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
12990
              `ETH_MODER_PRO | `ETH_MODER_BRO,
12991
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12992
    @(posedge wb_clk);
12993
    if(fail == 0)
12994
      test_ok;
12995
    else
12996
      fail = 0;
12997
  end
12998
 
12999
 
13000
  ////////////////////////////////////////////////////////////////////
13001
  ////                                                            ////
13002
  ////  Test receive packets form MINFL to MAXFL sizes at         ////
13003
  ////  maximum RX buffer decriptors ( 100Mbps ).                 ////
13004
  ////                                                            ////
13005
  ////////////////////////////////////////////////////////////////////
13006 243 tadejm
  if (test_num == 7) // 
13007 209 tadejm
  begin
13008 243 tadejm
    // TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )
13009
    test_name = "TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )";
13010
    `TIME; $display("  TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )");
13011 209 tadejm
 
13012
    // reset MAC registers
13013
    hard_reset;
13014
    // reset MAC and MII LOGIC with soft reset
13015 274 tadejm
//    reset_mac;
13016
//    reset_mii;
13017 209 tadejm
    // set wb slave response
13018
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
13019
 
13020
    max_tmp = 0;
13021
    min_tmp = 0;
13022
    num_of_frames = 0;
13023
    num_of_bd = 0;
13024
    // set maximum RX buffer descriptors (128) - must be set before RX enable
13025 274 tadejm
    wait (wbm_working == 0);
13026 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13027
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
13028 274 tadejm
    wait (wbm_working == 0);
13029 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
13030
              `ETH_MODER_PRO | `ETH_MODER_BRO,
13031
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13032
    // prepare two packets of MAXFL length
13033 274 tadejm
    wait (wbm_working == 0);
13034 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13035
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
13036
    min_tmp = tmp[31:16];
13037
    st_data = 8'hAC;
13038
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
13039
    st_data = 8'h35;
13040
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
13041
    // check WB INT signal
13042
    if (wb_int !== 1'b0)
13043
    begin
13044
      test_fail("WB INT signal should not be set");
13045
      fail = fail + 1;
13046
    end
13047
 
13048
    // write to phy's control register for 100Mbps
13049
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
13050
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
13051
    speed = 100;
13052
 
13053
    i_length = (min_tmp - 4);
13054
    while (i_length <= (max_tmp - 4))
13055
    begin
13056
      // append CRC to packet
13057
      if (i_length[0] == 1'b0)
13058
        append_rx_crc (0, i_length, 1'b0, 1'b0);
13059
      else
13060
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
13061
      // choose generating carrier sense and collision
13062
      case (i_length[1:0])
13063
      2'h0: // Interrupt is generated
13064
      begin
13065
        // Reset_tx_bd nable interrupt generation
13066
        // unmask interrupts
13067 274 tadejm
        wait (wbm_working == 0);
13068 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
13069
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13070
        // not detect carrier sense in FD and no collision
13071
        eth_phy.no_carrier_sense_rx_fd_detect(0);
13072
        eth_phy.collision(0);
13073
      end
13074
      2'h1: // Interrupt is not generated
13075
      begin
13076
        // set_tx_bd enable interrupt generation
13077
        // mask interrupts
13078 274 tadejm
        wait (wbm_working == 0);
13079 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13080
        // detect carrier sense in FD and no collision
13081
        eth_phy.no_carrier_sense_rx_fd_detect(1);
13082
        eth_phy.collision(0);
13083
      end
13084
      2'h2: // Interrupt is not generated
13085
      begin
13086
        // set_tx_bd disable the interrupt generation
13087
        // unmask interrupts
13088 274 tadejm
        wait (wbm_working == 0);
13089 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
13090
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13091
        // not detect carrier sense in FD and set collision
13092
        eth_phy.no_carrier_sense_rx_fd_detect(0);
13093
        eth_phy.collision(1);
13094
      end
13095
      default: // 2'h3: // Interrupt is not generated
13096
      begin
13097
        // set_tx_bd disable the interrupt generation
13098
        // mask interrupts
13099 274 tadejm
        wait (wbm_working == 0);
13100 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13101
        // detect carrier sense in FD and set collision
13102
        eth_phy.no_carrier_sense_rx_fd_detect(1);
13103
        eth_phy.collision(1);
13104
      end
13105
      endcase
13106
      // first 8 frames are received with RX BD 0 (wrap bit on RX BD 0)
13107
      // number of all frames is 154 (146 without first 8)
13108
      if (num_of_frames < 8)
13109
      begin
13110
        case (i_length[1:0])
13111
        2'h0: // Interrupt is generated
13112
        begin
13113
          // enable interrupt generation
13114
          set_rx_bd(0, 0, 1'b1, (`MEMORY_BASE + i_length[1:0]));
13115
          // interrupts are unmasked
13116
        end
13117
        2'h1: // Interrupt is not generated
13118
        begin
13119
          // enable interrupt generation
13120
          set_rx_bd(0, 0, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
13121
          // interrupts are masked
13122
        end
13123
        2'h2: // Interrupt is not generated
13124
        begin
13125
          // disable interrupt generation
13126
          set_rx_bd(0, 0, 1'b0, (`MEMORY_BASE + i_length[1:0]));
13127
          // interrupts are unmasked
13128
        end
13129
        default: // 2'h3: // Interrupt is not generated
13130
        begin
13131
          // disable interrupt generation
13132
          set_rx_bd(0, 0, 1'b0, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
13133
          // interrupts are masked
13134
        end
13135
        endcase
13136
        // set wrap bit
13137
        set_rx_bd_wrap(0);
13138
      end
13139
      // after first 8 number of frames, 128 frames form RX BD 0 to 127 will be received
13140
      else if ((num_of_frames - 8) == 0)
13141
      begin
13142
        tmp_len = i_length; // length of frame
13143
        tmp_bd_num = 0; // RX BD number
13144
        while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
13145
        begin
13146
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
13147
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13148
          if (tmp_len[0] == 0)
13149
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], (`MEMORY_BASE + tmp_len[1:0]));
13150
          else
13151
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13152
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13153
          if ((tmp_len + 4) < (min_tmp + 128))
13154
            tmp_len = tmp_len + 1;
13155
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
13156
            tmp_len = 256;
13157
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
13158
            tmp_len = tmp_len + 128;
13159
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
13160
            tmp_len = max_tmp - (4 + 16);
13161
          else if ((tmp_len + 4) >= (max_tmp - 16))
13162
            tmp_len = tmp_len + 1;
13163
          // set RX BD number
13164
          tmp_bd_num = tmp_bd_num + 1;
13165
        end
13166
        // set wrap bit
13167
        set_rx_bd_wrap(127);
13168
      end
13169
      // after 128 + first 8 number of frames, 19 frames form RX BD 0 to 18 will be received
13170
      else if ((num_of_frames - 8) == 20) // 128
13171
      begin
13172
        tmp_len = tmp_len; // length of frame remaines from previous settings
13173
        tmp_bd_num = 0; // TX BD number
13174
        while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
13175
        begin
13176
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
13177
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13178
          if (tmp_len[0] == 0)
13179
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], (`MEMORY_BASE + tmp_len[1:0]));
13180
          else
13181
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13182
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13183
          if ((tmp_len + 4) < (min_tmp + 128))
13184
            tmp_len = tmp_len + 1;
13185
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
13186
            tmp_len = 256;
13187
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
13188
            tmp_len = tmp_len + 128;
13189
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
13190
            tmp_len = max_tmp - (4 + 16);
13191
          else if ((tmp_len + 4) >= (max_tmp - 16))
13192
            tmp_len = tmp_len + 1;
13193
          // set TX BD number
13194
          tmp_bd_num = tmp_bd_num + 1;
13195
        end
13196
      end
13197
      // set empty bit
13198
      if (num_of_frames < 8)
13199
        set_rx_bd_empty(0, 0);
13200
      else if ((num_of_frames - 8) < 128)
13201
        set_rx_bd_empty((num_of_frames - 8), (num_of_frames - 8));
13202
      else if ((num_of_frames - 136) < 19)
13203
        set_rx_bd_empty((num_of_frames - 136), (num_of_frames - 136));
13204
      // CHECK END OF RECEIVE
13205
      fork
13206
        begin
13207
          if (i_length[0] == 1'b0)
13208
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
13209
          else
13210
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
13211
          repeat(10) @(posedge mrx_clk);
13212
        end
13213
        begin
13214
          #1 check_rx_bd(num_of_bd, data);
13215
          if (i_length < min_tmp) // just first four
13216
          begin
13217
            while (data[15] === 1)
13218
            begin
13219
              #1 check_rx_bd(num_of_bd, data);
13220
              @(posedge wb_clk);
13221
            end
13222
            repeat (1) @(posedge wb_clk);
13223
          end
13224
          else
13225
          begin
13226
            wait (MRxDV === 1'b1); // start transmit
13227
            #1 check_rx_bd(num_of_bd, data);
13228
            if (data[15] !== 1)
13229
            begin
13230
              test_fail("Wrong buffer descriptor's ready bit read out from MAC");
13231
              fail = fail + 1;
13232
            end
13233
            wait (MRxDV === 1'b0); // end transmit
13234
            while (data[15] === 1)
13235
            begin
13236
              #1 check_rx_bd(num_of_bd, data);
13237
              @(posedge wb_clk);
13238
            end
13239
            repeat (1) @(posedge wb_clk);
13240
          end
13241
        end
13242
      join
13243
      // check length of a PACKET
13244
      if (data[31:16] != (i_length + 4))
13245
      begin
13246
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
13247
                        data[31:16], (i_length + 4));
13248
        test_fail("Wrong length of the packet out from PHY");
13249
        fail = fail + 1;
13250
      end
13251
      // check received RX packet data and CRC
13252
      if (i_length[0] == 1'b0)
13253
      begin
13254
        check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
13255
      end
13256
      else
13257
      begin
13258
        check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
13259
      end
13260
      if (tmp > 0)
13261
      begin
13262
        `TIME; $display("*E Wrong data of the received packet");
13263
        test_fail("Wrong data of the received packet");
13264
        fail = fail + 1;
13265
      end
13266
      // check WB INT signal
13267
      if (i_length[1:0] == 2'h0)
13268
      begin
13269
        if (wb_int !== 1'b1)
13270
        begin
13271
          `TIME; $display("*E WB INT signal should be set");
13272
          test_fail("WB INT signal should be set");
13273
          fail = fail + 1;
13274
        end
13275
      end
13276
      else
13277
      begin
13278
        if (wb_int !== 1'b0)
13279
        begin
13280
          `TIME; $display("*E WB INT signal should not be set");
13281
          test_fail("WB INT signal should not be set");
13282
          fail = fail + 1;
13283
        end
13284
      end
13285
      // check RX buffer descriptor of a packet
13286
      check_rx_bd(num_of_bd, data);
13287
      if (i_length[1] == 1'b0) // interrupt enabled
13288
      begin
13289
        if ( ((data[15:0] !== 16'h6000) && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
13290
             ((data[15:0] !== 16'h4000) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
13291
        begin
13292
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
13293
          test_fail("RX buffer descriptor status is not correct");
13294
          fail = fail + 1;
13295
        end
13296
      end
13297
      else // interrupt not enabled
13298
      begin
13299
        if ( ((data[15:0] !== 16'h2000)  && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
13300
             ((data[15:0] !== 16'h0000) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
13301
        begin
13302
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
13303
          test_fail("RX buffer descriptor status is not correct");
13304
          fail = fail + 1;
13305
        end
13306
      end
13307
      // clear first half of 8 frames from RX buffer descriptor 0
13308
      if (num_of_frames < 4)
13309
        clear_rx_bd(num_of_bd, num_of_bd);
13310
      // clear BD with wrap bit
13311
      if (num_of_frames == 140)
13312
        clear_rx_bd(127, 127);
13313
      // check interrupts
13314 274 tadejm
      wait (wbm_working == 0);
13315 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13316
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
13317
      begin
13318
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
13319
        begin
13320
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
13321
          test_fail("Interrupt Receive Buffer was not set");
13322
          fail = fail + 1;
13323
        end
13324
        if ((data & (~`ETH_INT_RXB)) !== 0)
13325
        begin
13326
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
13327
          test_fail("Other interrupts (except Receive Buffer) were set");
13328
          fail = fail + 1;
13329
        end
13330
      end
13331
      else
13332
      begin
13333
        if (data !== 0)
13334
        begin
13335
          `TIME; $display("*E Any of interrupts (except Receive Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
13336
          test_fail("Any of interrupts (except Receive Buffer) was set");
13337
          fail = fail + 1;
13338
        end
13339
      end
13340
      // clear interrupts
13341 274 tadejm
      wait (wbm_working == 0);
13342 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13343
      // check WB INT signal
13344
      if (wb_int !== 1'b0)
13345
      begin
13346
        test_fail("WB INT signal should not be set");
13347
        fail = fail + 1;
13348
      end
13349
      // INTERMEDIATE DISPLAYS
13350
      if ((i_length + 4) == (min_tmp + 7))
13351
      begin
13352
        // starting length is min_tmp, ending length is (min_tmp + 128)
13353
        $display("    receive small packets is NOT selected");
13354
        $display("    using only RX BD 0 out of 128 BDs assigned to RX (wrap at first BD - RX BD 0)");
13355
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
13356
                 min_tmp, (min_tmp + 7));
13357
        $display("    ->all packets were received on RX BD 0");
13358
        // reset receive small, remain the rest
13359 274 tadejm
        wait (wbm_working == 0);
13360 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
13361
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
13362
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13363
      end
13364
      else if ((i_length + 4) == (min_tmp + 128))
13365
      begin
13366
        // starting length is min_tmp, ending length is (min_tmp + 128)
13367
        $display("    receive small packets is NOT selected");
13368
        $display("    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
13369
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13370
                 (min_tmp + 8), (min_tmp + 128));
13371
        $display("    ->packets were received on RX BD %0d to RX BD %0d respectively",
13372
                 1'b0, num_of_bd);
13373
        tmp_bd = num_of_bd + 1;
13374
        // set receive small, remain the rest
13375 274 tadejm
        wait (wbm_working == 0);
13376 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
13377
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
13378
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13379
      end
13380
      else if ((i_length + 4) == (max_tmp - 16))
13381
      begin
13382
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
13383
        $display("    receive small packets is selected");
13384
        $display("    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
13385
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
13386
                 (min_tmp + 64 + 128), tmp_data);
13387
        if (tmp_bd > num_of_bd)
13388
          $display("    ->packets were received from RX BD %0d to RX BD 127 and from RX BD 0 to RX BD %0d respectively",
13389
                   tmp_bd, num_of_bd);
13390
        else
13391
          $display("    ->packets were received from RX BD %0d to RX BD %0d respectively",
13392
                   tmp_bd, num_of_bd);
13393
        tmp_bd = num_of_bd + 1;
13394
        // reset receive small, remain the rest
13395 274 tadejm
        wait (wbm_working == 0);
13396 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
13397
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
13398
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13399
      end
13400
      else if ((i_length + 4) == max_tmp)
13401
      begin
13402
        $display("    receive small packets is NOT selected");
13403
        $display("    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
13404
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
13405
                 (max_tmp - (4 + 16)), max_tmp);
13406
        if (tmp_bd > num_of_bd)
13407
          $display("    ->packets were received from RX BD %0d to RX BD 127 and from RX BD 0 to RX BD %0d respectively",
13408
                   tmp_bd, num_of_bd);
13409
        else
13410
          $display("    ->packets were received from RX BD %0d to RX BD %0d respectively",
13411
                   tmp_bd, num_of_bd);
13412
      end
13413
      // set length (loop variable)
13414
      if ((i_length + 4) < (min_tmp + 128))
13415
        i_length = i_length + 1;
13416
      else if ( ((i_length + 4) == (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
13417
        i_length = 256;
13418
      else if ( ((i_length + 4) > (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
13419
      begin
13420
        i_length = i_length + 128;
13421
        tmp_data = i_length + 4; // last tmp_data is ending length
13422
      end
13423
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
13424
        i_length = max_tmp - (4 + 16);
13425
      else if ((i_length + 4) >= (max_tmp - 16))
13426
        i_length = i_length + 1;
13427
      else
13428
      begin
13429
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
13430
        #10 $stop;
13431
      end
13432
      // the number of frame transmitted
13433
      num_of_frames = num_of_frames + 1;
13434
      if ((num_of_frames <= 8) || ((num_of_frames - 8) == 128))
13435
        num_of_bd = 0;
13436
      else
13437
        num_of_bd = num_of_bd + 1;
13438
    end
13439
    // disable RX
13440 274 tadejm
    wait (wbm_working == 0);
13441 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
13442
              `ETH_MODER_PRO | `ETH_MODER_BRO,
13443
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13444
    @(posedge wb_clk);
13445
    if(fail == 0)
13446
      test_ok;
13447
    else
13448
      fail = 0;
13449
  end
13450
 
13451
 
13452
  ////////////////////////////////////////////////////////////////////
13453
  ////                                                            ////
13454 243 tadejm
  ////  Test receive packets form 0 to (MINFL + 12) sizes at       ////
13455 209 tadejm
  ////  8 RX buffer decriptors ( 10Mbps ).                        ////
13456
  ////                                                            ////
13457
  ////////////////////////////////////////////////////////////////////
13458 243 tadejm
  if (test_num == 8) // 
13459 209 tadejm
  begin
13460 243 tadejm
    // TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 10Mbps )
13461
    test_name = "TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 10Mbps )";
13462
    `TIME; $display("  TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 10Mbps )");
13463 209 tadejm
 
13464
    // reset MAC registers
13465
    hard_reset;
13466
    // reset MAC and MII LOGIC with soft reset
13467 274 tadejm
//    reset_mac;
13468
//    reset_mii;
13469 209 tadejm
    // set wb slave response
13470
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
13471
 
13472
    max_tmp = 0;
13473
    min_tmp = 0;
13474
    // set 8 RX buffer descriptors (120 - 127) - must be set before RX enable
13475 274 tadejm
    wait (wbm_working == 0);
13476 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h78, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13477
    // enable RX, set full-duplex mode, receive small, NO correct IFG
13478 274 tadejm
    wait (wbm_working == 0);
13479 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
13480
              `ETH_MODER_PRO | `ETH_MODER_BRO,
13481
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13482
    // prepare two packets of MAXFL length
13483 274 tadejm
    wait (wbm_working == 0);
13484 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13485
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
13486
    min_tmp = tmp[31:16];
13487
    st_data = 8'hAC;
13488
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
13489
    st_data = 8'h35;
13490
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
13491
    // check WB INT signal
13492
    if (wb_int !== 1'b0)
13493
    begin
13494
      test_fail("WB INT signal should not be set");
13495
      fail = fail + 1;
13496
    end
13497 243 tadejm
    // unmask interrupts
13498 274 tadejm
    wait (wbm_working == 0);
13499 243 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
13500
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13501 209 tadejm
 
13502
    // write to phy's control register for 10Mbps
13503
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
13504
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
13505
    speed = 10;
13506
 
13507 243 tadejm
    frame_ended = 0;
13508
    num_of_frames = 0;// 0; // 10;
13509
    num_of_bd = 120;
13510
    i_length = 0 - 4;// (0 - 4); // 6; // 4 less due to CRC
13511
    while ((i_length + 4) < 78) // (min_tmp - 4))
13512 209 tadejm
    begin
13513 243 tadejm
      // append CRC to packet
13514
      if ((i_length[0] == 1'b0) && (num_of_frames > 4))
13515
        append_rx_crc (0, i_length, 1'b0, 1'b0);
13516
      else if (num_of_frames > 4)
13517
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
13518 209 tadejm
      // choose generating carrier sense and collision
13519
      case (i_length[1:0])
13520 243 tadejm
      2'h0:
13521 209 tadejm
      begin
13522
        // not detect carrier sense in FD and no collision
13523 243 tadejm
        eth_phy.no_carrier_sense_rx_fd_detect(0);
13524 209 tadejm
        eth_phy.collision(0);
13525
      end
13526 243 tadejm
      2'h1:
13527 209 tadejm
      begin
13528
        // detect carrier sense in FD and no collision
13529 243 tadejm
        eth_phy.no_carrier_sense_rx_fd_detect(1);
13530 209 tadejm
        eth_phy.collision(0);
13531
      end
13532 243 tadejm
      2'h2:
13533 209 tadejm
      begin
13534
        // not detect carrier sense in FD and set collision
13535 243 tadejm
        eth_phy.no_carrier_sense_rx_fd_detect(0);
13536 209 tadejm
        eth_phy.collision(1);
13537
      end
13538 243 tadejm
      default: // 2'h3:
13539 209 tadejm
      begin
13540
        // detect carrier sense in FD and set collision
13541 243 tadejm
        eth_phy.no_carrier_sense_rx_fd_detect(1);
13542 209 tadejm
        eth_phy.collision(1);
13543
      end
13544
      endcase
13545
      #1;
13546 243 tadejm
      // first 10 frames are received with RX BD 120 (wrap bit on RX BD 120)
13547 209 tadejm
      if (num_of_frames <= 9)
13548
      begin
13549 243 tadejm
        case (i_length[1:0])
13550
        2'h0: // Interrupt is generated
13551
        begin
13552
          // enable interrupt generation
13553
          set_rx_bd(120, 120, 1'b1, (`MEMORY_BASE + i_length[1:0]));
13554
        end
13555
        2'h1: // Interrupt is generated
13556
        begin
13557
          // enable interrupt generation
13558
          set_rx_bd(120, 120, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
13559
        end
13560
        2'h2: // Interrupt is generated
13561
        begin
13562
          // enable interrupt generation
13563
          set_rx_bd(120, 120, 1'b1, (`MEMORY_BASE + i_length[1:0]));
13564
        end
13565
        default: // 2'h3: // Interrupt is generated
13566
        begin
13567
          // enable interrupt generation
13568
          set_rx_bd(120, 120, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
13569
        end
13570
        endcase
13571 209 tadejm
        // set wrap bit
13572 243 tadejm
        set_rx_bd_wrap(120);
13573 209 tadejm
      end
13574 243 tadejm
      // 10 <= num_of_frames < 18 => wrap set to TX BD 123
13575 209 tadejm
      else if ((num_of_frames == 10) || (num_of_frames == 14))
13576
      begin
13577
        tmp_len = i_length; // length of frame
13578 243 tadejm
        tmp_bd_num = 120; // RX BD number
13579
        while (tmp_bd_num < 124) // 
13580 209 tadejm
        begin
13581
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13582
          if (tmp_len[0] == 0)
13583 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13584 209 tadejm
          else
13585 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13586
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13587 209 tadejm
          tmp_len = tmp_len + 1;
13588 243 tadejm
          // set RX BD number
13589 209 tadejm
          tmp_bd_num = tmp_bd_num + 1;
13590
        end
13591
        // set wrap bit
13592 243 tadejm
        set_rx_bd_wrap(123);
13593 209 tadejm
      end
13594 243 tadejm
      // 18 <= num_of_frames < 28 => wrap set to RX BD 124
13595 209 tadejm
      else if ((num_of_frames == 18) || (num_of_frames == 23))
13596
      begin
13597
        tmp_len = i_length; // length of frame
13598 243 tadejm
        tmp_bd_num = 120; // RX BD number
13599
        while (tmp_bd_num < 125) // 
13600 209 tadejm
        begin
13601
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13602
          if (tmp_len[0] == 0)
13603 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13604 209 tadejm
          else
13605 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13606
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13607 209 tadejm
          tmp_len = tmp_len + 1;
13608 243 tadejm
          // set RX BD number
13609 209 tadejm
          tmp_bd_num = tmp_bd_num + 1;
13610
        end
13611
        // set wrap bit
13612 243 tadejm
        set_rx_bd_wrap(124);
13613 209 tadejm
      end
13614 243 tadejm
      // 28 <= num_of_frames < 40 => wrap set to RX BD 125
13615 209 tadejm
      else if ((num_of_frames == 28) || (num_of_frames == 34))
13616
      begin
13617
        tmp_len = i_length; // length of frame
13618 243 tadejm
        tmp_bd_num = 120; // RX BD number
13619
        while (tmp_bd_num < 126) // 
13620 209 tadejm
        begin
13621
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13622
          if (tmp_len[0] == 0)
13623 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13624 209 tadejm
          else
13625 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13626
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13627 209 tadejm
          tmp_len = tmp_len + 1;
13628 243 tadejm
          // set RX BD number
13629 209 tadejm
          tmp_bd_num = tmp_bd_num + 1;
13630
        end
13631
        // set wrap bit
13632 243 tadejm
        set_rx_bd_wrap(125);
13633 209 tadejm
      end
13634 243 tadejm
      // 40 <= num_of_frames < 54 => wrap set to RX BD 126
13635 209 tadejm
      else if ((num_of_frames == 40) || (num_of_frames == 47))
13636
      begin
13637
        tmp_len = i_length; // length of frame
13638 243 tadejm
        tmp_bd_num = 120; // RX BD number
13639
        while (tmp_bd_num < 127) // 
13640 209 tadejm
        begin
13641
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13642
          if (tmp_len[0] == 0)
13643 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13644 209 tadejm
          else
13645 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13646
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13647 209 tadejm
          tmp_len = tmp_len + 1;
13648 243 tadejm
          // set RX BD number
13649 209 tadejm
          tmp_bd_num = tmp_bd_num + 1;
13650
        end
13651
        // set wrap bit
13652 243 tadejm
        set_rx_bd_wrap(126);
13653 209 tadejm
      end
13654 243 tadejm
      // 54 <= num_of_frames < 70 => wrap set to RX BD 127
13655 209 tadejm
      else if ((num_of_frames == 54) || (num_of_frames == 62))
13656
      begin
13657
        tmp_len = i_length; // length of frame
13658 243 tadejm
        tmp_bd_num = 120; // RX BD number
13659
        while (tmp_bd_num < 128) // 
13660 209 tadejm
        begin
13661
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13662
          if (tmp_len[0] == 0)
13663 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13664 209 tadejm
          else
13665 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13666
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13667 209 tadejm
          tmp_len = tmp_len + 1;
13668 243 tadejm
          // set RX BD number
13669 209 tadejm
          tmp_bd_num = tmp_bd_num + 1;
13670
        end
13671
        // set wrap bit
13672 243 tadejm
        set_rx_bd_wrap(127);
13673 209 tadejm
      end
13674 243 tadejm
      // 70 <= num_of_frames < 78 => wrap set to RX BD 127
13675
      else if (num_of_frames == 70)
13676
      begin
13677
        tmp_len = i_length; // length of frame
13678
        tmp_bd_num = 120; // RX BD number
13679
        while (tmp_bd_num < 128) // 
13680
        begin
13681
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13682
          if (tmp_len[0] == 0)
13683
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13684
          else
13685
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13686
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13687
          tmp_len = tmp_len + 1;
13688
          // set RX BD number
13689
          tmp_bd_num = tmp_bd_num + 1;
13690
        end
13691
        // set wrap bit
13692
        set_rx_bd_wrap(127);
13693
      end
13694 209 tadejm
      #1;
13695 243 tadejm
      // SET empty bit
13696 209 tadejm
      if (num_of_frames < 10)
13697 243 tadejm
        set_rx_bd_empty(120, 120);
13698 209 tadejm
      else if (num_of_frames < 14)
13699 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 10), (120 + num_of_frames - 10));
13700 209 tadejm
      else if (num_of_frames < 18)
13701 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 14), (120 + num_of_frames - 14));
13702 209 tadejm
      else if (num_of_frames < 23)
13703 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 18), (120 + num_of_frames - 18));
13704 209 tadejm
      else if (num_of_frames < 28)
13705 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 23), (120 + num_of_frames - 23));
13706 209 tadejm
      else if (num_of_frames < 34)
13707 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 28), (120 + num_of_frames - 28));
13708 209 tadejm
      else if (num_of_frames < 40)
13709 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 34), (120 + num_of_frames - 34));
13710 209 tadejm
      else if (num_of_frames < 47)
13711 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 40), (120 + num_of_frames - 40));
13712 209 tadejm
      else if (num_of_frames < 54)
13713 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 47), (120 + num_of_frames - 47));
13714 209 tadejm
      else if (num_of_frames < 62)
13715 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 54), (120 + num_of_frames - 54));
13716 209 tadejm
      else if (num_of_frames < 70)
13717 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 62), (120 + num_of_frames - 62));
13718
      else if (num_of_frames < 78)
13719
        set_rx_bd_empty((120 + num_of_frames - 70), (120 + num_of_frames - 70));
13720
      // CHECK END OF RECEIVE
13721 252 tadejm
      // receive just preamble between some packets
13722
      if ((num_of_frames == 0) || (num_of_frames == 4) || (num_of_frames == 9))
13723
      begin
13724
        #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h6, 8'h55, 0, 0, 1'b0);
13725
        @(posedge mrx_clk);
13726
        wait (MRxDV === 1'b0); // end receive
13727
        repeat(10) @(posedge mrx_clk);
13728
        repeat(15) @(posedge wb_clk);
13729
      end
13730
      // receiving frames and checking end of them
13731 243 tadejm
      frame_ended = 0;
13732
      check_frame = 0;
13733 209 tadejm
      fork
13734
        begin
13735 243 tadejm
          if (i_length[0] == 1'b0)
13736
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
13737
          else
13738
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
13739
          repeat(10) @(posedge mrx_clk);
13740
        end
13741
        begin: fr_end1
13742
          wait (MRxDV === 1'b1); // start receive
13743
          #1 check_rx_bd(num_of_bd, data);
13744
          if (data[15] !== 1)
13745 209 tadejm
          begin
13746 243 tadejm
            test_fail("Wrong buffer descriptor's empty bit read out from MAC");
13747
            fail = fail + 1;
13748 209 tadejm
          end
13749 243 tadejm
          wait (MRxDV === 1'b0); // end receive
13750
          while ((data[15] === 1) && (check_frame == 0))
13751
          begin
13752
            #1 check_rx_bd(num_of_bd, data);
13753
            @(posedge wb_clk);
13754
          end
13755
          if (data[15] === 0)
13756
            frame_ended = 1;
13757
          repeat (1) @(posedge wb_clk);
13758 209 tadejm
        end
13759 243 tadejm
        begin
13760
          wait (MRxDV === 1'b1); // start receive
13761
          wait (MRxDV === 1'b0); // end receive
13762
          repeat(10) @(posedge mrx_clk);
13763
          repeat(15) @(posedge wb_clk);
13764
          check_frame = 1;
13765
        end
13766
      join
13767
      // check length of a PACKET
13768
      if ( ((data[31:16] != (i_length + 4)) && (num_of_frames >= 3)) ||
13769
           ((data[31:16] != 0) && (num_of_frames < 3)) )
13770
      begin
13771
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
13772
                        data[31:16], (i_length + 4));
13773
        test_fail("Wrong length of the packet out from PHY");
13774
        fail = fail + 1;
13775
      end
13776
      // check received RX packet data and CRC
13777
      if ((frame_ended == 1) && (num_of_frames >= 5)) // 5 bytes is minimum size without CRC error, since
13778
      begin                                           // CRC has 4 bytes for itself
13779
        if (i_length[0] == 1'b0)
13780
        begin
13781
          check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
13782
        end
13783 209 tadejm
        else
13784
        begin
13785 243 tadejm
          check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
13786 209 tadejm
        end
13787 243 tadejm
        if (tmp > 0)
13788
        begin
13789
          `TIME; $display("*E Wrong data of the received packet");
13790
          test_fail("Wrong data of the received packet");
13791
          fail = fail + 1;
13792
        end
13793 209 tadejm
      end
13794 243 tadejm
      // check WB INT signal
13795
      if (num_of_frames >= 3) // Frames smaller than 3 are not received.
13796
      begin                   // Frames greater then 5 always cause an interrupt (Frame received)
13797
        if (wb_int !== 1'b1)  // Frames with length 3 or 4 always cause an interrupt (CRC error)
13798
        begin
13799
          `TIME; $display("*E WB INT signal should be set");
13800
          test_fail("WB INT signal should be set");
13801
          fail = fail + 1;
13802
        end
13803
      end
13804
      else
13805
      begin
13806
        if (wb_int !== 1'b0)
13807
        begin
13808
          `TIME; $display("*E WB INT signal should not be set");
13809
          test_fail("WB INT signal should not be set");
13810
          fail = fail + 1;
13811
        end
13812
      end
13813
      // check RX buffer descriptor of a packet
13814 254 mohor
      // check RX buffer descriptor of a packet
13815 243 tadejm
      if (num_of_frames >= min_tmp)
13816
      begin
13817 254 mohor
        if ( (data[15:0] !== 16'h6080) && // wrap bit
13818
             (data[15:0] !== 16'h4080) ) // without wrap bit
13819 243 tadejm
        begin
13820
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
13821
          test_fail("RX buffer descriptor status is not correct");
13822
          fail = fail + 1;
13823
        end
13824
      end
13825 254 mohor
      else if (num_of_frames > 6)
13826 243 tadejm
      begin
13827 254 mohor
        if ( (data[15:0] !== 16'h6084) && // wrap bit
13828
             (data[15:0] !== 16'h4084) ) // without wrap bit
13829
        begin
13830
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
13831
          test_fail("RX buffer descriptor status is not correct");
13832
          fail = fail + 1;
13833
        end
13834
      end
13835
      else if (num_of_frames > 4) // MAC does not recognize Dest. ADDR. for lengths 5, 6 => no MISS
13836
      begin
13837 243 tadejm
        if ( (data[15:0] !== 16'h6004) && // wrap bit
13838
             (data[15:0] !== 16'h4004) ) // without wrap bit
13839
        begin
13840
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
13841
          test_fail("RX buffer descriptor status is not correct");
13842
          fail = fail + 1;
13843
        end
13844
      end
13845 254 mohor
      else if (num_of_frames > 2) // MAC does not recognize Dest. ADDR. for length 3, 4 => no MISS, CRC ERROR
13846 243 tadejm
      begin
13847
        if ( (data[15:0] !== 16'h6006) && // wrap bit
13848
             (data[15:0] !== 16'h4006) ) // without wrap bit
13849
        begin
13850
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
13851
          test_fail("RX buffer descriptor status is not correct");
13852
          fail = fail + 1;
13853
        end
13854
      end
13855
      else
13856
      begin
13857
        if (data[15] !== 1'b1)
13858
        begin
13859
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
13860
          test_fail("RX buffer descriptor status is not correct");
13861
          fail = fail + 1;
13862
        end
13863
      end
13864
      // check interrupts
13865 274 tadejm
      wait (wbm_working == 0);
13866 243 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13867 209 tadejm
      if (num_of_frames >= 5)
13868
      begin
13869 243 tadejm
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
13870 209 tadejm
        begin
13871 243 tadejm
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
13872
          test_fail("Interrupt Receive Buffer was not set");
13873
          fail = fail + 1;
13874 209 tadejm
        end
13875 243 tadejm
        if ((data & (~`ETH_INT_RXB)) !== 0)
13876 209 tadejm
        begin
13877 243 tadejm
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
13878
          test_fail("Other interrupts (except Receive Buffer) were set");
13879
          fail = fail + 1;
13880 209 tadejm
        end
13881 243 tadejm
      end
13882
      else if ((num_of_frames < 3)) // Frames smaller than 3 are not received.
13883
      begin
13884
        if (data) // Checking if any interrupt is pending)
13885 209 tadejm
        begin
13886 243 tadejm
          `TIME; $display("*E Interrupt(s) is(are) pending although frame was ignored, interrupt reg: %0h", data);
13887
          test_fail("Interrupts were set");
13888
          fail = fail + 1;
13889
        end
13890
      end
13891
      else
13892
      begin
13893
        if ((data & `ETH_INT_RXE) !== `ETH_INT_RXE)
13894
        begin
13895
          `TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
13896
          test_fail("Interrupt Receive Buffer Error was not set");
13897
          fail = fail + 1;
13898
        end
13899
        if ((data & (~`ETH_INT_RXE)) !== 0)
13900
        begin
13901
          `TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
13902
          test_fail("Other interrupts (except Receive Buffer Error) were set");
13903
          fail = fail + 1;
13904
        end
13905
      end
13906
      // clear interrupts
13907 274 tadejm
      wait (wbm_working == 0);
13908 243 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13909
      // check WB INT signal
13910
      if (wb_int !== 1'b0)
13911
      begin
13912
        test_fail("WB INT signal should not be set");
13913
        fail = fail + 1;
13914
      end
13915
      // INTERMEDIATE DISPLAYS
13916
      if (num_of_frames == 3)
13917
      begin
13918
        $display("    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
13919
        $display("    ->packets with lengths from %0d to %0d are not received (length increasing by 1 byte)",
13920
                 0, 3);
13921
      end
13922
      else if (num_of_frames == 9)
13923
      begin
13924
        $display("    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
13925
        $display("    ->packet with length 4 is not received (length increasing by 1 byte)");
13926
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13927
                 5, 9);
13928
      end
13929
      else if (num_of_frames == 17)
13930
      begin
13931
        $display("    using 4 BDs out of 8 BDs (120..127) assigned to RX (wrap at 4th BD - RX BD 123)");
13932
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13933
                 10, 17);
13934
      end
13935
      else if (num_of_frames == 27)
13936
      begin
13937
        $display("    using 5 BDs out of 8 BDs (120..127) assigned to RX (wrap at 5th BD - RX BD 124)");
13938
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13939
                 18, 27);
13940
      end
13941
      else if (num_of_frames == 40)
13942
      begin
13943
        $display("    using 6 BDs out of 8 BDs (120..127) assigned to RX (wrap at 6th BD - RX BD 125)");
13944
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13945
                 28, 40);
13946
      end
13947
      else if (num_of_frames == 54)
13948
      begin
13949
        $display("    using 7 BDs out of 8 BDs (120..127) assigned to RX (wrap at 7th BD - RX BD 126)");
13950
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13951
                 41, 54);
13952
      end
13953
      else if (num_of_frames == 69)
13954
      begin
13955
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
13956
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13957
                 55, 69);
13958
      end
13959
      else if (num_of_frames == 69)
13960
      begin
13961
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
13962
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13963
                 55, 69);
13964
      end
13965
      else if (num_of_frames == 77)
13966
      begin
13967
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
13968
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13969
                 70, 77);
13970
      end
13971
      // set length (loop variable)
13972
      i_length = i_length + 1;
13973
      // the number of frame transmitted
13974
      num_of_frames = num_of_frames + 1;
13975
      if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
13976
          (num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
13977
          (num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
13978
          (num_of_frames == 54) || (num_of_frames == 62) || (num_of_frames == 70))
13979
        num_of_bd = 120;
13980
      else
13981
        num_of_bd = num_of_bd + 1;
13982
    end
13983
    // disable RX
13984 274 tadejm
    wait (wbm_working == 0);
13985 243 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
13986
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13987
    @(posedge wb_clk);
13988
    if(fail == 0)
13989
      test_ok;
13990
    else
13991
      fail = 0;
13992
  end
13993
 
13994
 
13995
  ////////////////////////////////////////////////////////////////////
13996
  ////                                                            ////
13997
  ////  Test receive packets form 0 to (MINFL + 12) sizes at      ////
13998
  ////  8 RX buffer decriptors ( 100Mbps ).                       ////
13999
  ////                                                            ////
14000
  ////////////////////////////////////////////////////////////////////
14001
  if (test_num == 9) // 
14002
  begin
14003
    // TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 100Mbps )
14004
    test_name = "TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 100Mbps )";
14005
    `TIME; $display("  TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 100Mbps )");
14006
 
14007
    // reset MAC registers
14008
    hard_reset;
14009
    // reset MAC and MII LOGIC with soft reset
14010 274 tadejm
//    reset_mac;
14011
//    reset_mii;
14012 243 tadejm
    // set wb slave response
14013
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
14014
 
14015
    max_tmp = 0;
14016
    min_tmp = 0;
14017
    // set 8 RX buffer descriptors (120 - 127) - must be set before RX enable
14018 274 tadejm
    wait (wbm_working == 0);
14019 243 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h78, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14020
    // enable RX, set full-duplex mode, receive small, NO correct IFG
14021 274 tadejm
    wait (wbm_working == 0);
14022 243 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
14023
              `ETH_MODER_PRO | `ETH_MODER_BRO,
14024
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14025
    // prepare two packets of MAXFL length
14026 274 tadejm
    wait (wbm_working == 0);
14027 243 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14028
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
14029
    min_tmp = tmp[31:16];
14030
    st_data = 8'hAC;
14031
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
14032
    st_data = 8'h35;
14033
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
14034
    // check WB INT signal
14035
    if (wb_int !== 1'b0)
14036
    begin
14037
      test_fail("WB INT signal should not be set");
14038
      fail = fail + 1;
14039
    end
14040
    // unmask interrupts
14041 274 tadejm
    wait (wbm_working == 0);
14042 243 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
14043
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14044
 
14045
    // write to phy's control register for 100Mbps
14046
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
14047
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
14048
    speed = 100;
14049
 
14050
    frame_ended = 0;
14051 252 tadejm
    num_of_frames = 0;// 0; // 10;
14052 243 tadejm
    num_of_bd = 120;
14053
    i_length = 0 - 4;// (0 - 4); // 6; // 4 less due to CRC
14054
    while ((i_length + 4) < 78) // (min_tmp - 4))
14055
    begin
14056
      // append CRC to packet
14057 252 tadejm
      if ((i_length[0] == 1'b0) && (num_of_frames > 4))
14058 243 tadejm
        append_rx_crc (0, i_length, 1'b0, 1'b0);
14059 252 tadejm
      else if (num_of_frames > 4)
14060 243 tadejm
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
14061
      // choose generating carrier sense and collision
14062
      case (i_length[1:0])
14063
      2'h0:
14064
      begin
14065
        // not detect carrier sense in FD and no collision
14066
        eth_phy.no_carrier_sense_rx_fd_detect(0);
14067
        eth_phy.collision(0);
14068
      end
14069
      2'h1:
14070
      begin
14071
        // detect carrier sense in FD and no collision
14072
        eth_phy.no_carrier_sense_rx_fd_detect(1);
14073
        eth_phy.collision(0);
14074
      end
14075
      2'h2:
14076
      begin
14077
        // not detect carrier sense in FD and set collision
14078
        eth_phy.no_carrier_sense_rx_fd_detect(0);
14079
        eth_phy.collision(1);
14080
      end
14081
      default: // 2'h3:
14082
      begin
14083
        // detect carrier sense in FD and set collision
14084
        eth_phy.no_carrier_sense_rx_fd_detect(1);
14085
        eth_phy.collision(1);
14086
      end
14087
      endcase
14088
      #1;
14089
      // first 10 frames are received with RX BD 120 (wrap bit on RX BD 120)
14090
      if (num_of_frames <= 9)
14091
      begin
14092
        case (i_length[1:0])
14093
        2'h0: // Interrupt is generated
14094
        begin
14095
          // enable interrupt generation
14096
          set_rx_bd(120, 120, 1'b1, (`MEMORY_BASE + i_length[1:0]));
14097
        end
14098
        2'h1: // Interrupt is generated
14099
        begin
14100
          // enable interrupt generation
14101
          set_rx_bd(120, 120, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
14102
        end
14103
        2'h2: // Interrupt is generated
14104
        begin
14105
          // enable interrupt generation
14106
          set_rx_bd(120, 120, 1'b1, (`MEMORY_BASE + i_length[1:0]));
14107
        end
14108
        default: // 2'h3: // Interrupt is generated
14109
        begin
14110
          // enable interrupt generation
14111
          set_rx_bd(120, 120, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
14112
        end
14113
        endcase
14114
        // set wrap bit
14115
        set_rx_bd_wrap(120);
14116
      end
14117
      // 10 <= num_of_frames < 18 => wrap set to TX BD 123
14118
      else if ((num_of_frames == 10) || (num_of_frames == 14))
14119
      begin
14120
        tmp_len = i_length; // length of frame
14121
        tmp_bd_num = 120; // RX BD number
14122
        while (tmp_bd_num < 124) // 
14123
        begin
14124
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
14125
          if (tmp_len[0] == 0)
14126
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
14127
          else
14128
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
14129
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
14130
          tmp_len = tmp_len + 1;
14131
          // set RX BD number
14132
          tmp_bd_num = tmp_bd_num + 1;
14133
        end
14134
        // set wrap bit
14135
        set_rx_bd_wrap(123);
14136
      end
14137
      // 18 <= num_of_frames < 28 => wrap set to RX BD 124
14138
      else if ((num_of_frames == 18) || (num_of_frames == 23))
14139
      begin
14140
        tmp_len = i_length; // length of frame
14141
        tmp_bd_num = 120; // RX BD number
14142
        while (tmp_bd_num < 125) // 
14143
        begin
14144
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
14145
          if (tmp_len[0] == 0)
14146
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
14147
          else
14148
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
14149
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
14150
          tmp_len = tmp_len + 1;
14151
          // set RX BD number
14152
          tmp_bd_num = tmp_bd_num + 1;
14153
        end
14154
        // set wrap bit
14155
        set_rx_bd_wrap(124);
14156
      end
14157
      // 28 <= num_of_frames < 40 => wrap set to RX BD 125
14158
      else if ((num_of_frames == 28) || (num_of_frames == 34))
14159
      begin
14160
        tmp_len = i_length; // length of frame
14161
        tmp_bd_num = 120; // RX BD number
14162
        while (tmp_bd_num < 126) // 
14163
        begin
14164
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
14165
          if (tmp_len[0] == 0)
14166
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
14167
          else
14168
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
14169
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
14170
          tmp_len = tmp_len + 1;
14171
          // set RX BD number
14172
          tmp_bd_num = tmp_bd_num + 1;
14173
        end
14174
        // set wrap bit
14175
        set_rx_bd_wrap(125);
14176
      end
14177
      // 40 <= num_of_frames < 54 => wrap set to RX BD 126
14178
      else if ((num_of_frames == 40) || (num_of_frames == 47))
14179
      begin
14180
        tmp_len = i_length; // length of frame
14181
        tmp_bd_num = 120; // RX BD number
14182
        while (tmp_bd_num < 127) // 
14183
        begin
14184
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
14185
          if (tmp_len[0] == 0)
14186
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
14187
          else
14188
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
14189
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
14190
          tmp_len = tmp_len + 1;
14191
          // set RX BD number
14192
          tmp_bd_num = tmp_bd_num + 1;
14193
        end
14194
        // set wrap bit
14195
        set_rx_bd_wrap(126);
14196
      end
14197
      // 54 <= num_of_frames < 70 => wrap set to RX BD 127
14198
      else if ((num_of_frames == 54) || (num_of_frames == 62))
14199
      begin
14200
        tmp_len = i_length; // length of frame
14201
        tmp_bd_num = 120; // RX BD number
14202
        while (tmp_bd_num < 128) // 
14203
        begin
14204
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
14205
          if (tmp_len[0] == 0)
14206
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
14207
          else
14208
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
14209
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
14210
          tmp_len = tmp_len + 1;
14211
          // set RX BD number
14212
          tmp_bd_num = tmp_bd_num + 1;
14213
        end
14214
        // set wrap bit
14215
        set_rx_bd_wrap(127);
14216
      end
14217
      // 70 <= num_of_frames < 78 => wrap set to RX BD 127
14218
      else if (num_of_frames == 70)
14219
      begin
14220
        tmp_len = i_length; // length of frame
14221
        tmp_bd_num = 120; // RX BD number
14222
        while (tmp_bd_num < 128) // 
14223
        begin
14224
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
14225
          if (tmp_len[0] == 0)
14226
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
14227
          else
14228
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
14229
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
14230
          tmp_len = tmp_len + 1;
14231
          // set RX BD number
14232
          tmp_bd_num = tmp_bd_num + 1;
14233
        end
14234
        // set wrap bit
14235
        set_rx_bd_wrap(127);
14236
      end
14237
      #1;
14238
      // SET empty bit
14239
      if (num_of_frames < 10)
14240
        set_rx_bd_empty(120, 120);
14241
      else if (num_of_frames < 14)
14242
        set_rx_bd_empty((120 + num_of_frames - 10), (120 + num_of_frames - 10));
14243
      else if (num_of_frames < 18)
14244
        set_rx_bd_empty((120 + num_of_frames - 14), (120 + num_of_frames - 14));
14245
      else if (num_of_frames < 23)
14246
        set_rx_bd_empty((120 + num_of_frames - 18), (120 + num_of_frames - 18));
14247
      else if (num_of_frames < 28)
14248
        set_rx_bd_empty((120 + num_of_frames - 23), (120 + num_of_frames - 23));
14249
      else if (num_of_frames < 34)
14250
        set_rx_bd_empty((120 + num_of_frames - 28), (120 + num_of_frames - 28));
14251
      else if (num_of_frames < 40)
14252
        set_rx_bd_empty((120 + num_of_frames - 34), (120 + num_of_frames - 34));
14253
      else if (num_of_frames < 47)
14254
        set_rx_bd_empty((120 + num_of_frames - 40), (120 + num_of_frames - 40));
14255
      else if (num_of_frames < 54)
14256
        set_rx_bd_empty((120 + num_of_frames - 47), (120 + num_of_frames - 47));
14257
      else if (num_of_frames < 62)
14258
        set_rx_bd_empty((120 + num_of_frames - 54), (120 + num_of_frames - 54));
14259
      else if (num_of_frames < 70)
14260
        set_rx_bd_empty((120 + num_of_frames - 62), (120 + num_of_frames - 62));
14261
      else if (num_of_frames < 78)
14262
        set_rx_bd_empty((120 + num_of_frames - 70), (120 + num_of_frames - 70));
14263
      // CHECK END OF RECEIVE
14264 252 tadejm
      // receive just preamble between some packets
14265
      if ((num_of_frames == 0) || (num_of_frames == 4) || (num_of_frames == 9))
14266
      begin
14267
        #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h6, 8'h55, 0, 0, 1'b0);
14268
        @(posedge mrx_clk);
14269
        wait (MRxDV === 1'b0); // end receive
14270
        repeat(10) @(posedge mrx_clk);
14271
        repeat(15) @(posedge wb_clk);
14272
      end
14273
      // receiving frames and checking end of them
14274 243 tadejm
      frame_ended = 0;
14275
      check_frame = 0;
14276
      fork
14277
        begin
14278
          if (i_length[0] == 1'b0)
14279
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
14280
          else
14281
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
14282
          repeat(10) @(posedge mrx_clk);
14283
        end
14284 254 mohor
        begin: fr_end2
14285 243 tadejm
          wait (MRxDV === 1'b1); // start receive
14286
          #1 check_rx_bd(num_of_bd, data);
14287
          if (data[15] !== 1)
14288 209 tadejm
          begin
14289 243 tadejm
            test_fail("Wrong buffer descriptor's empty bit read out from MAC");
14290 209 tadejm
            fail = fail + 1;
14291
          end
14292 243 tadejm
          wait (MRxDV === 1'b0); // end receive
14293
          while ((data[15] === 1) && (check_frame == 0))
14294
          begin
14295
            #1 check_rx_bd(num_of_bd, data);
14296
            @(posedge wb_clk);
14297
          end
14298
          if (data[15] === 0)
14299
            frame_ended = 1;
14300
          repeat (1) @(posedge wb_clk);
14301 209 tadejm
        end
14302
        begin
14303 243 tadejm
          wait (MRxDV === 1'b1); // start receive
14304
          wait (MRxDV === 1'b0); // end receive
14305
          repeat(10) @(posedge mrx_clk);
14306
          repeat(15) @(posedge wb_clk);
14307
          check_frame = 1;
14308 209 tadejm
        end
14309 243 tadejm
      join
14310
      // check length of a PACKET
14311 252 tadejm
      if ( ((data[31:16] != (i_length + 4)) && (num_of_frames >= 3)) ||
14312
           ((data[31:16] != 0) && (num_of_frames < 3)) )
14313 243 tadejm
      begin
14314
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
14315
                        data[31:16], (i_length + 4));
14316
        test_fail("Wrong length of the packet out from PHY");
14317
        fail = fail + 1;
14318
      end
14319
      // check received RX packet data and CRC
14320 252 tadejm
      if ((frame_ended == 1) && (num_of_frames >= 5)) // 5 bytes is minimum size without CRC error, since
14321
      begin                                           // CRC has 4 bytes for itself
14322 243 tadejm
        if (i_length[0] == 1'b0)
14323 209 tadejm
        begin
14324 243 tadejm
          check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
14325 209 tadejm
        end
14326 243 tadejm
        else
14327 209 tadejm
        begin
14328 243 tadejm
          check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
14329 209 tadejm
        end
14330
        if (tmp > 0)
14331
        begin
14332 243 tadejm
          `TIME; $display("*E Wrong data of the received packet");
14333
          test_fail("Wrong data of the received packet");
14334 209 tadejm
          fail = fail + 1;
14335
        end
14336
      end
14337
      // check WB INT signal
14338 252 tadejm
      if (num_of_frames >= 3) // Frames smaller than 3 are not received.
14339
      begin                   // Frames greater then 5 always cause an interrupt (Frame received)
14340
        if (wb_int !== 1'b1)  // Frames with length 3 or 4 always cause an interrupt (CRC error)
14341 209 tadejm
        begin
14342
          `TIME; $display("*E WB INT signal should be set");
14343
          test_fail("WB INT signal should be set");
14344
          fail = fail + 1;
14345
        end
14346
      end
14347 252 tadejm
      else
14348 209 tadejm
      begin
14349
        if (wb_int !== 1'b0)
14350
        begin
14351
          `TIME; $display("*E WB INT signal should not be set");
14352
          test_fail("WB INT signal should not be set");
14353
          fail = fail + 1;
14354
        end
14355
      end
14356 243 tadejm
      // check RX buffer descriptor of a packet
14357
      if (num_of_frames >= min_tmp)
14358
      begin
14359 254 mohor
        if ( (data[15:0] !== 16'h6080) && // wrap bit
14360
             (data[15:0] !== 16'h4080) ) // without wrap bit
14361 209 tadejm
        begin
14362 243 tadejm
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
14363
          test_fail("RX buffer descriptor status is not correct");
14364
          fail = fail + 1;
14365 209 tadejm
        end
14366 243 tadejm
      end
14367 254 mohor
      else if (num_of_frames > 6)
14368 243 tadejm
      begin
14369 254 mohor
        if ( (data[15:0] !== 16'h6084) && // wrap bit
14370
             (data[15:0] !== 16'h4084) ) // without wrap bit
14371
        begin
14372
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
14373
          test_fail("RX buffer descriptor status is not correct");
14374
          fail = fail + 1;
14375
        end
14376
      end
14377
      else if (num_of_frames > 4) // MAC does not recognize Dest. ADDR. for lengths 5, 6 => no MISS
14378
      begin
14379 243 tadejm
        if ( (data[15:0] !== 16'h6004) && // wrap bit
14380
             (data[15:0] !== 16'h4004) ) // without wrap bit
14381 209 tadejm
        begin
14382 243 tadejm
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
14383
          test_fail("RX buffer descriptor status is not correct");
14384
          fail = fail + 1;
14385 209 tadejm
        end
14386
      end
14387 254 mohor
      else if (num_of_frames > 2) // MAC does not recognize Dest. ADDR. for length 3, 4 => no MISS, CRC ERROR
14388 243 tadejm
      begin
14389
        if ( (data[15:0] !== 16'h6006) && // wrap bit
14390
             (data[15:0] !== 16'h4006) ) // without wrap bit
14391
        begin
14392
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
14393
          test_fail("RX buffer descriptor status is not correct");
14394
          fail = fail + 1;
14395
        end
14396
      end
14397 209 tadejm
      else
14398
      begin
14399
        if (data[15] !== 1'b1)
14400
        begin
14401 243 tadejm
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
14402
          test_fail("RX buffer descriptor status is not correct");
14403 209 tadejm
          fail = fail + 1;
14404
        end
14405
      end
14406
      // check interrupts
14407 274 tadejm
      wait (wbm_working == 0);
14408 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14409 252 tadejm
      if (num_of_frames >= 5)
14410 209 tadejm
      begin
14411 252 tadejm
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
14412 209 tadejm
        begin
14413 243 tadejm
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
14414
          test_fail("Interrupt Receive Buffer was not set");
14415 209 tadejm
          fail = fail + 1;
14416
        end
14417 243 tadejm
        if ((data & (~`ETH_INT_RXB)) !== 0)
14418 209 tadejm
        begin
14419 243 tadejm
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
14420
          test_fail("Other interrupts (except Receive Buffer) were set");
14421 209 tadejm
          fail = fail + 1;
14422
        end
14423
      end
14424 252 tadejm
      else if ((num_of_frames < 3)) // Frames smaller than 3 are not received.
14425
      begin
14426
        if (data) // Checking if any interrupt is pending)
14427
        begin
14428
          `TIME; $display("*E Interrupt(s) is(are) pending although frame was ignored, interrupt reg: %0h", data);
14429
          test_fail("Interrupts were set");
14430
          fail = fail + 1;
14431
        end
14432
      end
14433 209 tadejm
      else
14434
      begin
14435 252 tadejm
        if ((data & `ETH_INT_RXE) !== `ETH_INT_RXE)
14436 209 tadejm
        begin
14437 243 tadejm
          `TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
14438
          test_fail("Interrupt Receive Buffer Error was not set");
14439 209 tadejm
          fail = fail + 1;
14440
        end
14441 243 tadejm
        if ((data & (~`ETH_INT_RXE)) !== 0)
14442
        begin
14443
          `TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
14444
          test_fail("Other interrupts (except Receive Buffer Error) were set");
14445
          fail = fail + 1;
14446
        end
14447 209 tadejm
      end
14448
      // clear interrupts
14449 274 tadejm
      wait (wbm_working == 0);
14450 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14451
      // check WB INT signal
14452
      if (wb_int !== 1'b0)
14453
      begin
14454
        test_fail("WB INT signal should not be set");
14455
        fail = fail + 1;
14456
      end
14457
      // INTERMEDIATE DISPLAYS
14458 243 tadejm
      if (num_of_frames == 3)
14459 209 tadejm
      begin
14460 243 tadejm
        $display("    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
14461
        $display("    ->packets with lengths from %0d to %0d are not received (length increasing by 1 byte)",
14462 209 tadejm
                 0, 3);
14463
      end
14464 243 tadejm
      else if (num_of_frames == 9)
14465 209 tadejm
      begin
14466 243 tadejm
        $display("    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
14467
        $display("    ->packet with length 4 is not received (length increasing by 1 byte)");
14468 209 tadejm
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
14469
                 5, 9);
14470
      end
14471 243 tadejm
      else if (num_of_frames == 17)
14472 209 tadejm
      begin
14473 243 tadejm
        $display("    using 4 BDs out of 8 BDs (120..127) assigned to RX (wrap at 4th BD - RX BD 123)");
14474 209 tadejm
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
14475
                 10, 17);
14476
      end
14477 243 tadejm
      else if (num_of_frames == 27)
14478 209 tadejm
      begin
14479 243 tadejm
        $display("    using 5 BDs out of 8 BDs (120..127) assigned to RX (wrap at 5th BD - RX BD 124)");
14480 209 tadejm
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
14481
                 18, 27);
14482
      end
14483 243 tadejm
      else if (num_of_frames == 40)
14484 209 tadejm
      begin
14485 243 tadejm
        $display("    using 6 BDs out of 8 BDs (120..127) assigned to RX (wrap at 6th BD - RX BD 125)");
14486 209 tadejm
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
14487
                 28, 40);
14488
      end
14489 243 tadejm
      else if (num_of_frames == 54)
14490 209 tadejm
      begin
14491 243 tadejm
        $display("    using 7 BDs out of 8 BDs (120..127) assigned to RX (wrap at 7th BD - RX BD 126)");
14492 209 tadejm
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
14493
                 41, 54);
14494
      end
14495 243 tadejm
      else if (num_of_frames == 69)
14496 209 tadejm
      begin
14497 243 tadejm
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
14498 209 tadejm
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
14499
                 55, 69);
14500
      end
14501 243 tadejm
      else if (num_of_frames == 69)
14502
      begin
14503
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
14504
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
14505
                 55, 69);
14506
      end
14507
      else if (num_of_frames == 77)
14508
      begin
14509
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
14510
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
14511
                 70, 77);
14512
      end
14513 209 tadejm
      // set length (loop variable)
14514
      i_length = i_length + 1;
14515
      // the number of frame transmitted
14516
      num_of_frames = num_of_frames + 1;
14517
      if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
14518
          (num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
14519
          (num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
14520 243 tadejm
          (num_of_frames == 54) || (num_of_frames == 62) || (num_of_frames == 70))
14521
        num_of_bd = 120;
14522 209 tadejm
      else
14523
        num_of_bd = num_of_bd + 1;
14524
    end
14525 243 tadejm
    // disable RX
14526 274 tadejm
    wait (wbm_working == 0);
14527 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
14528
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14529
    @(posedge wb_clk);
14530
    if(fail == 0)
14531
      test_ok;
14532
    else
14533
      fail = 0;
14534
  end
14535
 
14536
 
14537 243 tadejm
  ////////////////////////////////////////////////////////////////////
14538
  ////                                                            ////
14539
  ////  Test receive packet synchronization with receive          ////
14540
  ////  disable/enable ( 10Mbps ).                                ////
14541
  ////                                                            ////
14542
  ////////////////////////////////////////////////////////////////////
14543
  if (test_num == 10) // Test no receive when all buffers are TX ( 10Mbps ).
14544
  begin
14545
    // TEST 10: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
14546
    test_name   = "TEST 10: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
14547
    `TIME; $display("  TEST 10: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
14548 209 tadejm
 
14549 243 tadejm
 
14550
 
14551
 
14552
 
14553
 
14554
  end
14555
 
14556
 
14557
  ////////////////////////////////////////////////////////////////////
14558
  ////                                                            ////
14559
  ////  Test receive packet synchronization with receive          ////
14560
  ////  disable/enable ( 10Mbps ).                                ////
14561
  ////                                                            ////
14562
  ////////////////////////////////////////////////////////////////////
14563
  if (test_num == 12) // Test no receive when all buffers are TX ( 10Mbps ).
14564
  begin
14565
    // TEST 12: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
14566
    test_name   = "TEST 12: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
14567
    `TIME; $display("  TEST 12: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
14568
 
14569
 
14570
 
14571
 
14572
 
14573
 
14574
  end
14575
 
14576
 
14577
  ////////////////////////////////////////////////////////////////////
14578
  ////                                                            ////
14579
  ////  Test receive packet synchronization with receive          ////
14580
  ////  disable/enable ( 10Mbps ).                                ////
14581
  ////                                                            ////
14582
  ////////////////////////////////////////////////////////////////////
14583
  if (test_num == 14) // Test no receive when all buffers are TX ( 10Mbps ).
14584
  begin
14585
    // TEST 14: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
14586
    test_name   = "TEST 14: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
14587
    `TIME; $display("  TEST 14: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
14588
 
14589
 
14590
 
14591
 
14592
 
14593
 
14594
  end
14595
 
14596
 
14597
  ////////////////////////////////////////////////////////////////////
14598
  ////                                                            ////
14599
  ////  Test receive packet synchronization with receive          ////
14600
  ////  disable/enable ( 10Mbps ).                                ////
14601
  ////                                                            ////
14602
  ////////////////////////////////////////////////////////////////////
14603
  if (test_num == 16) // Test no receive when all buffers are TX ( 10Mbps ).
14604
  begin
14605
    // TEST 16: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
14606
    test_name   = "TEST 16: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
14607
    `TIME; $display("  TEST 16: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
14608
 
14609
 
14610
 
14611
 
14612
 
14613
 
14614
  end
14615
 
14616
 
14617
 
14618 209 tadejm
end   //  for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
14619
 
14620
end
14621
endtask // test_mac_full_duplex_receive
14622
 
14623
 
14624 263 mohor
task test_mac_full_duplex_flow_control;
14625 209 tadejm
  input  [31:0]  start_task;
14626
  input  [31:0]  end_task;
14627
  integer        bit_start_1;
14628
  integer        bit_end_1;
14629
  integer        bit_start_2;
14630
  integer        bit_end_2;
14631
  integer        num_of_reg;
14632
  integer        num_of_frames;
14633 274 tadejm
  integer        num_of_rx_frames;
14634 209 tadejm
  integer        num_of_bd;
14635
  integer        i_addr;
14636
  integer        i_data;
14637
  integer        i_length;
14638
  integer        tmp_len;
14639
  integer        tmp_bd;
14640
  integer        tmp_bd_num;
14641
  integer        tmp_data;
14642
  integer        tmp_ipgt;
14643
  integer        test_num;
14644 274 tadejm
  integer        rx_len;
14645
  integer        tx_len;
14646 209 tadejm
  reg    [31:0]  tx_bd_num;
14647 274 tadejm
  reg    [31:0]  rx_bd_num;
14648 209 tadejm
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
14649
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
14650
  integer        i;
14651
  integer        i1;
14652
  integer        i2;
14653
  integer        i3;
14654
  integer        fail;
14655
  integer        speed;
14656 260 mohor
  integer        mac_hi_addr;
14657
  integer        mac_lo_addr;
14658 209 tadejm
  reg            frame_started;
14659
  reg            frame_ended;
14660
  reg            wait_for_frame;
14661
  reg    [31:0]  addr;
14662
  reg    [31:0]  data;
14663
  reg    [31:0]  tmp;
14664
  reg    [ 7:0]  st_data;
14665
  reg    [15:0]  max_tmp;
14666
  reg    [15:0]  min_tmp;
14667 263 mohor
  reg            PassAll;
14668
  reg            RxFlow;
14669 266 mohor
  reg            enable_irq_in_rxbd;
14670 267 mohor
  reg    [15:0]  pause_value;
14671 274 tadejm
 
14672 209 tadejm
begin
14673 263 mohor
// MAC FULL DUPLEX FLOW CONTROL TEST
14674
test_heading("MAC FULL DUPLEX FLOW CONTROL TEST");
14675 209 tadejm
$display(" ");
14676 263 mohor
$display("MAC FULL DUPLEX FLOW CONTROL TEST");
14677 209 tadejm
fail = 0;
14678
 
14679
// reset MAC registers
14680
hard_reset;
14681
// reset MAC and MII LOGIC with soft reset
14682 274 tadejm
//reset_mac;
14683
//reset_mii;
14684 209 tadejm
// set wb slave response
14685
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
14686
 
14687
  /*
14688
  TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
14689
  -------------------------------------------------------------------------------------
14690
  set_tx_bd
14691
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0], len[15:0], irq, pad, crc, txpnt[31:0]);
14692
  set_tx_bd_wrap
14693
    (tx_bd_num_end[6:0]);
14694
  set_tx_bd_ready
14695
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
14696
  check_tx_bd
14697
    (tx_bd_num_start[6:0], tx_bd_status[31:0]);
14698
  clear_tx_bd
14699
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
14700
 
14701
  TASKS for set and control RX buffer descriptors:
14702
  ------------------------------------------------
14703
  set_rx_bd
14704
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0], irq, rxpnt[31:0]);
14705
  set_rx_bd_wrap
14706
    (rx_bd_num_end[6:0]);
14707
  set_rx_bd_empty
14708
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
14709
  check_rx_bd
14710
    (rx_bd_num_end[6:0], rx_bd_status);
14711
  clear_rx_bd
14712
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
14713
 
14714
  TASKS for set and check TX packets:
14715
  -----------------------------------
14716
  set_tx_packet
14717
    (txpnt[31:0], len[15:0], eth_start_data[7:0]);
14718
  check_tx_packet
14719
    (txpnt_wb[31:0], txpnt_phy[31:0], len[15:0], failure[31:0]);
14720
 
14721
  TASKS for set and check RX packets:
14722
  -----------------------------------
14723
  set_rx_packet
14724
    (rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
14725
  check_rx_packet
14726
    (rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
14727
 
14728
  TASKS for append and check CRC to/of TX packet:
14729
  -----------------------------------------------
14730
  append_tx_crc
14731
    (txpnt_wb[31:0], len[15:0], negated_crc);
14732
  check_tx_crc
14733
    (txpnt_phy[31:0], len[15:0], negated_crc, failure[31:0]);
14734
 
14735
  TASK for append CRC to RX packet (CRC is checked together with check_rx_packet):
14736
  --------------------------------------------------------------------------------
14737
  append_rx_crc
14738
    (rxpnt_phy[31:0], len[15:0], plus_nibble, negated_crc);
14739
  */
14740
 
14741
//////////////////////////////////////////////////////////////////////
14742
////                                                              ////
14743 263 mohor
////  test_mac_full_duplex_flow_control:                          ////
14744 209 tadejm
////                                                              ////
14745
////  0: Test                                                     ////
14746
////                                                              ////
14747
//////////////////////////////////////////////////////////////////////
14748 260 mohor
 
14749 209 tadejm
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
14750
begin
14751
 
14752
  ////////////////////////////////////////////////////////////////////
14753
  ////                                                            ////
14754 254 mohor
  ////  Test inserts control frames while transmitting normal     ////
14755
  ////  frames. Using 4 TX buffer decriptors ( 10Mbps ).          ////
14756 209 tadejm
  ////                                                            ////
14757
  ////////////////////////////////////////////////////////////////////
14758 254 mohor
  if (test_num == 0) // 
14759 209 tadejm
  begin
14760 254 mohor
    // TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps )
14761
    test_name = "TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps )";
14762
    `TIME; $display("  TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps )");
14763 260 mohor
 
14764 254 mohor
    // reset MAC completely
14765
    hard_reset;
14766
    // set wb slave response
14767
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
14768
    max_tmp = 0;
14769
    min_tmp = 0;
14770
    // set 4 TX buffer descriptors - must be set before TX enable
14771
    wbm_write(`ETH_TX_BD_NUM, 32'h4, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14772
    // enable TX, set full-duplex mode, padding and CRC appending
14773
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
14774
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14775
    // enable TX flow control
14776
    wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_TXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14777 260 mohor
    // Set MAC address
14778
    mac_hi_addr = 32'h00000001;
14779
    mac_lo_addr = 32'h02030405;
14780
    wbm_write(`ETH_MAC_ADDR1, mac_hi_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14781
    wbm_write(`ETH_MAC_ADDR0, mac_lo_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14782 254 mohor
    // prepare two packets of MAXFL length
14783
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14784
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
14785
    min_tmp = tmp[31:16];
14786 260 mohor
    st_data = 8'h34;
14787 254 mohor
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC. Writing data to the memory
14788 260 mohor
    st_data = 8'h56;
14789 254 mohor
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp - 4), st_data); // length without CRC. Writing data to the memory
14790
    // check WB INT signal
14791
    if (wb_int !== 1'b0)
14792
    begin
14793
      test_fail("WB INT signal should not be set");
14794
      fail = fail + 1;
14795
    end
14796
 
14797
    // write to phy's control register for 10Mbps
14798
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
14799
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
14800
    speed = 10;
14801
 
14802
    frame_started = 0;
14803
    num_of_frames = 0;
14804
    num_of_bd = 0;
14805
    i_length = 0; // 0;
14806 260 mohor
    // Initialize one part of memory with data of control packet
14807
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h0), 32'h0180c200, 4'hF);
14808
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h4), {16'h0001, mac_hi_addr[15:0]}, 4'hF);
14809
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h8), mac_lo_addr, 4'hF);
14810
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'hc), 32'h88080001, 4'hF);
14811
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), 32'h11110000, 4'hF);
14812
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h14), 32'h00000000, 4'hF);
14813
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h18), 32'h00000000, 4'hF);
14814
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h1c), 32'h00000000, 4'hF);
14815
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h20), 32'h00000000, 4'hF);
14816
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h24), 32'h00000000, 4'hF);
14817
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h28), 32'h00000000, 4'hF);
14818
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h2c), 32'h00000000, 4'hF);
14819
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h30), 32'h00000000, 4'hF);
14820
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h34), 32'h00000000, 4'hF);
14821
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h38), 32'h00000000, 4'hF);
14822
//    append_tx_crc(`MEMORY_BASE + 2 * max_tmp, 60, 0);       // CRC is appended after the data
14823 254 mohor
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14824
    // In the following section, control frame will be sent while no other transmission is in progress.//
14825
    // TXC interrupt won't be unmasked.                                                                //
14826
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14827 274 tadejm
    // check interrupts
14828 254 mohor
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14829
    if(data)
14830
      begin
14831
        test_fail("IRQ already pending!");
14832
        fail = fail + 1;
14833
        `TIME; $display("*E IRQ already pending!");
14834
      end
14835
    if (wb_int)
14836
    begin
14837
      test_fail("WB INT signal should not be set!");
14838
      fail = fail + 1;
14839
      `TIME; $display("*E WB INT signal should not be set!");
14840
    end
14841 260 mohor
    // first destination address on ethernet PHY
14842
    eth_phy.set_tx_mem_addr(0);
14843
    // Request sending the control frame with pause value = 0x1111
14844
    wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | 32'h1111, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14845 274 tadejm
    // wait for transmission to come over
14846 254 mohor
    wait (MTxEn === 1'b1); // start transmit
14847
    wait (MTxEn === 1'b0); // end transmit
14848
    repeat(10) @ (posedge wb_clk);  // wait some time
14849
    repeat(10) @ (posedge mtx_clk); // wait some time
14850 274 tadejm
    // check interrupt
14851 254 mohor
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14852
    if(data !== `ETH_INT_TXC)
14853
      begin
14854
        test_fail("TXC IRQ should be set!");
14855
        fail = fail + 1;
14856
        `TIME; $display("*E TXC IRQ should be set!");
14857
      end
14858
    if (wb_int)
14859
    begin
14860
      test_fail("WB INT signal should not be set because TXC irq is masked!");
14861
      fail = fail + 1;
14862
      `TIME; $display("*E WB INT signal should not be set because TXC irq is masked!");
14863
    end
14864
    // Clear TXC interrupt
14865
    wbm_write(`ETH_INT, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14866
    if (wb_int)
14867
    begin
14868
      test_fail("WB INT signal should not be set!");
14869
      fail = fail + 1;
14870
      `TIME; $display("*E WB INT signal should not be set!");
14871
    end
14872 274 tadejm
    // check transmited TX packet
14873 260 mohor
    check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
14874
    if (tmp > 0)
14875
    begin
14876
      $display("Wrong data of the transmitted packet");
14877
      test_fail("Wrong data of the transmitted packet");
14878
      fail = fail + 1;
14879
    end
14880
    // check transmited TX packet CRC
14881
    #1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
14882
    if (tmp > 0)
14883
    begin
14884
      $display("Wrong CRC of the transmitted packet");
14885
      test_fail("Wrong CRC of the transmitted packet");
14886
      fail = fail + 1;
14887
    end
14888 254 mohor
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14889
    // In the following section, control frame will be sent while no other transmission is in progress.//
14890
    // TXC interrupt is unmasked.                                                                      //
14891
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14892
    // unmask all interrupts
14893
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
14894
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14895 274 tadejm
    // check interrupts
14896 254 mohor
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14897
    if(data)
14898
      begin
14899
        test_fail("IRQ already pending!");
14900
        fail = fail + 1;
14901
        `TIME; $display("*E IRQ already pending!");
14902
      end
14903
    if (wb_int)
14904
    begin
14905
      test_fail("WB INT signal should not be set!");
14906
      fail = fail + 1;
14907
      `TIME; $display("*E WB INT signal should not be set!");
14908
    end
14909
    // unmask only TXC interrupts
14910
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14911 260 mohor
    // first destination address on ethernet PHY
14912
    eth_phy.set_tx_mem_addr(0);
14913
    // Request sending the control frame with pause value = 0x2222
14914
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), 32'h22220000, 4'hF);  // Just for data test
14915
    wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | 32'h2222, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14916 274 tadejm
    // wait for transmit to come over
14917 254 mohor
    wait (MTxEn === 1'b1); // start transmit
14918
    wait (MTxEn === 1'b0); // end transmit
14919
    repeat(10) @ (posedge wb_clk);  // wait some time
14920
    repeat(10) @ (posedge mtx_clk); // wait some time
14921 274 tadejm
    // check INT
14922 254 mohor
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14923
    if(data !== `ETH_INT_TXC)
14924
      begin
14925
        test_fail("TXC IRQ should be set!");
14926
        fail = fail + 1;
14927
        `TIME; $display("*E TXC IRQ should be set!");
14928
      end
14929
    if (!wb_int)
14930
    begin
14931
      test_fail("WB INT signal should be set!");
14932
      fail = fail + 1;
14933
      `TIME; $display("*E WB INT signal should be set!");
14934
    end
14935
    // Clear TXC interrupt
14936
    wbm_write(`ETH_INT, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14937
    if (wb_int)
14938
    begin
14939
      test_fail("WB INT signal should not be set!");
14940
      fail = fail + 1;
14941
      `TIME; $display("*E WB INT signal should not be set!");
14942
    end
14943 274 tadejm
    // check transmited TX packet
14944 260 mohor
    check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
14945
    if (tmp > 0)
14946
    begin
14947
      $display("Wrong data of the transmitted packet");
14948
      test_fail("Wrong data of the transmitted packet");
14949
      fail = fail + 1;
14950
    end
14951
    // check transmited TX packet CRC
14952
    #1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
14953
    if (tmp > 0)
14954
    begin
14955
      $display("Wrong CRC of the transmitted packet");
14956
      test_fail("Wrong CRC of the transmitted packet");
14957
      fail = fail + 1;
14958
    end
14959 254 mohor
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14960 260 mohor
    // In the following section, control frame sending is requested while no other transmission        //
14961
    // is in progress. TXC interrupt is unmasked.                                                      //
14962 254 mohor
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14963
    // unmask all interrupts
14964
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
14965
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14966
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14967
    if(data)
14968
      begin
14969
        test_fail("IRQ already pending!");
14970
        fail = fail + 1;
14971
        `TIME; $display("*E IRQ already pending!");
14972
      end
14973
    if (wb_int)
14974
    begin
14975
      test_fail("WB INT signal should not be set!");
14976
      fail = fail + 1;
14977
      `TIME; $display("*E WB INT signal should not be set!");
14978
    end
14979 260 mohor
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14980
    // In the following section, control frame request and data send request are both set. At the      //
14981
    // beginning control frame request will be faster than data send request, later the opposite.      //
14982
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14983
    for (i=0; i<32; i=i+1)
14984
    begin
14985
      // Request sending the control frame with pause value = 0x5678
14986
      set_tx_bd(0, 0, 16'h100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE)); // irq, pad, crc
14987
      set_tx_bd_wrap(0);
14988
      // first destination address on ethernet PHY
14989
      eth_phy.set_tx_mem_addr(0);
14990
      set_tx_bd_ready(0, 0);
14991 274 tadejm
      // wait for transmission to start  
14992 260 mohor
      wait (MTxEn === 1'b1); // start transmit
14993
      repeat(i) @ (posedge mtx_clk);  // We need to wait some time until TX module starts using the data (preamble stage is over)
14994
      // Send control frame request
14995
      wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), {i[3:0], i[3:0], i[3:0], i[3:0], 16'h0}, 4'hF);  // Just for data test
14996
      wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | {16'h0, i[3:0], i[3:0], i[3:0], i[3:0]}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14997 274 tadejm
      // wait until transmission is over  
14998 260 mohor
      wait (MTxEn === 1'b0); // Wait until data frame transmission is over
14999
      repeat(10) @ (posedge mtx_clk); // wait some time so status is written
15000
      tmp_len = eth_phy.tx_len; // the length of a packet which was sent out first!!!
15001
      repeat(10) @ (posedge wb_clk);  // wait some time so status is written
15002
      // first destination address on ethernet PHY
15003
      eth_phy.set_tx_mem_addr(0);
15004 274 tadejm
      // check interrupt depending on which packet was sent
15005 260 mohor
      if(tmp_len == 64)  // Control frame
15006 254 mohor
      begin
15007 260 mohor
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15008
        if(data !== `ETH_INT_TXC)
15009
        begin
15010
          test_fail("TXC IRQ should be set!");
15011
          fail = fail + 1;
15012
          `TIME; $display("*E TXC IRQ should be set!");
15013
          `TIME; $display("ETH_INT = 0x%0x", data);
15014
        end
15015
      end
15016
      else
15017
      begin
15018
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15019
        if(data !== `ETH_INT_TXB)
15020
        begin
15021
          test_fail("TXB IRQ should be set!");
15022
          fail = fail + 1;
15023
          `TIME; $display("*E TXB IRQ should be set!");
15024
          `TIME; $display("ETH_INT = 0x%0x", data);
15025
        end
15026
      end
15027 274 tadejm
      // check transmited TX packet
15028 260 mohor
      if(tmp_len == 64)  // Control frame
15029
        check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
15030
      else
15031
        check_tx_packet((`MEMORY_BASE), 0, 32'h100, tmp);
15032
      if (tmp > 0)
15033
      begin
15034
        $display("Wrong data of the transmitted packet");
15035
        test_fail("Wrong data of the transmitted packet");
15036 254 mohor
        fail = fail + 1;
15037
      end
15038 260 mohor
      // check transmited TX packet CRC
15039
      if(tmp_len == 64)  // Control frame
15040
        #1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
15041
      else
15042
        #1 check_tx_crc(0, 32'h100, 1'b0, tmp); // length without CRC
15043
 
15044
      if (tmp > 0)
15045 254 mohor
      begin
15046 260 mohor
        $display("Wrong CRC of the transmitted packet");
15047
        test_fail("Wrong CRC of the transmitted packet");
15048
        fail = fail + 1;
15049
      end
15050 274 tadejm
      // wait for control frame to transmit
15051 260 mohor
      wait (MTxEn === 1'b1); // start transmit of the control frame
15052
      wait (MTxEn === 1'b0); // end transmit of the control frame
15053
      repeat(10) @ (posedge wb_clk);  // wait some time
15054
      repeat(10) @ (posedge mtx_clk); // wait some time so status is written
15055 274 tadejm
      // check interrupts  
15056 260 mohor
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15057
      if(data !== (`ETH_INT_TXC | `ETH_INT_TXB))
15058
      begin
15059 254 mohor
        test_fail("TXC and TXB IRQ should be set!");
15060
        fail = fail + 1;
15061 260 mohor
        `TIME; $display("*E TXC and TXB IRQ should be set! (ETH_INT=0x%0x)", data);
15062 254 mohor
      end
15063 260 mohor
      if (!wb_int)
15064
      begin
15065
        test_fail("WB INT signal should be set!");
15066
        fail = fail + 1;
15067
        `TIME; $display("*E WB INT signal should be set!");
15068
      end
15069
      // Clear TXC and TXB interrupt
15070
      wbm_write(`ETH_INT, `ETH_INT_TXC | `ETH_INT_TXB, 4'hF, 1, 4'h0, 4'h0);
15071
      if (wb_int)
15072
      begin
15073
        test_fail("WB INT signal should not be set!");
15074
        fail = fail + 1;
15075
        `TIME; $display("*E WB INT signal should not be set!");
15076
      end
15077
      if(tmp_len == 64)  // Control frame
15078
        check_tx_packet((`MEMORY_BASE), 0, 32'h100, tmp);
15079
      else
15080
        check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
15081
      if (tmp > 0)
15082
      begin
15083
        $display("Wrong data of the transmitted packet");
15084
        test_fail("Wrong data of the transmitted packet");
15085
        fail = fail + 1;
15086
      end
15087
      // check transmited TX packet CRC
15088
      if(tmp_len == 64)  // Control frame
15089
        #1 check_tx_crc(0, 32'h100, 1'b0, tmp); // length without CRC
15090
      else
15091
        #1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
15092
      if (tmp > 0)
15093
      begin
15094
        $display("Wrong CRC of the transmitted packet");
15095
        test_fail("Wrong CRC of the transmitted packet");
15096
        fail = fail + 1;
15097
      end
15098
    end // for loop
15099
    if(fail == 0)
15100
      test_ok;
15101
    else
15102
      fail = 0;
15103
  end
15104 254 mohor
 
15105
 
15106 274 tadejm
  ////////////////////////////////////////////////////////////////////
15107
  ////                                                            ////
15108
  ////  Test inserts control frames while transmitting normal     ////
15109
  ////  frames. Using 4 TX buffer decriptors ( 100Mbps ).         ////
15110
  ////                                                            ////
15111
  ////////////////////////////////////////////////////////////////////
15112 263 mohor
  if (test_num == 1) // 
15113
  begin
15114
    // TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps )
15115
    test_name = "TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps )";
15116
    `TIME; $display("  TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps )");
15117 274 tadejm
 
15118
    // reset MAC completely
15119
    hard_reset;
15120
    // set wb slave response
15121
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
15122
    max_tmp = 0;
15123
    min_tmp = 0;
15124
    // set 4 TX buffer descriptors - must be set before TX enable
15125
    wbm_write(`ETH_TX_BD_NUM, 32'h4, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15126
    // enable TX, set full-duplex mode, padding and CRC appending
15127
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
15128
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15129
    // enable TX flow control
15130
    wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_TXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15131
    // Set MAC address
15132
    mac_hi_addr = 32'h00000001;
15133
    mac_lo_addr = 32'h02030405;
15134
    wbm_write(`ETH_MAC_ADDR1, mac_hi_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15135
    wbm_write(`ETH_MAC_ADDR0, mac_lo_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15136
    // prepare two packets of MAXFL length
15137
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15138
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
15139
    min_tmp = tmp[31:16];
15140
    st_data = 8'h34;
15141
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC. Writing data to the memory
15142
    st_data = 8'h56;
15143
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp - 4), st_data); // length without CRC. Writing data to the memory
15144
    // check WB INT signal
15145
    if (wb_int !== 1'b0)
15146
    begin
15147
      test_fail("WB INT signal should not be set");
15148
      fail = fail + 1;
15149
    end
15150
 
15151
    // write to phy's control register for 100Mbps
15152
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
15153
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
15154
    speed = 100;
15155
 
15156
    frame_started = 0;
15157
    num_of_frames = 0;
15158
    num_of_bd = 0;
15159
    i_length = 0; // 0;
15160
    // Initialize one part of memory with data of control packet
15161
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h0), 32'h0180c200, 4'hF);
15162
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h4), {16'h0001, mac_hi_addr[15:0]}, 4'hF);
15163
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h8), mac_lo_addr, 4'hF);
15164
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'hc), 32'h88080001, 4'hF);
15165
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), 32'h11110000, 4'hF);
15166
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h14), 32'h00000000, 4'hF);
15167
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h18), 32'h00000000, 4'hF);
15168
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h1c), 32'h00000000, 4'hF);
15169
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h20), 32'h00000000, 4'hF);
15170
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h24), 32'h00000000, 4'hF);
15171
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h28), 32'h00000000, 4'hF);
15172
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h2c), 32'h00000000, 4'hF);
15173
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h30), 32'h00000000, 4'hF);
15174
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h34), 32'h00000000, 4'hF);
15175
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h38), 32'h00000000, 4'hF);
15176
//    append_tx_crc(`MEMORY_BASE + 2 * max_tmp, 60, 0);       // CRC is appended after the data
15177
    /////////////////////////////////////////////////////////////////////////////////////////////////////
15178
    // In the following section, control frame will be sent while no other transmission is in progress.//
15179
    // TXC interrupt won't be unmasked.                                                                //
15180
    /////////////////////////////////////////////////////////////////////////////////////////////////////
15181
    // check interrupts
15182
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15183
    if(data)
15184
      begin
15185
        test_fail("IRQ already pending!");
15186
        fail = fail + 1;
15187
        `TIME; $display("*E IRQ already pending!");
15188
      end
15189
    if (wb_int)
15190
    begin
15191
      test_fail("WB INT signal should not be set!");
15192
      fail = fail + 1;
15193
      `TIME; $display("*E WB INT signal should not be set!");
15194
    end
15195
    // first destination address on ethernet PHY
15196
    eth_phy.set_tx_mem_addr(0);
15197
    // Request sending the control frame with pause value = 0x1111
15198
    wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | 32'h1111, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15199
    // wait for transmission to come over
15200
    wait (MTxEn === 1'b1); // start transmit
15201
    wait (MTxEn === 1'b0); // end transmit
15202
    repeat(10) @ (posedge wb_clk);  // wait some time
15203
    repeat(10) @ (posedge mtx_clk); // wait some time
15204
    // check interrupt
15205
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15206
    if(data !== `ETH_INT_TXC)
15207
      begin
15208
        test_fail("TXC IRQ should be set!");
15209
        fail = fail + 1;
15210
        `TIME; $display("*E TXC IRQ should be set!");
15211
      end
15212
    if (wb_int)
15213
    begin
15214
      test_fail("WB INT signal should not be set because TXC irq is masked!");
15215
      fail = fail + 1;
15216
      `TIME; $display("*E WB INT signal should not be set because TXC irq is masked!");
15217
    end
15218
    // Clear TXC interrupt
15219
    wbm_write(`ETH_INT, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15220
    if (wb_int)
15221
    begin
15222
      test_fail("WB INT signal should not be set!");
15223
      fail = fail + 1;
15224
      `TIME; $display("*E WB INT signal should not be set!");
15225
    end
15226
    // check transmited TX packet
15227
    check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
15228
    if (tmp > 0)
15229
    begin
15230
      $display("Wrong data of the transmitted packet");
15231
      test_fail("Wrong data of the transmitted packet");
15232
      fail = fail + 1;
15233
    end
15234
    // check transmited TX packet CRC
15235
    #1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
15236
    if (tmp > 0)
15237
    begin
15238
      $display("Wrong CRC of the transmitted packet");
15239
      test_fail("Wrong CRC of the transmitted packet");
15240
      fail = fail + 1;
15241
    end
15242
    /////////////////////////////////////////////////////////////////////////////////////////////////////
15243
    // In the following section, control frame will be sent while no other transmission is in progress.//
15244
    // TXC interrupt is unmasked.                                                                      //
15245
    /////////////////////////////////////////////////////////////////////////////////////////////////////
15246
    // unmask all interrupts
15247
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
15248
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15249
    // check interrupts
15250
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15251
    if(data)
15252
      begin
15253
        test_fail("IRQ already pending!");
15254
        fail = fail + 1;
15255
        `TIME; $display("*E IRQ already pending!");
15256
      end
15257
    if (wb_int)
15258
    begin
15259
      test_fail("WB INT signal should not be set!");
15260
      fail = fail + 1;
15261
      `TIME; $display("*E WB INT signal should not be set!");
15262
    end
15263
    // unmask only TXC interrupts
15264
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15265
    // first destination address on ethernet PHY
15266
    eth_phy.set_tx_mem_addr(0);
15267
    // Request sending the control frame with pause value = 0x2222
15268
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), 32'h22220000, 4'hF);  // Just for data test
15269
    wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | 32'h2222, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15270
    // wait for transmit to come over
15271
    wait (MTxEn === 1'b1); // start transmit
15272
    wait (MTxEn === 1'b0); // end transmit
15273
    repeat(10) @ (posedge wb_clk);  // wait some time
15274
    repeat(10) @ (posedge mtx_clk); // wait some time
15275
    // check INT
15276
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15277
    if(data !== `ETH_INT_TXC)
15278
      begin
15279
        test_fail("TXC IRQ should be set!");
15280
        fail = fail + 1;
15281
        `TIME; $display("*E TXC IRQ should be set!");
15282
      end
15283
    if (!wb_int)
15284
    begin
15285
      test_fail("WB INT signal should be set!");
15286
      fail = fail + 1;
15287
      `TIME; $display("*E WB INT signal should be set!");
15288
    end
15289
    // Clear TXC interrupt
15290
    wbm_write(`ETH_INT, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15291
    if (wb_int)
15292
    begin
15293
      test_fail("WB INT signal should not be set!");
15294
      fail = fail + 1;
15295
      `TIME; $display("*E WB INT signal should not be set!");
15296
    end
15297
    // check transmited TX packet
15298
    check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
15299
    if (tmp > 0)
15300
    begin
15301
      $display("Wrong data of the transmitted packet");
15302
      test_fail("Wrong data of the transmitted packet");
15303
      fail = fail + 1;
15304
    end
15305
    // check transmited TX packet CRC
15306
    #1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
15307
    if (tmp > 0)
15308
    begin
15309
      $display("Wrong CRC of the transmitted packet");
15310
      test_fail("Wrong CRC of the transmitted packet");
15311
      fail = fail + 1;
15312
    end
15313
    /////////////////////////////////////////////////////////////////////////////////////////////////////
15314
    // In the following section, control frame sending is requested while no other transmission        //
15315
    // is in progress. TXC interrupt is unmasked.                                                      //
15316
    /////////////////////////////////////////////////////////////////////////////////////////////////////
15317
    // unmask all interrupts
15318
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
15319
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15320
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15321
    if(data)
15322
      begin
15323
        test_fail("IRQ already pending!");
15324
        fail = fail + 1;
15325
        `TIME; $display("*E IRQ already pending!");
15326
      end
15327
    if (wb_int)
15328
    begin
15329
      test_fail("WB INT signal should not be set!");
15330
      fail = fail + 1;
15331
      `TIME; $display("*E WB INT signal should not be set!");
15332
    end
15333
 
15334
    /////////////////////////////////////////////////////////////////////////////////////////////////////
15335
    // In the following section, control frame request and data send request are both set. At the      //
15336
    // beginning control frame request will be faster than data send request, later the opposite.      //
15337
    /////////////////////////////////////////////////////////////////////////////////////////////////////
15338
    for (i=0; i<32; i=i+1)
15339
    begin
15340
      // Request sending the control frame with pause value = 0x5678
15341
      set_tx_bd(0, 0, 16'h100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE)); // irq, pad, crc
15342
      set_tx_bd_wrap(0);
15343
      // first destination address on ethernet PHY
15344
      eth_phy.set_tx_mem_addr(0);
15345
      set_tx_bd_ready(0, 0);
15346
      // wait for transmission to start  
15347
      wait (MTxEn === 1'b1); // start transmit
15348
      repeat(i) @ (posedge mtx_clk);  // We need to wait some time until TX module starts using the data (preamble stage is over)
15349
      // Send control frame request
15350
      wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), {i[3:0], i[3:0], i[3:0], i[3:0], 16'h0}, 4'hF);  // Just for data test
15351
      wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | {16'h0, i[3:0], i[3:0], i[3:0], i[3:0]}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15352
      // wait until transmission is over  
15353
      wait (MTxEn === 1'b0); // Wait until data frame transmission is over
15354
      repeat(10) @ (posedge mtx_clk); // wait some time so status is written
15355
      tmp_len = eth_phy.tx_len; // the length of a packet which was sent out first!!!
15356
      repeat(10) @ (posedge wb_clk);  // wait some time so status is written
15357
      // first destination address on ethernet PHY
15358
      eth_phy.set_tx_mem_addr(0);
15359
      // check interrupt depending on which packet was sent
15360
 
15361
      if(tmp_len == 64)  // Control frame
15362
      begin
15363
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15364
        if(data !== `ETH_INT_TXC)
15365
        begin
15366
          test_fail("TXC IRQ should be set!");
15367
          fail = fail + 1;
15368
          `TIME; $display("*E TXC IRQ should be set!");
15369
          `TIME; $display("ETH_INT = 0x%0x", data);
15370
        end
15371
      end
15372
      else
15373
      begin
15374
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15375
        if(data !== `ETH_INT_TXB)
15376
        begin
15377
          test_fail("TXB IRQ should be set!");
15378
          fail = fail + 1;
15379
          `TIME; $display("*E TXB IRQ should be set!");
15380
          `TIME; $display("ETH_INT = 0x%0x", data);
15381
        end
15382
      end
15383
      // check transmited TX packet
15384
      if(tmp_len == 64)  // Control frame
15385
        check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
15386
      else
15387
        check_tx_packet((`MEMORY_BASE), 0, 32'h100, tmp);
15388
      if (tmp > 0)
15389
      begin
15390
        $display("Wrong data of the transmitted packet");
15391
        test_fail("Wrong data of the transmitted packet");
15392
        fail = fail + 1;
15393
      end
15394
      // check transmited TX packet CRC
15395
      if(tmp_len == 64)  // Control frame
15396
        #1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
15397
      else
15398
        #1 check_tx_crc(0, 32'h100, 1'b0, tmp); // length without CRC
15399
 
15400
      if (tmp > 0)
15401
      begin
15402
        $display("Wrong CRC of the transmitted packet");
15403
        test_fail("Wrong CRC of the transmitted packet");
15404
        fail = fail + 1;
15405
      end
15406
      // wait for control frame to transmit
15407
      wait (MTxEn === 1'b1); // start transmit of the control frame
15408
      wait (MTxEn === 1'b0); // end transmit of the control frame
15409
      repeat(10) @ (posedge wb_clk);  // wait some time
15410
      repeat(10) @ (posedge mtx_clk); // wait some time so status is written
15411
      // check interrupts  
15412
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15413
      if(data !== (`ETH_INT_TXC | `ETH_INT_TXB))
15414
      begin
15415
        test_fail("TXC and TXB IRQ should be set!");
15416
        fail = fail + 1;
15417
        `TIME; $display("*E TXC and TXB IRQ should be set! (ETH_INT=0x%0x)", data);
15418
      end
15419
      if (!wb_int)
15420
      begin
15421
        test_fail("WB INT signal should be set!");
15422
        fail = fail + 1;
15423
        `TIME; $display("*E WB INT signal should be set!");
15424
      end
15425
      // Clear TXC and TXB interrupt
15426
      wbm_write(`ETH_INT, `ETH_INT_TXC | `ETH_INT_TXB, 4'hF, 1, 4'h0, 4'h0);
15427
      if (wb_int)
15428
      begin
15429
        test_fail("WB INT signal should not be set!");
15430
        fail = fail + 1;
15431
        `TIME; $display("*E WB INT signal should not be set!");
15432
      end
15433
      if(tmp_len == 64)  // Control frame
15434
        check_tx_packet((`MEMORY_BASE), 0, 32'h100, tmp);
15435
      else
15436
        check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
15437
      if (tmp > 0)
15438
      begin
15439
        $display("Wrong data of the transmitted packet");
15440
        test_fail("Wrong data of the transmitted packet");
15441
        fail = fail + 1;
15442
      end
15443
      // check transmited TX packet CRC
15444
      if(tmp_len == 64)  // Control frame
15445
        #1 check_tx_crc(0, 32'h100, 1'b0, tmp); // length without CRC
15446
      else
15447
        #1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
15448
      if (tmp > 0)
15449
      begin
15450
        $display("Wrong CRC of the transmitted packet");
15451
        test_fail("Wrong CRC of the transmitted packet");
15452
        fail = fail + 1;
15453
      end
15454
    end // for loop
15455
    if(fail == 0)
15456
      test_ok;
15457
    else
15458
      fail = 0;
15459 263 mohor
  end
15460 254 mohor
 
15461 274 tadejm
 
15462 260 mohor
  ////////////////////////////////////////////////////////////////////
15463
  ////                                                            ////
15464 267 mohor
  ////  Receive control frames with PASSALL option turned on and  ////
15465
  ////  off. Using only one RX buffer decriptor ( 10Mbps ).       ////
15466 260 mohor
  ////                                                            ////
15467
  ////////////////////////////////////////////////////////////////////
15468 263 mohor
  if (test_num == 2) // 
15469 260 mohor
  begin
15470 267 mohor
    // TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 10Mbps )
15471
    test_name   = "TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 10Mbps )";
15472
    `TIME; $display("  TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 10Mbps )");
15473 254 mohor
 
15474 260 mohor
    // unmask interrupts
15475
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
15476
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15477
    // set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
15478
    wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15479
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
15480 267 mohor
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
15481 260 mohor
              `ETH_MODER_PRO | `ETH_MODER_BRO,
15482
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15483 263 mohor
    // enable RX_FLOW control
15484
    wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15485 260 mohor
    // prepare one packet of 100 bytes long
15486 267 mohor
//    st_data = 8'h1A;
15487
//    set_rx_packet(64, 100, 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data); 
15488
//    append_rx_crc (64, 100, 1'b0, 1'b0); // CRC for data packet
15489
    st_data = 8'h01;
15490
    set_tx_packet(`MEMORY_BASE + 64, 100, 8'h01); // length without CRC
15491
    set_tx_bd(0, 0, 100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + 64));
15492
    set_tx_bd_wrap(0);
15493 260 mohor
    // check WB INT signal
15494
    if (wb_int !== 1'b0)
15495
    begin
15496
      test_fail("WB INT signal should not be set");
15497
      fail = fail + 1;
15498
    end
15499 274 tadejm
 
15500 260 mohor
    // write to phy's control register for 10Mbps
15501
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
15502
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
15503
    speed = 10;
15504 254 mohor
 
15505 266 mohor
    // RXB and RXC interrupts masked
15506
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXE | `ETH_INT_BUSY |
15507
                             `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15508
    // Test irq logic while RXB and RXC interrupts are masked. IRQ in RxBD is cleared
15509
    for (i=0; i<3; i=i+1)
15510
    begin
15511 274 tadejm
      pause_value = i+2;
15512 267 mohor
      set_rx_control_packet(0, pause_value);  // CRC already appended
15513 266 mohor
      // choose generating carrier sense and collision for first and last 64 lengths of frames
15514
      case (i)
15515
      0: // PASSALL = 0, RXFLOW = 1, IRQ in RxBD = 1
15516
      begin
15517
        PassAll=0; RxFlow=1; enable_irq_in_rxbd=1;
15518
        // enable interrupt generation
15519
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
15520
        // Set PASSALL = 0 and RXFLOW = 0
15521
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15522
      end
15523
      1: // PASSALL = 1, RXFLOW = 0, IRQ in RxBD = 1
15524
      begin
15525
        PassAll=1; RxFlow=0; enable_irq_in_rxbd=1;
15526
        // enable interrupt generation
15527
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
15528
        // Set PASSALL = 0 and RXFLOW = 0
15529
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15530
      end
15531
      2: // PASSALL = 1, RXFLOW = 0, IRQ in RxBD = 0
15532
      begin
15533
        PassAll=1; RxFlow=0; enable_irq_in_rxbd=0;
15534
        // enable interrupt generation
15535
        set_rx_bd(127, 127, 1'b0, `MEMORY_BASE);
15536
        // Set PASSALL = 0 and RXFLOW = 0
15537
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15538
      end
15539
      default:
15540
      begin
15541
        $display("*E We should never get here !!!");
15542
        test_fail("We should never get here !!!");
15543
        fail = fail + 1;
15544
      end
15545
      endcase
15546
      // not detect carrier sense in FD and no collision
15547
      eth_phy.no_carrier_sense_rx_fd_detect(0);
15548
      eth_phy.collision(0);
15549
      // set wrap bit and empty bit
15550
      set_rx_bd_wrap(127);
15551
      set_rx_bd_empty(127, 127);
15552 274 tadejm
      // transmit
15553 266 mohor
      fork
15554
        begin
15555
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, 64, 1'b0);
15556
          repeat(10) @(posedge mrx_clk);
15557
        end
15558
        begin
15559
          wait (MRxDV === 1'b1); // start transmit
15560
          #1 check_rx_bd(127, data);
15561
          if (data[15] !== 1)
15562
          begin
15563
            $display("*E Wrong buffer descriptor's ready bit read out from MAC");
15564
            test_fail("Wrong buffer descriptor's ready bit read out from MAC");
15565
            fail = fail + 1;
15566
          end
15567 267 mohor
          wait (MRxDV === 1'b0); // received pause frame
15568
          repeat(5) @(posedge mrx_clk);  // Wait some time so pause is activated.
15569
          repeat(5) @(posedge mtx_clk);  // Wait some time so pause is activated.
15570
          set_tx_bd_ready(0, 0); // Request sending the data. Data should not be sent when pause frame was received
15571
                                 // and RxFlow enabled.
15572
          // When we exit the while loop, status frame is received
15573
          repeat(`ETH_TX_FIFO_DEPTH) @(eth_ma_wb_ack_i);  // Waiting until TX fifo is filled.
15574
          repeat(10) @(posedge mtx_clk);  // Wait some time for tx start.
15575 266 mohor
        end
15576
      join
15577
      #1 check_rx_bd(127, data);
15578
      // Checking buffer descriptor
15579
      if(PassAll)
15580
      begin
15581
        if(enable_irq_in_rxbd)
15582
        begin
15583
          if(data !== 32'h406100)    // Rx BD must not be marked as EMPTY (control frame is received)
15584
          begin
15585
            $display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
15586
            $display("RxBD = 0x%0x", data);
15587
            test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
15588
            fail = fail + 1;
15589
          end
15590
        end
15591
        else
15592
        begin
15593
          if(data !== 32'h402100)    // Rx BD must not be marked as EMPTY (control frame is received)
15594
          begin
15595
            $display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
15596
            $display("RxBD = 0x%0x", data);
15597
            test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
15598
            fail = fail + 1;
15599
          end
15600
        end
15601
      end
15602
      else
15603
      begin
15604
        if(data !== 32'he000)    // Rx BD must be marked as EMPTY (no packet received)
15605
        begin
15606
          $display("*E Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
15607
          $display("RxBD = 0x%0x", data);
15608
          test_fail("Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
15609
          fail = fail + 1;
15610
        end
15611
      end
15612
      // Checking if interrupt was generated
15613
      if (wb_int)
15614
      begin
15615
        `TIME; $display("*E WB INT signal should not be set because both RXB and RXC interrupts are masked");
15616
        test_fail("WB INT signal should not be set because both RXB and RXC interrupts are masked");
15617
        fail = fail + 1;
15618
      end
15619
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15620
      if(RxFlow)
15621
      begin
15622
        if(data !== (`ETH_INT_RXC))
15623
        begin
15624
          test_fail("RXC is not set or multiple IRQs active!");
15625
          fail = fail + 1;
15626
          `TIME; $display("*E RXC is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
15627
        end
15628
        // Clear RXC interrupt
15629
        wbm_write(`ETH_INT, `ETH_INT_RXC, 4'hF, 1, 4'h0, 4'h0);
15630
      end
15631
      else if(enable_irq_in_rxbd)
15632
      begin
15633
        if(data !== (`ETH_INT_RXB))
15634
        begin
15635
          test_fail("RXB is not set or multiple IRQs active!");
15636
          fail = fail + 1;
15637
          `TIME; $display("*E RXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
15638
        end
15639
        // Clear RXC interrupt
15640
        wbm_write(`ETH_INT, `ETH_INT_RXB, 4'hF, 1, 4'h0, 4'h0);
15641
      end
15642
      else
15643
      begin
15644
        if(data !== 0)
15645
        begin
15646
          test_fail("Some IRQs is active!");
15647
          fail = fail + 1;
15648
          `TIME; $display("*E Some IRQs is active! (ETH_INT=0x%0x)", data);
15649
        end
15650
      end
15651 267 mohor
      if(RxFlow)
15652
        begin
15653
          if(MTxEn)   // If pause frame was received OK, transmission of the data packet should not start
15654
            begin
15655
              `TIME; $display("*E Transmission should not be started because pause frame was received.");
15656
              test_fail("Transmission should not be started because pause frame was received.");
15657
              fail = fail + 1;
15658
            end
15659
          while(pause_value)
15660
            begin
15661
              pause_value=pause_value-1;
15662
              repeat(2*64) @(posedge mtx_clk);  // Wait for the time needed for the pause (1 slot).
15663
              if((!pause_value) && (!MTxEn))        // Transmission should be enabled now.
15664
                begin
15665
                  `TIME; $display("*E Transmission should be started because pause passed.");
15666
                  test_fail("Transmission should be started because pause passed.");
15667
                  fail = fail + 1;
15668
                end
15669
              else if((pause_value) && (MTxEn))     // Transmission should not be enabled now.
15670
                begin
15671
                  `TIME; $display("*E Transmission should still be paused.");
15672
                  test_fail("Transmission should still be paused.");
15673
                  fail = fail + 1;
15674
                end
15675
            end
15676
        end
15677
      else
15678
        begin
15679
          if(!MTxEn)   // Pause frame was not received because RxFlow is turned off.
15680
            begin
15681
              `TIME; $display("*E Transmission should be started because pause frame was not received (RxFlow=0).");
15682
              test_fail("Transmission should be started because pause frame was not received (RxFlow=0).");
15683
              fail = fail + 1;
15684
            end
15685
        end
15686
      wait(wb_int);   // Wait antil frame transmission is over and irq generated
15687
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15688
      if(data !== (`ETH_INT_TXB))
15689
        begin
15690
          test_fail("TXB is not set or multiple IRQs active!");
15691
          fail = fail + 1;
15692
          `TIME; $display("*E TXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
15693
        end
15694
        // Clear TXB interrupt
15695
        wbm_write(`ETH_INT, `ETH_INT_TXB, 4'hF, 1, 4'h0, 4'h0);
15696 266 mohor
    end
15697
    // End: Test is irq is set while RXB and RXC interrupts are masked.
15698
 
15699
    // Now all interrupts are unmasked. Performing tests again.
15700 263 mohor
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
15701
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15702 260 mohor
    for (i=0; i<4; i=i+1)
15703 254 mohor
    begin
15704 267 mohor
      pause_value = i+1;
15705
      set_rx_control_packet(0, pause_value);  // CRC already appended
15706 260 mohor
      // choose generating carrier sense and collision for first and last 64 lengths of frames
15707
      case (i)
15708 263 mohor
      0: // PASSALL = 0, RXFLOW = 0
15709 254 mohor
      begin
15710 263 mohor
        PassAll=0; RxFlow=0;
15711 260 mohor
        // enable interrupt generation
15712 263 mohor
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
15713
        // Set PASSALL = 0 and RXFLOW = 0
15714
        wbm_write(`ETH_CTRLMODER, 0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15715 254 mohor
      end
15716 263 mohor
      1: // PASSALL = 0, RXFLOW = 1
15717 254 mohor
      begin
15718 263 mohor
        PassAll=0; RxFlow=1;
15719 260 mohor
        // enable interrupt generation
15720 263 mohor
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
15721
        // Set PASSALL = 0 and RXFLOW = 0
15722
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15723 254 mohor
      end
15724 263 mohor
      2: // PASSALL = 1, RXFLOW = 0
15725 254 mohor
      begin
15726 263 mohor
        PassAll=1; RxFlow=0;
15727
        // enable interrupt generation
15728
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
15729
        // Set PASSALL = 0 and RXFLOW = 0
15730
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15731 254 mohor
      end
15732 263 mohor
      default: // 3: PASSALL = 1, RXFLOW = 1
15733 254 mohor
      begin
15734 263 mohor
        PassAll=1; RxFlow=1;
15735
        // enable interrupt generation
15736
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
15737
        // Set PASSALL = 1 and RXFLOW = 1
15738
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL | `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15739 254 mohor
      end
15740
      endcase
15741 263 mohor
      // not detect carrier sense in FD and no collision
15742
      eth_phy.no_carrier_sense_rx_fd_detect(0);
15743
      eth_phy.collision(0);
15744
      // set wrap bit and empty bit
15745 260 mohor
      set_rx_bd_wrap(127);
15746
      set_rx_bd_empty(127, 127);
15747 274 tadejm
      // transmit
15748 260 mohor
      fork
15749 254 mohor
        begin
15750 260 mohor
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, 64, 1'b0);
15751
          repeat(10) @(posedge mrx_clk);
15752 254 mohor
        end
15753
        begin
15754 260 mohor
          #1 check_rx_bd(127, data);
15755
          wait (MRxDV === 1'b1); // start transmit
15756 263 mohor
          #1 check_rx_bd(127, data);
15757 260 mohor
          if (data[15] !== 1)
15758
          begin
15759 263 mohor
            $display("*E Wrong buffer descriptor's ready bit read out from MAC");
15760 260 mohor
            test_fail("Wrong buffer descriptor's ready bit read out from MAC");
15761
            fail = fail + 1;
15762
          end
15763
          wait (MRxDV === 1'b0); // end transmit
15764 263 mohor
          repeat(50) @(posedge mrx_clk);  // Wait some time so frame is received and
15765
          repeat (100) @(posedge wb_clk); // status/irq is written.
15766 267 mohor
 
15767
          if(RxFlow)    // Waiting x slot times before continuing so pause is deactivated.
15768
            repeat(64 * 2 * pause_value) @(posedge mrx_clk);
15769 254 mohor
        end
15770 260 mohor
      join
15771 263 mohor
      #1 check_rx_bd(127, data);
15772
      // Checking buffer descriptor
15773
      if(PassAll)
15774 254 mohor
      begin
15775 263 mohor
        if(data !== 32'h406100)    // Rx BD must not be marked as EMPTY (control frame is received)
15776
        begin
15777
          $display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
15778
          $display("RxBD = 0x%0x", data);
15779
          test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
15780
          fail = fail + 1;
15781
        end
15782 254 mohor
      end
15783 260 mohor
      else
15784 254 mohor
      begin
15785 263 mohor
        if(data !== 32'he000)    // Rx BD must be marked as EMPTY (no packet received)
15786
        begin
15787
          $display("*E Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
15788
          $display("RxBD = 0x%0x", data);
15789
          test_fail("Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
15790
          fail = fail + 1;
15791
        end
15792 254 mohor
      end
15793 263 mohor
      // Checking if interrupt was generated
15794
      if(RxFlow || PassAll)
15795 254 mohor
      begin
15796 263 mohor
        if (!wb_int)
15797 254 mohor
        begin
15798
          `TIME; $display("*E WB INT signal should be set");
15799
          test_fail("WB INT signal should be set");
15800
          fail = fail + 1;
15801
        end
15802
      end
15803
      else
15804
      begin
15805 263 mohor
        if (wb_int)
15806 254 mohor
        begin
15807
          `TIME; $display("*E WB INT signal should not be set");
15808
          test_fail("WB INT signal should not be set");
15809
          fail = fail + 1;
15810
        end
15811
      end
15812 274 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15813
      if(RxFlow)
15814
      begin
15815
        if(data !== (`ETH_INT_RXC))
15816
        begin
15817
          test_fail("RXC is not set or multiple IRQs active!");
15818
          fail = fail + 1;
15819
          `TIME; $display("*E RXC is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
15820
        end
15821
        // Clear RXC interrupt
15822
        wbm_write(`ETH_INT, `ETH_INT_RXC, 4'hF, 1, 4'h0, 4'h0);
15823
      end
15824
      else if(PassAll)
15825
      begin
15826
        if(data !== (`ETH_INT_RXB))
15827
        begin
15828
          test_fail("RXB is not set or multiple IRQs active!");
15829
          fail = fail + 1;
15830
          `TIME; $display("*E RXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
15831
        end
15832
        // Clear RXB interrupt
15833
        wbm_write(`ETH_INT, `ETH_INT_RXB, 4'hF, 1, 4'h0, 4'h0);
15834
      end
15835
      else
15836
      begin
15837
        if(data !== 0)
15838
        begin
15839
          test_fail("No interrupt should be set!");
15840
          fail = fail + 1;
15841
          `TIME; $display("*E No interrupt should be set! (ETH_INT=0x%0x)", data);
15842
        end
15843
      end
15844
    end
15845
    // disable RX
15846
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
15847
              `ETH_MODER_PRO | `ETH_MODER_BRO,
15848
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15849
    if(fail == 0)
15850
      test_ok;
15851
    else
15852
      fail = 0;
15853
  end
15854 263 mohor
 
15855 274 tadejm
 
15856
  ////////////////////////////////////////////////////////////////////
15857
  ////                                                            ////
15858
  ////  Receive control frames with PASSALL option turned on and  ////
15859
  ////  off. Using only one RX buffer decriptor ( 100Mbps ).      ////
15860
  ////                                                            ////
15861
  ////////////////////////////////////////////////////////////////////
15862
  if (test_num == 3) // 
15863
  begin
15864
    // TEST 3: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 100Mbps )
15865
    test_name   = "TEST 3: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 100Mbps )";
15866
    `TIME; $display("  TEST 3: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 100Mbps )");
15867
 
15868
    // unmask interrupts
15869
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
15870
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15871
    // set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
15872
    wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15873
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
15874
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
15875
              `ETH_MODER_PRO | `ETH_MODER_BRO,
15876
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15877
    // enable RX_FLOW control
15878
    wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15879
    // prepare one packet of 100 bytes long
15880
//    st_data = 8'h1A;
15881
//    set_rx_packet(64, 100, 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data); 
15882
//    append_rx_crc (64, 100, 1'b0, 1'b0); // CRC for data packet
15883
    st_data = 8'h01;
15884
    set_tx_packet(`MEMORY_BASE + 64, 100, 8'h01); // length without CRC
15885
    set_tx_bd(0, 0, 100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + 64));
15886
    set_tx_bd_wrap(0);
15887
    // check WB INT signal
15888
    if (wb_int !== 1'b0)
15889
    begin
15890
      test_fail("WB INT signal should not be set");
15891
      fail = fail + 1;
15892
    end
15893
 
15894
    // write to phy's control register for 100Mbps
15895
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
15896
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
15897
    speed = 100;
15898
 
15899
    // RXB and RXC interrupts masked
15900
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXE | `ETH_INT_BUSY |
15901
                             `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15902
    // Test irq logic while RXB and RXC interrupts are masked. IRQ in RxBD is cleared
15903
    for (i=0; i<3; i=i+1)
15904
    begin
15905
      pause_value = i+2;
15906
      set_rx_control_packet(0, pause_value);  // CRC already appended
15907
      // choose generating carrier sense and collision for first and last 64 lengths of frames
15908
      case (i)
15909
      0: // PASSALL = 0, RXFLOW = 1, IRQ in RxBD = 1
15910
      begin
15911
        PassAll=0; RxFlow=1; enable_irq_in_rxbd=1;
15912
        // enable interrupt generation
15913
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
15914
        // Set PASSALL = 0 and RXFLOW = 0
15915
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15916
      end
15917
      1: // PASSALL = 1, RXFLOW = 0, IRQ in RxBD = 1
15918
      begin
15919
        PassAll=1; RxFlow=0; enable_irq_in_rxbd=1;
15920
        // enable interrupt generation
15921
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
15922
        // Set PASSALL = 0 and RXFLOW = 0
15923
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15924
      end
15925
      2: // PASSALL = 1, RXFLOW = 0, IRQ in RxBD = 0
15926
      begin
15927
        PassAll=1; RxFlow=0; enable_irq_in_rxbd=0;
15928
        // enable interrupt generation
15929
        set_rx_bd(127, 127, 1'b0, `MEMORY_BASE);
15930
        // Set PASSALL = 0 and RXFLOW = 0
15931
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15932
      end
15933
      default:
15934
      begin
15935
        `TIME; $display("*E We should never get here !!!");
15936
        test_fail("We should never get here !!!");
15937
        fail = fail + 1;
15938
      end
15939
      endcase
15940
      // not detect carrier sense in FD and no collision
15941
      eth_phy.no_carrier_sense_rx_fd_detect(0);
15942
      eth_phy.collision(0);
15943
      // set wrap bit and empty bit
15944
      set_rx_bd_wrap(127);
15945
      set_rx_bd_empty(127, 127);
15946
      // transmit
15947
      fork
15948
        begin
15949
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, 64, 1'b0);
15950
          repeat(10) @(posedge mrx_clk);
15951
        end
15952
        begin
15953
          wait (MRxDV === 1'b1); // start transmit
15954
          #1 check_rx_bd(127, data);
15955
          if (data[15] !== 1)
15956
          begin
15957
            `TIME; $display("*E Wrong buffer descriptor's ready bit read out from MAC");
15958
            test_fail("Wrong buffer descriptor's ready bit read out from MAC");
15959
            fail = fail + 1;
15960
          end
15961
          wait (MRxDV === 1'b0); // received pause frame
15962
          repeat(5) @(posedge mrx_clk);  // Wait some time so pause is activated.
15963
          repeat(5) @(posedge mtx_clk);  // Wait some time so pause is activated.
15964
          set_tx_bd_ready(0, 0); // Request sending the data. Data should not be sent when pause frame was received
15965
                                 // and RxFlow enabled.
15966
          // When we exit the while loop, status frame is received
15967
          repeat(`ETH_TX_FIFO_DEPTH) @(eth_ma_wb_ack_i);  // Waiting until TX fifo is filled.
15968
          repeat(10) @(posedge mtx_clk);  // Wait some time for tx start.
15969
        end
15970
      join
15971
      #1 check_rx_bd(127, data);
15972
      // Checking buffer descriptor
15973
      if(PassAll)
15974
      begin
15975
        if(enable_irq_in_rxbd)
15976
        begin
15977
          if(data !== 32'h406100)    // Rx BD must not be marked as EMPTY (control frame is received)
15978
          begin
15979
            `TIME; $display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
15980
            $display("RxBD = 0x%0x", data);
15981
            test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
15982
            fail = fail + 1;
15983
          end
15984
        end
15985
        else
15986
        begin
15987
          if(data !== 32'h402100)    // Rx BD must not be marked as EMPTY (control frame is received)
15988
          begin
15989
            `TIME; $display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
15990
            $display("RxBD = 0x%0x", data);
15991
            test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
15992
            fail = fail + 1;
15993
          end
15994
        end
15995
      end
15996
      else
15997
      begin
15998
        if(data !== 32'he000)    // Rx BD must be marked as EMPTY (no packet received)
15999
        begin
16000
          `TIME; $display("*E Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
16001
          $display("RxBD = 0x%0x", data);
16002
          test_fail("Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
16003
          fail = fail + 1;
16004
        end
16005
      end
16006
      // Checking if interrupt was generated
16007
      if (wb_int)
16008
      begin
16009
        `TIME; $display("*E WB INT signal should not be set because both RXB and RXC interrupts are masked");
16010
        test_fail("WB INT signal should not be set because both RXB and RXC interrupts are masked");
16011
        fail = fail + 1;
16012
      end
16013 263 mohor
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16014
      if(RxFlow)
16015 254 mohor
      begin
16016 263 mohor
        if(data !== (`ETH_INT_RXC))
16017 254 mohor
        begin
16018 263 mohor
          test_fail("RXC is not set or multiple IRQs active!");
16019 260 mohor
          fail = fail + 1;
16020 263 mohor
          `TIME; $display("*E RXC is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
16021 254 mohor
        end
16022 263 mohor
        // Clear RXC interrupt
16023
        wbm_write(`ETH_INT, `ETH_INT_RXC, 4'hF, 1, 4'h0, 4'h0);
16024 254 mohor
      end
16025 274 tadejm
      else if(enable_irq_in_rxbd)
16026
      begin
16027
        if(data !== (`ETH_INT_RXB))
16028
        begin
16029
          test_fail("RXB is not set or multiple IRQs active!");
16030
          fail = fail + 1;
16031
          `TIME; $display("*E RXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
16032
        end
16033
        // Clear RXC interrupt
16034
        wbm_write(`ETH_INT, `ETH_INT_RXB, 4'hF, 1, 4'h0, 4'h0);
16035
      end
16036
      else
16037
      begin
16038
        if(data !== 0)
16039
        begin
16040
          test_fail("Some IRQs is active!");
16041
          fail = fail + 1;
16042
          `TIME; $display("*E Some IRQs is active! (ETH_INT=0x%0x)", data);
16043
        end
16044
      end
16045
      if(RxFlow)
16046
        begin
16047
          if(MTxEn)   // If pause frame was received OK, transmission of the data packet should not start
16048
            begin
16049
              `TIME; $display("*E Transmission should not be started because pause frame was received.");
16050
              test_fail("Transmission should not be started because pause frame was received.");
16051
              fail = fail + 1;
16052
            end
16053
          while(pause_value)
16054
            begin
16055
              pause_value=pause_value-1;
16056
              repeat(2*64) @(posedge mtx_clk);  // Wait for the time needed for the pause (1 slot).
16057
              if((!pause_value) && (!MTxEn))        // Transmission should be enabled now.
16058
                begin
16059
                  `TIME; $display("*E Transmission should be started because pause passed.");
16060
                  test_fail("Transmission should be started because pause passed.");
16061
                  fail = fail + 1;
16062
                end
16063
              else if((pause_value) && (MTxEn))     // Transmission should not be enabled now.
16064
                begin
16065
                  `TIME; $display("*E Transmission should still be paused.");
16066
                  test_fail("Transmission should still be paused.");
16067
                  fail = fail + 1;
16068
                end
16069
            end
16070
        end
16071
      else
16072
        begin
16073
          if(!MTxEn)   // Pause frame was not received because RxFlow is turned off.
16074
            begin
16075
              `TIME; $display("*E Transmission should be started because pause frame was not received (RxFlow=0).");
16076
              test_fail("Transmission should be started because pause frame was not received (RxFlow=0).");
16077
              fail = fail + 1;
16078
            end
16079
        end
16080
      wait(wb_int);   // Wait antil frame transmission is over and irq generated
16081
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16082
      if(data !== (`ETH_INT_TXB))
16083
        begin
16084
          test_fail("TXB is not set or multiple IRQs active!");
16085
          fail = fail + 1;
16086
          `TIME; $display("*E TXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
16087
        end
16088
        // Clear TXB interrupt
16089
        wbm_write(`ETH_INT, `ETH_INT_TXB, 4'hF, 1, 4'h0, 4'h0);
16090
    end
16091
    // End: Test is irq is set while RXB and RXC interrupts are masked.
16092
 
16093
    // Now all interrupts are unmasked. Performing tests again.
16094
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
16095
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16096
    for (i=0; i<4; i=i+1)
16097
    begin
16098
      pause_value = i+1;
16099
      set_rx_control_packet(0, pause_value);  // CRC already appended
16100
      // choose generating carrier sense and collision for first and last 64 lengths of frames
16101
      case (i)
16102
      0: // PASSALL = 0, RXFLOW = 0
16103
      begin
16104
        PassAll=0; RxFlow=0;
16105
        // enable interrupt generation
16106
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
16107
        // Set PASSALL = 0 and RXFLOW = 0
16108
        wbm_write(`ETH_CTRLMODER, 0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16109
      end
16110
      1: // PASSALL = 0, RXFLOW = 1
16111
      begin
16112
        PassAll=0; RxFlow=1;
16113
        // enable interrupt generation
16114
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
16115
        // Set PASSALL = 0 and RXFLOW = 0
16116
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16117
      end
16118
      2: // PASSALL = 1, RXFLOW = 0
16119
      begin
16120
        PassAll=1; RxFlow=0;
16121
        // enable interrupt generation
16122
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
16123
        // Set PASSALL = 0 and RXFLOW = 0
16124
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16125
      end
16126
      default: // 3: PASSALL = 1, RXFLOW = 1
16127
      begin
16128
        PassAll=1; RxFlow=1;
16129
        // enable interrupt generation
16130
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
16131
        // Set PASSALL = 1 and RXFLOW = 1
16132
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL | `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16133
      end
16134
      endcase
16135
      // not detect carrier sense in FD and no collision
16136
      eth_phy.no_carrier_sense_rx_fd_detect(0);
16137
      eth_phy.collision(0);
16138
      // set wrap bit and empty bit
16139
      set_rx_bd_wrap(127);
16140
      set_rx_bd_empty(127, 127);
16141
      // transmit
16142
      fork
16143
        begin
16144
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, 64, 1'b0);
16145
          repeat(10) @(posedge mrx_clk);
16146
        end
16147
        begin
16148
          #1 check_rx_bd(127, data);
16149
          wait (MRxDV === 1'b1); // start transmit
16150
          #1 check_rx_bd(127, data);
16151
          if (data[15] !== 1)
16152
          begin
16153
            $display("*E Wrong buffer descriptor's ready bit read out from MAC");
16154
            test_fail("Wrong buffer descriptor's ready bit read out from MAC");
16155
            fail = fail + 1;
16156
          end
16157
          wait (MRxDV === 1'b0); // end transmit
16158
          repeat(50) @(posedge mrx_clk);  // Wait some time so frame is received and
16159
          repeat (100) @(posedge wb_clk); // status/irq is written.
16160
 
16161
          if(RxFlow)    // Waiting x slot times before continuing so pause is deactivated.
16162
            repeat(64 * 2 * pause_value) @(posedge mrx_clk);
16163
        end
16164
      join
16165
      #1 check_rx_bd(127, data);
16166
      // Checking buffer descriptor
16167
      if(PassAll)
16168
      begin
16169
        if(data !== 32'h406100)    // Rx BD must not be marked as EMPTY (control frame is received)
16170
        begin
16171
          `TIME; $display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
16172
          $display("RxBD = 0x%0x", data);
16173
          test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
16174
          fail = fail + 1;
16175
        end
16176
      end
16177
      else
16178
      begin
16179
        if(data !== 32'he000)    // Rx BD must be marked as EMPTY (no packet received)
16180
        begin
16181
          `TIME; $display("*E Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
16182
          $display("RxBD = 0x%0x", data);
16183
          test_fail("Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
16184
          fail = fail + 1;
16185
        end
16186
      end
16187
      // Checking if interrupt was generated
16188
 
16189
      if(RxFlow | PassAll)
16190
      begin
16191
        if (!wb_int)
16192
        begin
16193
          `TIME; $display("*E WB INT signal should be set");
16194
          test_fail("WB INT signal should be set");
16195
          fail = fail + 1;
16196
        end
16197
      end
16198
      else
16199
      begin
16200
        if (wb_int)
16201
        begin
16202
          `TIME; $display("*E WB INT signal should not be set");
16203
          test_fail("WB INT signal should not be set");
16204
          fail = fail + 1;
16205
        end
16206
      end
16207
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16208
      if(RxFlow)
16209
      begin
16210
        if(data !== (`ETH_INT_RXC))
16211
        begin
16212
          test_fail("RXC is not set or multiple IRQs active!");
16213
          fail = fail + 1;
16214
          `TIME; $display("*E RXC is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
16215
        end
16216
        // Clear RXC interrupt
16217
        wbm_write(`ETH_INT, `ETH_INT_RXC, 4'hF, 1, 4'h0, 4'h0);
16218
      end
16219 263 mohor
      else if(PassAll)
16220 254 mohor
      begin
16221 263 mohor
        if(data !== (`ETH_INT_RXB))
16222 254 mohor
        begin
16223 263 mohor
          test_fail("RXB is not set or multiple IRQs active!");
16224 254 mohor
          fail = fail + 1;
16225 263 mohor
          `TIME; $display("*E RXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
16226 254 mohor
        end
16227 263 mohor
        // Clear RXB interrupt
16228
        wbm_write(`ETH_INT, `ETH_INT_RXB, 4'hF, 1, 4'h0, 4'h0);
16229 254 mohor
      end
16230
      else
16231
      begin
16232 263 mohor
        if(data !== 0)
16233 254 mohor
        begin
16234 263 mohor
          test_fail("No interrupt should be set!");
16235 254 mohor
          fail = fail + 1;
16236 263 mohor
          `TIME; $display("*E No interrupt should be set! (ETH_INT=0x%0x)", data);
16237 254 mohor
        end
16238
      end
16239
    end
16240 274 tadejm
    // disable RX
16241
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
16242
              `ETH_MODER_PRO | `ETH_MODER_BRO,
16243
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16244
    if(fail == 0)
16245
      test_ok;
16246
    else
16247
      fail = 0;
16248
  end
16249 266 mohor
 
16250 274 tadejm
 
16251
  ////////////////////////////////////////////////////////////////////
16252
  ////                                                            ////
16253
  ////  Receive control frames with PASSALL option turned on and  ////
16254
  ////  off. Using only one RX buffer decriptor ( 10Mbps ).       ////
16255
  ////                                                            ////
16256
  ////////////////////////////////////////////////////////////////////
16257
  if (test_num == 4) // 
16258
  begin
16259
    // TEST 4: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 10Mbps )
16260
    test_name   = "TEST 4: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 10Mbps )";
16261
    `TIME; $display("  TEST 4: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 10Mbps )");
16262
 
16263
    // unmask interrupts
16264
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
16265
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16266
    // set 1 TX and 1 RX buffer descriptor (8'h01) - must be set before RX enable
16267
    wbm_write(`ETH_TX_BD_NUM, 32'h01, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16268
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
16269
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
16270
              `ETH_MODER_PRO | `ETH_MODER_BRO,
16271
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16272
    // enable flow control
16273
 
16274
    wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL | `ETH_CTRLMODER_RXFLOW | `ETH_CTRLMODER_TXFLOW,
16275
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16276
    // prepare one RX and one TX packet of 100 bytes long
16277
    rx_len = 100; // length of frame without CRC
16278
    st_data = 8'h1A;
16279
    set_rx_packet(200, rx_len, 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
16280
    append_rx_crc (200, rx_len, 1'b0, 1'b0); // CRC for data packet
16281
    tx_len = 64; // length of frame without CRC
16282
    st_data = 8'h01;
16283
    set_tx_packet(`MEMORY_BASE + 64, tx_len, st_data); // length without CRC
16284
    // set TX and RX Buffer Descriptors 
16285
    tx_bd_num = 0; // tx BDs go from 0 to 0
16286
    rx_bd_num = 1; // rx BDs go from 1 to 1
16287
    // check WB INT signal
16288
    if (wb_int !== 1'b0)
16289
    begin
16290
      test_fail("WB INT signal should not be set");
16291
      fail = fail + 1;
16292
    end
16293
 
16294
    // set EQUAL mrx_clk to mtx_clk!
16295
//    eth_phy.set_mrx_equal_mtx = 1'b1;
16296 263 mohor
 
16297 274 tadejm
    // write to phy's control register for 10Mbps
16298
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
16299
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
16300
    speed = 10;
16301
 
16302
    // TXB and RXB interrupts masked
16303
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXE | `ETH_INT_RXE | `ETH_INT_BUSY | `ETH_INT_TXC | `ETH_INT_RXC,
16304
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16305
 
16306
    tmp_len = 0;
16307
    num_of_frames = 0;
16308
    num_of_rx_frames = 0;
16309
//    num_of_iter = 0;
16310
    // TX frame loop & RX frame loop work independently
16311
 
16312
 
16313
    fork
16314
      // TX frame loop
16315
      while (num_of_frames < 400)
16316
      begin
16317
        eth_phy.set_tx_mem_addr(64 + num_of_frames);
16318
        // set tx bd
16319
          // wait for WB master if it is working
16320
          @(posedge wb_clk);
16321
          while (wbm_working)
16322
          begin
16323
            @(posedge wb_clk);
16324
          end
16325
        set_tx_bd(0, 0, tx_len, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + 64));
16326
        set_tx_bd_wrap(0);
16327
        set_tx_bd_ready(0, 0);
16328
        check_tx_bd(0, data);
16329
        // check frame
16330
        i = 0;
16331
        while((i < 100) && (MTxEn === 1'b0)) // wait for start of TX frame!
16332
        begin
16333
          @(posedge mtx_clk);
16334
          i = i + 1;
16335
        end
16336
        if (MTxEn != 1'b1)
16337
        begin
16338
          `TIME; $display("*E Tx Frame %0d: MAC TX didn't start transmitting the packet", num_of_frames);
16339
          test_fail("MAC TX didn't start transmitting the packet");
16340
          fail = fail + 1;
16341
          #10000 $stop;
16342
        end
16343
 
16344
        repeat (30) @(posedge mtx_clk); // waiting some time so PHY clears the tx_len
16345
 
16346
        wait ((MTxEn === 1'b0) || (eth_phy.tx_len > (tx_len + 4))) // wait for end of TX frame
16347
        if (MTxEn != 1'b0)
16348
        begin
16349
          `TIME; $display("*E Tx Frame %0d: MAC TX didn't stop transmitting the packet", num_of_frames);
16350
          test_fail("MAC TX didn't stop transmitting the packet");
16351
          fail = fail + 1;
16352
          #10000 $stop;
16353
        end
16354
        tmp_len = eth_phy.tx_len;
16355
          // wait for WB master if it is working
16356
          @(posedge wb_clk);
16357
          while (wbm_working)
16358
          begin
16359
            @(posedge wb_clk);
16360
          end
16361
        check_tx_bd(0, data);
16362
        while (data[15] === 1)
16363
        begin
16364
            // wait for WB master if it is working
16365
            @(posedge wb_clk);
16366
            while (wbm_working)
16367
            begin
16368
              @(posedge wb_clk);
16369
            end
16370
          check_tx_bd(0, data);
16371
        end
16372
        repeat (1) @(posedge wb_clk);
16373
        // check length of a PACKET
16374
        if (tmp_len != (tx_len + 4))
16375
        begin
16376
          `TIME; $display("*E Tx Frame %0d: Wrong length of the packet out from MAC (%0d instead of %0d)", num_of_frames,
16377
                          tmp_len, (tx_len + 4));
16378
          test_fail("Wrong length of the packet out from MAC");
16379
          fail = fail + 1;
16380
        end
16381
        // check transmitted TX packet data
16382
        check_tx_packet((`MEMORY_BASE + 64), (64 + num_of_frames), (tx_len), tmp);
16383
        if (tmp > 0)
16384
        begin
16385
          `TIME; $display("*E Tx Frame %0d: Wrong data of the transmitted packet", num_of_frames);
16386
          test_fail("Wrong data of the transmitted packet");
16387
          fail = fail + 1;
16388
        end
16389
        // check transmited TX packet CRC
16390
        check_tx_crc((64 + num_of_frames), (tx_len), 1'b0, tmp); // length without CRC
16391
        if (tmp > 0)
16392
        begin
16393
          `TIME; $display("*E Tx Frame %0d: Wrong CRC of the transmitted packet", num_of_frames);
16394
          test_fail("Wrong CRC of the transmitted packet");
16395
          fail = fail + 1;
16396
        end
16397
        // check WB INT signal
16398
        if (wb_int !== 1'b0)
16399
        begin
16400
          `TIME; $display("*E Tx Frame %0d: WB INT signal should not be set", num_of_frames);
16401
          test_fail("WB INT signal should not be set");
16402
          fail = fail + 1;
16403
        end
16404
        // check TX buffer descriptor of a packet
16405
          // wait for WB master if it is working
16406
          @(posedge wb_clk);
16407
          while (wbm_working)
16408
          begin
16409
            @(posedge wb_clk);
16410
          end
16411
        check_tx_bd(0, data);
16412
        if (data[15:0] !== 16'h7800)
16413
        begin
16414
          `TIME; $display("*E Tx Frame %0d: TX buffer descriptor status is not correct: %0h", num_of_frames, data[15:0]);
16415
          test_fail("TX buffer descriptor status is not correct");
16416
          fail = fail + 1;
16417
        end
16418
        // check interrupts
16419
          // wait for WB master if it is working
16420
          @(posedge wb_clk);
16421
          while (wbm_working)
16422
          begin
16423
            @(posedge wb_clk);
16424
          end
16425
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16426
        if ((data & `ETH_INT_TXB) !== `ETH_INT_TXB)
16427
        begin
16428
          `TIME; $display("*E Tx Frame %0d: Interrupt Transmit Buffer was not set, interrupt reg: %0h", num_of_frames, data);
16429
          test_fail("Interrupt Transmit Buffer was not set");
16430
          fail = fail + 1;
16431
        end
16432
        if ((data & (~(`ETH_INT_TXB | `ETH_INT_RXB))) !== 0) // RXB might occur at the same time - not error
16433
        begin
16434
          `TIME; $display("*E Tx Frame %0d: Other interrupts (except Tx and Rx Buffer) were set, interrupt reg: %0h",
16435
                          num_of_frames, data);
16436
          test_fail("Other interrupts (except Transmit Buffer) were set");
16437
          fail = fail + 1;
16438
        end
16439
        // clear interrupts (except RXB)
16440
          // wait for WB master if it is working
16441
          @(posedge wb_clk);
16442
          while (wbm_working)
16443
          begin
16444
            @(posedge wb_clk);
16445
          end
16446
        wbm_write(`ETH_INT, (data & (~`ETH_INT_RXB)), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16447
        // check WB INT signal
16448
        if (wb_int !== 1'b0)
16449
        begin
16450
          `TIME; $display("*E Tx Frame %0d: WB INT signal should not be set", num_of_frames);
16451
          test_fail("WB INT signal should not be set");
16452
          fail = fail + 1;
16453
        end
16454
        // Displays
16455
        if (num_of_frames[2:0] == 3'b111)
16456
        begin
16457
          `TIME; $display("   ->8 frames transmitted");
16458
        end
16459
        // set length (loop variable)
16460
        num_of_frames = num_of_frames + 1;
16461
      end // TX frame loop
16462
      // RX frame loop
16463
      while (num_of_rx_frames < 400)
16464
      begin
16465
        // set rx bd
16466
          // wait for WB master if it is working
16467
          @(posedge wb_clk);
16468
          #1;
16469
          while (wbm_working)
16470
          begin
16471
            @(posedge wb_clk);
16472
            #1;
16473
          end
16474
        set_rx_bd(1, 1, 1'b1, (`MEMORY_BASE + 200 + num_of_rx_frames));
16475
        set_rx_bd_wrap(1);
16476
        set_rx_bd_empty(1, 1);
16477
        // check frame
16478
        fork
16479
          begin
16480
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 200, (rx_len + 4), 1'b0);
16481
            repeat(10) @(posedge mrx_clk);
16482
          end
16483
          begin
16484
            wait (MRxDV === 1'b1); // start receive
16485
              // wait for WB master if it is working
16486
              @(posedge wb_clk);
16487
              #1;
16488
              while (wbm_working)
16489
              begin
16490
                @(posedge wb_clk);
16491
                #1;
16492
              end
16493
            check_rx_bd(1, data);
16494
            if (data[15] !== 1)
16495
            begin
16496
              `TIME; $display("*E Rx Frame %0d: Wrong buffer descriptor's ready bit read out from MAC", num_of_rx_frames);
16497
              test_fail("Wrong buffer descriptor's ready bit read out from MAC");
16498
              fail = fail + 1;
16499
            end
16500
            wait (MRxDV === 1'b0); // end receive
16501
 
16502
            while (data[15] === 1)
16503
            begin
16504
                // wait for WB master if it is working
16505
                @(posedge wb_clk);
16506
                #1;
16507
                while (wbm_working)
16508
                begin
16509
                  @(posedge wb_clk);
16510
                  #1;
16511
                end
16512
              check_rx_bd(1, data);
16513
            end
16514
            repeat (1) @(posedge wb_clk);
16515
          end
16516
        join
16517
        // check length of a PACKET
16518
 
16519
        // Additional read because simulator was not working OK.
16520
        // wait for WB master if it is working
16521
        @(posedge wb_clk);
16522
        #1;
16523
        while (wbm_working)
16524
        begin
16525
          @(posedge wb_clk);
16526
          #1;
16527
        end
16528
        check_rx_bd(1, data);
16529
 
16530
        if (data[31:16] != (rx_len + 4))
16531
        begin
16532
          `TIME; $display("*E Rx Frame %0d: Wrong length of the packet written to MAC's register (%0d instead of %0d)",
16533
                          num_of_rx_frames, data[31:16], (rx_len + 4));
16534
          test_fail("Wrong length of the packet out from PHY");
16535
          fail = fail + 1;
16536
        end
16537
        // check received RX packet data and CRC
16538
        check_rx_packet(200, (`MEMORY_BASE + 200 + num_of_rx_frames), (rx_len + 4), 1'b0, 1'b0, tmp);
16539
        if (tmp > 0)
16540
        begin
16541
          `TIME; $display("*E Rx Frame %0d: Wrong data of the received packet", num_of_rx_frames);
16542
          test_fail("Wrong data of the received packet");
16543
          fail = fail + 1;
16544
        end
16545
        // check WB INT signal
16546
        if (wb_int !== 1'b0)
16547
        begin
16548
          `TIME; $display("*E Rx Frame %0d: WB INT signal should not be set", num_of_rx_frames);
16549
          test_fail("WB INT signal should not be set");
16550
          fail = fail + 1;
16551
        end
16552
        // check RX buffer descriptor of a packet
16553
          // wait for WB master if it is working
16554
          @(posedge wb_clk);
16555
          #1;
16556
          while (wbm_working)
16557
          begin
16558
            @(posedge wb_clk);
16559
            #1;
16560
          end
16561
        check_rx_bd(1, data);
16562
        if (data[15:0] !== 16'h6080)
16563
        begin
16564
          `TIME; $display("*E Rx Frame %0d: RX buffer descriptor status is not correct: %0h", num_of_rx_frames, data[15:0]);
16565
          test_fail("RX buffer descriptor status is not correct");
16566
          fail = fail + 1;
16567
        end
16568
        // check interrupts
16569
          // wait for WB master if it is working
16570
          @(posedge wb_clk);
16571
          #1;
16572
          while (wbm_working)
16573
          begin
16574
            @(posedge wb_clk);
16575
            #1;
16576
          end
16577
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16578
 
16579
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
16580
        begin
16581
          `TIME; $display("*E Rx Frame %0d: Interrupt Receive Buffer was not set, interrupt reg: %0h",
16582
                          num_of_rx_frames, data);
16583
          test_fail("Interrupt Receive Buffer was not set");
16584
          fail = fail + 1;
16585
        end
16586
        if ((data & (~(`ETH_INT_RXB | `ETH_INT_TXB))) !== 0) // TXB might occur at the same time - not error
16587
        begin
16588
          `TIME; $display("*E Rx Frame %0d: Other interrupts (except Rx and Tx Buffer) were set, interrupt reg: %0h",
16589
                          num_of_rx_frames, data);
16590
          test_fail("Other interrupts (except Receive Buffer) were set");
16591
          fail = fail + 1;
16592
        end
16593
        // clear interrupts (except TXB)
16594
          // wait for WB master if it is working
16595
          @(posedge wb_clk);
16596
          #1;
16597
          while (wbm_working)
16598
          begin
16599
            @(posedge wb_clk);
16600
            #1;
16601
          end
16602
        wbm_write(`ETH_INT, (data & (~`ETH_INT_TXB)), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16603
        // check WB INT signal
16604
        if (wb_int !== 1'b0)
16605
        begin
16606
          `TIME; $display("*E Rx Frame %0d: WB INT signal should not be set", num_of_rx_frames);
16607
          test_fail("WB INT signal should not be set");
16608
          fail = fail + 1;
16609
        end
16610
        // Displays
16611
        if (num_of_rx_frames[2:0] == 3'b111)
16612
        begin
16613
          `TIME; $display("   ->8 frames received");
16614
        end
16615
        // set length (loop variable)
16616
        num_of_rx_frames = num_of_rx_frames + 1;
16617
      end // RX frame loop
16618
    join
16619
    // disable TX & RX
16620
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_PAD | `ETH_MODER_CRCEN |
16621
              `ETH_MODER_IFG | `ETH_MODER_PRO | `ETH_MODER_BRO,
16622
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16623
    // set DIFFERENT mrx_clk to mtx_clk!
16624
//    eth_phy.set_mrx_equal_mtx = 1'b0;
16625
    if(fail == 0)
16626
      test_ok;
16627
    else
16628
      fail = 0;
16629
  end
16630
 
16631
end   //  for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
16632
 
16633
end
16634
endtask // test_mac_full_duplex_flow_control
16635
 
16636
 
16637
task test_mac_half_duplex_flow;
16638
  input  [31:0]  start_task;
16639
  input  [31:0]  end_task;
16640
  integer        bit_start_1;
16641
  integer        bit_end_1;
16642
  integer        bit_start_2;
16643
  integer        bit_end_2;
16644
  integer        num_of_reg;
16645
  integer        num_of_frames;
16646
  integer        num_of_bd;
16647
  integer        num_of_iter;
16648
  integer        i_addr;
16649
  integer        i_data;
16650
  integer        i_length;
16651
  integer        tmp_len;
16652
  integer        tmp_bd;
16653
  integer        tmp_bd_num;
16654
  integer        tmp_data;
16655
  integer        tmp_ipgt;
16656
  integer        test_num;
16657
  reg    [31:0]  tx_bd_num;
16658
  reg    [31:0]  rx_bd_num;
16659
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
16660
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
16661
  integer        i;
16662
  integer        i1;
16663
  integer        i2;
16664
  integer        i3;
16665
  integer        fail;
16666
  integer        speed;
16667
  integer        mac_hi_addr;
16668
  integer        mac_lo_addr;
16669
  reg            frame_started;
16670
  reg            frame_ended;
16671
  reg            check_rx_frame;
16672
  reg            wait_for_tx_frame;
16673
  reg    [31:0]  addr;
16674
  reg    [31:0]  data;
16675
  reg    [31:0]  tmp;
16676
  reg    [ 7:0]  st_data;
16677
  reg    [15:0]  max_tmp;
16678
  reg    [15:0]  min_tmp;
16679
begin
16680
// MAC HALF DUPLEX FLOW TEST
16681
test_heading("MAC HALF DUPLEX FLOW TEST");
16682
$display(" ");
16683
$display("MAC HALF DUPLEX FLOW TEST");
16684
fail = 0;
16685
 
16686
// reset MAC registers
16687
hard_reset;
16688
// reset MAC and MII LOGIC with soft reset
16689
//reset_mac;
16690
//reset_mii;
16691
// set wb slave response
16692
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
16693
 
16694
  /*
16695
  TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
16696
  -------------------------------------------------------------------------------------
16697
  set_tx_bd
16698
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0], len[15:0], irq, pad, crc, txpnt[31:0]);
16699
  set_tx_bd_wrap
16700
    (tx_bd_num_end[6:0]);
16701
  set_tx_bd_ready
16702
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
16703
  check_tx_bd
16704
    (tx_bd_num_start[6:0], tx_bd_status[31:0]);
16705
  clear_tx_bd
16706
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
16707
 
16708
  TASKS for set and control RX buffer descriptors:
16709
  ------------------------------------------------
16710
  set_rx_bd
16711
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0], irq, rxpnt[31:0]);
16712
  set_rx_bd_wrap
16713
    (rx_bd_num_end[6:0]);
16714
  set_rx_bd_empty
16715
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
16716
  check_rx_bd
16717
    (rx_bd_num_end[6:0], rx_bd_status);
16718
  clear_rx_bd
16719
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
16720
 
16721
  TASKS for set and check TX packets:
16722
  -----------------------------------
16723
  set_tx_packet
16724
    (txpnt[31:0], len[15:0], eth_start_data[7:0]);
16725
  check_tx_packet
16726
    (txpnt_wb[31:0], txpnt_phy[31:0], len[15:0], failure[31:0]);
16727
 
16728
  TASKS for set and check RX packets:
16729
  -----------------------------------
16730
  set_rx_packet
16731
    (rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
16732
  check_rx_packet
16733
    (rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
16734
 
16735
  TASKS for append and check CRC to/of TX packet:
16736
  -----------------------------------------------
16737
  append_tx_crc
16738
    (txpnt_wb[31:0], len[15:0], negated_crc);
16739
  check_tx_crc
16740
    (txpnt_phy[31:0], len[15:0], negated_crc, failure[31:0]);
16741
 
16742
  TASK for append CRC to RX packet (CRC is checked together with check_rx_packet):
16743
  --------------------------------------------------------------------------------
16744
  append_rx_crc
16745
    (rxpnt_phy[31:0], len[15:0], plus_nibble, negated_crc);
16746
  */
16747
 
16748
//////////////////////////////////////////////////////////////////////
16749
////                                                              ////
16750
////  test_mac_half_duplex_flow:                                  ////
16751
////                                                              ////
16752
////  0: Test                                                     ////
16753
////                                                              ////
16754
//////////////////////////////////////////////////////////////////////
16755
 
16756
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
16757
begin
16758
 
16759
  ////////////////////////////////////////////////////////////////////
16760
  ////                                                            ////
16761
  ////  Test collision and late collision while transmitting and  ////
16762
  ////  receiving normal frames. Using 4 TX and RX buffer         ////
16763
  ////  decriptors ( 10Mbps ).                                    ////
16764
  ////                                                            ////
16765
  ////////////////////////////////////////////////////////////////////
16766
  if (test_num == 0) // 
16767
  begin
16768
    // TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )
16769
    //         
16770
    test_name = "TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )";
16771
    `TIME; $display("  TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )");
16772
 
16773
    // reset MAC completely
16774
    hard_reset;
16775
    // set wb slave response
16776
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
16777
 
16778
    max_tmp = 0;
16779
    min_tmp = 0;
16780
    // set 4 TX buffer descriptors (4 TX and 4 RX BDs will be used) - must be set before TX/RX enable
16781
    wait (wbm_working == 0);
16782
    wbm_write(`ETH_TX_BD_NUM, 32'h4, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16783
    // enable TX and RX, set half-duplex mode, receive small, NO correct IFG
16784
    wait (wbm_working == 0);
16785
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_RXEN | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
16786
              `ETH_MODER_PRO | `ETH_MODER_BRO,
16787
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16788
    // prepare two packets of MAXFL length for TX and RX
16789
    wait (wbm_working == 0);
16790
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16791
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
16792
    min_tmp = tmp[31:16];
16793
    st_data = 8'h17;
16794
    set_rx_packet(0, (min_tmp), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
16795
    append_rx_crc (0, (min_tmp), 1'b0, 1'b0);
16796
    st_data = 8'h92;
16797
    set_tx_packet(`MEMORY_BASE, (min_tmp), st_data); // length without CRC
16798
    append_tx_crc (`MEMORY_BASE, (min_tmp), 1'b0);
16799
 
16800
    // check WB INT signal
16801
    if (wb_int !== 1'b0)
16802
    begin
16803
      test_fail("WB INT signal should not be set");
16804
      fail = fail + 1;
16805
    end
16806
    // unmask interrupts
16807
    wait (wbm_working == 0);
16808
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
16809
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16810
 
16811
    // write to phy's control register for 10Mbps
16812
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
16813
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
16814
    speed = 10;
16815
 
16816
    // set TX and RX Buffer Descriptors 
16817
    tx_bd_num = 0; // tx BDs go from 0 to 3
16818
    rx_bd_num = 4; // rx BDs go from 4 to 7
16819
    set_tx_bd(0, 3, i_length[15:0], 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
16820
    set_tx_bd_wrap(3);
16821
    set_rx_bd(4, 7, 1'b1, `MEMORY_BASE);
16822
    set_rx_bd_wrap(7);
16823
    set_rx_bd_empty(4, 7);
16824
 
16825
//    frame_ended = 0;
16826
    tmp_len = 0;
16827
    num_of_frames = 0;// 0; // 10;
16828
    num_of_iter = 0;
16829
//    num_of_bd = 0;
16830
//    i_length = 0;// (0 - 4); // 6; // 4 less due to CRC
16831
    while (num_of_frames < 80)
16832
    begin
16833
      // change COLLVALID bits in COLLCONF register
16834
      if ((num_of_frames == 0) && (num_of_iter == 0))
16835
      begin
16836
        wait (wbm_working == 0);
16837
        wbm_read(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16838
        tmp[5:0] = 6'h00; // 6'b00_0000 ->  0 + 1 =  1 byte from preamble
16839
        wait (wbm_working == 0);
16840
        wbm_write(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16841
        $display("    Collision window is set to 1 byte after preamble and SFD");
16842
      end
16843
      else if ((num_of_frames == 0) && (num_of_iter == 1))
16844
      begin
16845
        wait (wbm_working == 0);
16846
        wbm_read(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16847
        tmp[5:0] = 6'h15; // 6'b01_0101 -> 21 + 1 = 22 bytes from preamble
16848
        wait (wbm_working == 0);
16849
        wbm_write(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16850
        $display("    Collision window is set to 22 bytes after preamble and SFD");
16851
      end
16852
      else if ((num_of_frames == 0) && (num_of_iter == 2))
16853
      begin
16854
        wait (wbm_working == 0);
16855
        wbm_read(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16856
        tmp[5:0] = 6'h2A; // 6'b10_1010 -> 42 + 1 = 43 bytes from preamble
16857
        wait (wbm_working == 0);
16858
        wbm_write(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16859
        $display("    Collision window is set to 43 bytes after preamble and SFD");
16860
      end
16861
      else if ((num_of_frames == 0) && (num_of_iter == 3))
16862
      begin
16863
        wait (wbm_working == 0);
16864
        wbm_read(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16865
        tmp[5:0] = 6'h3F; // 6'b11_1111 -> 63 + 1 = 64 bytes from preamble
16866
        wait (wbm_working == 0);
16867
        wbm_write(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16868
        $display("    Collision window is set to 64 bytes after preamble and SFD");
16869
      end
16870
 
16871
 
16872
//wire          MRxDV;    // This goes to PHY
16873
//wire          MRxErr;   // This goes to PHY
16874
//wire          MColl;    // This goes to PHY
16875
//wire          MCrs;     // This goes to PHY
16876
//wire          MTxEn;
16877
//wire          MTxErr;
16878
      // CHECK END OF RECEIVE WHILE TRANSMITTING
16879
      frame_ended = 0;
16880
      check_rx_frame = 0;
16881
      fork
16882
        // send frames
16883
        begin // start with RX frame
16884
          repeat(num_of_frames) @(posedge mrx_clk);
16885
          #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (min_tmp + 4), 1'b0);
16886
          repeat(10) @(posedge mrx_clk);
16887
        end
16888
        begin // start with TX frame 
16889
          repeat(2) @(posedge mrx_clk);
16890
          repeat(2) @(posedge wb_clk);
16891
          #1 set_tx_bd_ready(tx_bd_num, tx_bd_num);
16892
        end
16893
        // observe TX Enable, Carrier Sense and Collision - TX frame is not repeated after Late Collision
16894
        begin
16895
          wait (MCrs || MTxEn);
16896
          #1;
16897
          if ((MCrs == 1'b1) && (MTxEn == 1'b0)) // defer TX due to Carrier Sense
16898
            wait_for_tx_frame = 1'b1; // wait for retransmission of TX frame
16899
          else
16900
          begin
16901
            i = 0;
16902
            while (MColl == 1'b0) // wait for Collision to occure
16903
            begin
16904
              repeat(2) @(posedge mtx_clk); // counting bytes
16905
              #1 i = i + 1'b1;
16906
            end
16907
            i = i - 8; // subtract preamble and SFD (bytes) - Late Collision is measured from SFD!
16908
            tmp_len = eth_phy.tx_len; // without preamble and SFD (bytes)
16909
            //wait (MTxEn == 1'b0); // wait for TX frame to end
16910
            repeat(10) @(posedge mrx_clk);
16911
            repeat(8) @(posedge wb_clk);
16912
            #1 check_tx_bd(tx_bd_num, data);
16913
            if (data[15] === 0) // if transmit is aborted, then it was Late Collision
16914
            begin
16915
              wait_for_tx_frame = 1'b0; // don't wait for retransmission of TX frame
16916
              $display("    ->Late Collision occured on %0d. byte after frame and SFD", i);
16917
            end
16918
            else
16919
              wait_for_tx_frame = 1'b1; // wait for retransmission of TX frame
16920
          end
16921
        end
16922
        // check if RX frame is accepted
16923
        begin
16924
          wait (MRxDV === 1'b1); // start receive
16925
          wait (MRxDV === 1'b0); // end receive
16926
          repeat(10) @(posedge mrx_clk);
16927
          repeat(8) @(posedge wb_clk);
16928
          #1 check_rx_bd(rx_bd_num, data);
16929
          if (data[15] === 0)
16930
          begin
16931
            check_rx_frame = 1'b1; // RX frame accepted and must be checked
16932
            if ((i + 8) == 0) // add preamble and SFD length (bytes)
16933
              $display("    ->RX frame, which started before or at beginning of TX frame, was accepted");
16934
            else
16935
              $display("    ->RX frame, which started %0d byte(s) after beginning of TX frame, was accepted", (i + 8));
16936
          end
16937
          else
16938
            check_rx_frame = 1'b0; // RX frame rejected
16939
          repeat(1) @(posedge wb_clk);
16940
        end
16941
      join
16942
 
16943
 
16944
 
16945
      // check length of a PACKET
16946
      if ( ((data[31:16] != (i_length + 4)) && (num_of_frames >= 3)) ||
16947
           ((data[31:16] != 0) && (num_of_frames < 3)) )
16948
      begin
16949
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
16950
                        data[31:16], (i_length + 4));
16951
        test_fail("Wrong length of the packet out from PHY");
16952
        fail = fail + 1;
16953
      end
16954
      // check received RX packet data and CRC
16955
//if ((num_of_frames == 5))
16956
//begin                                           // CRC has 4 bytes for itself
16957
//  if (i_length[0] == 1'b1)
16958
//  begin
16959
//    check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
16960
//  end
16961
//  else
16962
//  begin
16963
//    check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
16964
//  end
16965
//  if (tmp > 0)
16966
//  begin
16967
//    `TIME; $display("*E Wrong data of the received packet");
16968
//    test_fail("Wrong data of the received packet");
16969
//    fail = fail + 1;
16970
//  end
16971
//end
16972
//else
16973
//if ((num_of_frames == 10))
16974
//begin                                           // CRC has 4 bytes for itself
16975
//  if (i_length[0] == 1'b1)
16976
//  begin
16977
//    check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
16978
//  end
16979
//  else
16980
//  begin
16981
//    check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
16982
//  end
16983
//  if (tmp > 0)
16984
//  begin
16985
//    `TIME; $display("*E Wrong data of the received packet");
16986
//    test_fail("Wrong data of the received packet");
16987
//    fail = fail + 1;
16988
//  end
16989
//end
16990
//else
16991
      if ((frame_ended == 1) && (num_of_frames >= 5)) // 5 bytes is minimum size without CRC error, since
16992
      begin                                           // CRC has 4 bytes for itself
16993
        if (i_length[0] == 1'b0)
16994
        begin
16995
          check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
16996
        end
16997
        else
16998
        begin
16999
          check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
17000
        end
17001
        if (tmp > 0)
17002
        begin
17003
          `TIME; $display("*E Wrong data of the received packet");
17004
          test_fail("Wrong data of the received packet");
17005
          fail = fail + 1;
17006
        end
17007
      end
17008
 
17009
      // check WB INT signal
17010
      if (num_of_frames >= 3) // Frames smaller than 3 are not received.
17011
      begin                   // Frames greater then 5 always cause an interrupt (Frame received)
17012
        if (wb_int !== 1'b1)  // Frames with length 3 or 4 always cause an interrupt (CRC error)
17013
        begin
17014
          `TIME; $display("*E WB INT signal should be set");
17015
          test_fail("WB INT signal should be set");
17016
          fail = fail + 1;
17017
        end
17018
      end
17019
      else
17020
      begin
17021
        if (wb_int !== 1'b0)
17022
        begin
17023
          `TIME; $display("*E WB INT signal should not be set");
17024
          test_fail("WB INT signal should not be set");
17025
          fail = fail + 1;
17026
        end
17027
      end
17028
 
17029
      // check RX buffer descriptor of a packet
17030
      if (num_of_frames >= min_tmp)
17031
      begin
17032
        if ( (data[15:0] !== 16'h6000) && // wrap bit
17033
             (data[15:0] !== 16'h4000) ) // without wrap bit
17034
        begin
17035
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
17036
          test_fail("RX buffer descriptor status is not correct");
17037
          fail = fail + 1;
17038
        end
17039
      end
17040
      else if (num_of_frames > 4)
17041
      begin
17042
        if ( (data[15:0] !== 16'h6004) && // wrap bit
17043
             (data[15:0] !== 16'h4004) ) // without wrap bit
17044
        begin
17045
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
17046
          test_fail("RX buffer descriptor status is not correct");
17047
          fail = fail + 1;
17048
        end
17049
      end
17050
      else if (num_of_frames > 2)
17051
      begin
17052
        if ( (data[15:0] !== 16'h6006) && // wrap bit
17053
             (data[15:0] !== 16'h4006) ) // without wrap bit
17054
        begin
17055
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
17056
          test_fail("RX buffer descriptor status is not correct");
17057
          fail = fail + 1;
17058
        end
17059
      end
17060
      else
17061
      begin
17062
        if (data[15] !== 1'b1)
17063
        begin
17064
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
17065
          test_fail("RX buffer descriptor status is not correct");
17066
          fail = fail + 1;
17067
        end
17068
      end
17069
      // check interrupts
17070
      wait (wbm_working == 0);
17071
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17072
      if (num_of_frames >= 5)
17073
      begin
17074
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
17075
        begin
17076
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
17077
          test_fail("Interrupt Receive Buffer was not set");
17078
          fail = fail + 1;
17079
        end
17080
        if ((data & (~`ETH_INT_RXB)) !== 0)
17081
        begin
17082
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
17083
          test_fail("Other interrupts (except Receive Buffer) were set");
17084
          fail = fail + 1;
17085
        end
17086
      end
17087
      else if ((num_of_frames < 3)) // Frames smaller than 3 are not received.
17088
      begin
17089
        if (data) // Checking if any interrupt is pending)
17090
        begin
17091
          `TIME; $display("*E Interrupt(s) is(are) pending although frame was ignored, interrupt reg: %0h", data);
17092
          test_fail("Interrupts were set");
17093
          fail = fail + 1;
17094
        end
17095
      end
17096
      else
17097
      begin
17098
        if ((data & `ETH_INT_RXE) !== `ETH_INT_RXE)
17099
        begin
17100
          `TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
17101
          test_fail("Interrupt Receive Buffer Error was not set");
17102
          fail = fail + 1;
17103
        end
17104
        if ((data & (~`ETH_INT_RXE)) !== 0)
17105
        begin
17106
          `TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
17107
          test_fail("Other interrupts (except Receive Buffer Error) were set");
17108
          fail = fail + 1;
17109
        end
17110
      end
17111
      // clear interrupts
17112
      wait (wbm_working == 0);
17113
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17114
      // check WB INT signal
17115
      if (wb_int !== 1'b0)
17116
      begin
17117
        test_fail("WB INT signal should not be set");
17118
        fail = fail + 1;
17119
      end
17120
      // INTERMEDIATE DISPLAYS
17121
      if (num_of_frames == 3)
17122
      begin
17123
        $display("    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
17124
        $display("    ->packets with lengths from %0d to %0d are not received (length increasing by 1 byte)",
17125
                 0, 3);
17126
      end
17127
      else if (num_of_frames == 9)
17128
      begin
17129
        $display("    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
17130
        $display("    ->packet with length 4 is not received (length increasing by 1 byte)");
17131
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
17132
                 5, 9);
17133
      end
17134
      else if (num_of_frames == 17)
17135
      begin
17136
        $display("    using 4 BDs out of 8 BDs (120..127) assigned to RX (wrap at 4th BD - RX BD 123)");
17137
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
17138
                 10, 17);
17139
      end
17140
      else if (num_of_frames == 27)
17141
      begin
17142
        $display("    using 5 BDs out of 8 BDs (120..127) assigned to RX (wrap at 5th BD - RX BD 124)");
17143
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
17144
                 18, 27);
17145
      end
17146
      else if (num_of_frames == 40)
17147
      begin
17148
        $display("    using 6 BDs out of 8 BDs (120..127) assigned to RX (wrap at 6th BD - RX BD 125)");
17149
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
17150
                 28, 40);
17151
      end
17152
      else if (num_of_frames == 54)
17153
      begin
17154
        $display("    using 7 BDs out of 8 BDs (120..127) assigned to RX (wrap at 7th BD - RX BD 126)");
17155
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
17156
                 41, 54);
17157
      end
17158
      else if (num_of_frames == 69)
17159
      begin
17160
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
17161
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
17162
                 55, 69);
17163
      end
17164
      else if (num_of_frames == 69)
17165
      begin
17166
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
17167
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
17168
                 55, 69);
17169
      end
17170
      else if (num_of_frames == 77)
17171
      begin
17172
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
17173
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
17174
                 70, 77);
17175
      end
17176
      // set length (loop variable)
17177
      i_length = i_length + 1;
17178
      // the number of frame transmitted
17179
      num_of_frames = num_of_frames + 1;
17180
      if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
17181
          (num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
17182
          (num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
17183
          (num_of_frames == 54) || (num_of_frames == 62) || (num_of_frames == 70))
17184
        num_of_bd = 120;
17185
      else
17186
        num_of_bd = num_of_bd + 1;
17187
    end
17188 260 mohor
    // disable RX
17189 274 tadejm
    wait (wbm_working == 0);
17190
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
17191
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17192
    @(posedge wb_clk);
17193
    if(fail == 0)
17194
      test_ok;
17195
    else
17196
      fail = 0;
17197
  end
17198
 
17199
 
17200
  ////////////////////////////////////////////////////////////////////
17201
  ////                                                            ////
17202
  ////  Receive control frames with PASSALL option turned off     ////
17203
  ////  Using only one RX buffer decriptor ( 10Mbps ).            ////
17204
  ////                                                            ////
17205
  ////////////////////////////////////////////////////////////////////
17206
  if (test_num == 1) // 
17207
  begin
17208
    // TEST 1: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps )
17209
    test_name   = "TEST 1: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps )";
17210
    `TIME; $display("  TEST 1: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps )");
17211
 
17212
    // unmask interrupts
17213
    wait (wbm_working == 0);
17214
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
17215
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17216
    // set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
17217
    wait (wbm_working == 0);
17218
    wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17219
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
17220
    wait (wbm_working == 0);
17221
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
17222
              `ETH_MODER_PRO | `ETH_MODER_BRO,
17223
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17224
    // prepare one control (PAUSE)packet
17225
    st_data = 8'h00;
17226
    set_rx_packet(0, 60, 1'b0, 48'h0180_c200_0001, 48'h0708_090A_0B0C, 16'h8808, st_data); // length without CRC
17227
    // prepare one packet of 100 bytes long
17228
    st_data = 8'h1A;
17229
    set_rx_packet(64, 100, 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
17230
    // check WB INT signal
17231
    if (wb_int !== 1'b0)
17232
    begin
17233
      test_fail("WB INT signal should not be set");
17234
      fail = fail + 1;
17235
    end
17236
 
17237
    // write to phy's control register for 10Mbps
17238
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
17239
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
17240
    speed = 10;
17241
 
17242
    for (i=0; i<4; i=i+1)
17243
    begin
17244
      // choose generating carrier sense and collision for first and last 64 lengths of frames
17245
      case (i)
17246
      0: // Interrupt is generated
17247
      begin
17248
        // enable interrupt generation
17249
        set_rx_bd(127, 127, 1'b1, (`MEMORY_BASE + i));
17250
        // unmask interrupts
17251
        wait (wbm_working == 0);
17252
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
17253
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17254
        // not detect carrier sense in FD and no collision
17255
        eth_phy.no_carrier_sense_rx_fd_detect(0);
17256
        eth_phy.collision(0);
17257
      end
17258
      1: // Interrupt is not generated
17259
      begin
17260
        // enable interrupt generation
17261
        set_rx_bd(127, 127, 1'b1, ((`MEMORY_BASE + i) + 64));
17262
        // mask interrupts
17263
        wait (wbm_working == 0);
17264
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17265
        // detect carrier sense in FD and no collision
17266
        eth_phy.no_carrier_sense_rx_fd_detect(1);
17267
        eth_phy.collision(0);
17268
      end
17269
      2: // Interrupt is not generated
17270
      begin
17271
        // disable interrupt generation
17272
        set_rx_bd(127, 127, 1'b0, (`MEMORY_BASE + i));
17273
        // unmask interrupts
17274
        wait (wbm_working == 0);
17275
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
17276
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17277
        // not detect carrier sense in FD and set collision
17278
        eth_phy.no_carrier_sense_rx_fd_detect(0);
17279
        eth_phy.collision(1);
17280
      end
17281
      default: // 3: // Interrupt is not generated
17282
      begin
17283
        // disable interrupt generation
17284
        set_rx_bd(127, 127, 1'b0, ((`MEMORY_BASE + i) + 64));
17285
        // mask interrupts
17286
        wait (wbm_working == 0);
17287
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17288
        // detect carrier sense in FD and set collision
17289
        eth_phy.no_carrier_sense_rx_fd_detect(1);
17290
        eth_phy.collision(1);
17291
      end
17292
      endcase
17293
 
17294
      append_rx_crc (64, 100, 1'b0, 1'b0); // To the second (data) packet
17295
      // set wrap bit
17296
      set_rx_bd_wrap(127);
17297
      set_rx_bd_empty(127, 127);
17298
      fork
17299
        begin
17300
          if (i[0] == 1'b0)
17301
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, 64, 1'b0);
17302
          else
17303
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 64, 104, 1'b0);
17304
          repeat(10) @(posedge mrx_clk);
17305
$display("1111");
17306
        end
17307
        begin
17308
          #1 check_rx_bd(127, data);
17309
$display("aaaa");
17310
          wait (MRxDV === 1'b1); // start transmit
17311
$display("bbbb");
17312
          #1 check_rx_bd(127, data);
17313
          if (data[15] !== 1)
17314
          begin
17315
            test_fail("Wrong buffer descriptor's ready bit read out from MAC");
17316
            fail = fail + 1;
17317
          end
17318
          wait (MRxDV === 1'b0); // end transmit
17319
$display("cccc");
17320
          while (data[15] === 1)
17321
          begin
17322
            #1 check_rx_bd(127, data);
17323
            @(posedge wb_clk);
17324
          end
17325
          repeat (1) @(posedge wb_clk);
17326
$display("2222");
17327
        end
17328
      join
17329
$display("dddd");
17330
      // check length of a PACKET
17331
      if (data[31:16] != (i_length + 4))
17332
      begin
17333
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
17334
                        data[31:16], (i_length + 4));
17335
        test_fail("Wrong length of the packet out from PHY");
17336
        fail = fail + 1;
17337
      end
17338
      // checking in the following if statement is performed only for first and last 64 lengths
17339
      // check received RX packet data and CRC
17340
      if (i_length[0] == 1'b0)
17341
      begin
17342
        check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
17343
      end
17344
      else
17345
      begin
17346
        check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
17347
      end
17348
      if (tmp > 0)
17349
      begin
17350
        `TIME; $display("*E Wrong data of the received packet");
17351
        test_fail("Wrong data of the received packet");
17352
        fail = fail + 1;
17353
      end
17354
      // check WB INT signal
17355
      if (i_length[1:0] == 2'h0)
17356
      begin
17357
        if (wb_int !== 1'b1)
17358
        begin
17359
          `TIME; $display("*E WB INT signal should be set");
17360
          test_fail("WB INT signal should be set");
17361
          fail = fail + 1;
17362
        end
17363
      end
17364
      else
17365
      begin
17366
        if (wb_int !== 1'b0)
17367
        begin
17368
          `TIME; $display("*E WB INT signal should not be set");
17369
          test_fail("WB INT signal should not be set");
17370
          fail = fail + 1;
17371
        end
17372
      end
17373
      // check RX buffer descriptor of a packet
17374
      check_rx_bd(127, data);
17375
      if (i_length[1] == 1'b0) // interrupt enabled no_carrier_sense_rx_fd_detect
17376
      begin
17377
        if ( ((data[15:0] !== 16'h6000) && (i_length[0] == 1'b0)) ||
17378
             ((data[15:0] !== 16'h6000) && (i_length[0] == 1'b1)) )
17379
        begin
17380
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
17381
          test_fail("RX buffer descriptor status is not correct");
17382
          fail = fail + 1;
17383
        end
17384
      end
17385
      else // interrupt not enabled
17386
      begin
17387
        if ( ((data[15:0] !== 16'h2000) && (i_length[0] == 1'b0)) ||
17388
             ((data[15:0] !== 16'h2000) && (i_length[0] == 1'b1)) )
17389
        begin
17390
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
17391
          test_fail("RX buffer descriptor status is not correct");
17392
          fail = fail + 1;
17393
        end
17394
      end
17395
      // clear RX buffer descriptor for first 4 frames
17396
      if (i_length < min_tmp)
17397
        clear_rx_bd(127, 127);
17398
      // check interrupts
17399
      wait (wbm_working == 0);
17400
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17401
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
17402
      begin
17403
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
17404
        begin
17405
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
17406
          test_fail("Interrupt Receive Buffer was not set");
17407
          fail = fail + 1;
17408
        end
17409
        if ((data & (~`ETH_INT_RXB)) !== 0)
17410
        begin
17411
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
17412
          test_fail("Other interrupts (except Receive Buffer) were set");
17413
          fail = fail + 1;
17414
        end
17415
      end
17416
      else
17417
      begin
17418
        if (data !== 0)
17419
        begin
17420
          `TIME; $display("*E Any of interrupts (except Receive Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
17421
          test_fail("Any of interrupts (except Receive Buffer) was set");
17422
          fail = fail + 1;
17423
        end
17424
      end
17425
      // clear interrupts
17426
      wait (wbm_working == 0);
17427
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17428
      // check WB INT signal
17429
      if (wb_int !== 1'b0)
17430
      begin
17431
        test_fail("WB INT signal should not be set");
17432
        fail = fail + 1;
17433
      end
17434
      // INTERMEDIATE DISPLAYS
17435
      if ((i_length + 4) == (min_tmp + 64))
17436
      begin
17437
        // starting length is min_tmp, ending length is (min_tmp + 64)
17438
        $display("    receive small packets is NOT selected");
17439
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
17440
                 min_tmp, (min_tmp + 64));
17441
        // set receive small, remain the rest
17442
        wait (wbm_working == 0);
17443
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
17444
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
17445
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17446
      end
17447
      else if ((i_length + 4) == (max_tmp - 16))
17448
      begin
17449
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
17450
        $display("    receive small packets is selected");
17451
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
17452
                 (min_tmp + 64 + 128), tmp_data);
17453
        // reset receive small, remain the rest
17454
        wait (wbm_working == 0);
17455
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
17456
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
17457
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17458
      end
17459
      else if ((i_length + 4) == max_tmp)
17460
      begin
17461
        $display("    receive small packets is NOT selected");
17462
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
17463
                 (max_tmp - (4 + 16)), max_tmp);
17464
      end
17465
      // set length (loop variable)
17466
      if ((i_length + 4) < (min_tmp + 64))
17467
        i_length = i_length + 1;
17468
      else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
17469
      begin
17470
        i_length = i_length + 128;
17471
        tmp_data = i_length + 4; // last tmp_data is ending length
17472
      end
17473
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
17474
        i_length = max_tmp - (4 + 16);
17475
      else if ((i_length + 4) >= (max_tmp - 16))
17476
        i_length = i_length + 1;
17477
      else
17478
      begin
17479
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
17480
        #10 $stop;
17481
      end
17482
    end
17483
    // disable RX
17484
    wait (wbm_working == 0);
17485 260 mohor
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
17486
              `ETH_MODER_PRO | `ETH_MODER_BRO,
17487 254 mohor
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17488
    if(fail == 0)
17489
      test_ok;
17490
    else
17491
      fail = 0;
17492 209 tadejm
  end
17493
 
17494
 
17495
end   //  for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
17496
 
17497 260 mohor
 
17498 209 tadejm
end
17499 274 tadejm
endtask // test_mac_half_duplex_flow
17500 209 tadejm
 
17501
 
17502 169 mohor
//////////////////////////////////////////////////////////////
17503
// WB Behavioral Models Basic tasks
17504
//////////////////////////////////////////////////////////////
17505
 
17506
task wbm_write;
17507
  input  [31:0] address_i;
17508
  input  [((`MAX_BLK_SIZE * 32) - 1):0] data_i;
17509
  input  [3:0]  sel_i;
17510
  input  [31:0] size_i;
17511
  input  [3:0]  init_waits_i;
17512
  input  [3:0]  subseq_waits_i;
17513
 
17514
  reg `WRITE_STIM_TYPE write_data;
17515
  reg `WB_TRANSFER_FLAGS flags;
17516
  reg `WRITE_RETURN_TYPE write_status;
17517
  integer i;
17518
begin
17519 274 tadejm
  wbm_working = 1;
17520
 
17521 169 mohor
  write_status = 0;
17522
 
17523
  flags                    = 0;
17524
  flags`WB_TRANSFER_SIZE   = size_i;
17525
  flags`INIT_WAITS         = init_waits_i;
17526
  flags`SUBSEQ_WAITS       = subseq_waits_i;
17527
 
17528
  write_data               = 0;
17529
  write_data`WRITE_DATA    = data_i[31:0];
17530
  write_data`WRITE_ADDRESS = address_i;
17531
  write_data`WRITE_SEL     = sel_i;
17532
 
17533
  for (i = 0; i < size_i; i = i + 1)
17534
  begin
17535
    wb_master.blk_write_data[i] = write_data;
17536
    data_i                      = data_i >> 32;
17537
    write_data`WRITE_DATA       = data_i[31:0];
17538
    write_data`WRITE_ADDRESS    = write_data`WRITE_ADDRESS + 4;
17539 116 mohor
  end
17540
 
17541 169 mohor
  wb_master.wb_block_write(flags, write_status);
17542 116 mohor
 
17543 169 mohor
  if (write_status`CYC_ACTUAL_TRANSFER !== size_i)
17544
  begin
17545
    `TIME;
17546
    $display("*E WISHBONE Master was unable to complete the requested write operation to MAC!");
17547
  end
17548 274 tadejm
 
17549
  @(posedge wb_clk);
17550
  #3;
17551
  wbm_working = 0;
17552
  #1;
17553 169 mohor
end
17554
endtask // wbm_write
17555 116 mohor
 
17556 169 mohor
task wbm_read;
17557
  input  [31:0] address_i;
17558
  output [((`MAX_BLK_SIZE * 32) - 1):0] data_o;
17559
  input  [3:0]  sel_i;
17560
  input  [31:0] size_i;
17561
  input  [3:0]  init_waits_i;
17562
  input  [3:0]  subseq_waits_i;
17563
 
17564
  reg `READ_RETURN_TYPE read_data;
17565
  reg `WB_TRANSFER_FLAGS flags;
17566
  reg `READ_RETURN_TYPE read_status;
17567
  integer i;
17568
begin
17569 274 tadejm
  wbm_working = 1;
17570
 
17571 169 mohor
  read_status = 0;
17572
  data_o      = 0;
17573
 
17574
  flags                  = 0;
17575
  flags`WB_TRANSFER_SIZE = size_i;
17576
  flags`INIT_WAITS       = init_waits_i;
17577
  flags`SUBSEQ_WAITS     = subseq_waits_i;
17578
 
17579
  read_data              = 0;
17580
  read_data`READ_ADDRESS = address_i;
17581
  read_data`READ_SEL     = sel_i;
17582
 
17583
  for (i = 0; i < size_i; i = i + 1)
17584 116 mohor
  begin
17585 169 mohor
    wb_master.blk_read_data_in[i] = read_data;
17586
    read_data`READ_ADDRESS        = read_data`READ_ADDRESS + 4;
17587
  end
17588
 
17589
  wb_master.wb_block_read(flags, read_status);
17590
 
17591
  if (read_status`CYC_ACTUAL_TRANSFER !== size_i)
17592
  begin
17593
    `TIME;
17594
    $display("*E WISHBONE Master was unable to complete the requested read operation from MAC!");
17595
  end
17596
 
17597
  for (i = 0; i < size_i; i = i + 1)
17598
  begin
17599
    data_o       = data_o << 32;
17600
    read_data    = wb_master.blk_read_data_out[(size_i - 1) - i]; // [31 - i];
17601
    data_o[31:0] = read_data`READ_DATA;
17602
  end
17603 274 tadejm
 
17604
  @(posedge wb_clk);
17605
  #3;
17606
  wbm_working = 0;
17607
  #1;
17608 169 mohor
end
17609
endtask // wbm_read
17610
 
17611
 
17612
//////////////////////////////////////////////////////////////
17613
// Ethernet Basic tasks
17614
//////////////////////////////////////////////////////////////
17615
 
17616
task hard_reset; //  MAC registers
17617
begin
17618
  // reset MAC registers
17619
  @(posedge wb_clk);
17620
  #2 wb_rst = 1'b1;
17621
  repeat(2) @(posedge wb_clk);
17622
  #2 wb_rst = 1'b0;
17623
end
17624
endtask // hard_reset
17625
 
17626
task reset_mac; //  MAC module
17627
  reg [31:0] tmp;
17628
  reg [31:0] tmp_no_rst;
17629
begin
17630
  // read MODER register first
17631
  wbm_read(`ETH_MODER, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17632
  // set reset bit - write back to MODER register with RESET bit
17633
  wbm_write(`ETH_MODER, (`ETH_MODER_RST | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17634
  // clear reset bit - write back to MODER register without RESET bit
17635
  tmp_no_rst = `ETH_MODER_RST;
17636
  tmp_no_rst = ~tmp_no_rst;
17637
  wbm_write(`ETH_MODER, (tmp_no_rst & tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17638
end
17639
endtask // reset_mac
17640
 
17641
task set_tx_bd;
17642
  input  [6:0]  tx_bd_num_start;
17643
  input  [6:0]  tx_bd_num_end;
17644
  input  [15:0] len;
17645
  input         irq;
17646
  input         pad;
17647
  input         crc;
17648
  input  [31:0] txpnt;
17649
 
17650
  integer       i;
17651
  integer       bd_status_addr, bd_ptr_addr;
17652
//  integer       buf_addr;
17653
begin
17654
  for(i = tx_bd_num_start; i <= tx_bd_num_end; i = i + 1)
17655
  begin
17656
//    buf_addr = `TX_BUF_BASE + i * 32'h600;
17657
    bd_status_addr = `TX_BD_BASE + i * 8;
17658
    bd_ptr_addr = bd_status_addr + 4;
17659
    // initialize BD - status
17660
    wbm_write(bd_status_addr, {len, 1'b0, irq, 1'b0, pad, crc, 11'h0},
17661
              4'hF, 1, wbm_init_waits, wbm_subseq_waits); // IRQ + PAD + CRC
17662
    // initialize BD - pointer
17663
    wbm_write(bd_ptr_addr, txpnt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Initializing BD-pointer
17664
  end
17665
end
17666
endtask // set_tx_bd
17667
 
17668
task set_tx_bd_wrap;
17669
  input  [6:0]  tx_bd_num_end;
17670
  integer       bd_status_addr, tmp;
17671
begin
17672
  bd_status_addr = `TX_BD_BASE + tx_bd_num_end * 8;
17673
  wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17674
  // set wrap bit to this BD - this BD should be last-one
17675
  wbm_write(bd_status_addr, (`ETH_TX_BD_WRAP | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17676
end
17677
endtask // set_tx_bd_wrap
17678
 
17679
task set_tx_bd_ready;
17680
  input  [6:0]  tx_nd_num_strat;
17681
  input  [6:0]  tx_bd_num_end;
17682
  integer       i;
17683
  integer       bd_status_addr, tmp;
17684
begin
17685
  for(i = tx_nd_num_strat; i <= tx_bd_num_end; i = i + 1)
17686
  begin
17687
    bd_status_addr = `TX_BD_BASE + i * 8;
17688
    wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17689
    // set empty bit to this BD - this BD should be ready
17690
    wbm_write(bd_status_addr, (`ETH_TX_BD_READY | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17691
  end
17692
end
17693
endtask // set_tx_bd_ready
17694
 
17695
task check_tx_bd;
17696
  input  [6:0]  tx_bd_num_end;
17697
  output [31:0] tx_bd_status;
17698
  integer       bd_status_addr, tmp;
17699
begin
17700
  bd_status_addr = `TX_BD_BASE + tx_bd_num_end * 8;
17701
  wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17702 274 tadejm
  tx_bd_status = tmp;
17703 169 mohor
end
17704
endtask // check_tx_bd
17705
 
17706
task clear_tx_bd;
17707
  input  [6:0]  tx_nd_num_strat;
17708
  input  [6:0]  tx_bd_num_end;
17709
  integer       i;
17710
  integer       bd_status_addr, bd_ptr_addr;
17711
begin
17712
  for(i = tx_nd_num_strat; i <= tx_bd_num_end; i = i + 1)
17713
  begin
17714
    bd_status_addr = `TX_BD_BASE + i * 8;
17715
    bd_ptr_addr = bd_status_addr + 4;
17716
    // clear BD - status
17717
    wbm_write(bd_status_addr, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17718
    // clear BD - pointer
17719
    wbm_write(bd_ptr_addr, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17720
  end
17721
end
17722
endtask // clear_tx_bd
17723
 
17724
task set_rx_bd;
17725
  input  [6:0]  rx_bd_num_strat;
17726
  input  [6:0]  rx_bd_num_end;
17727
  input         irq;
17728
  input  [31:0] rxpnt;
17729
//  input  [6:0]  rxbd_num;
17730
  integer       i;
17731
  integer       bd_status_addr, bd_ptr_addr;
17732
//  integer       buf_addr;
17733
begin
17734
  for(i = rx_bd_num_strat; i <= rx_bd_num_end; i = i + 1)
17735
  begin
17736
//    buf_addr = `RX_BUF_BASE + i * 32'h600;
17737 209 tadejm
//    bd_status_addr = `RX_BD_BASE + i * 8;
17738
//    bd_ptr_addr = bd_status_addr + 4; 
17739
    bd_status_addr = `TX_BD_BASE + i * 8;
17740
    bd_ptr_addr = bd_status_addr + 4;
17741 116 mohor
 
17742 169 mohor
    // initialize BD - status
17743
//    wbm_write(bd_status_addr, 32'h0000c000, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // IRQ + PAD + CRC
17744
    wbm_write(bd_status_addr, {17'h0, irq, 14'h0},
17745
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17746
    // initialize BD - pointer
17747
//    wbm_write(bd_ptr_addr, buf_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Initializing BD-pointer
17748
    wbm_write(bd_ptr_addr, rxpnt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Initializing BD-pointer
17749
  end
17750
end
17751
endtask // set_rx_bd
17752 116 mohor
 
17753 169 mohor
task set_rx_bd_wrap;
17754
  input  [6:0]  rx_bd_num_end;
17755
  integer       bd_status_addr, tmp;
17756
begin
17757 209 tadejm
//  bd_status_addr = `RX_BD_BASE + rx_bd_num_end * 8;
17758
  bd_status_addr = `TX_BD_BASE + rx_bd_num_end * 8;
17759 169 mohor
  wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17760
  // set wrap bit to this BD - this BD should be last-one
17761
  wbm_write(bd_status_addr, (`ETH_RX_BD_WRAP | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17762
end
17763
endtask // set_rx_bd_wrap
17764 116 mohor
 
17765 169 mohor
task set_rx_bd_empty;
17766
  input  [6:0]  rx_bd_num_strat;
17767
  input  [6:0]  rx_bd_num_end;
17768
  integer       i;
17769
  integer       bd_status_addr, tmp;
17770
begin
17771
  for(i = rx_bd_num_strat; i <= rx_bd_num_end; i = i + 1)
17772
  begin
17773 209 tadejm
//    bd_status_addr = `RX_BD_BASE + i * 8;
17774
    bd_status_addr = `TX_BD_BASE + i * 8;
17775 169 mohor
    wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17776
    // set empty bit to this BD - this BD should be ready
17777
    wbm_write(bd_status_addr, (`ETH_RX_BD_EMPTY | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17778 116 mohor
  end
17779 169 mohor
end
17780
endtask // set_rx_bd_empty
17781 116 mohor
 
17782 169 mohor
task check_rx_bd;
17783
  input  [6:0]  rx_bd_num_end;
17784
  output [31:0] rx_bd_status;
17785
  integer       bd_status_addr, tmp;
17786
begin
17787 209 tadejm
//  bd_status_addr = `RX_BD_BASE + rx_bd_num_end * 8;
17788
  bd_status_addr = `TX_BD_BASE + rx_bd_num_end * 8;
17789 169 mohor
  wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17790 274 tadejm
  rx_bd_status = tmp;
17791 169 mohor
end
17792
endtask // check_rx_bd
17793 116 mohor
 
17794 169 mohor
task clear_rx_bd;
17795
  input  [6:0]  rx_bd_num_strat;
17796
  input  [6:0]  rx_bd_num_end;
17797
  integer       i;
17798
  integer       bd_status_addr, bd_ptr_addr;
17799
begin
17800
  for(i = rx_bd_num_strat; i <= rx_bd_num_end; i = i + 1)
17801
  begin
17802 209 tadejm
//    bd_status_addr = `RX_BD_BASE + i * 8;
17803
    bd_status_addr = `TX_BD_BASE + i * 8;
17804 169 mohor
    bd_ptr_addr = bd_status_addr + 4;
17805
    // clear BD - status
17806
    wbm_write(bd_status_addr, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17807
    // clear BD - pointer
17808
    wbm_write(bd_ptr_addr, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17809
  end
17810
end
17811
endtask // clear_rx_bd
17812 116 mohor
 
17813 169 mohor
task set_tx_packet;
17814
  input  [31:0] txpnt;
17815
  input  [15:0] len;
17816
  input  [7:0]  eth_start_data;
17817
  integer       i, sd;
17818
  integer       buffer;
17819
  reg           delta_t;
17820
begin
17821
  buffer = txpnt;
17822
  sd = eth_start_data;
17823
  delta_t = 0;
17824 116 mohor
 
17825 169 mohor
  // First write might not be word allign.
17826
  if(buffer[1:0] == 1)
17827
  begin
17828
    wb_slave.wr_mem(buffer - 1, {8'h0, sd[7:0], sd[7:0] + 3'h1, sd[7:0] + 3'h2}, 4'h7);
17829
    sd = sd + 3;
17830
    i = 3;
17831
  end
17832
  else if(buffer[1:0] == 2)
17833
  begin
17834
    wb_slave.wr_mem(buffer - 2, {16'h0, sd[7:0], sd[7:0] + 3'h1}, 4'h3);
17835
    sd = sd + 2;
17836
    i = 2;
17837
  end
17838
  else if(buffer[1:0] == 3)
17839
  begin
17840
    wb_slave.wr_mem(buffer - 3, {24'h0, sd[7:0]}, 4'h1);
17841
    sd = sd + 1;
17842
    i = 1;
17843
  end
17844
  else
17845
    i = 0;
17846
  delta_t = !delta_t;
17847 116 mohor
 
17848 169 mohor
  for(i = i; i < (len - 4); i = i + 4) // Last 0-3 bytes are not written
17849
  begin
17850
    wb_slave.wr_mem(buffer + i, {sd[7:0], sd[7:0] + 3'h1, sd[7:0] + 3'h2, sd[7:0] + 3'h3}, 4'hF);
17851
    sd = sd + 4;
17852
  end
17853
  delta_t = !delta_t;
17854
 
17855
  // Last word
17856
  if((len - i) == 3)
17857 116 mohor
  begin
17858 169 mohor
    wb_slave.wr_mem(buffer + i, {sd[7:0], sd[7:0] + 3'h1, sd[7:0] + 3'h2, 8'h0}, 4'hE);
17859
  end
17860
  else if((len - i) == 2)
17861
  begin
17862
    wb_slave.wr_mem(buffer + i, {sd[7:0], sd[7:0] + 3'h1, 16'h0}, 4'hC);
17863
  end
17864
  else if((len - i) == 1)
17865
  begin
17866
    wb_slave.wr_mem(buffer + i, {sd[7:0], 24'h0}, 4'h8);
17867
  end
17868
  else if((len - i) == 4)
17869
  begin
17870
    wb_slave.wr_mem(buffer + i, {sd[7:0], sd[7:0] + 3'h1, sd[7:0] + 3'h2, sd[7:0] + 3'h3}, 4'hF);
17871
  end
17872
  else
17873
    $display("(%0t)(%m) ERROR", $time);
17874
  delta_t = !delta_t;
17875
end
17876
endtask // set_tx_packet
17877
 
17878
task check_tx_packet;
17879
  input  [31:0] txpnt_wb;  // source
17880
  input  [31:0] txpnt_phy; // destination
17881
  input  [15:0] len;
17882
  output [31:0] failure;
17883
  integer       i, data_wb, data_phy;
17884
  reg    [31:0] addr_wb, addr_phy;
17885
  reg    [31:0] failure;
17886
  reg           delta_t;
17887
begin
17888
  addr_wb = txpnt_wb;
17889
  addr_phy = txpnt_phy;
17890
  delta_t = 0;
17891
  failure = 0;
17892 209 tadejm
  #1;
17893 169 mohor
  // First write might not be word allign.
17894
  if(addr_wb[1:0] == 1)
17895
  begin
17896
    wb_slave.rd_mem(addr_wb - 1, data_wb, 4'h7);
17897
    data_phy[31:24] = 0;
17898
    data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0]];
17899
    data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + 1];
17900
    data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + 2];
17901
    i = 3;
17902
    if (data_phy[23:0] !== data_wb[23:0])
17903
    begin
17904
      `TIME;
17905 209 tadejm
      $display("*E Wrong 1. word (3 bytes) of TX packet! phy: %0h, wb: %0h", data_phy[23:0], data_wb[23:0]);
17906
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
17907 169 mohor
      failure = 1;
17908
    end
17909
  end
17910
  else if (addr_wb[1:0] == 2)
17911
  begin
17912
    wb_slave.rd_mem(addr_wb - 2, data_wb, 4'h3);
17913
    data_phy[31:16] = 0;
17914
    data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0]];
17915
    data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + 1];
17916
    i = 2;
17917
    if (data_phy[15:0] !== data_wb[15:0])
17918
    begin
17919
      `TIME;
17920 209 tadejm
      $display("*E Wrong 1. word (2 bytes) of TX packet! phy: %0h, wb: %0h", data_phy[15:0], data_wb[15:0]);
17921
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
17922 169 mohor
      failure = 1;
17923
    end
17924
  end
17925
  else if (addr_wb[1:0] == 3)
17926
  begin
17927
    wb_slave.rd_mem(addr_wb - 3, data_wb, 4'h1);
17928
    data_phy[31: 8] = 0;
17929
    data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0]];
17930
    i = 1;
17931
    if (data_phy[7:0] !== data_wb[7:0])
17932
    begin
17933
      `TIME;
17934 209 tadejm
      $display("*E Wrong 1. word (1 byte) of TX packet! phy: %0h, wb: %0h", data_phy[7:0], data_wb[7:0]);
17935
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
17936 169 mohor
      failure = 1;
17937
    end
17938
  end
17939
  else
17940
    i = 0;
17941
  delta_t = !delta_t;
17942 209 tadejm
  #1;
17943 169 mohor
  for(i = i; i < (len - 4); i = i + 4) // Last 0-3 bytes are not checked
17944
  begin
17945
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hF);
17946
    data_phy[31:24] = eth_phy.tx_mem[addr_phy[21:0] + i];
17947
    data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0] + i + 1];
17948
    data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + i + 2];
17949
    data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + i + 3];
17950 279 mohor
 
17951 169 mohor
    if (data_phy[31:0] !== data_wb[31:0])
17952
    begin
17953
      `TIME;
17954 209 tadejm
      $display("*E Wrong %d. word (4 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
17955
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
17956 169 mohor
      failure = failure + 1;
17957
    end
17958
  end
17959
  delta_t = !delta_t;
17960 209 tadejm
  #1;
17961 169 mohor
  // Last word
17962
  if((len - i) == 3)
17963
  begin
17964
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hE);
17965
    data_phy[31:24] = eth_phy.tx_mem[addr_phy[21:0] + i];
17966
    data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0] + i + 1];
17967
    data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + i + 2];
17968
    data_phy[ 7: 0] = 0;
17969
    if (data_phy[31:8] !== data_wb[31:8])
17970
    begin
17971
      `TIME;
17972 209 tadejm
      $display("*E Wrong %d. word (3 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:8], data_wb[31:8]);
17973
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
17974 169 mohor
      failure = failure + 1;
17975
    end
17976
  end
17977
  else if((len - i) == 2)
17978
  begin
17979
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hC);
17980
    data_phy[31:24] = eth_phy.tx_mem[addr_phy[21:0] + i];
17981
    data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0] + i + 1];
17982
    data_phy[15: 8] = 0;
17983
    data_phy[ 7: 0] = 0;
17984
    if (data_phy[31:16] !== data_wb[31:16])
17985
    begin
17986
      `TIME;
17987 209 tadejm
      $display("*E Wrong %d. word (2 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:16], data_wb[31:16]);
17988
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
17989 169 mohor
      failure = failure + 1;
17990
    end
17991
  end
17992
  else if((len - i) == 1)
17993
  begin
17994
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'h8);
17995
    data_phy[31:24] = eth_phy.tx_mem[addr_phy[21:0] + i];
17996
    data_phy[23:16] = 0;
17997
    data_phy[15: 8] = 0;
17998
    data_phy[ 7: 0] = 0;
17999
    if (data_phy[31:24] !== data_wb[31:24])
18000
    begin
18001
      `TIME;
18002 209 tadejm
      $display("*E Wrong %d. word (1 byte) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:24], data_wb[31:24]);
18003
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
18004 169 mohor
      failure = failure + 1;
18005
    end
18006
  end
18007
  else if((len - i) == 4)
18008
  begin
18009
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hF);
18010
    data_phy[31:24] = eth_phy.tx_mem[addr_phy[21:0] + i];
18011
    data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0] + i + 1];
18012
    data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + i + 2];
18013
    data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + i + 3];
18014
    if (data_phy[31:0] !== data_wb[31:0])
18015
    begin
18016
      `TIME;
18017 209 tadejm
      $display("*E Wrong %d. word (4 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
18018
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
18019 169 mohor
      failure = failure + 1;
18020
    end
18021
  end
18022
  else
18023
    $display("(%0t)(%m) ERROR", $time);
18024
  delta_t = !delta_t;
18025
end
18026
endtask // check_tx_packet
18027
 
18028
task set_rx_packet;
18029
  input  [31:0] rxpnt;
18030
  input  [15:0] len;
18031
  input         plus_dribble_nibble; // if length is longer for one nibble
18032
  input  [47:0] eth_dest_addr;
18033
  input  [47:0] eth_source_addr;
18034
  input  [15:0] eth_type_len;
18035
  input  [7:0]  eth_start_data;
18036
  integer       i, sd;
18037
  reg    [47:0] dest_addr;
18038
  reg    [47:0] source_addr;
18039
  reg    [15:0] type_len;
18040
  reg    [21:0] buffer;
18041
  reg           delta_t;
18042
begin
18043
  buffer = rxpnt[21:0];
18044
  dest_addr = eth_dest_addr;
18045
  source_addr = eth_source_addr;
18046
  type_len = eth_type_len;
18047
  sd = eth_start_data;
18048
  delta_t = 0;
18049
  for(i = 0; i < len; i = i + 1)
18050
  begin
18051
    if (i < 6)
18052
    begin
18053
      eth_phy.rx_mem[buffer] = dest_addr[47:40];
18054
      dest_addr = dest_addr << 8;
18055
    end
18056
    else if (i < 12)
18057
    begin
18058
      eth_phy.rx_mem[buffer] = source_addr[47:40];
18059
      source_addr = source_addr << 8;
18060
    end
18061
    else if (i < 14)
18062
    begin
18063
      eth_phy.rx_mem[buffer] = type_len[15:8];
18064
      type_len = type_len << 8;
18065
    end
18066
    else
18067
    begin
18068
      eth_phy.rx_mem[buffer] = sd[7:0];
18069
      sd = sd + 1;
18070
    end
18071
    buffer = buffer + 1;
18072
  end
18073
  delta_t = !delta_t;
18074
  if (plus_dribble_nibble)
18075
    eth_phy.rx_mem[buffer] = {4'h0, 4'hD /*sd[3:0]*/};
18076
  delta_t = !delta_t;
18077
end
18078
endtask // set_rx_packet
18079
 
18080 267 mohor
task set_rx_control_packet;
18081
  input  [31:0] rxpnt;
18082
  input  [15:0] PauseTV;
18083
  integer       i;
18084
  reg    [47:0] dest_addr;
18085
  reg    [47:0] source_addr;
18086
  reg    [15:0] type_len;
18087
  reg    [21:0] buffer;
18088
  reg           delta_t;
18089
  reg    [15:0] PTV;
18090
  reg    [15:0] opcode;
18091
begin
18092
  buffer = rxpnt[21:0];
18093
  dest_addr = 48'h0180_c200_0001;
18094
  source_addr = 48'h0708_090A_0B0C;
18095
  type_len = 16'h8808;
18096
  opcode = 16'h0001;
18097
  PTV = PauseTV;
18098
  delta_t = 0;
18099
  for(i = 0; i < 60; i = i + 1)
18100
  begin
18101
    if (i < 6)
18102
    begin
18103
      eth_phy.rx_mem[buffer] = dest_addr[47:40];
18104
      dest_addr = dest_addr << 8;
18105
    end
18106
    else if (i < 12)
18107
    begin
18108
      eth_phy.rx_mem[buffer] = source_addr[47:40];
18109
      source_addr = source_addr << 8;
18110
    end
18111
    else if (i < 14)
18112
    begin
18113
      eth_phy.rx_mem[buffer] = type_len[15:8];
18114
      type_len = type_len << 8;
18115
    end
18116
    else if (i < 16)
18117
    begin
18118
      eth_phy.rx_mem[buffer] = opcode[15:8];
18119
      opcode = opcode << 8;
18120
    end
18121
    else if (i < 18)
18122
    begin
18123
      eth_phy.rx_mem[buffer] = PTV[15:8];
18124
      PTV = PTV << 8;
18125
    end
18126
    else
18127
    begin
18128
      eth_phy.rx_mem[buffer] = 0;
18129
    end
18130
    buffer = buffer + 1;
18131
  end
18132
  delta_t = !delta_t;
18133
  append_rx_crc (rxpnt, 60, 1'b0, 1'b0); // CRC for control packet
18134
end
18135
endtask // set_rx_control_packet
18136
 
18137 243 tadejm
task set_rx_addr_type;
18138
  input  [31:0] rxpnt;
18139
  input  [47:0] eth_dest_addr;
18140
  input  [47:0] eth_source_addr;
18141
  input  [15:0] eth_type_len;
18142
  integer       i;
18143
  reg    [47:0] dest_addr;
18144
  reg    [47:0] source_addr;
18145
  reg    [15:0] type_len;
18146
  reg    [21:0] buffer;
18147
  reg           delta_t;
18148
begin
18149
  buffer = rxpnt[21:0];
18150
  dest_addr = eth_dest_addr;
18151
  source_addr = eth_source_addr;
18152
  type_len = eth_type_len;
18153
  delta_t = 0;
18154
  for(i = 0; i < 14; i = i + 1)
18155
  begin
18156
    if (i < 6)
18157
    begin
18158
      eth_phy.rx_mem[buffer] = dest_addr[47:40];
18159
      dest_addr = dest_addr << 8;
18160
    end
18161
    else if (i < 12)
18162
    begin
18163
      eth_phy.rx_mem[buffer] = source_addr[47:40];
18164
      source_addr = source_addr << 8;
18165
    end
18166
    else // if (i < 14)
18167
    begin
18168
      eth_phy.rx_mem[buffer] = type_len[15:8];
18169
      type_len = type_len << 8;
18170
    end
18171
    buffer = buffer + 1;
18172
  end
18173
  delta_t = !delta_t;
18174
end
18175
endtask // set_rx_addr_type
18176
 
18177 169 mohor
task check_rx_packet;
18178
  input  [31:0] rxpnt_phy; // source
18179
  input  [31:0] rxpnt_wb;  // destination
18180
  input  [15:0] len;
18181
  input         plus_dribble_nibble; // if length is longer for one nibble
18182
  input         successful_dribble_nibble; // if additional nibble is stored into memory
18183
  output [31:0] failure;
18184
  integer       i, data_wb, data_phy;
18185
  reg    [31:0] addr_wb, addr_phy;
18186
  reg    [31:0] failure;
18187
  reg    [21:0] buffer;
18188
  reg           delta_t;
18189
begin
18190
  addr_phy = rxpnt_phy;
18191
  addr_wb = rxpnt_wb;
18192
  delta_t = 0;
18193
  failure = 0;
18194
 
18195
  // First write might not be word allign.
18196
  if(addr_wb[1:0] == 1)
18197
  begin
18198
    wb_slave.rd_mem(addr_wb - 1, data_wb, 4'h7);
18199
    data_phy[31:24] = 0;
18200
    data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0]];
18201
    data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + 1];
18202
    data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + 2];
18203
    i = 3;
18204
    if (data_phy[23:0] !== data_wb[23:0])
18205
    begin
18206
      `TIME;
18207 243 tadejm
      $display("   addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
18208
      $display("*E Wrong 1. word (3 bytes) of RX packet! phy = %h, wb = %h", data_phy[23:0], data_wb[23:0]);
18209 169 mohor
      failure = 1;
18210
    end
18211
  end
18212
  else if (addr_wb[1:0] == 2)
18213
  begin
18214
    wb_slave.rd_mem(addr_wb - 2, data_wb, 4'h3);
18215
    data_phy[31:16] = 0;
18216
    data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0]];
18217
    data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + 1];
18218
    i = 2;
18219
    if (data_phy[15:0] !== data_wb[15:0])
18220
    begin
18221
      `TIME;
18222 243 tadejm
      $display("   addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
18223
      $display("*E Wrong 1. word (2 bytes) of RX packet! phy = %h, wb = %h", data_phy[15:0], data_wb[15:0]);
18224 169 mohor
      failure = 1;
18225
    end
18226
  end
18227
  else if (addr_wb[1:0] == 3)
18228
  begin
18229
    wb_slave.rd_mem(addr_wb - 3, data_wb, 4'h1);
18230
    data_phy[31: 8] = 0;
18231
    data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0]];
18232
    i = 1;
18233
    if (data_phy[7:0] !== data_wb[7:0])
18234
    begin
18235
      `TIME;
18236 243 tadejm
      $display("   addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
18237
      $display("*E Wrong 1. word (1 byte) of RX packet! phy = %h, wb = %h", data_phy[7:0], data_wb[7:0]);
18238 169 mohor
      failure = 1;
18239
    end
18240
  end
18241
  else
18242
    i = 0;
18243
  delta_t = !delta_t;
18244
 
18245
  for(i = i; i < (len - 4); i = i + 4) // Last 0-3 bytes are not checked
18246
  begin
18247
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hF);
18248
    data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
18249
    data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
18250
    data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + i + 2];
18251
    data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + i + 3];
18252
    if (data_phy[31:0] !== data_wb[31:0])
18253
    begin
18254
      `TIME;
18255 243 tadejm
      if (i == 0)
18256
        $display("   addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
18257
      $display("*E Wrong %0d. word (4 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
18258 169 mohor
      failure = failure + 1;
18259
    end
18260
  end
18261
  delta_t = !delta_t;
18262
 
18263
  // Last word
18264
  if((len - i) == 3)
18265
  begin
18266
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hF);
18267
    data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
18268
    data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
18269
    data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + i + 2];
18270
    if (plus_dribble_nibble)
18271
      data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + i + 3];
18272
    else
18273
      data_phy[ 7: 0] = 0;
18274
    if (data_phy[31:8] !== data_wb[31:8])
18275
    begin
18276
      `TIME;
18277 243 tadejm
      $display("*E Wrong %0d. word (3 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:8], data_wb[31:8]);
18278 169 mohor
      failure = failure + 1;
18279
    end
18280
    if (plus_dribble_nibble && successful_dribble_nibble)
18281
    begin
18282
      if (data_phy[3:0] !== data_wb[3:0])
18283 116 mohor
      begin
18284 169 mohor
        `TIME;
18285 243 tadejm
        $display("*E Wrong dribble nibble in %0d. word (3 bytes) of RX packet!", ((i/4)+1));
18286 169 mohor
        failure = failure + 1;
18287 116 mohor
      end
18288 169 mohor
    end
18289
    else if (plus_dribble_nibble && !successful_dribble_nibble)
18290
    begin
18291
      if (data_phy[3:0] === data_wb[3:0])
18292 116 mohor
      begin
18293 169 mohor
        `TIME;
18294 243 tadejm
        $display("*E Wrong dribble nibble in %0d. word (3 bytes) of RX packet!", ((i/4)+1));
18295 169 mohor
        failure = failure + 1;
18296 116 mohor
      end
18297 169 mohor
    end
18298
  end
18299
  else if((len - i) == 2)
18300
  begin
18301
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hE);
18302
    data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
18303
    data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
18304
    if (plus_dribble_nibble)
18305
      data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + i + 2];
18306
    else
18307
      data_phy[15: 8] = 0;
18308
    data_phy[ 7: 0] = 0;
18309
    if (data_phy[31:16] !== data_wb[31:16])
18310
    begin
18311
      `TIME;
18312 243 tadejm
      $display("*E Wrong %0d. word (2 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:16], data_wb[31:16]);
18313 169 mohor
      failure = failure + 1;
18314
    end
18315
    if (plus_dribble_nibble && successful_dribble_nibble)
18316
    begin
18317
      if (data_phy[11:8] !== data_wb[11:8])
18318
      begin
18319
        `TIME;
18320 243 tadejm
        $display("*E Wrong dribble nibble in %0d. word (2 bytes) of RX packet!", ((i/4)+1));
18321 169 mohor
        failure = failure + 1;
18322
      end
18323
    end
18324
    else if (plus_dribble_nibble && !successful_dribble_nibble)
18325
    begin
18326
      if (data_phy[11:8] === data_wb[11:8])
18327
      begin
18328
        `TIME;
18329 243 tadejm
        $display("*E Wrong dribble nibble in %0d. word (2 bytes) of RX packet!", ((i/4)+1));
18330 169 mohor
        failure = failure + 1;
18331
      end
18332
    end
18333
  end
18334
  else if((len - i) == 1)
18335
  begin
18336
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hC);
18337
    data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
18338
    if (plus_dribble_nibble)
18339
      data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
18340
    else
18341
      data_phy[23:16] = 0;
18342
    data_phy[15: 8] = 0;
18343
    data_phy[ 7: 0] = 0;
18344
    if (data_phy[31:24] !== data_wb[31:24])
18345
    begin
18346
      `TIME;
18347 243 tadejm
      $display("*E Wrong %0d. word (1 byte) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:24], data_wb[31:24]);
18348 169 mohor
      failure = failure + 1;
18349
    end
18350
    if (plus_dribble_nibble && successful_dribble_nibble)
18351
    begin
18352
      if (data_phy[19:16] !== data_wb[19:16])
18353
      begin
18354
        `TIME;
18355 243 tadejm
        $display("*E Wrong dribble nibble in %0d. word (1 byte) of RX packet!", ((i/4)+1));
18356 169 mohor
        failure = failure + 1;
18357
      end
18358
    end
18359
    else if (plus_dribble_nibble && !successful_dribble_nibble)
18360
    begin
18361
      if (data_phy[19:16] === data_wb[19:16])
18362
      begin
18363
        `TIME;
18364 243 tadejm
        $display("*E Wrong dribble nibble in %0d. word (1 byte) of RX packet!", ((i/4)+1));
18365 169 mohor
        failure = failure + 1;
18366
      end
18367
    end
18368
  end
18369
  else if((len - i) == 4)
18370
  begin
18371
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hF);
18372
    data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
18373
    data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
18374
    data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + i + 2];
18375
    data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + i + 3];
18376
    if (data_phy[31:0] !== data_wb[31:0])
18377
    begin
18378
      `TIME;
18379 243 tadejm
      $display("*E Wrong %0d. word (4 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
18380 169 mohor
      failure = failure + 1;
18381
    end
18382
    if (plus_dribble_nibble)
18383
    begin
18384
      wb_slave.rd_mem(addr_wb + i + 4, data_wb, 4'h8);
18385
      data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i + 4];
18386
      if (successful_dribble_nibble)
18387
      begin
18388
        if (data_phy[27:24] !== data_wb[27:24])
18389
        begin
18390
          `TIME;
18391 243 tadejm
          $display("*E Wrong dribble nibble in %0d. word (0 bytes) of RX packet!", ((i/4)+2));
18392 169 mohor
          failure = failure + 1;
18393
        end
18394
      end
18395
      else
18396
      begin
18397
        if (data_phy[27:24] === data_wb[27:24])
18398
        begin
18399
          `TIME;
18400 243 tadejm
          $display("*E Wrong dribble nibble in %0d. word (0 bytes) of RX packet!", ((i/4)+2));
18401 169 mohor
          failure = failure + 1;
18402
        end
18403
      end
18404
    end
18405
  end
18406
  else
18407
    $display("(%0t)(%m) ERROR", $time);
18408
  delta_t = !delta_t;
18409
end
18410
endtask // check_rx_packet
18411 116 mohor
 
18412 169 mohor
//////////////////////////////////////////////////////////////
18413
// Ethernet CRC Basic tasks
18414
//////////////////////////////////////////////////////////////
18415
 
18416
task append_tx_crc;
18417
  input  [31:0] txpnt_wb;  // source
18418
  input  [15:0] len; // length in bytes without CRC
18419
  input         negated_crc; // if appended CRC is correct or not
18420
  reg    [31:0] crc;
18421
  reg    [31:0] addr_wb;
18422
  reg           delta_t;
18423
begin
18424 243 tadejm
  addr_wb = txpnt_wb + {16'h0, len};
18425 169 mohor
  delta_t = 0;
18426
  // calculate CRC from prepared packet
18427
  paralel_crc_mac(txpnt_wb, {16'h0, len}, 1'b0, crc);
18428
  if (negated_crc)
18429
    crc = ~crc;
18430
  delta_t = !delta_t;
18431
 
18432
  // Write might not be word allign.
18433
  if (addr_wb[1:0] == 1)
18434
  begin
18435
    wb_slave.wr_mem(addr_wb - 1, {8'h0, crc[7:0], crc[15:8], crc[23:16]}, 4'h7);
18436
    wb_slave.wr_mem(addr_wb + 3, {crc[31:24], 24'h0}, 4'h8);
18437 116 mohor
  end
18438 169 mohor
  else if (addr_wb[1:0] == 2)
18439
  begin
18440
    wb_slave.wr_mem(addr_wb - 2, {16'h0, crc[7:0], crc[15:8]}, 4'h3);
18441
    wb_slave.wr_mem(addr_wb + 2, {crc[23:16], crc[31:24], 16'h0}, 4'hC);
18442
  end
18443
  else if (addr_wb[1:0] == 3)
18444
  begin
18445
    wb_slave.wr_mem(addr_wb - 3, {24'h0, crc[7:0]}, 4'h1);
18446
    wb_slave.wr_mem(addr_wb + 1, {crc[15:8], crc[23:16], crc[31:24], 8'h0}, 4'hE);
18447
  end
18448
  else
18449
  begin
18450
    wb_slave.wr_mem(addr_wb, {crc[7:0], crc[15:8], crc[23:16], crc[31:24]}, 4'hF);
18451
  end
18452
  delta_t = !delta_t;
18453
end
18454
endtask // append_tx_crc
18455 116 mohor
 
18456 169 mohor
task check_tx_crc; // used to check crc added to TX packets by MAC
18457
  input  [31:0] txpnt_phy; // destination
18458
  input  [15:0] len; // length in bytes without CRC
18459
  input         negated_crc; // if appended CRC is correct or not
18460
  output [31:0] failure;
18461
  reg    [31:0] failure;
18462
  reg    [31:0] crc_calc;
18463
  reg    [31:0] crc;
18464
  reg    [31:0] addr_phy;
18465
  reg           delta_t;
18466
begin
18467
  addr_phy = txpnt_phy;
18468
  failure = 0;
18469
  // calculate CRC from sent packet
18470
//  serial_crc_phy_tx(addr_phy, {16'h0, len}, 1'b0, crc_calc);
18471
//#10;
18472
  paralel_crc_phy_tx(addr_phy, {16'h0, len}, 1'b0, crc_calc);
18473 209 tadejm
  #1;
18474 169 mohor
  addr_phy = addr_phy + len;
18475
  // Read CRC - BIG endian
18476
  crc[31:24] = eth_phy.tx_mem[addr_phy[21:0]];
18477
  crc[23:16] = eth_phy.tx_mem[addr_phy[21:0] + 1];
18478
  crc[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + 2];
18479
  crc[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + 3];
18480
 
18481
  delta_t = !delta_t;
18482
  if (negated_crc)
18483
  begin
18484
    if ((~crc_calc) !== crc)
18485
    begin
18486
      `TIME;
18487
      $display("*E Negated CRC was not successfuly transmitted!");
18488
      failure = failure + 1;
18489
    end
18490
  end
18491
  else
18492
  begin
18493
    if (crc_calc !== crc)
18494
    begin
18495
      `TIME;
18496 209 tadejm
      $display("*E Transmitted CRC was not correct; crc_calc: %0h, crc_mem: %0h", crc_calc, crc);
18497 169 mohor
      failure = failure + 1;
18498
    end
18499
  end
18500
  delta_t = !delta_t;
18501
end
18502
endtask // check_tx_crc
18503
 
18504
task append_rx_crc;
18505
  input  [31:0] rxpnt_phy; // source
18506
  input  [15:0] len; // length in bytes without CRC
18507
  input         plus_dribble_nibble; // if length is longer for one nibble
18508
  input         negated_crc; // if appended CRC is correct or not
18509
  reg    [31:0] crc;
18510
  reg    [7:0]  tmp;
18511
  reg    [31:0] addr_phy;
18512
  reg           delta_t;
18513
begin
18514
  addr_phy = rxpnt_phy + len;
18515
  delta_t = 0;
18516
  // calculate CRC from prepared packet
18517
  paralel_crc_phy_rx(rxpnt_phy, {16'h0, len}, plus_dribble_nibble, crc);
18518
  if (negated_crc)
18519
    crc = ~crc;
18520
  delta_t = !delta_t;
18521
 
18522
  if (plus_dribble_nibble)
18523
  begin
18524
    tmp = eth_phy.rx_mem[addr_phy];
18525 209 tadejm
    eth_phy.rx_mem[addr_phy]     = {crc[27:24], tmp[3:0]};
18526
    eth_phy.rx_mem[addr_phy + 1] = {crc[19:16], crc[31:28]};
18527
    eth_phy.rx_mem[addr_phy + 2] = {crc[11:8], crc[23:20]};
18528
    eth_phy.rx_mem[addr_phy + 3] = {crc[3:0], crc[15:12]};
18529
    eth_phy.rx_mem[addr_phy + 4] = {4'h0, crc[7:4]};
18530 169 mohor
  end
18531
  else
18532
  begin
18533 209 tadejm
    eth_phy.rx_mem[addr_phy]     = crc[31:24];
18534
    eth_phy.rx_mem[addr_phy + 1] = crc[23:16];
18535
    eth_phy.rx_mem[addr_phy + 2] = crc[15:8];
18536
    eth_phy.rx_mem[addr_phy + 3] = crc[7:0];
18537 169 mohor
  end
18538
end
18539
endtask // append_rx_crc
18540
 
18541
// paralel CRC checking for PHY TX
18542
task paralel_crc_phy_tx;
18543
  input  [31:0] start_addr; // start address
18544
  input  [31:0] len; // length of frame in Bytes without CRC length
18545
  input         plus_dribble_nibble; // if length is longer for one nibble
18546
  output [31:0] crc_out;
18547
  reg    [21:0] addr_cnt; // only 22 address lines
18548
  integer       word_cnt;
18549
  integer       nibble_cnt;
18550
  reg    [31:0] load_reg;
18551
  reg           delta_t;
18552
  reg    [31:0] crc_next;
18553
  reg    [31:0] crc;
18554
  reg           crc_error;
18555
  reg     [3:0] data_in;
18556
  integer       i;
18557
begin
18558
  #1 addr_cnt = start_addr[21:0];
18559
  word_cnt = 24; // 27; // start of the frame - nibble granularity (MSbit first)
18560
  crc = 32'hFFFF_FFFF; // INITIAL value
18561
  delta_t = 0;
18562
  // length must include 4 bytes of ZEROs, to generate CRC
18563
  // get number of nibbles from Byte length (2^1 = 2)
18564
  if (plus_dribble_nibble)
18565
    nibble_cnt = ((len + 4) << 1) + 1'b1; // one nibble longer
18566
  else
18567
    nibble_cnt = ((len + 4) << 1);
18568
  // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
18569
  load_reg[31:24] = eth_phy.tx_mem[addr_cnt];
18570
  addr_cnt = addr_cnt + 1;
18571
  load_reg[23:16] = eth_phy.tx_mem[addr_cnt];
18572
  addr_cnt = addr_cnt + 1;
18573
  load_reg[15: 8] = eth_phy.tx_mem[addr_cnt];
18574
  addr_cnt = addr_cnt + 1;
18575
  load_reg[ 7: 0] = eth_phy.tx_mem[addr_cnt];
18576
  addr_cnt = addr_cnt + 1;
18577
  while (nibble_cnt > 0)
18578
  begin
18579
    // wait for delta time
18580
    delta_t = !delta_t;
18581
    // shift data in
18582
 
18583
    if(nibble_cnt <= 8) // for additional 8 nibbles shift ZEROs in!
18584
      data_in[3:0] = 4'h0;
18585
    else
18586
 
18587
      data_in[3:0] = {load_reg[word_cnt], load_reg[word_cnt+1], load_reg[word_cnt+2], load_reg[word_cnt+3]};
18588
    crc_next[0]  = (data_in[0] ^ crc[28]);
18589
    crc_next[1]  = (data_in[1] ^ data_in[0] ^ crc[28]    ^ crc[29]);
18590
    crc_next[2]  = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]);
18591
    crc_next[3]  = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]);
18592
    crc_next[4]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[0];
18593
    crc_next[5]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[1];
18594
    crc_next[6]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[ 2];
18595
    crc_next[7]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[3];
18596
    crc_next[8]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[4];
18597
    crc_next[9]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[5];
18598
    crc_next[10] = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[6];
18599
    crc_next[11] = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[7];
18600
    crc_next[12] = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]) ^ crc[8];
18601
    crc_next[13] = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]) ^ crc[9];
18602
    crc_next[14] = (data_in[3] ^ data_in[2] ^ crc[30]    ^ crc[31]) ^ crc[10];
18603
    crc_next[15] = (data_in[3] ^ crc[31])   ^ crc[11];
18604
    crc_next[16] = (data_in[0] ^ crc[28])   ^ crc[12];
18605
    crc_next[17] = (data_in[1] ^ crc[29])   ^ crc[13];
18606
    crc_next[18] = (data_in[2] ^ crc[30])   ^ crc[14];
18607
    crc_next[19] = (data_in[3] ^ crc[31])   ^ crc[15];
18608
    crc_next[20] =  crc[16];
18609
    crc_next[21] =  crc[17];
18610
    crc_next[22] = (data_in[0] ^ crc[28])   ^ crc[18];
18611
    crc_next[23] = (data_in[1] ^ data_in[0] ^ crc[29]    ^ crc[28]) ^ crc[19];
18612
    crc_next[24] = (data_in[2] ^ data_in[1] ^ crc[30]    ^ crc[29]) ^ crc[20];
18613
    crc_next[25] = (data_in[3] ^ data_in[2] ^ crc[31]    ^ crc[30]) ^ crc[21];
18614
    crc_next[26] = (data_in[3] ^ data_in[0] ^ crc[31]    ^ crc[28]) ^ crc[22];
18615
    crc_next[27] = (data_in[1] ^ crc[29])   ^ crc[23];
18616
    crc_next[28] = (data_in[2] ^ crc[30])   ^ crc[24];
18617
    crc_next[29] = (data_in[3] ^ crc[31])   ^ crc[25];
18618
    crc_next[30] =  crc[26];
18619
    crc_next[31] =  crc[27];
18620
 
18621
    crc = crc_next;
18622
    crc_error = crc[31:0] != 32'hc704dd7b;  // CRC not equal to magic number
18623
    case (nibble_cnt)
18624
    9: crc_out = {!crc[24], !crc[25], !crc[26], !crc[27], !crc[28], !crc[29], !crc[30], !crc[31],
18625
                  !crc[16], !crc[17], !crc[18], !crc[19], !crc[20], !crc[21], !crc[22], !crc[23],
18626
                  !crc[ 8], !crc[ 9], !crc[10], !crc[11], !crc[12], !crc[13], !crc[14], !crc[15],
18627
                  !crc[ 0], !crc[ 1], !crc[ 2], !crc[ 3], !crc[ 4], !crc[ 5], !crc[ 6], !crc[ 7]};
18628
    default: crc_out = crc_out;
18629
    endcase
18630
    // wait for delta time
18631
    delta_t = !delta_t;
18632
    // increment address and load new data
18633
    if ((word_cnt+3) == 7)//4)
18634
    begin
18635
      // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
18636
      load_reg[31:24] = eth_phy.tx_mem[addr_cnt];
18637
      addr_cnt = addr_cnt + 1;
18638
      load_reg[23:16] = eth_phy.tx_mem[addr_cnt];
18639
      addr_cnt = addr_cnt + 1;
18640
      load_reg[15: 8] = eth_phy.tx_mem[addr_cnt];
18641
      addr_cnt = addr_cnt + 1;
18642
      load_reg[ 7: 0] = eth_phy.tx_mem[addr_cnt];
18643
      addr_cnt = addr_cnt + 1;
18644
    end
18645
    // set new load bit position
18646
    if((word_cnt+3) == 31)
18647
      word_cnt = 16;
18648
    else if ((word_cnt+3) == 23)
18649
      word_cnt = 8;
18650
    else if ((word_cnt+3) == 15)
18651
      word_cnt = 0;
18652
    else if ((word_cnt+3) == 7)
18653
      word_cnt = 24;
18654
    else
18655
      word_cnt = word_cnt + 4;// - 4;
18656
    // decrement nibble counter
18657
    nibble_cnt = nibble_cnt - 1;
18658
    // wait for delta time
18659
    delta_t = !delta_t;
18660
  end // while
18661
  #1;
18662
end
18663
endtask // paralel_crc_phy_tx
18664
 
18665
// paralel CRC calculating for PHY RX
18666
task paralel_crc_phy_rx;
18667
  input  [31:0] start_addr; // start address
18668
  input  [31:0] len; // length of frame in Bytes without CRC length
18669
  input         plus_dribble_nibble; // if length is longer for one nibble
18670 209 tadejm
  output [31:0] crc_out;
18671 169 mohor
  reg    [21:0] addr_cnt; // only 22 address lines
18672
  integer       word_cnt;
18673 209 tadejm
  integer       nibble_cnt;
18674 169 mohor
  reg    [31:0] load_reg;
18675
  reg           delta_t;
18676 209 tadejm
  reg    [31:0] crc_next;
18677
  reg    [31:0] crc;
18678
  reg           crc_error;
18679
  reg     [3:0] data_in;
18680
  integer       i;
18681 169 mohor
begin
18682
  #1 addr_cnt = start_addr[21:0];
18683 209 tadejm
  word_cnt = 24; // 27; // start of the frame - nibble granularity (MSbit first)
18684
  crc = 32'hFFFF_FFFF; // INITIAL value
18685 169 mohor
  delta_t = 0;
18686
  // length must include 4 bytes of ZEROs, to generate CRC
18687 209 tadejm
  // get number of nibbles from Byte length (2^1 = 2)
18688 169 mohor
  if (plus_dribble_nibble)
18689 209 tadejm
    nibble_cnt = ((len + 4) << 1) + 1'b1; // one nibble longer
18690 169 mohor
  else
18691 209 tadejm
    nibble_cnt = ((len + 4) << 1);
18692
  // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
18693 169 mohor
  load_reg[31:24] = eth_phy.rx_mem[addr_cnt];
18694
  addr_cnt = addr_cnt + 1;
18695
  load_reg[23:16] = eth_phy.rx_mem[addr_cnt];
18696
  addr_cnt = addr_cnt + 1;
18697 209 tadejm
  load_reg[15: 8] = eth_phy.rx_mem[addr_cnt];
18698 169 mohor
  addr_cnt = addr_cnt + 1;
18699 209 tadejm
  load_reg[ 7: 0] = eth_phy.rx_mem[addr_cnt];
18700
  addr_cnt = addr_cnt + 1;
18701
  while (nibble_cnt > 0)
18702 169 mohor
  begin
18703
    // wait for delta time
18704
    delta_t = !delta_t;
18705
    // shift data in
18706 209 tadejm
 
18707
    if(nibble_cnt <= 8) // for additional 8 nibbles shift ZEROs in!
18708
      data_in[3:0] = 4'h0;
18709 169 mohor
    else
18710 209 tadejm
 
18711
      data_in[3:0] = {load_reg[word_cnt], load_reg[word_cnt+1], load_reg[word_cnt+2], load_reg[word_cnt+3]};
18712
    crc_next[0]  = (data_in[0] ^ crc[28]);
18713
    crc_next[1]  = (data_in[1] ^ data_in[0] ^ crc[28]    ^ crc[29]);
18714
    crc_next[2]  = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]);
18715
    crc_next[3]  = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]);
18716
    crc_next[4]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[0];
18717
    crc_next[5]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[1];
18718
    crc_next[6]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[ 2];
18719
    crc_next[7]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[3];
18720
    crc_next[8]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[4];
18721
    crc_next[9]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[5];
18722
    crc_next[10] = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[6];
18723
    crc_next[11] = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[7];
18724
    crc_next[12] = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]) ^ crc[8];
18725
    crc_next[13] = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]) ^ crc[9];
18726
    crc_next[14] = (data_in[3] ^ data_in[2] ^ crc[30]    ^ crc[31]) ^ crc[10];
18727
    crc_next[15] = (data_in[3] ^ crc[31])   ^ crc[11];
18728
    crc_next[16] = (data_in[0] ^ crc[28])   ^ crc[12];
18729
    crc_next[17] = (data_in[1] ^ crc[29])   ^ crc[13];
18730
    crc_next[18] = (data_in[2] ^ crc[30])   ^ crc[14];
18731
    crc_next[19] = (data_in[3] ^ crc[31])   ^ crc[15];
18732
    crc_next[20] =  crc[16];
18733
    crc_next[21] =  crc[17];
18734
    crc_next[22] = (data_in[0] ^ crc[28])   ^ crc[18];
18735
    crc_next[23] = (data_in[1] ^ data_in[0] ^ crc[29]    ^ crc[28]) ^ crc[19];
18736
    crc_next[24] = (data_in[2] ^ data_in[1] ^ crc[30]    ^ crc[29]) ^ crc[20];
18737
    crc_next[25] = (data_in[3] ^ data_in[2] ^ crc[31]    ^ crc[30]) ^ crc[21];
18738
    crc_next[26] = (data_in[3] ^ data_in[0] ^ crc[31]    ^ crc[28]) ^ crc[22];
18739
    crc_next[27] = (data_in[1] ^ crc[29])   ^ crc[23];
18740
    crc_next[28] = (data_in[2] ^ crc[30])   ^ crc[24];
18741
    crc_next[29] = (data_in[3] ^ crc[31])   ^ crc[25];
18742
    crc_next[30] =  crc[26];
18743
    crc_next[31] =  crc[27];
18744
 
18745
    crc = crc_next;
18746
    crc_error = crc[31:0] != 32'hc704dd7b;  // CRC not equal to magic number
18747
    case (nibble_cnt)
18748
    9: crc_out = {!crc[24], !crc[25], !crc[26], !crc[27], !crc[28], !crc[29], !crc[30], !crc[31],
18749
                  !crc[16], !crc[17], !crc[18], !crc[19], !crc[20], !crc[21], !crc[22], !crc[23],
18750
                  !crc[ 8], !crc[ 9], !crc[10], !crc[11], !crc[12], !crc[13], !crc[14], !crc[15],
18751
                  !crc[ 0], !crc[ 1], !crc[ 2], !crc[ 3], !crc[ 4], !crc[ 5], !crc[ 6], !crc[ 7]};
18752
    default: crc_out = crc_out;
18753
    endcase
18754 169 mohor
    // wait for delta time
18755
    delta_t = !delta_t;
18756
    // increment address and load new data
18757 209 tadejm
    if ((word_cnt+3) == 7)//4)
18758 169 mohor
    begin
18759 209 tadejm
      // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
18760 169 mohor
      load_reg[31:24] = eth_phy.rx_mem[addr_cnt];
18761
      addr_cnt = addr_cnt + 1;
18762
      load_reg[23:16] = eth_phy.rx_mem[addr_cnt];
18763
      addr_cnt = addr_cnt + 1;
18764 209 tadejm
      load_reg[15: 8] = eth_phy.rx_mem[addr_cnt];
18765 169 mohor
      addr_cnt = addr_cnt + 1;
18766 209 tadejm
      load_reg[ 7: 0] = eth_phy.rx_mem[addr_cnt];
18767
      addr_cnt = addr_cnt + 1;
18768 169 mohor
    end
18769
    // set new load bit position
18770 209 tadejm
    if((word_cnt+3) == 31)
18771 169 mohor
      word_cnt = 16;
18772 209 tadejm
    else if ((word_cnt+3) == 23)
18773 169 mohor
      word_cnt = 8;
18774 209 tadejm
    else if ((word_cnt+3) == 15)
18775 169 mohor
      word_cnt = 0;
18776 209 tadejm
    else if ((word_cnt+3) == 7)
18777 169 mohor
      word_cnt = 24;
18778
    else
18779 209 tadejm
      word_cnt = word_cnt + 4;// - 4;
18780
    // decrement nibble counter
18781
    nibble_cnt = nibble_cnt - 1;
18782 169 mohor
    // wait for delta time
18783
    delta_t = !delta_t;
18784
  end // while
18785
  #1;
18786
end
18787
endtask // paralel_crc_phy_rx
18788
 
18789
// paralel CRC checking for MAC
18790
task paralel_crc_mac;
18791
  input  [31:0] start_addr; // start address
18792
  input  [31:0] len; // length of frame in Bytes without CRC length
18793
  input         plus_dribble_nibble; // if length is longer for one nibble
18794 209 tadejm
  output [31:0] crc_out;
18795
 
18796
  reg    [21:0] addr_cnt; // only 22 address lines
18797 169 mohor
  integer       word_cnt;
18798 209 tadejm
  integer       nibble_cnt;
18799 169 mohor
  reg    [31:0] load_reg;
18800
  reg           delta_t;
18801 209 tadejm
  reg    [31:0] crc_next;
18802
  reg    [31:0] crc;
18803
  reg           crc_error;
18804
  reg     [3:0] data_in;
18805
  integer       i;
18806 169 mohor
begin
18807
  #1 addr_cnt = start_addr[19:0];
18808
  // set starting point depending with which byte frame starts (e.g. if addr_cnt[1:0] == 0, then
18809
  //   MSB of the packet must be written to the LSB of Big ENDIAN Word [31:24])
18810
  if (addr_cnt[1:0] == 2'h1)
18811
    word_cnt = 16; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
18812
  else if (addr_cnt[1:0] == 2'h2)
18813
    word_cnt = 8; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
18814
  else if (addr_cnt[1:0] == 2'h3)
18815
    word_cnt = 0; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
18816
  else
18817
    word_cnt = 24; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
18818 209 tadejm
  crc = 32'hFFFF_FFFF; // INITIAL value
18819 169 mohor
  delta_t = 0;
18820
  // length must include 4 bytes of ZEROs, to generate CRC
18821 209 tadejm
  // get number of nibbles from Byte length (2^1 = 2)
18822 169 mohor
  if (plus_dribble_nibble)
18823 209 tadejm
    nibble_cnt = ((len + 4) << 1) + 1'b1; // one nibble longer
18824 169 mohor
  else
18825 209 tadejm
    nibble_cnt = ((len + 4) << 1);
18826 169 mohor
  load_reg = wb_slave.wb_memory[{12'h0, addr_cnt}];
18827 209 tadejm
  addr_cnt = addr_cnt + 4;
18828
  while (nibble_cnt > 0)
18829 169 mohor
  begin
18830
    // wait for delta time
18831
    delta_t = !delta_t;
18832
    // shift data in
18833 209 tadejm
 
18834
    if(nibble_cnt <= 8) // for additional 8 nibbles shift ZEROs in!
18835
      data_in[3:0] = 4'h0;
18836 169 mohor
    else
18837 209 tadejm
 
18838
      data_in[3:0] = {load_reg[word_cnt], load_reg[word_cnt+1], load_reg[word_cnt+2], load_reg[word_cnt+3]};
18839
    crc_next[0]  = (data_in[0] ^ crc[28]);
18840
    crc_next[1]  = (data_in[1] ^ data_in[0] ^ crc[28]    ^ crc[29]);
18841
    crc_next[2]  = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]);
18842
    crc_next[3]  = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]);
18843
    crc_next[4]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[0];
18844
    crc_next[5]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[1];
18845
    crc_next[6]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[ 2];
18846
    crc_next[7]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[3];
18847
    crc_next[8]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[4];
18848
    crc_next[9]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[5];
18849
    crc_next[10] = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[6];
18850
    crc_next[11] = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[7];
18851
    crc_next[12] = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]) ^ crc[8];
18852
    crc_next[13] = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]) ^ crc[9];
18853
    crc_next[14] = (data_in[3] ^ data_in[2] ^ crc[30]    ^ crc[31]) ^ crc[10];
18854
    crc_next[15] = (data_in[3] ^ crc[31])   ^ crc[11];
18855
    crc_next[16] = (data_in[0] ^ crc[28])   ^ crc[12];
18856
    crc_next[17] = (data_in[1] ^ crc[29])   ^ crc[13];
18857
    crc_next[18] = (data_in[2] ^ crc[30])   ^ crc[14];
18858
    crc_next[19] = (data_in[3] ^ crc[31])   ^ crc[15];
18859
    crc_next[20] =  crc[16];
18860
    crc_next[21] =  crc[17];
18861
    crc_next[22] = (data_in[0] ^ crc[28])   ^ crc[18];
18862
    crc_next[23] = (data_in[1] ^ data_in[0] ^ crc[29]    ^ crc[28]) ^ crc[19];
18863
    crc_next[24] = (data_in[2] ^ data_in[1] ^ crc[30]    ^ crc[29]) ^ crc[20];
18864
    crc_next[25] = (data_in[3] ^ data_in[2] ^ crc[31]    ^ crc[30]) ^ crc[21];
18865
    crc_next[26] = (data_in[3] ^ data_in[0] ^ crc[31]    ^ crc[28]) ^ crc[22];
18866
    crc_next[27] = (data_in[1] ^ crc[29])   ^ crc[23];
18867
    crc_next[28] = (data_in[2] ^ crc[30])   ^ crc[24];
18868
    crc_next[29] = (data_in[3] ^ crc[31])   ^ crc[25];
18869
    crc_next[30] =  crc[26];
18870
    crc_next[31] =  crc[27];
18871
 
18872
    crc = crc_next;
18873
    crc_error = crc[31:0] != 32'hc704dd7b;  // CRC not equal to magic number
18874
    case (nibble_cnt)
18875
    9: crc_out = {!crc[24], !crc[25], !crc[26], !crc[27], !crc[28], !crc[29], !crc[30], !crc[31],
18876
                  !crc[16], !crc[17], !crc[18], !crc[19], !crc[20], !crc[21], !crc[22], !crc[23],
18877
                  !crc[ 8], !crc[ 9], !crc[10], !crc[11], !crc[12], !crc[13], !crc[14], !crc[15],
18878
                  !crc[ 0], !crc[ 1], !crc[ 2], !crc[ 3], !crc[ 4], !crc[ 5], !crc[ 6], !crc[ 7]};
18879
    default: crc_out = crc_out;
18880
    endcase
18881 169 mohor
    // wait for delta time
18882
    delta_t = !delta_t;
18883 209 tadejm
    // increment address and load new data
18884
    if ((word_cnt+3) == 7)//4)
18885 169 mohor
    begin
18886 209 tadejm
      // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
18887
      load_reg = wb_slave.wb_memory[{12'h0, addr_cnt}];
18888 169 mohor
      addr_cnt = addr_cnt + 4;
18889
    end
18890 209 tadejm
    // set new load bit position
18891
    if((word_cnt+3) == 31)
18892 169 mohor
      word_cnt = 16;
18893 209 tadejm
    else if ((word_cnt+3) == 23)
18894 169 mohor
      word_cnt = 8;
18895 209 tadejm
    else if ((word_cnt+3) == 15)
18896 169 mohor
      word_cnt = 0;
18897 209 tadejm
    else if ((word_cnt+3) == 7)
18898 169 mohor
      word_cnt = 24;
18899
    else
18900 209 tadejm
      word_cnt = word_cnt + 4;// - 4;
18901
    // decrement nibble counter
18902
    nibble_cnt = nibble_cnt - 1;
18903 169 mohor
    // wait for delta time
18904
    delta_t = !delta_t;
18905
  end // while
18906
  #1;
18907
end
18908
endtask // paralel_crc_mac
18909
 
18910
// serial CRC checking for PHY TX
18911
task serial_crc_phy_tx;
18912
  input  [31:0] start_addr; // start address
18913
  input  [31:0] len; // length of frame in Bytes without CRC length
18914
  input         plus_dribble_nibble; // if length is longer for one nibble
18915
  output [31:0] crc;
18916
  reg    [21:0] addr_cnt; // only 22 address lines
18917
  integer       word_cnt;
18918
  integer       bit_cnt;
18919
  reg    [31:0] load_reg;
18920
  reg    [31:0] crc_shift_reg;
18921
  reg    [31:0] crc_store_reg;
18922
  reg           delta_t;
18923
begin
18924
  #1 addr_cnt = start_addr[21:0];
18925
  word_cnt = 24; // 27; // start of the frame - nibble granularity (MSbit first)
18926
  crc_store_reg = 32'hFFFF_FFFF; // INITIAL value
18927
  delta_t = 0;
18928
  // length must include 4 bytes of ZEROs, to generate CRC
18929
  // get number of bits from Byte length (2^3 = 8)
18930
  if (plus_dribble_nibble)
18931
    bit_cnt = ((len + 4) << 3) + 3'h4; // one nibble longer
18932
  else
18933
    bit_cnt = ((len + 4) << 3);
18934
  // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
18935
  load_reg[31:24] = eth_phy.tx_mem[addr_cnt];
18936
  addr_cnt = addr_cnt + 1;
18937
  load_reg[23:16] = eth_phy.tx_mem[addr_cnt];
18938
  addr_cnt = addr_cnt + 1;
18939
  load_reg[15: 8] = eth_phy.tx_mem[addr_cnt];
18940
  addr_cnt = addr_cnt + 1;
18941
  load_reg[ 7: 0] = eth_phy.tx_mem[addr_cnt];
18942
  addr_cnt = addr_cnt + 1;
18943
#1;
18944
  while (bit_cnt > 0)
18945
  begin
18946
    // wait for delta time
18947
    delta_t = !delta_t;
18948
#1;
18949
    // shift data in
18950
 
18951
    if(bit_cnt <= 32) // for additional 32 bits shift ZEROs in!
18952
     crc_shift_reg[0] = 1'b0               ^ crc_store_reg[31];
18953
    else
18954
 
18955
     crc_shift_reg[0] = load_reg[word_cnt] ^ crc_store_reg[31];
18956
    crc_shift_reg[1]  = crc_store_reg[0]   ^ crc_store_reg[31];
18957
    crc_shift_reg[2]  = crc_store_reg[1]   ^ crc_store_reg[31];
18958
    crc_shift_reg[3]  = crc_store_reg[2];
18959
    crc_shift_reg[4]  = crc_store_reg[3]   ^ crc_store_reg[31];
18960
    crc_shift_reg[5]  = crc_store_reg[4]   ^ crc_store_reg[31];
18961
    crc_shift_reg[6]  = crc_store_reg[5];
18962
    crc_shift_reg[7]  = crc_store_reg[6]   ^ crc_store_reg[31];
18963
    crc_shift_reg[8]  = crc_store_reg[7]   ^ crc_store_reg[31];
18964
    crc_shift_reg[9]  = crc_store_reg[8];
18965
    crc_shift_reg[10] = crc_store_reg[9]   ^ crc_store_reg[31];
18966
    crc_shift_reg[11] = crc_store_reg[10]  ^ crc_store_reg[31];
18967
    crc_shift_reg[12] = crc_store_reg[11]  ^ crc_store_reg[31];
18968
    crc_shift_reg[13] = crc_store_reg[12];
18969
    crc_shift_reg[14] = crc_store_reg[13];
18970
    crc_shift_reg[15] = crc_store_reg[14];
18971
    crc_shift_reg[16] = crc_store_reg[15]  ^ crc_store_reg[31];
18972
    crc_shift_reg[17] = crc_store_reg[16];
18973
    crc_shift_reg[18] = crc_store_reg[17];
18974
    crc_shift_reg[19] = crc_store_reg[18];
18975
    crc_shift_reg[20] = crc_store_reg[19];
18976
    crc_shift_reg[21] = crc_store_reg[20];
18977
    crc_shift_reg[22] = crc_store_reg[21]  ^ crc_store_reg[31];
18978
    crc_shift_reg[23] = crc_store_reg[22]  ^ crc_store_reg[31];
18979
    crc_shift_reg[24] = crc_store_reg[23];
18980
    crc_shift_reg[25] = crc_store_reg[24];
18981
    crc_shift_reg[26] = crc_store_reg[25]  ^ crc_store_reg[31];
18982
    crc_shift_reg[27] = crc_store_reg[26];
18983
    crc_shift_reg[28] = crc_store_reg[27];
18984
    crc_shift_reg[29] = crc_store_reg[28];
18985
    crc_shift_reg[30] = crc_store_reg[29];
18986
    crc_shift_reg[31] = crc_store_reg[30];
18987
    // wait for delta time
18988
    delta_t = !delta_t;
18989
 
18990
    // store previous data
18991
    crc_store_reg = crc_shift_reg;
18992
 
18993
    // put CRC out
18994
    case (bit_cnt)
18995
    33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 1:
18996
    begin
18997
      crc = crc_store_reg;
18998
      crc = {!crc[24], !crc[25], !crc[26], !crc[27], !crc[28], !crc[29], !crc[30], !crc[31],
18999
             !crc[16], !crc[17], !crc[18], !crc[19], !crc[20], !crc[21], !crc[22], !crc[23],
19000
             !crc[ 8], !crc[ 9], !crc[10], !crc[11], !crc[12], !crc[13], !crc[14], !crc[15],
19001
             !crc[ 0], !crc[ 1], !crc[ 2], !crc[ 3], !crc[ 4], !crc[ 5], !crc[ 6], !crc[ 7]};
19002
    end
19003
    default: crc = crc;
19004
    endcase
19005
 
19006
    // increment address and load new data
19007
#1;
19008
    if (word_cnt == 7)//4)
19009
    begin
19010
      // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
19011
      load_reg[31:24] = eth_phy.tx_mem[addr_cnt];
19012
//      load_reg[31:24] = {load_reg[28], load_reg[29], load_reg[30], load_reg[31], 
19013
//                         load_reg[24], load_reg[25], load_reg[26], load_reg[27]};
19014
      addr_cnt = addr_cnt + 1;
19015
      load_reg[23:16] = eth_phy.tx_mem[addr_cnt];
19016
//      load_reg[23:16] = {load_reg[20], load_reg[21], load_reg[22], load_reg[23], 
19017
//                         load_reg[16], load_reg[17], load_reg[18], load_reg[19]};
19018
      addr_cnt = addr_cnt + 1;
19019
      load_reg[15: 8] = eth_phy.tx_mem[addr_cnt];
19020
//      load_reg[15: 8] = {load_reg[12], load_reg[13], load_reg[14], load_reg[15], 
19021
//                         load_reg[ 8], load_reg[ 9], load_reg[10], load_reg[11]};
19022
      addr_cnt = addr_cnt + 1;
19023
      load_reg[ 7: 0] = eth_phy.tx_mem[addr_cnt];
19024
//      load_reg[ 7: 0] = {load_reg[ 4], load_reg[ 5], load_reg[ 6], load_reg[ 7], 
19025
//                         load_reg[ 0], load_reg[ 1], load_reg[ 2], load_reg[ 3]};
19026
      addr_cnt = addr_cnt + 1;
19027
    end
19028
#1;
19029
    // set new load bit position
19030
    if(word_cnt == 31)
19031
      word_cnt = 16;
19032
    else if (word_cnt == 23)
19033
      word_cnt = 8;
19034
    else if (word_cnt == 15)
19035
      word_cnt = 0;
19036
    else if (word_cnt == 7)
19037
      word_cnt = 24;
19038
 
19039
//   if(word_cnt == 24)
19040
//     word_cnt = 31;
19041
//   else if (word_cnt == 28)
19042
//     word_cnt = 19;
19043
//   else if (word_cnt == 16)
19044
//     word_cnt = 23;
19045
//   else if (word_cnt == 20)
19046
//     word_cnt = 11;
19047
//   else if(word_cnt == 8)
19048
//     word_cnt = 15;
19049
//   else if (word_cnt == 12)
19050
//     word_cnt = 3;
19051
//   else if (word_cnt == 0)
19052
//     word_cnt = 7;
19053
//   else if (word_cnt == 4)
19054
//     word_cnt = 27;
19055
    else
19056
      word_cnt = word_cnt + 1;// - 1;
19057
#1;
19058
    // decrement bit counter
19059
    bit_cnt = bit_cnt - 1;
19060
#1;
19061
    // wait for delta time
19062
    delta_t = !delta_t;
19063
  end // while
19064
 
19065
  #1;
19066
end
19067
endtask // serial_crc_phy_tx
19068
 
19069
// serial CRC calculating for PHY RX
19070
task serial_crc_phy_rx;
19071
  input  [31:0] start_addr; // start address
19072
  input  [31:0] len; // length of frame in Bytes without CRC length
19073
  input         plus_dribble_nibble; // if length is longer for one nibble
19074
  output [31:0] crc;
19075
  reg    [21:0] addr_cnt; // only 22 address lines
19076
  integer       word_cnt;
19077
  integer       bit_cnt;
19078
  reg    [31:0] load_reg;
19079
  reg    [31:0] crc_shift_reg;
19080
  reg    [31:0] crc_store_reg;
19081
  reg           delta_t;
19082
begin
19083
  #1 addr_cnt = start_addr[21:0];
19084
  word_cnt = 24; // start of the frame
19085
  crc_shift_reg = 0;
19086
  delta_t = 0;
19087
  // length must include 4 bytes of ZEROs, to generate CRC
19088
  // get number of bits from Byte length (2^3 = 8)
19089
  if (plus_dribble_nibble)
19090
    bit_cnt = ((len + 4) << 3) + 3'h4; // one nibble longer
19091
  else
19092
    bit_cnt = ((len + 4) << 3);
19093
  load_reg[31:24] = eth_phy.rx_mem[addr_cnt];
19094
  addr_cnt = addr_cnt + 1;
19095
  load_reg[23:16] = eth_phy.rx_mem[addr_cnt];
19096
  addr_cnt = addr_cnt + 1;
19097
  load_reg[15:8]  = eth_phy.rx_mem[addr_cnt];
19098
  addr_cnt = addr_cnt + 1;
19099
  load_reg[7:0]   = eth_phy.rx_mem[addr_cnt];
19100
 
19101
  while (bit_cnt > 0)
19102
  begin
19103
    // wait for delta time
19104
    delta_t = !delta_t;
19105
    // store previous data
19106
    crc_store_reg = crc_shift_reg;
19107
    // shift data in
19108
    if(bit_cnt <= 32) // for additional 32 bits shift ZEROs in!
19109
     crc_shift_reg[0] = 1'b0               ^ crc_store_reg[31];
19110
    else
19111
     crc_shift_reg[0] = load_reg[word_cnt] ^ crc_store_reg[31];
19112
    crc_shift_reg[1]  = crc_store_reg[0]   ^ crc_store_reg[31];
19113
    crc_shift_reg[2]  = crc_store_reg[1]   ^ crc_store_reg[31];
19114
    crc_shift_reg[3]  = crc_store_reg[2];
19115
    crc_shift_reg[4]  = crc_store_reg[3]   ^ crc_store_reg[31];
19116
    crc_shift_reg[5]  = crc_store_reg[4]   ^ crc_store_reg[31];
19117
    crc_shift_reg[6]  = crc_store_reg[5];
19118
    crc_shift_reg[7]  = crc_store_reg[6]   ^ crc_store_reg[31];
19119
    crc_shift_reg[8]  = crc_store_reg[7]   ^ crc_store_reg[31];
19120
    crc_shift_reg[9]  = crc_store_reg[8];
19121
    crc_shift_reg[10] = crc_store_reg[9]   ^ crc_store_reg[31];
19122
    crc_shift_reg[11] = crc_store_reg[10]  ^ crc_store_reg[31];
19123
    crc_shift_reg[12] = crc_store_reg[11]  ^ crc_store_reg[31];
19124
    crc_shift_reg[13] = crc_store_reg[12];
19125
    crc_shift_reg[14] = crc_store_reg[13];
19126
    crc_shift_reg[15] = crc_store_reg[14];
19127
    crc_shift_reg[16] = crc_store_reg[15]  ^ crc_store_reg[31];
19128
    crc_shift_reg[17] = crc_store_reg[16];
19129
    crc_shift_reg[18] = crc_store_reg[17];
19130
    crc_shift_reg[19] = crc_store_reg[18];
19131
    crc_shift_reg[20] = crc_store_reg[19];
19132
    crc_shift_reg[21] = crc_store_reg[20];
19133
    crc_shift_reg[22] = crc_store_reg[21]  ^ crc_store_reg[31];
19134
    crc_shift_reg[23] = crc_store_reg[22]  ^ crc_store_reg[31];
19135
    crc_shift_reg[24] = crc_store_reg[23];
19136
    crc_shift_reg[25] = crc_store_reg[24];
19137
    crc_shift_reg[26] = crc_store_reg[25]  ^ crc_store_reg[31];
19138
    crc_shift_reg[27] = crc_store_reg[26];
19139
    crc_shift_reg[28] = crc_store_reg[27];
19140
    crc_shift_reg[29] = crc_store_reg[28];
19141
    crc_shift_reg[30] = crc_store_reg[29];
19142
    crc_shift_reg[31] = crc_store_reg[30];
19143
    // wait for delta time
19144
    delta_t = !delta_t;
19145
    // increment address and load new data
19146
    if (word_cnt == 7)
19147
    begin
19148
      addr_cnt = addr_cnt + 1;
19149
      load_reg[31:24] = eth_phy.rx_mem[addr_cnt];
19150
      addr_cnt = addr_cnt + 1;
19151
      load_reg[23:16] = eth_phy.rx_mem[addr_cnt];
19152
      addr_cnt = addr_cnt + 1;
19153
      load_reg[15:8]  = eth_phy.rx_mem[addr_cnt];
19154
      addr_cnt = addr_cnt + 1;
19155
      load_reg[7:0]   = eth_phy.rx_mem[addr_cnt];
19156
    end
19157
    // set new load bit position
19158
    if(word_cnt == 31)
19159
      word_cnt = 16;
19160
    else if (word_cnt == 23)
19161
      word_cnt = 8;
19162
    else if (word_cnt == 15)
19163
      word_cnt = 0;
19164
    else if (word_cnt == 7)
19165
      word_cnt = 24;
19166
    else
19167
      word_cnt = word_cnt + 1;
19168
    // decrement bit counter
19169
    bit_cnt = bit_cnt - 1;
19170
    // wait for delta time
19171
    delta_t = !delta_t;
19172
  end // while
19173
 
19174
  // put CRC out
19175
  crc = crc_shift_reg;
19176
  #1;
19177
end
19178
endtask // serial_crc_phy_rx
19179
 
19180
// serial CRC checking for MAC
19181
task serial_crc_mac;
19182
  input  [31:0] start_addr; // start address
19183
  input  [31:0] len; // length of frame in Bytes without CRC length
19184
  input         plus_dribble_nibble; // if length is longer for one nibble
19185
  output [31:0] crc;
19186
  reg    [19:0] addr_cnt; // only 20 address lines
19187
  integer       word_cnt;
19188
  integer       bit_cnt;
19189
  reg    [31:0] load_reg;
19190
  reg    [31:0] crc_shift_reg;
19191
  reg    [31:0] crc_store_reg;
19192
  reg           delta_t;
19193
begin
19194
  #1 addr_cnt = start_addr[19:0];
19195
  // set starting point depending with which byte frame starts (e.g. if addr_cnt[1:0] == 0, then
19196
  //   MSB of the packet must be written to the LSB of Big ENDIAN Word [31:24])
19197
  if (addr_cnt[1:0] == 2'h1)
19198
    word_cnt = 16; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
19199
  else if (addr_cnt[1:0] == 2'h2)
19200
    word_cnt = 8; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
19201
  else if (addr_cnt[1:0] == 2'h3)
19202
    word_cnt = 0; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
19203
  else
19204
    word_cnt = 24; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
19205
 
19206
  crc_shift_reg = 0;
19207
  delta_t = 0;
19208
  // length must include 4 bytes of ZEROs, to generate CRC
19209
  // get number of bits from Byte length (2^3 = 8)
19210
  if (plus_dribble_nibble)
19211
    bit_cnt = ((len + 4) << 3) + 3'h4; // one nibble longer
19212
  else
19213
    bit_cnt = ((len + 4) << 3);
19214
  load_reg = wb_slave.wb_memory[{12'h0, addr_cnt}];
19215
 
19216
  while (bit_cnt > 0)
19217
  begin
19218
    // wait for delta time
19219
    delta_t = !delta_t;
19220
    // store previous data
19221
    crc_store_reg = crc_shift_reg;
19222
    // shift data in
19223
    if(bit_cnt <= 32) // for additional 32 bits shift ZEROs in!
19224
     crc_shift_reg[0] = 1'b0               ^ crc_store_reg[31];
19225
    else
19226
     crc_shift_reg[0] = load_reg[word_cnt] ^ crc_store_reg[31];
19227
    crc_shift_reg[1]  = crc_store_reg[0]   ^ crc_store_reg[31];
19228
    crc_shift_reg[2]  = crc_store_reg[1]   ^ crc_store_reg[31];
19229
    crc_shift_reg[3]  = crc_store_reg[2];
19230
    crc_shift_reg[4]  = crc_store_reg[3]   ^ crc_store_reg[31];
19231
    crc_shift_reg[5]  = crc_store_reg[4]   ^ crc_store_reg[31];
19232
    crc_shift_reg[6]  = crc_store_reg[5];
19233
    crc_shift_reg[7]  = crc_store_reg[6]   ^ crc_store_reg[31];
19234
    crc_shift_reg[8]  = crc_store_reg[7]   ^ crc_store_reg[31];
19235
    crc_shift_reg[9]  = crc_store_reg[8];
19236
    crc_shift_reg[10] = crc_store_reg[9]   ^ crc_store_reg[31];
19237
    crc_shift_reg[11] = crc_store_reg[10]  ^ crc_store_reg[31];
19238
    crc_shift_reg[12] = crc_store_reg[11]  ^ crc_store_reg[31];
19239
    crc_shift_reg[13] = crc_store_reg[12];
19240
    crc_shift_reg[14] = crc_store_reg[13];
19241
    crc_shift_reg[15] = crc_store_reg[14];
19242
    crc_shift_reg[16] = crc_store_reg[15]  ^ crc_store_reg[31];
19243
    crc_shift_reg[17] = crc_store_reg[16];
19244
    crc_shift_reg[18] = crc_store_reg[17];
19245
    crc_shift_reg[19] = crc_store_reg[18];
19246
    crc_shift_reg[20] = crc_store_reg[19];
19247
    crc_shift_reg[21] = crc_store_reg[20];
19248
    crc_shift_reg[22] = crc_store_reg[21]  ^ crc_store_reg[31];
19249
    crc_shift_reg[23] = crc_store_reg[22]  ^ crc_store_reg[31];
19250
    crc_shift_reg[24] = crc_store_reg[23];
19251
    crc_shift_reg[25] = crc_store_reg[24];
19252
    crc_shift_reg[26] = crc_store_reg[25]  ^ crc_store_reg[31];
19253
    crc_shift_reg[27] = crc_store_reg[26];
19254
    crc_shift_reg[28] = crc_store_reg[27];
19255
    crc_shift_reg[29] = crc_store_reg[28];
19256
    crc_shift_reg[30] = crc_store_reg[29];
19257
    crc_shift_reg[31] = crc_store_reg[30];
19258
    // wait for delta time
19259
    delta_t = !delta_t;
19260
    // increment address and load new data for Big ENDIAN Bytes (Litle ENDIAN bits)
19261
    if (word_cnt == 7)
19262
    begin
19263
      addr_cnt = addr_cnt + 4;
19264
      load_reg = wb_slave.wb_memory[{12'h0, addr_cnt}];
19265
    end
19266
    // set new load bit position for Big ENDIAN Bytes (Litle ENDIAN bits)
19267
    if(word_cnt == 31)
19268
      word_cnt = 16;
19269
    else if (word_cnt == 23)
19270
      word_cnt = 8;
19271
    else if (word_cnt == 15)
19272
      word_cnt = 0;
19273
    else if (word_cnt == 7)
19274
      word_cnt = 24;
19275
    else
19276
      word_cnt = word_cnt + 1;
19277
    // decrement bit counter
19278
    bit_cnt = bit_cnt - 1;
19279
    // wait for delta time
19280
    delta_t = !delta_t;
19281
  end // while
19282
 
19283
  // put CRC out
19284
  crc = crc_shift_reg;
19285
  #1;
19286
end
19287
endtask // serial_crc_mac
19288
 
19289
//////////////////////////////////////////////////////////////
19290
// MIIM Basic tasks
19291
//////////////////////////////////////////////////////////////
19292
 
19293
task reset_mii; //  MII module
19294
  reg [31:0] tmp;
19295
  reg [31:0] tmp_no_rst;
19296
begin
19297
  // read MII mode register first
19298
  wbm_read(`ETH_MIIMODER, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19299
  // set reset bit - write back to MII mode register with RESET bit
19300
  wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_RST | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19301
  // clear reset bit - write back to MII mode register without RESET bit
19302
  tmp_no_rst = `ETH_MIIMODER_RST;
19303
  tmp_no_rst = ~tmp_no_rst;
19304
  wbm_write(`ETH_MIIMODER, (tmp_no_rst & tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19305
end
19306
endtask // reset_mii
19307
 
19308
task mii_set_clk_div; // set clock divider for MII clock
19309
  input [7:0]  clk_div;
19310
begin
19311
  // MII mode register
19312
  wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_CLKDIV & clk_div), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19313
end
19314
endtask // mii_set_clk_div
19315
 
19316
 
19317
task check_mii_busy; // MII - check if BUSY
19318
  reg [31:0] tmp;
19319
begin
19320
  @(posedge wb_clk);
19321
  // MII read status register
19322
  wbm_read(`ETH_MIISTATUS, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19323
  while(tmp[`ETH_MIISTATUS_BUSY] !== 1'b0) //`ETH_MIISTATUS_BUSY
19324
  begin
19325
    @(posedge wb_clk);
19326
    wbm_read(`ETH_MIISTATUS, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19327
  end
19328
end
19329
endtask // check_mii_busy
19330
 
19331
 
19332
task check_mii_scan_valid; // MII - check if SCAN data are valid
19333
  reg [31:0] tmp;
19334
begin
19335
  @(posedge wb_clk);
19336
  // MII read status register
19337
  wbm_read(`ETH_MIISTATUS, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19338
  while(tmp[`ETH_MIISTATUS_NVALID] !== 1'b0) //`ETH_MIISTATUS_NVALID
19339
  begin
19340
    @(posedge wb_clk);
19341
    wbm_read(`ETH_MIISTATUS, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19342
  end
19343
end
19344
endtask // check_mii_scan_valid
19345
 
19346
 
19347
task mii_write_req; // requests write to MII
19348
  input [4:0]  phy_addr;
19349
  input [4:0]  reg_addr;
19350
  input [15:0] data_in;
19351
begin
19352
  // MII address, PHY address = 1, command register address = 0
19353
  wbm_write(`ETH_MIIADDRESS, (`ETH_MIIADDRESS_FIAD & phy_addr) | (`ETH_MIIADDRESS_RGAD & (reg_addr << 8)),
19354
            4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19355
  // MII TX data
19356
  wbm_write(`ETH_MIITX_DATA, {16'h0000, data_in}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19357
  // MII command
19358
  wbm_write(`ETH_MIICOMMAND, `ETH_MIICOMMAND_WCTRLDATA, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19359
  @(posedge wb_clk);
19360
end
19361
endtask // mii_write_req
19362
 
19363
 
19364
task mii_read_req; // requests read from MII
19365
  input [4:0]  phy_addr;
19366
  input [4:0]  reg_addr;
19367
begin
19368
  // MII address, PHY address = 1, command register address = 0
19369
  wbm_write(`ETH_MIIADDRESS, (`ETH_MIIADDRESS_FIAD & phy_addr) | (`ETH_MIIADDRESS_RGAD & (reg_addr << 8)),
19370
            4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19371
  // MII command
19372
  wbm_write(`ETH_MIICOMMAND, `ETH_MIICOMMAND_RSTAT, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19373
  @(posedge wb_clk);
19374
end
19375
endtask // mii_read_req
19376
 
19377
 
19378
task mii_scan_req; // requests scan from MII
19379
  input [4:0]  phy_addr;
19380
  input [4:0]  reg_addr;
19381
begin
19382
  // MII address, PHY address = 1, command register address = 0
19383
  wbm_write(`ETH_MIIADDRESS, (`ETH_MIIADDRESS_FIAD & phy_addr) | (`ETH_MIIADDRESS_RGAD & (reg_addr << 8)),
19384
            4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19385
  // MII command
19386
  wbm_write(`ETH_MIICOMMAND, `ETH_MIICOMMAND_SCANSTAT, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19387
  @(posedge wb_clk);
19388
end
19389
endtask // mii_scan_req
19390
 
19391
 
19392
task mii_scan_finish; // finish scan from MII
19393
begin
19394
  // MII command
19395
  wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19396
  @(posedge wb_clk);
19397
end
19398
endtask // mii_scan_finish
19399
 
19400
//////////////////////////////////////////////////////////////
19401
// Log files and memory tasks
19402
//////////////////////////////////////////////////////////////
19403
 
19404
task clear_memories;
19405
  reg    [22:0]  adr_i;
19406
  reg            delta_t;
19407
begin
19408
  for (adr_i = 0; adr_i < 4194304; adr_i = adr_i + 1)
19409
  begin
19410
    eth_phy.rx_mem[adr_i[21:0]] = 0;
19411
    eth_phy.tx_mem[adr_i[21:0]] = 0;
19412
    wb_slave.wb_memory[adr_i[21:2]] = 0;
19413
  end
19414
end
19415
endtask // clear_memories
19416
 
19417 243 tadejm
task clear_buffer_descriptors;
19418
  reg    [8:0]  adr_i;
19419
  reg            delta_t;
19420
begin
19421
  delta_t = 0;
19422
  for (adr_i = 0; adr_i < 256; adr_i = adr_i + 1)
19423
  begin
19424
    wbm_write((`TX_BD_BASE + {adr_i[7:0], 2'b0}), 32'h0, 4'hF, 1, 4'h1, 4'h1);
19425
    delta_t = !delta_t;
19426
  end
19427
end
19428
endtask // clear_buffer_descriptors
19429
 
19430 169 mohor
task test_note;
19431
  input [799:0] test_note ;
19432
  reg   [799:0] display_note ;
19433
begin
19434
  display_note = test_note;
19435
  while ( display_note[799:792] == 0 )
19436
    display_note = display_note << 8 ;
19437
  $fdisplay( tb_log_file, " " ) ;
19438
  $fdisplay( tb_log_file, "NOTE: %s", display_note ) ;
19439
  $fdisplay( tb_log_file, " " ) ;
19440
end
19441
endtask // test_note
19442
 
19443
task test_heading;
19444
  input [799:0] test_heading ;
19445
  reg   [799:0] display_test ;
19446
begin
19447
  display_test = test_heading;
19448
  while ( display_test[799:792] == 0 )
19449
    display_test = display_test << 8 ;
19450
  $fdisplay( tb_log_file, "  ***************************************************************************************" ) ;
19451
  $fdisplay( tb_log_file, "  ***************************************************************************************" ) ;
19452
  $fdisplay( tb_log_file, "  Heading: %s", display_test ) ;
19453
  $fdisplay( tb_log_file, "  ***************************************************************************************" ) ;
19454
  $fdisplay( tb_log_file, "  ***************************************************************************************" ) ;
19455
  $fdisplay( tb_log_file, " " ) ;
19456
end
19457
endtask // test_heading
19458
 
19459
 
19460
task test_fail ;
19461
  input [7999:0] failure_reason ;
19462
//  reg   [8007:0] display_failure ;
19463
  reg   [7999:0] display_failure ;
19464
  reg   [799:0] display_test ;
19465
begin
19466
  tests_failed = tests_failed + 1 ;
19467
 
19468
  display_failure = failure_reason; // {failure_reason, "!"} ;
19469
  while ( display_failure[7999:7992] == 0 )
19470
    display_failure = display_failure << 8 ;
19471
 
19472
  display_test = test_name ;
19473
  while ( display_test[799:792] == 0 )
19474
    display_test = display_test << 8 ;
19475
 
19476
  $fdisplay( tb_log_file, "    *************************************************************************************" ) ;
19477
  $fdisplay( tb_log_file, "    At time: %t ", $time ) ;
19478
  $fdisplay( tb_log_file, "    Test: %s", display_test ) ;
19479
  $fdisplay( tb_log_file, "    *FAILED* because") ;
19480
  $fdisplay( tb_log_file, "    %s", display_failure ) ;
19481
  $fdisplay( tb_log_file, "    *************************************************************************************" ) ;
19482
  $fdisplay( tb_log_file, " " ) ;
19483
 
19484
 `ifdef STOP_ON_FAILURE
19485
    #20 $stop ;
19486
 `endif
19487
end
19488
endtask // test_fail
19489
 
19490
 
19491
task test_ok ;
19492
  reg [799:0] display_test ;
19493
begin
19494
  tests_successfull = tests_successfull + 1 ;
19495
 
19496
  display_test = test_name ;
19497
  while ( display_test[799:792] == 0 )
19498
    display_test = display_test << 8 ;
19499
 
19500
  $fdisplay( tb_log_file, "    *************************************************************************************" ) ;
19501
  $fdisplay( tb_log_file, "    At time: %t ", $time ) ;
19502
  $fdisplay( tb_log_file, "    Test: %s", display_test ) ;
19503
  $fdisplay( tb_log_file, "    reported *SUCCESSFULL*! ") ;
19504
  $fdisplay( tb_log_file, "    *************************************************************************************" ) ;
19505
  $fdisplay( tb_log_file, " " ) ;
19506
end
19507
endtask // test_ok
19508
 
19509
 
19510
task test_summary;
19511
begin
19512
  $fdisplay(tb_log_file, "**************************** Ethernet MAC test summary **********************************") ;
19513
  $fdisplay(tb_log_file, "Tests performed:   %d", tests_successfull + tests_failed) ;
19514
  $fdisplay(tb_log_file, "Failed tests   :   %d", tests_failed) ;
19515
  $fdisplay(tb_log_file, "Successfull tests: %d", tests_successfull) ;
19516
  $fdisplay(tb_log_file, "**************************** Ethernet MAC test summary **********************************") ;
19517
  $fclose(tb_log_file) ;
19518
end
19519
endtask // test_summary
19520
 
19521
 
19522 116 mohor
endmodule

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