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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Blame information for rev 299

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1 116 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  tb_ethernet.v                                               ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9 169 mohor
////      - Tadej Markovic, tadej@opencores.org                   ////
10 243 tadejm
////      - Igor Mohor,     igorM@opencores.org                  ////
11 116 mohor
////                                                              ////
12 169 mohor
////  All additional information is available in the Readme.txt   ////
13 116 mohor
////  file.                                                       ////
14
////                                                              ////
15
//////////////////////////////////////////////////////////////////////
16
////                                                              ////
17
//// Copyright (C) 2001, 2002 Authors                             ////
18
////                                                              ////
19
//// This source file may be used and distributed without         ////
20
//// restriction provided that this copyright statement is not    ////
21
//// removed from the file and that any derivative work contains  ////
22
//// the original copyright notice and the associated disclaimer. ////
23
////                                                              ////
24
//// This source file is free software; you can redistribute it   ////
25
//// and/or modify it under the terms of the GNU Lesser General   ////
26
//// Public License as published by the Free Software Foundation; ////
27
//// either version 2.1 of the License, or (at your option) any   ////
28
//// later version.                                               ////
29
////                                                              ////
30
//// This source is distributed in the hope that it will be       ////
31
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
32
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
33
//// PURPOSE.  See the GNU Lesser General Public License for more ////
34
//// details.                                                     ////
35
////                                                              ////
36
//// You should have received a copy of the GNU Lesser General    ////
37
//// Public License along with this source; if not, download it   ////
38
//// from http://www.opencores.org/lgpl.shtml                     ////
39
////                                                              ////
40
//////////////////////////////////////////////////////////////////////
41
//
42
// CVS Revision History
43
//
44
// $Log: not supported by cvs2svn $
45 299 mohor
// Revision 1.28  2003/01/31 15:58:27  mohor
46
// Tests test_mac_full_duplex_receive 4-7  fixed to proper BD.
47
//
48 281 mohor
// Revision 1.27  2003/01/30 13:38:15  mohor
49
// Underrun test fixed. Many other tests fixed.
50
//
51 279 mohor
// Revision 1.26  2003/01/22 19:40:10  tadejm
52
// Backup version. Not fully working.
53
//
54 274 tadejm
// Revision 1.25  2002/11/27 16:21:55  mohor
55
// Full duplex control frames tested.
56
//
57 267 mohor
// Revision 1.24  2002/11/22 17:29:42  mohor
58
// Flow control test almost finished.
59
//
60 266 mohor
// Revision 1.23  2002/11/22 02:12:16  mohor
61
// test_mac_full_duplex_flow_control tests pretty much finished.
62
// TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
63
// FRM. AT 4 TX BD ( 10Mbps ) finished.
64
// TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
65
// TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
66
//
67 263 mohor
// Revision 1.22  2002/11/21 13:56:50  mohor
68
// test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
69
// finished.
70
//
71 260 mohor
// Revision 1.21  2002/11/19 20:27:45  mohor
72
// Temp version.
73
//
74 254 mohor
// Revision 1.20  2002/11/19 17:41:19  tadejm
75
// Just some updates.
76
//
77 252 tadejm
// Revision 1.19  2002/11/14 13:12:47  tadejm
78
// Late collision is not reported any more.
79
//
80 243 tadejm
// Revision 1.18  2002/10/18 17:03:34  tadejm
81
// Changed BIST scan signals.
82
//
83 227 tadejm
// Revision 1.17  2002/10/18 13:58:22  tadejm
84
// Some code changed due to bug fixes.
85
//
86 223 tadejm
// Revision 1.16  2002/10/09 13:16:51  tadejm
87
// Just back-up; not completed testbench and some testcases are not
88
// wotking properly yet.
89
//
90 209 tadejm
// Revision 1.15  2002/09/20 14:29:12  tadej
91
// Full duplex tests modified and testbench bug repaired.
92
//
93 194 tadej
// Revision 1.14  2002/09/18 17:56:38  tadej
94
// Some additional reports added
95
//
96 192 tadej
// Revision 1.13  2002/09/16 17:53:49  tadej
97
// Full duplex test improved.
98
//
99 182 tadej
// Revision 1.12  2002/09/16 15:10:42  mohor
100
// MIIM test look better.
101
//
102 181 mohor
// Revision 1.11  2002/09/13 19:18:04  mohor
103
// Bench outputs data to display every 128 bytes.
104
//
105 180 mohor
// Revision 1.10  2002/09/13 18:44:29  mohor
106
// Beautiful tests merget together
107
//
108 179 mohor
// Revision 1.9  2002/09/13 18:41:45  mohor
109
// Rearanged testcases
110
//
111 178 mohor
// Revision 1.8  2002/09/13 14:50:15  mohor
112
// Bug in MIIM fixed.
113
//
114 177 mohor
// Revision 1.7  2002/09/13 12:29:14  mohor
115
// Headers changed.
116
//
117 170 mohor
// Revision 1.6  2002/09/13 11:57:20  mohor
118
// New testbench. Thanks to Tadej M - "The Spammer".
119
//
120 121 mohor
// Revision 1.2  2002/07/19 14:02:47  mohor
121
// Clock mrx_clk set to 2.5 MHz.
122
//
123 117 mohor
// Revision 1.1  2002/07/19 13:57:53  mohor
124
// Testing environment also includes traffic cop, memory interface and host
125
// interface.
126 116 mohor
//
127
//
128
//
129
//
130 117 mohor
//
131 116 mohor
 
132
 
133 169 mohor
`include "eth_phy_defines.v"
134
`include "wb_model_defines.v"
135 116 mohor
`include "tb_eth_defines.v"
136
`include "eth_defines.v"
137
`include "timescale.v"
138
 
139
module tb_ethernet();
140
 
141
 
142 169 mohor
reg           wb_clk;
143
reg           wb_rst;
144
wire          wb_int;
145 116 mohor
 
146 169 mohor
wire          mtx_clk;  // This goes to PHY
147
wire          mrx_clk;  // This goes to PHY
148 116 mohor
 
149
wire   [3:0]  MTxD;
150
wire          MTxEn;
151
wire          MTxErr;
152
 
153 169 mohor
wire   [3:0]  MRxD;     // This goes to PHY
154
wire          MRxDV;    // This goes to PHY
155
wire          MRxErr;   // This goes to PHY
156
wire          MColl;    // This goes to PHY
157
wire          MCrs;     // This goes to PHY
158 116 mohor
 
159
wire          Mdi_I;
160
wire          Mdo_O;
161
wire          Mdo_OE;
162 169 mohor
tri           Mdio_IO;
163 116 mohor
wire          Mdc_O;
164
 
165
 
166 169 mohor
parameter Tp = 1;
167 116 mohor
 
168 121 mohor
 
169 116 mohor
// Ethernet Slave Interface signals
170 169 mohor
wire [31:0] eth_sl_wb_adr;
171 116 mohor
wire [31:0] eth_sl_wb_adr_i, eth_sl_wb_dat_o, eth_sl_wb_dat_i;
172
wire  [3:0] eth_sl_wb_sel_i;
173
wire        eth_sl_wb_we_i, eth_sl_wb_cyc_i, eth_sl_wb_stb_i, eth_sl_wb_ack_o, eth_sl_wb_err_o;
174
 
175
// Ethernet Master Interface signals
176
wire [31:0] eth_ma_wb_adr_o, eth_ma_wb_dat_i, eth_ma_wb_dat_o;
177
wire  [3:0] eth_ma_wb_sel_o;
178
wire        eth_ma_wb_we_o, eth_ma_wb_cyc_o, eth_ma_wb_stb_o, eth_ma_wb_ack_i, eth_ma_wb_err_i;
179
 
180
 
181
 
182
 
183
// Connecting Ethernet top module
184 169 mohor
eth_top eth_top
185 116 mohor
(
186
  // WISHBONE common
187 169 mohor
  .wb_clk_i(wb_clk),              .wb_rst_i(wb_rst),
188 116 mohor
 
189
  // WISHBONE slave
190 169 mohor
  .wb_adr_i(eth_sl_wb_adr_i[11:2]), .wb_sel_i(eth_sl_wb_sel_i),   .wb_we_i(eth_sl_wb_we_i),
191
  .wb_cyc_i(eth_sl_wb_cyc_i),       .wb_stb_i(eth_sl_wb_stb_i),   .wb_ack_o(eth_sl_wb_ack_o),
192
  .wb_err_o(eth_sl_wb_err_o),       .wb_dat_i(eth_sl_wb_dat_i),   .wb_dat_o(eth_sl_wb_dat_o),
193 116 mohor
 
194
  // WISHBONE master
195
  .m_wb_adr_o(eth_ma_wb_adr_o),     .m_wb_sel_o(eth_ma_wb_sel_o), .m_wb_we_o(eth_ma_wb_we_o),
196
  .m_wb_dat_i(eth_ma_wb_dat_i),     .m_wb_dat_o(eth_ma_wb_dat_o), .m_wb_cyc_o(eth_ma_wb_cyc_o),
197
  .m_wb_stb_o(eth_ma_wb_stb_o),     .m_wb_ack_i(eth_ma_wb_ack_i), .m_wb_err_i(eth_ma_wb_err_i),
198
 
199
  //TX
200
  .mtx_clk_pad_i(mtx_clk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
201
 
202
  //RX
203
  .mrx_clk_pad_i(mrx_clk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
204
  .mcoll_pad_i(MColl),    .mcrs_pad_i(MCrs),
205
 
206
  // MIIM
207
  .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoe_o(Mdo_OE),
208
 
209 169 mohor
  .int_o(wb_int)
210 227 tadejm
 
211
  // Bist
212
`ifdef ETH_BIST
213
  ,
214 299 mohor
  .scanb_rst      (1'b1),
215 227 tadejm
  .scanb_clk      (1'b0),
216
  .scanb_si       (1'b0),
217
  .scanb_so       (),
218
  .scanb_en       (1'b0)
219
`endif
220 116 mohor
);
221
 
222
 
223
 
224 169 mohor
// Connecting Ethernet PHY Module
225
assign Mdio_IO = Mdo_OE ? Mdo_O : 1'bz ;
226
assign Mdi_I   = Mdio_IO;
227
integer phy_log_file_desc;
228
 
229
eth_phy eth_phy
230 116 mohor
(
231 169 mohor
  // WISHBONE reset
232
  .m_rst_n_i(!wb_rst),
233 116 mohor
 
234 169 mohor
  // MAC TX
235
  .mtx_clk_o(mtx_clk),    .mtxd_i(MTxD),    .mtxen_i(MTxEn),    .mtxerr_i(MTxErr),
236
 
237
  // MAC RX
238
  .mrx_clk_o(mrx_clk),    .mrxd_o(MRxD),    .mrxdv_o(MRxDV),    .mrxerr_o(MRxErr),
239
  .mcoll_o(MColl),        .mcrs_o(MCrs),
240
 
241
  // MIIM
242
  .mdc_i(Mdc_O),          .md_io(Mdio_IO),
243
 
244
  // SYSTEM
245
  .phy_log(phy_log_file_desc)
246 116 mohor
);
247
 
248
 
249 169 mohor
 
250
// Connecting WB Master as Host Interface
251
integer host_log_file_desc;
252
 
253
WB_MASTER_BEHAVIORAL wb_master
254 116 mohor
(
255 169 mohor
    .CLK_I(wb_clk),
256
    .RST_I(wb_rst),
257
    .TAG_I({`WB_TAG_WIDTH{1'b0}}),
258
    .TAG_O(),
259
    .ACK_I(eth_sl_wb_ack_o),
260
    .ADR_O(eth_sl_wb_adr), // only eth_sl_wb_adr_i[11:2] used
261
    .CYC_O(eth_sl_wb_cyc_i),
262
    .DAT_I(eth_sl_wb_dat_o),
263
    .DAT_O(eth_sl_wb_dat_i),
264
    .ERR_I(eth_sl_wb_err_o),
265
    .RTY_I(1'b0),  // inactive (1'b0)
266
    .SEL_O(eth_sl_wb_sel_i),
267
    .STB_O(eth_sl_wb_stb_i),
268
    .WE_O (eth_sl_wb_we_i),
269
    .CAB_O()       // NOT USED for now!
270
);
271
 
272
assign eth_sl_wb_adr_i = {20'h0, eth_sl_wb_adr[11:2], 2'h0};
273
 
274
 
275
 
276
// Connecting WB Slave as Memory Interface Module
277
integer memory_log_file_desc;
278
 
279
WB_SLAVE_BEHAVIORAL wb_slave
280
(
281
    .CLK_I(wb_clk),
282
    .RST_I(wb_rst),
283
    .ACK_O(eth_ma_wb_ack_i),
284
    .ADR_I(eth_ma_wb_adr_o),
285
    .CYC_I(eth_ma_wb_cyc_o),
286
    .DAT_O(eth_ma_wb_dat_i),
287
    .DAT_I(eth_ma_wb_dat_o),
288
    .ERR_O(eth_ma_wb_err_i),
289
    .RTY_O(),      // NOT USED for now!
290
    .SEL_I(eth_ma_wb_sel_o),
291
    .STB_I(eth_ma_wb_stb_o),
292
    .WE_I (eth_ma_wb_we_o),
293
    .CAB_I(1'b0)   // inactive (1'b0)
294
);
295
 
296
 
297
 
298
// Connecting WISHBONE Bus Monitors to ethernet master and slave interfaces
299
integer wb_s_mon_log_file_desc ;
300
integer wb_m_mon_log_file_desc ;
301
 
302
WB_BUS_MON wb_eth_slave_bus_mon
303
(
304 116 mohor
  // WISHBONE common
305 169 mohor
  .CLK_I(wb_clk),
306
  .RST_I(wb_rst),
307 116 mohor
 
308 169 mohor
  // WISHBONE slave
309
  .ACK_I(eth_sl_wb_ack_o),
310
  .ADDR_O({20'h0, eth_sl_wb_adr_i[11:2], 2'b0}),
311
  .CYC_O(eth_sl_wb_cyc_i),
312
  .DAT_I(eth_sl_wb_dat_o),
313
  .DAT_O(eth_sl_wb_dat_i),
314
  .ERR_I(eth_sl_wb_err_o),
315
  .RTY_I(1'b0),
316
  .SEL_O(eth_sl_wb_sel_i),
317
  .STB_O(eth_sl_wb_stb_i),
318
  .WE_O (eth_sl_wb_we_i),
319
  .TAG_I({`WB_TAG_WIDTH{1'b0}}),
320
  .TAG_O(),
321
  .CAB_O(1'b0),
322
  .log_file_desc (wb_s_mon_log_file_desc)
323
);
324
 
325
WB_BUS_MON wb_eth_master_bus_mon
326
(
327
  // WISHBONE common
328
  .CLK_I(wb_clk),
329
  .RST_I(wb_rst),
330
 
331 116 mohor
  // WISHBONE master
332 169 mohor
  .ACK_I(eth_ma_wb_ack_i),
333
  .ADDR_O(eth_ma_wb_adr_o),
334
  .CYC_O(eth_ma_wb_cyc_o),
335
  .DAT_I(eth_ma_wb_dat_i),
336
  .DAT_O(eth_ma_wb_dat_o),
337
  .ERR_I(eth_ma_wb_err_i),
338
  .RTY_I(1'b0),
339
  .SEL_O(eth_ma_wb_sel_o),
340
  .STB_O(eth_ma_wb_stb_o),
341
  .WE_O (eth_ma_wb_we_o),
342
  .TAG_I({`WB_TAG_WIDTH{1'b0}}),
343
  .TAG_O(),
344
  .CAB_O(1'b0),
345
  .log_file_desc(wb_m_mon_log_file_desc)
346 116 mohor
);
347
 
348
 
349
 
350 169 mohor
reg         StartTB;
351
integer     tb_log_file;
352 116 mohor
 
353 169 mohor
initial
354
begin
355
  tb_log_file = $fopen("../log/eth_tb.log");
356
  if (tb_log_file < 2)
357
  begin
358
    $display("*E Could not open/create testbench log file in ../log/ directory!");
359
    $finish;
360
  end
361
  $fdisplay(tb_log_file, "========================== ETHERNET IP Core Testbench results ===========================");
362
  $fdisplay(tb_log_file, " ");
363 116 mohor
 
364 169 mohor
  phy_log_file_desc = $fopen("../log/eth_tb_phy.log");
365
  if (phy_log_file_desc < 2)
366
  begin
367
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_phy.log file in ../log/ directory!");
368
    $finish;
369
  end
370
  $fdisplay(phy_log_file_desc, "================ PHY Module  Testbench access log ================");
371
  $fdisplay(phy_log_file_desc, " ");
372
 
373
  memory_log_file_desc = $fopen("../log/eth_tb_memory.log");
374
  if (memory_log_file_desc < 2)
375
  begin
376
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_memory.log file in ../log/ directory!");
377
    $finish;
378
  end
379
  $fdisplay(memory_log_file_desc, "=============== MEMORY Module Testbench access log ===============");
380
  $fdisplay(memory_log_file_desc, " ");
381
 
382
  host_log_file_desc = $fopen("../log/eth_tb_host.log");
383
  if (host_log_file_desc < 2)
384
  begin
385
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_host.log file in ../log/ directory!");
386
    $finish;
387
  end
388
  $fdisplay(host_log_file_desc, "================ HOST Module Testbench access log ================");
389
  $fdisplay(host_log_file_desc, " ");
390
 
391
  wb_s_mon_log_file_desc = $fopen("../log/eth_tb_wb_s_mon.log");
392
  if (wb_s_mon_log_file_desc < 2)
393
  begin
394
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_wb_s_mon.log file in ../log/ directory!");
395
    $finish;
396
  end
397
  $fdisplay(wb_s_mon_log_file_desc, "============== WISHBONE Slave Bus Monitor error log ==============");
398
  $fdisplay(wb_s_mon_log_file_desc, " ");
399
  $fdisplay(wb_s_mon_log_file_desc, "   Only ERRONEOUS conditions are logged !");
400
  $fdisplay(wb_s_mon_log_file_desc, " ");
401
 
402
  wb_m_mon_log_file_desc = $fopen("../log/eth_tb_wb_m_mon.log");
403
  if (wb_m_mon_log_file_desc < 2)
404
  begin
405
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_wb_m_mon.log file in ../log/ directory!");
406
    $finish;
407
  end
408
  $fdisplay(wb_m_mon_log_file_desc, "============= WISHBONE Master Bus Monitor  error log =============");
409
  $fdisplay(wb_m_mon_log_file_desc, " ");
410
  $fdisplay(wb_m_mon_log_file_desc, "   Only ERRONEOUS conditions are logged !");
411
  $fdisplay(wb_m_mon_log_file_desc, " ");
412
 
413 243 tadejm
  // Reset pulse
414
  wb_rst =  1'b1;
415
  #423 wb_rst =  1'b0;
416
 
417 169 mohor
  // Clear memories
418
  clear_memories;
419 243 tadejm
  clear_buffer_descriptors;
420 169 mohor
 
421
  #423 StartTB  =  1'b1;
422
end
423
 
424
 
425
 
426
// Generating wb_clk clock
427 116 mohor
initial
428
begin
429 169 mohor
  wb_clk=0;
430
//  forever #2.5 wb_clk = ~wb_clk;  // 2*2.5 ns -> 200.0 MHz    
431 274 tadejm
//  forever #5 wb_clk = ~wb_clk;  // 2*5 ns -> 100.0 MHz    
432 169 mohor
//  forever #10 wb_clk = ~wb_clk;  // 2*10 ns -> 50.0 MHz    
433
//  forever #12.5 wb_clk = ~wb_clk;  // 2*12.5 ns -> 40 MHz    
434 274 tadejm
  forever #15 wb_clk = ~wb_clk;  // 2*10 ns -> 33.3 MHz    
435 209 tadejm
//  forever #20 wb_clk = ~wb_clk;  // 2*20 ns -> 25 MHz    
436 169 mohor
//  forever #25 wb_clk = ~wb_clk;  // 2*25 ns -> 20.0 MHz
437
//  forever #31.25 wb_clk = ~wb_clk;  // 2*31.25 ns -> 16.0 MHz    
438
//  forever #50 wb_clk = ~wb_clk;  // 2*50 ns -> 10.0 MHz
439
//  forever #55 wb_clk = ~wb_clk;  // 2*55 ns ->  9.1 MHz    
440 116 mohor
end
441
 
442
 
443
 
444 169 mohor
integer      tests_successfull;
445
integer      tests_failed;
446
reg [799:0]  test_name; // used for tb_log_file
447 121 mohor
 
448 169 mohor
reg   [3:0]  wbm_init_waits; // initial wait cycles between CYC_O and STB_O of WB Master
449
reg   [3:0]  wbm_subseq_waits; // subsequent wait cycles between STB_Os of WB Master
450
reg   [2:0]  wbs_waits; // wait cycles befor WB Slave responds
451
reg   [7:0]  wbs_retries; // if RTY response, then this is the number of retries before ACK
452
 
453 274 tadejm
reg          wbm_working; // tasks wbm_write and wbm_read set signal when working and reset it when stop working
454
 
455
 
456 116 mohor
initial
457
begin
458 169 mohor
  wait(StartTB);  // Start of testbench
459
 
460
  // Initial global values
461
  tests_successfull = 0;
462
  tests_failed = 0;
463 274 tadejm
 
464
  wbm_working = 0;
465 169 mohor
 
466
  wbm_init_waits = 4'h1;
467
  wbm_subseq_waits = 4'h3;
468
  wbs_waits = 4'h1;
469
  wbs_retries = 8'h2;
470
  wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
471
 
472 274 tadejm
  // set DIFFERENT mrx_clk to mtx_clk!
473
//  eth_phy.set_mrx_equal_mtx = 1'b0;
474 169 mohor
 
475
  //  Call tests
476
  //  ----------
477 274 tadejm
//    test_access_to_mac_reg(0, 0);           // 0 - 3
478 194 tadej
//    test_mii(0, 17);                        // 0 - 17
479 169 mohor
  test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
480
  eth_phy.carrier_sense_real_delay(0);
481 279 mohor
    test_mac_full_duplex_transmit(0, 21);    // 0 - (21)
482 281 mohor
    test_mac_full_duplex_receive(0, 13);     // 0 - 13
483
    test_mac_full_duplex_flow_control(0, 4);  // 0 - 4
484 274 tadejm
                                              // 4 is executed, everything is OK
485
//    test_mac_half_duplex_flow(0, 0);
486 169 mohor
 
487 243 tadejm
  test_note("PHY generates 'real delayed' Carrier sense and Collision signals for following tests");
488 169 mohor
  eth_phy.carrier_sense_real_delay(1);
489
 
490
 
491
  // Finish test's logs
492
  test_summary;
493
  $display("\n\n END of SIMULATION");
494
  $fclose(tb_log_file | phy_log_file_desc | memory_log_file_desc | host_log_file_desc);
495
  $fclose(wb_s_mon_log_file_desc | wb_m_mon_log_file_desc);
496
 
497
  $stop;
498 116 mohor
end
499 169 mohor
 
500 116 mohor
 
501 169 mohor
 
502
//////////////////////////////////////////////////////////////
503
// Test tasks
504
//////////////////////////////////////////////////////////////
505
 
506
task test_access_to_mac_reg;
507
  input  [31:0]  start_task;
508
  input  [31:0]  end_task;
509
  integer        bit_start_1;
510
  integer        bit_end_1;
511
  integer        bit_start_2;
512
  integer        bit_end_2;
513
  integer        num_of_reg;
514
  integer        i_addr;
515
  integer        i_data;
516
  integer        i_length;
517
  integer        tmp_data;
518
  reg    [31:0]  tx_bd_num;
519
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
520
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
521
  integer        i;
522
  integer        i1;
523
  integer        i2;
524
  integer        i3;
525
  integer        fail;
526 178 mohor
  integer        test_num;
527 169 mohor
  reg    [31:0]  addr;
528
  reg    [31:0]  data;
529
  reg    [31:0]  data_max;
530 116 mohor
begin
531 169 mohor
// ACCESS TO MAC REGISTERS TEST
532
test_heading("ACCESS TO MAC REGISTERS TEST");
533
$display(" ");
534
$display("ACCESS TO MAC REGISTERS TEST");
535
fail = 0;
536
 
537 192 tadej
// reset MAC registers
538
hard_reset;
539
// reset MAC and MII LOGIC with soft reset
540 274 tadejm
//reset_mac;
541
//reset_mii;
542 169 mohor
 
543 192 tadej
 
544 178 mohor
//////////////////////////////////////////////////////////////////////
545
////                                                              ////
546
////  test_access_to_mac_reg:                                     ////
547
////                                                              ////
548
////  0: Walking 1 with single cycles across MAC regs.            ////
549
////  1: Walking 1 with single cycles across MAC buffer descript. ////
550
////  2: Test max reg. values and reg. values after writing       ////
551
////     inverse reset values and hard reset of the MAC           ////
552
////  3: Test buffer desc. RAM preserving values after hard reset ////
553
////     of the MAC and resetting the logic                       ////
554
////                                                              ////
555
//////////////////////////////////////////////////////////////////////
556 194 tadej
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
557 169 mohor
begin
558
 
559 178 mohor
  ////////////////////////////////////////////////////////////////////
560
  ////                                                            ////
561
  ////  Walking 1 with single cycles across MAC regs.             ////
562
  ////                                                            ////
563
  ////////////////////////////////////////////////////////////////////
564
  if (test_num == 0) // Walking 1 with single cycles across MAC regs.
565 194 tadej
  begin
566
    // TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
567
    test_name   = "TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
568
    `TIME; $display("  TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
569 178 mohor
 
570 194 tadej
    data = 0;
571
    for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
572
      begin
573
        wbm_init_waits = i;
574
        wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
575
        for (i_addr = 0; i_addr <= 32'h4C; i_addr = i_addr + 4) // register address
576
          begin
577
            addr = `ETH_BASE + i_addr;
578
            // set ranges of R/W bits
579
            case (addr)
580
              `ETH_MODER:
581
                begin
582
                  bit_start_1 = 0;
583
                  bit_end_1   = 16;
584
                  bit_start_2 = 32; // not used
585
                  bit_end_2   = 32; // not used
586
                end
587
              `ETH_INT: // READONLY - tested within INT test
588
                begin
589
                  bit_start_1 = 32; // not used
590
                  bit_end_1   = 32; // not used
591
                  bit_start_2 = 32; // not used
592
                  bit_end_2   = 32; // not used
593
                end
594
              `ETH_INT_MASK:
595
                begin
596
                  bit_start_1 = 0;
597
                  bit_end_1   = 6;
598
                  bit_start_2 = 32; // not used
599
                  bit_end_2   = 32; // not used
600
                end
601
              `ETH_IPGT:
602
                begin
603
                  bit_start_1 = 0;
604
                  bit_end_1   = 6;
605
                  bit_start_2 = 32; // not used
606
                  bit_end_2   = 32; // not used
607
                end
608
              `ETH_IPGR1:
609
                begin
610
                  bit_start_1 = 0;
611
                  bit_end_1   = 6;
612
                  bit_start_2 = 32; // not used
613
                  bit_end_2   = 32; // not used
614
                end
615
              `ETH_IPGR2:
616
                begin
617
                  bit_start_1 = 0;
618
                  bit_end_1   = 6;
619
                  bit_start_2 = 32; // not used
620
                  bit_end_2   = 32; // not used
621
                end
622
              `ETH_PACKETLEN:
623
                begin
624
                  bit_start_1 = 0;
625
                  bit_end_1   = 31;
626
                  bit_start_2 = 32; // not used
627
                  bit_end_2   = 32; // not used
628
                end
629
              `ETH_COLLCONF:
630
                begin
631
                  bit_start_1 = 0;
632
                  bit_end_1   = 5;
633
                  bit_start_2 = 16;
634
                  bit_end_2   = 19;
635
                end
636
              `ETH_TX_BD_NUM:
637
                begin
638
                  bit_start_1 = 0;
639
                  bit_end_1   = 7;
640
                  bit_start_2 = 32; // not used
641
                  bit_end_2   = 32; // not used
642
                end
643
              `ETH_CTRLMODER:
644
                begin
645
                  bit_start_1 = 0;
646
                  bit_end_1   = 2;
647
                  bit_start_2 = 32; // not used
648
                  bit_end_2   = 32; // not used
649
                end
650
              `ETH_MIIMODER:
651
                begin
652
                  bit_start_1 = 0;
653
                  bit_end_1   = 9;
654
                  bit_start_2 = 32; // not used
655
                  bit_end_2   = 32; // not used
656
                end
657
              `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
658
                begin
659
                  bit_start_1 = 32; // not used
660
                  bit_end_1   = 32; // not used
661
                  bit_start_2 = 32; // not used
662
                  bit_end_2   = 32; // not used
663
                end
664
              `ETH_MIIADDRESS:
665
                begin
666
                  bit_start_1 = 0;
667
                  bit_end_1   = 4;
668
                  bit_start_2 = 8;
669
                  bit_end_2   = 12;
670
                end
671
              `ETH_MIITX_DATA:
672
                begin
673
                  bit_start_1 = 0;
674
                  bit_end_1   = 15;
675
                  bit_start_2 = 32; // not used
676
                  bit_end_2   = 32; // not used
677
                end
678
              `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
679
                begin
680
                  bit_start_1 = 32; // not used
681
                  bit_end_1   = 32; // not used
682
                  bit_start_2 = 32; // not used
683
                  bit_end_2   = 32; // not used
684
                end
685
              `ETH_MIISTATUS: // READONLY - tested within MIIM test
686
                begin
687
                  bit_start_1 = 32; // not used
688
                  bit_end_1   = 32; // not used
689
                  bit_start_2 = 32; // not used
690
                  bit_end_2   = 32; // not used
691
                end
692
              `ETH_MAC_ADDR0:
693
                begin
694
                  bit_start_1 = 0;
695
                  bit_end_1   = 31;
696
                  bit_start_2 = 32; // not used
697
                  bit_end_2   = 32; // not used
698 178 mohor
                  end
699 194 tadej
              `ETH_MAC_ADDR1:
700
                begin
701
                  bit_start_1 = 0;
702
                  bit_end_1   = 15;
703
                  bit_start_2 = 32; // not used
704
                  bit_end_2   = 32; // not used
705
                end
706
              `ETH_HASH_ADDR0:
707
                begin
708
                  bit_start_1 = 0;
709
                  bit_end_1   = 31;
710
                  bit_start_2 = 32; // not used
711
                  bit_end_2   = 32; // not used
712
                end
713
              default: // `ETH_HASH_ADDR1:
714
                begin
715
                  bit_start_1 = 0;
716
                  bit_end_1   = 31;
717
                  bit_start_2 = 32; // not used
718
                  bit_end_2   = 32; // not used
719
                end
720
            endcase
721
 
722
            for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
723
              begin
724
                data = 1'b1 << i_data;
725
                if ( (addr == `ETH_MIICOMMAND) && (i_data <= 2) ) // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
726
                  ;
727
                else
728 178 mohor
                  begin
729 194 tadej
                    wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
730 274 tadejm
                    wait (wbm_working == 0);
731 194 tadej
                    wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
732
                    if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
733
                         ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
734
                      begin
735
                        if (tmp_data !== data)
736 178 mohor
                        begin
737 194 tadej
                          fail = fail + 1;
738
                          test_fail("RW bit of the MAC register was not written or not read");
739
                          `TIME;
740
                          $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
741
                                    wbm_init_waits, addr, data, tmp_data);
742
                        end
743
                      end
744
                    else // data should not be equal to tmp_data
745
                      begin
746
                        if (tmp_data === data)
747 178 mohor
                          begin
748
                            fail = fail + 1;
749 194 tadej
                            test_fail("NON RW bit of the MAC register was written, but it shouldn't be");
750 178 mohor
                            `TIME;
751 194 tadej
                            $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
752 178 mohor
                                      wbm_init_waits, addr, data, tmp_data);
753
                          end
754 194 tadej
                      end
755
                  end
756
              end
757
          end
758
      end
759 209 tadejm
    // INTERMEDIATE DISPLAYS (The only one)
760
    $display("    ->buffer descriptors tested with 0, 1, 2, 3 and 4 bus delay cycles");
761 194 tadej
    if(fail == 0)
762
      test_ok;
763
    else
764
      fail = 0;    // Errors were reported previously
765
  end
766 178 mohor
 
767
 
768
  ////////////////////////////////////////////////////////////////////
769
  ////                                                            ////
770
  ////  Walking 1 with single cycles across MAC buffer descript.  ////
771
  ////                                                            ////
772
  ////////////////////////////////////////////////////////////////////
773
  if (test_num == 1) // Start Walking 1 with single cycles across MAC buffer descript.
774 169 mohor
  begin
775 194 tadej
    // TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )
776
    test_name   = "TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )";
777
    `TIME; $display("  TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )");
778 178 mohor
 
779
    data = 0;
780
    // set TX and RX buffer descriptors
781
    tx_bd_num = 32'h40;
782
    wbm_write(`ETH_TX_BD_NUM, tx_bd_num, 4'hF, 1, 0, 0);
783
    for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
784
    begin
785 169 mohor
      wbm_init_waits = i;
786
      wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
787 178 mohor
      for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
788 169 mohor
      begin
789
        addr = `ETH_BASE + i_addr;
790 178 mohor
        if (i_addr < (32'h400 + (tx_bd_num << 3))) // TX buffer descriptors
791
        begin
792
          // set ranges of R/W bits
793
          case (addr[3])
794
            1'b0: // buffer control bits
795
            begin
796
              bit_start_1 = 0;
797
              bit_end_1   = 31; // 8;
798
              bit_start_2 = 11;
799
              bit_end_2   = 31;
800
            end
801
            default: // 1'b1: // buffer pointer
802
            begin
803
              bit_start_1 = 0;
804
              bit_end_1   = 31;
805
              bit_start_2 = 32; // not used
806
              bit_end_2   = 32; // not used
807
            end
808
          endcase
809
        end
810
        else // RX buffer descriptors
811
        begin
812
          // set ranges of R/W bits
813
          case (addr[3])
814
            1'b0: // buffer control bits
815
            begin
816
              bit_start_1 = 0;
817
              bit_end_1   = 31; // 7;
818
              bit_start_2 = 13;
819
              bit_end_2   = 31;
820
            end
821
            default: // 1'b1: // buffer pointer
822
            begin
823
              bit_start_1 = 0;
824
              bit_end_1   = 31;
825
              bit_start_2 = 32; // not used
826
              bit_end_2   = 32; // not used
827
            end
828
          endcase
829
        end
830
 
831 169 mohor
        for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
832
        begin
833
          data = 1'b1 << i_data;
834 178 mohor
          if ( (addr[3] == 0) && (i_data == 15) ) // DO NOT WRITE to this bit !!!
835
            ;
836 169 mohor
          else
837
          begin
838
            wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
839
            wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
840
            if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
841
                 ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
842
            begin
843
              if (tmp_data !== data)
844
              begin
845
                fail = fail + 1;
846 178 mohor
                test_fail("RW bit of the MAC buffer descriptors was not written or not read");
847 169 mohor
                `TIME;
848
                $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
849
                          wbm_init_waits, addr, data, tmp_data);
850
              end
851
            end
852
            else // data should not be equal to tmp_data
853
            begin
854
              if (tmp_data === data)
855
              begin
856
                fail = fail + 1;
857 178 mohor
                test_fail("NON RW bit of the MAC buffer descriptors was written, but it shouldn't be");
858 169 mohor
                `TIME;
859
                $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
860
                          wbm_init_waits, addr, data, tmp_data);
861
              end
862
            end
863
          end
864
        end
865
      end
866 178 mohor
      // INTERMEDIATE DISPLAYS
867
      case (i)
868 209 tadejm
        0:       $display("    ->buffer descriptors tested with 0 bus delay");
869
        1:       $display("    ->buffer descriptors tested with 1 bus delay cycle");
870
        2:       $display("    ->buffer descriptors tested with 2 bus delay cycles");
871
        3:       $display("    ->buffer descriptors tested with 3 bus delay cycles");
872
        default: $display("    ->buffer descriptors tested with 4 bus delay cycles");
873 178 mohor
      endcase
874
    end
875
    if(fail == 0)
876
      test_ok;
877
    else
878
      fail = 0;
879 169 mohor
  end
880 178 mohor
 
881
 
882
  ////////////////////////////////////////////////////////////////////
883
  ////                                                            ////
884
  ////  Test max reg. values and reg. values after writing        ////
885
  ////  inverse reset values and hard reset of the MAC            ////
886
  ////                                                            ////
887
  ////////////////////////////////////////////////////////////////////
888
  if (test_num == 2) // Start this task
889 169 mohor
  begin
890 194 tadej
    // TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC
891 178 mohor
    test_name   =
892 194 tadej
      "TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC";
893 178 mohor
    `TIME; $display(
894 194 tadej
      "  TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC");
895 178 mohor
 
896
    // reset MAC registers
897
    hard_reset;
898
    for (i = 0; i <= 4; i = i + 1) // 0, 2 - WRITE; 1, 3, 4 - READ
899 169 mohor
    begin
900 178 mohor
      for (i_addr = 0; i_addr <= 32'h4C; i_addr = i_addr + 4) // register address
901 169 mohor
      begin
902 178 mohor
        addr = `ETH_BASE + i_addr;
903
        // set ranges of R/W bits
904
        case (addr)
905
          `ETH_MODER:
906 169 mohor
          begin
907 178 mohor
            data = 32'h0000_A800;
908
            data_max = 32'h0001_FFFF;
909 169 mohor
          end
910 178 mohor
          `ETH_INT: // READONLY - tested within INT test
911 169 mohor
          begin
912 178 mohor
            data = 32'h0000_0000;
913
            data_max = 32'h0000_0000;
914 169 mohor
          end
915
          `ETH_INT_MASK:
916 178 mohor
          begin
917
            data = 32'h0000_0000;
918
            data_max = 32'h0000_007F;
919
          end
920 169 mohor
          `ETH_IPGT:
921 178 mohor
          begin
922
            data = 32'h0000_0012;
923
            data_max = 32'h0000_007F;
924
          end
925 169 mohor
          `ETH_IPGR1:
926 178 mohor
          begin
927
            data = 32'h0000_000C;
928
            data_max = 32'h0000_007F;
929
          end
930 169 mohor
          `ETH_IPGR2:
931 178 mohor
          begin
932
            data = 32'h0000_0012;
933
            data_max = 32'h0000_007F;
934
          end
935 169 mohor
          `ETH_PACKETLEN:
936 178 mohor
          begin
937
            data = 32'h0040_0600;
938
            data_max = 32'hFFFF_FFFF;
939
          end
940 169 mohor
          `ETH_COLLCONF:
941 178 mohor
          begin
942
            data = 32'h000F_003F;
943
            data_max = 32'h000F_003F;
944
          end
945 169 mohor
          `ETH_TX_BD_NUM:
946 178 mohor
          begin
947
            data = 32'h0000_0040;
948
            data_max = 32'h0000_0080;
949
          end
950 169 mohor
          `ETH_CTRLMODER:
951 178 mohor
          begin
952
            data = 32'h0000_0000;
953
            data_max = 32'h0000_0007;
954
          end
955 169 mohor
          `ETH_MIIMODER:
956 178 mohor
          begin
957
            data = 32'h0000_0064;
958
            data_max = 32'h0000_03FF;
959
          end
960 169 mohor
          `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
961 178 mohor
          begin
962
            data = 32'h0000_0000;
963
            data_max = 32'h0000_0007;
964
          end
965 169 mohor
          `ETH_MIIADDRESS:
966 178 mohor
          begin
967
            data = 32'h0000_0000;
968
            data_max = 32'h0000_1F1F;
969
          end
970 169 mohor
          `ETH_MIITX_DATA:
971 178 mohor
          begin
972
            data = 32'h0000_0000;
973
            data_max = 32'h0000_FFFF;
974
          end
975 169 mohor
          `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
976
          begin
977 178 mohor
            data = 32'h0000_0000;
978
            data_max = 32'h0000_0000;
979 169 mohor
          end
980 178 mohor
          `ETH_MIISTATUS: // READONLY - tested within MIIM test
981 169 mohor
          begin
982 178 mohor
            data = 32'h0000_0000;
983
            data_max = 32'h0000_0000;
984 169 mohor
          end
985 178 mohor
          `ETH_MAC_ADDR0:
986 169 mohor
          begin
987 178 mohor
            data = 32'h0000_0000;
988
            data_max = 32'hFFFF_FFFF;
989 169 mohor
          end
990 178 mohor
          `ETH_MAC_ADDR1:
991 169 mohor
          begin
992 178 mohor
            data = 32'h0000_0000;
993
            data_max = 32'h0000_FFFF;
994 169 mohor
          end
995 178 mohor
          `ETH_HASH_ADDR0:
996 169 mohor
          begin
997 178 mohor
            data = 32'h0000_0000;
998
            data_max = 32'hFFFF_FFFF;
999 169 mohor
          end
1000 178 mohor
          default: // `ETH_HASH_ADDR1:
1001 169 mohor
          begin
1002 178 mohor
            data = 32'h0000_0000;
1003
            data_max = 32'hFFFF_FFFF;
1004 169 mohor
          end
1005
        endcase
1006 178 mohor
 
1007
        wbm_init_waits = {$random} % 3;
1008
        wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
1009
        if (i == 0)
1010 274 tadejm
        begin
1011 178 mohor
          wbm_write(addr, ~data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1012 274 tadejm
        end
1013 178 mohor
        else if (i == 2)
1014 274 tadejm
        begin
1015 178 mohor
          wbm_write(addr, 32'hFFFFFFFF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1016 274 tadejm
        end
1017 178 mohor
        else if ((i == 1) || (i == 4))
1018 169 mohor
        begin
1019 178 mohor
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1020
          if (tmp_data !== data)
1021
          begin
1022
            fail = fail + 1;
1023
            test_fail("RESET value of the MAC register is not correct");
1024
            `TIME;
1025
            $display("  addr %h, data %h, tmp_data %h", addr, data, tmp_data);
1026
          end
1027 169 mohor
        end
1028 178 mohor
        else // check maximum values
1029 169 mohor
        begin
1030
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1031 178 mohor
          if (addr == `ETH_TX_BD_NUM) // previous data should remain in this register
1032 169 mohor
          begin
1033
            if (tmp_data !== data)
1034
            begin
1035
              fail = fail + 1;
1036 178 mohor
              test_fail("Previous value of the TX_BD_NUM register did not remain");
1037 169 mohor
              `TIME;
1038 178 mohor
              $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1039 169 mohor
            end
1040 178 mohor
            // try maximum (80)
1041
            wbm_write(addr, data_max, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1042
            wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1043
            if (tmp_data !== data_max)
1044
            begin
1045
              fail = fail + 1;
1046
              test_fail("MAX value of the TX_BD_NUM register is not correct");
1047
              `TIME;
1048
              $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1049
            end
1050
            // try one less than maximum (80)
1051
            wbm_write(addr, (data_max - 1), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1052
            wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1053
            if (tmp_data !== (data_max - 1))
1054
            begin
1055
              fail = fail + 1;
1056
              test_fail("ONE less than MAX value of the TX_BD_NUM register is not correct");
1057
              `TIME;
1058
              $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1059
            end
1060
            // try one more than maximum (80)
1061
            wbm_write(addr, (data_max + 1), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1062
            wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1063
            if (tmp_data !== (data_max - 1)) // previous data should remain in this register
1064
            begin
1065
              fail = fail + 1;
1066
              test_fail("Previous value of the TX_BD_NUM register did not remain");
1067
              `TIME;
1068
              $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1069
            end
1070 169 mohor
          end
1071 178 mohor
          else
1072 169 mohor
          begin
1073 178 mohor
            if (tmp_data !== data_max)
1074 169 mohor
            begin
1075
              fail = fail + 1;
1076 178 mohor
              test_fail("MAX value of the MAC register is not correct");
1077 169 mohor
              `TIME;
1078 178 mohor
              $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1079 169 mohor
            end
1080
          end
1081
        end
1082
      end
1083 178 mohor
      // reset MAC registers
1084
      if ((i == 0) || (i == 3))
1085
        hard_reset;
1086 169 mohor
    end
1087 178 mohor
    if(fail == 0)
1088
      test_ok;
1089
    else
1090
      fail = 0;
1091 169 mohor
  end
1092 116 mohor
 
1093 156 mohor
 
1094 181 mohor
  ////////////////////////////////////////////////////////////////////
1095
  ////                                                            ////
1096
  ////  Test buffer desc. ram preserving values after hard reset  ////
1097
  ////  of the mac and reseting the logic                         ////
1098
  ////                                                            ////
1099
  ////////////////////////////////////////////////////////////////////
1100 178 mohor
  if (test_num == 3) // Start this task
1101 169 mohor
  begin
1102 194 tadej
    // TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC
1103
    test_name   = "TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC";
1104 178 mohor
    `TIME;
1105 194 tadej
    $display("  TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");
1106 178 mohor
 
1107
    // reset MAC registers
1108
    hard_reset;
1109
    // reset LOGIC with soft reset
1110 274 tadejm
//    reset_mac;
1111
//    reset_mii;
1112 178 mohor
    for (i = 0; i <= 3; i = i + 1) // 0, 2 - WRITE; 1, 3 - READ
1113 169 mohor
    begin
1114 178 mohor
      for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
1115 169 mohor
      begin
1116 178 mohor
        addr = `ETH_BASE + i_addr;
1117
 
1118
        wbm_init_waits = {$random} % 3;
1119
        wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
1120
        if (i == 0)
1121 169 mohor
        begin
1122 178 mohor
          data = 32'hFFFFFFFF;
1123
          wbm_write(addr, 32'hFFFFFFFF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1124 169 mohor
        end
1125 178 mohor
        else if (i == 2)
1126 169 mohor
        begin
1127 178 mohor
          data = 32'h00000000;
1128
          wbm_write(addr, 32'h00000000, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1129 169 mohor
        end
1130
        else
1131
        begin
1132 178 mohor
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1133
          if (tmp_data !== data)
1134 169 mohor
          begin
1135
            fail = fail + 1;
1136 178 mohor
            test_fail("PRESERVED value of the MAC buffer descriptors is not correct");
1137 169 mohor
            `TIME;
1138 178 mohor
            $display("  addr %h, data %h, tmp_data %h", addr, data, tmp_data);
1139 169 mohor
          end
1140
        end
1141
      end
1142 178 mohor
      if ((i == 0) || (i == 2))
1143
      begin
1144
        // reset MAC registers
1145
        hard_reset;
1146
        // reset LOGIC with soft reset
1147 274 tadejm
//        reset_mac;
1148
//        reset_mii;
1149 178 mohor
      end
1150 169 mohor
    end
1151 178 mohor
    if(fail == 0)
1152
      test_ok;
1153
    else
1154
    fail = 0;
1155 169 mohor
  end
1156 116 mohor
 
1157
 
1158 178 mohor
  if (test_num == 4) // Start this task
1159 169 mohor
  begin
1160 194 tadej
        /*  // TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
1161
          test_name   = "TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
1162
          `TIME; $display("  TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
1163 178 mohor
 
1164
          data = 0;
1165
          burst_data = 0;
1166
          burst_tmp_data = 0;
1167
          i_length = 10; // two bursts for length 20
1168
          for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
1169
          begin
1170
            for (i1 = 0; i1 <= 4; i1 = i1 + 1) // for initial wait cycles on WB bus
1171
            begin
1172
              wbm_init_waits = i;
1173
              wbm_subseq_waits = i1;
1174
              #1;
1175
              for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
1176
              begin
1177
                data = 1'b1 << i_data;
1178
                #1;
1179
                for (i2 = 32'h4C; i2 >= 0; i2 = i2 - 4)
1180
                begin
1181
                  burst_data = burst_data << 32;
1182
                  // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
1183
                  if ( ((`ETH_BASE + i2) == `ETH_MIICOMMAND) && (i_data <= 2) )
1184
                  begin
1185
                    #1 burst_data[31:0] = 0;
1186
                  end
1187
                  else
1188
                  begin
1189
                    #1 burst_data[31:0] = data;
1190
                  end
1191
                end
1192
                #1;
1193
                // 2 burst writes
1194
                addr = `ETH_BASE; // address of a first burst
1195
                wbm_write(addr, burst_data[(32 * 10 - 1):0], 4'hF, i_length, wbm_init_waits, wbm_subseq_waits);
1196
                burst_tmp_data = burst_data >> (32 * i_length);
1197
                addr = addr + 32'h28; // address of a second burst
1198
                wbm_write(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length, wbm_init_waits, wbm_subseq_waits);
1199
                #1;
1200
                // 2 burst reads
1201
                addr = `ETH_BASE; // address of a first burst
1202
                wbm_read(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length,
1203
                         wbm_init_waits, wbm_subseq_waits); // first burst
1204
                burst_tmp_data = burst_tmp_data << (32 * i_length);
1205
                addr = addr + 32'h28; // address of a second burst
1206
                wbm_read(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length,
1207
                         wbm_init_waits, wbm_subseq_waits); // second burst
1208
                #1;
1209
                for (i2 = 0; i2 <= 32'h4C; i2 = i2 + 4)
1210
                begin
1211
                  // set ranges of R/W bits
1212
                  case (`ETH_BASE + i2)
1213
                  `ETH_MODER:
1214
                    begin
1215
                      bit_start_1 = 0;
1216
                      bit_end_1   = 16;
1217
                      bit_start_2 = 32; // not used
1218
                      bit_end_2   = 32; // not used
1219
                    end
1220
                  `ETH_INT: // READONLY - tested within INT test
1221
                    begin
1222
                      bit_start_1 = 32; // not used
1223
                      bit_end_1   = 32; // not used
1224
                      bit_start_2 = 32; // not used
1225
                      bit_end_2   = 32; // not used
1226
                    end
1227
                  `ETH_INT_MASK:
1228
                    begin
1229
                      bit_start_1 = 0;
1230
                      bit_end_1   = 6;
1231
                      bit_start_2 = 32; // not used
1232
                      bit_end_2   = 32; // not used
1233
                    end
1234
                  `ETH_IPGT:
1235
                    begin
1236
                      bit_start_1 = 0;
1237
                      bit_end_1   = 6;
1238
                      bit_start_2 = 32; // not used
1239
                      bit_end_2   = 32; // not used
1240
                    end
1241
                  `ETH_IPGR1:
1242
                    begin
1243
                      bit_start_1 = 0;
1244
                      bit_end_1   = 6;
1245
                      bit_start_2 = 32; // not used
1246
                      bit_end_2   = 32; // not used
1247
                    end
1248
                  `ETH_IPGR2:
1249
                    begin
1250
                      bit_start_1 = 0;
1251
                      bit_end_1   = 6;
1252
                      bit_start_2 = 32; // not used
1253
                      bit_end_2   = 32; // not used
1254
                    end
1255
                  `ETH_PACKETLEN:
1256
                    begin
1257
                      bit_start_1 = 0;
1258
                      bit_end_1   = 31;
1259
                      bit_start_2 = 32; // not used
1260
                      bit_end_2   = 32; // not used
1261
                    end
1262
                  `ETH_COLLCONF:
1263
                    begin
1264
                      bit_start_1 = 0;
1265
                      bit_end_1   = 5;
1266
                      bit_start_2 = 16;
1267
                      bit_end_2   = 19;
1268
                    end
1269
                  `ETH_TX_BD_NUM:
1270
                    begin
1271
                      bit_start_1 = 0;
1272
                      bit_end_1   = 7;
1273
                      bit_start_2 = 32; // not used
1274
                      bit_end_2   = 32; // not used
1275
                    end
1276
                  `ETH_CTRLMODER:
1277
                    begin
1278
                      bit_start_1 = 0;
1279
                      bit_end_1   = 2;
1280
                      bit_start_2 = 32; // not used
1281
                      bit_end_2   = 32; // not used
1282
                    end
1283
                  `ETH_MIIMODER:
1284
                    begin
1285
                      bit_start_1 = 0;
1286
                      bit_end_1   = 9;
1287
                      bit_start_2 = 32; // not used
1288
                      bit_end_2   = 32; // not used
1289
                    end
1290
                  `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
1291
                    begin
1292
                      bit_start_1 = 32; // not used
1293
                      bit_end_1   = 32; // not used
1294
                      bit_start_2 = 32; // not used
1295
                      bit_end_2   = 32; // not used
1296
                    end
1297
                  `ETH_MIIADDRESS:
1298
                    begin
1299
                      bit_start_1 = 0;
1300
                      bit_end_1   = 4;
1301
                      bit_start_2 = 8;
1302
                      bit_end_2   = 12;
1303
                    end
1304
                  `ETH_MIITX_DATA:
1305
                    begin
1306
                      bit_start_1 = 0;
1307
                      bit_end_1   = 15;
1308
                      bit_start_2 = 32; // not used
1309
                      bit_end_2   = 32; // not used
1310
                    end
1311
                  `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
1312
                    begin
1313
                      bit_start_1 = 32; // not used
1314
                      bit_end_1   = 32; // not used
1315
                      bit_start_2 = 32; // not used
1316
                      bit_end_2   = 32; // not used
1317
                    end
1318
                  `ETH_MIISTATUS: // READONLY - tested within MIIM test
1319
                    begin
1320
                      bit_start_1 = 32; // not used
1321
                      bit_end_1   = 32; // not used
1322
                      bit_start_2 = 32; // not used
1323
                      bit_end_2   = 32; // not used
1324
                    end
1325
                  `ETH_MAC_ADDR0:
1326
                    begin
1327
                      bit_start_1 = 0;
1328
                      bit_end_1   = 31;
1329
                      bit_start_2 = 32; // not used
1330
                      bit_end_2   = 32; // not used
1331
                    end
1332
                  `ETH_MAC_ADDR1:
1333
                    begin
1334
                      bit_start_1 = 0;
1335
                      bit_end_1   = 15;
1336
                      bit_start_2 = 32; // not used
1337
                      bit_end_2   = 32; // not used
1338
                    end
1339
                  `ETH_HASH_ADDR0:
1340
                    begin
1341
                      bit_start_1 = 0;
1342
                      bit_end_1   = 31;
1343
                      bit_start_2 = 32; // not used
1344
                      bit_end_2   = 32; // not used
1345
                    end
1346
                  default: // `ETH_HASH_ADDR1:
1347
                    begin
1348
                      bit_start_1 = 0;
1349
                      bit_end_1   = 31;
1350
                      bit_start_2 = 32; // not used
1351
                      bit_end_2   = 32; // not used
1352
                    end
1353
                  endcase
1354
                  #1;
1355
                  // 3 LSBits of MIICOMMAND are NOT written !!!
1356
                  if ( ((`ETH_BASE + i2) == `ETH_MIICOMMAND) && (i_data <= 2) )
1357
                  begin
1358
                    if (burst_tmp_data[31:0] !== burst_data[31:0])
1359
                    begin
1360
                      fail = fail + 1;
1361
                      test_fail("NON WR bit of the MAC MIICOMMAND register was wrong written or read");
1362
                      `TIME;
1363
                      $display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
1364
                                wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
1365
                    end
1366
                  end
1367
                  else
1368
                  begin
1369
                    if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
1370
                         ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
1371
                    begin
1372
                      if (burst_tmp_data[31:0] !== burst_data[31:0])
1373
                      begin
1374
                        fail = fail + 1;
1375
                        test_fail("RW bit of the MAC register was not written or not read");
1376
                        `TIME;
1377
                        $display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
1378
                                  wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
1379
                      end
1380
                    end
1381
                    else // data should not be equal to tmp_data
1382
                    begin
1383
                      if (burst_tmp_data[31:0] === burst_data[31:0])
1384
                      begin
1385
                        fail = fail + 1;
1386
                        test_fail("NON RW bit of the MAC register was written, but it shouldn't be");
1387
                        `TIME;
1388
                        $display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
1389
                                  wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
1390
                      end
1391
                    end
1392
                  end
1393
                  burst_tmp_data = burst_tmp_data >> 32;
1394
                  burst_data = burst_data >> 32;
1395
                end
1396
              end
1397
            end
1398
          end
1399
          if(fail == 0)
1400
            test_ok;
1401
          else
1402
            fail = 0;*/
1403
  end
1404 116 mohor
 
1405 169 mohor
end
1406 156 mohor
 
1407 169 mohor
end
1408
endtask // test_access_to_mac_reg
1409 156 mohor
 
1410
 
1411 169 mohor
task test_mii;
1412
  input  [31:0]  start_task;
1413
  input  [31:0]  end_task;
1414
  integer        i;
1415
  integer        i1;
1416
  integer        i2;
1417
  integer        i3;
1418
  integer        cnt;
1419
  integer        fail;
1420 181 mohor
  integer        test_num;
1421 169 mohor
  reg     [8:0]  clk_div; // only 8 bits are valid!
1422
  reg     [4:0]  phy_addr;
1423
  reg     [4:0]  reg_addr;
1424
  reg     [15:0] phy_data;
1425
  reg     [15:0] tmp_data;
1426
begin
1427
// MIIM MODULE TEST
1428
test_heading("MIIM MODULE TEST");
1429
$display(" ");
1430
$display("MIIM MODULE TEST");
1431
fail = 0;
1432 156 mohor
 
1433 192 tadej
// reset MAC registers
1434
hard_reset;
1435
// reset MAC and MII LOGIC with soft reset
1436 274 tadejm
//reset_mac;
1437
//reset_mii;
1438 116 mohor
 
1439 194 tadej
 
1440 181 mohor
//////////////////////////////////////////////////////////////////////
1441
////                                                              ////
1442
////  test_mii:                                                   ////
1443
////                                                              ////
1444
////  0:  Test clock divider of mii management module with all    ////
1445
////      possible frequences.                                    ////
1446
////  1:  Test various readings from 'real' phy registers.        ////
1447
////  2:  Test various writings to 'real' phy registers (control  ////
1448
////      and non writable registers)                             ////
1449
////  3:  Test reset phy through mii management module            ////
1450
////  4:  Test 'walking one' across phy address (with and without ////
1451
////      preamble)                                               ////
1452
////  5:  Test 'walking one' across phy's register address (with  ////
1453
////      and without preamble)                                   ////
1454
////  6:  Test 'walking one' across phy's data (with and without  ////
1455
////      preamble)                                               ////
1456
////  7:  Test reading from phy with wrong phy address (host      ////
1457
////      reading high 'z' data)                                  ////
1458
////  8:  Test writing to phy with wrong phy address and reading  ////
1459
////      from correct one                                        ////
1460
////  9:  Test sliding stop scan command immediately after read   ////
1461
////      request (with and without preamble)                     ////
1462
//// 10:  Test sliding stop scan command immediately after write  ////
1463
////      request (with and without preamble)                     ////
1464
//// 11:  Test busy and nvalid status durations during write      ////
1465
////      (with and without preamble)                             ////
1466
//// 12:  Test busy and nvalid status durations during write      ////
1467
////      (with and without preamble)                             ////
1468
//// 13:  Test busy and nvalid status durations during scan (with ////
1469
////      and without preamble)                                   ////
1470
//// 14:  Test scan status from phy with detecting link-fail bit  ////
1471
////      (with and without preamble)                             ////
1472
//// 15:  Test scan status from phy with sliding link-fail bit    ////
1473
////      (with and without preamble)                             ////
1474
//// 16:  Test sliding stop scan command immediately after scan   ////
1475
////      request (with and without preamble)                     ////
1476
//// 17:  Test sliding stop scan command after 2. scan (with and  ////
1477
////      without preamble)                                       ////
1478
////                                                              ////
1479
//////////////////////////////////////////////////////////////////////
1480 194 tadej
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
1481 169 mohor
begin
1482 194 tadej
 
1483 181 mohor
  ////////////////////////////////////////////////////////////////////
1484
  ////                                                            ////
1485
  ////  Test clock divider of mii management module with all      ////
1486
  ////  possible frequences.                                      ////
1487
  ////                                                            ////
1488
  ////////////////////////////////////////////////////////////////////
1489
  if (test_num == 0) // Test clock divider of mii management module with all possible frequences.
1490 169 mohor
  begin
1491 194 tadej
    // TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES
1492
    test_name   = "TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES";
1493
    `TIME; $display("  TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES");
1494 181 mohor
 
1495
    wait(Mdc_O); // wait for MII clock to be 1
1496
    for(clk_div = 0; clk_div <= 255; clk_div = clk_div + 1)
1497
    begin
1498
      i1 = 0;
1499
      i2 = 0;
1500
      #Tp mii_set_clk_div(clk_div[7:0]);
1501
      @(posedge Mdc_O);
1502
      #Tp;
1503
      fork
1504 169 mohor
        begin
1505 181 mohor
          @(posedge Mdc_O);
1506 169 mohor
          #Tp;
1507 181 mohor
          disable count_i1;
1508
          disable count_i2;
1509 169 mohor
        end
1510 181 mohor
        begin: count_i1
1511
          forever
1512
          begin
1513
            @(posedge wb_clk);
1514
            i1 = i1 + 1;
1515
            #Tp;
1516
          end
1517
        end
1518
        begin: count_i2
1519
          forever
1520
          begin
1521
            @(negedge wb_clk);
1522
            i2 = i2 + 1;
1523
            #Tp;
1524
          end
1525
        end
1526
      join
1527
      if((clk_div[7:0] == 0) || (clk_div[7:0] == 1) || (clk_div[7:0] == 2) || (clk_div[7:0] == 3))
1528
      begin
1529
        if((i1 == i2) && (i1 == 2))
1530 169 mohor
        begin
1531
        end
1532 181 mohor
        else
1533
        begin
1534
          fail = fail + 1;
1535 209 tadejm
          test_fail("Clock divider of MII module did'nt divide frequency corectly (it should divide by 2)");
1536 181 mohor
        end
1537 169 mohor
      end
1538
      else
1539
      begin
1540 181 mohor
        if((i1 == i2) && (i1 == {clk_div[7:1], 1'b0}))
1541
        begin
1542
        end
1543
        else
1544
        begin
1545
          fail = fail + 1;
1546
          test_fail("Clock divider of MII module did'nt divide frequency corectly");
1547
        end
1548 169 mohor
      end
1549
    end
1550 181 mohor
    if(fail == 0)
1551
      test_ok;
1552 169 mohor
    else
1553 181 mohor
      fail = 0;
1554
  end
1555
 
1556
 
1557
  ////////////////////////////////////////////////////////////////////
1558
  ////                                                            ////
1559
  ////  Test various readings from 'real' phy registers.          ////
1560
  ////                                                            ////
1561
  ////////////////////////////////////////////////////////////////////
1562
  if (test_num == 1) // Test various readings from 'real' phy registers.
1563
  begin
1564 194 tadej
    // TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS
1565
    test_name   = "TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS";
1566
    `TIME; $display("  TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS");
1567 181 mohor
 
1568
    // set the fastest possible MII
1569
    clk_div = 0;
1570
    mii_set_clk_div(clk_div[7:0]);
1571
    // set address
1572
    reg_addr = 5'h1F;
1573
    phy_addr = 5'h1;
1574
    while(reg_addr >= 5'h4)
1575 169 mohor
    begin
1576 181 mohor
      // read request
1577
      #Tp mii_read_req(phy_addr, reg_addr);
1578
      check_mii_busy; // wait for read to finish
1579
      // read data
1580 274 tadejm
      wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1581 181 mohor
      if (phy_data !== 16'hDEAD)
1582 169 mohor
      begin
1583 181 mohor
        test_fail("Wrong data was read from PHY from 'not used' address space");
1584
        fail = fail + 1;
1585 169 mohor
      end
1586 181 mohor
      if (reg_addr == 5'h4) // go out of for loop
1587
        reg_addr = 5'h3;
1588 169 mohor
      else
1589 181 mohor
        reg_addr = reg_addr - 5'h9;
1590 169 mohor
    end
1591 181 mohor
 
1592
    // set address
1593
    reg_addr = 5'h3;
1594
    // read request
1595
    #Tp mii_read_req(phy_addr, reg_addr);
1596
    check_mii_busy; // wait for read to finish
1597
    // read data
1598 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1599 181 mohor
    if (phy_data !== {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM})
1600
    begin
1601
      test_fail("Wrong data was read from PHY from ID register 2");
1602
      fail = fail + 1;
1603
    end
1604
    if(fail == 0)
1605
      test_ok;
1606
    else
1607
      fail = 0;
1608 169 mohor
  end
1609 116 mohor
 
1610
 
1611 181 mohor
  ////////////////////////////////////////////////////////////////////
1612
  ////                                                            ////
1613
  ////  Test various writings to 'real' phy registers (control    ////
1614
  ////  and non writable registers)                               ////
1615
  ////                                                            ////
1616
  ////////////////////////////////////////////////////////////////////
1617
  if (test_num == 2) // 
1618 169 mohor
  begin
1619 194 tadej
    // TEST 2: VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )
1620
    test_name   = "TEST 2: VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )";
1621
    `TIME; $display("  TEST 2: VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )");
1622 181 mohor
 
1623
    // negate data and try to write into unwritable register
1624
    tmp_data = ~phy_data;
1625
    // write request
1626
    #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1627
    check_mii_busy; // wait for write to finish
1628 169 mohor
    // read request
1629
    #Tp mii_read_req(phy_addr, reg_addr);
1630
    check_mii_busy; // wait for read to finish
1631
    // read data
1632 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1633 181 mohor
    if (tmp_data !== phy_data)
1634
    begin
1635
      test_fail("Data was written into unwritable PHY register - ID register 2");
1636
      fail = fail + 1;
1637
    end
1638
 
1639
    // set address
1640
    reg_addr = 5'h0; // control register
1641
    // read request
1642
    #Tp mii_read_req(phy_addr, reg_addr);
1643
    check_mii_busy; // wait for read to finish
1644
    // read data
1645 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1646 181 mohor
    // write request
1647
    phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
1648
    #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1649
    check_mii_busy; // wait for write to finish
1650
    // read request
1651
    #Tp mii_read_req(phy_addr, reg_addr);
1652
    check_mii_busy; // wait for read to finish
1653
    // read data
1654 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1655 181 mohor
    if (phy_data !== 16'h7DFF)
1656 169 mohor
    begin
1657 181 mohor
      test_fail("Data was not correctly written into OR read from writable PHY register - control register");
1658 169 mohor
      fail = fail + 1;
1659
    end
1660 181 mohor
    // write request
1661
    #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1662
    check_mii_busy; // wait for write to finish
1663
    // read request
1664
    #Tp mii_read_req(phy_addr, reg_addr);
1665
    check_mii_busy; // wait for read to finish
1666
    // read data
1667 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1668 181 mohor
    if (phy_data !== tmp_data)
1669
    begin
1670
      test_fail("Data was not correctly written into OR read from writable PHY register - control register");
1671
      fail = fail + 1;
1672
    end
1673
    if(fail == 0)
1674
      test_ok;
1675 116 mohor
    else
1676 181 mohor
      fail = 0;
1677 169 mohor
  end
1678 116 mohor
 
1679
 
1680 181 mohor
  ////////////////////////////////////////////////////////////////////
1681
  ////                                                            ////
1682
  ////  Test reset phy through mii management module              ////
1683
  ////                                                            ////
1684
  ////////////////////////////////////////////////////////////////////
1685
  if (test_num == 3) // 
1686 169 mohor
  begin
1687 194 tadej
    // TEST 3: RESET PHY THROUGH MII MANAGEMENT MODULE
1688
    test_name   = "TEST 3: RESET PHY THROUGH MII MANAGEMENT MODULE";
1689
    `TIME; $display("  TEST 3: RESET PHY THROUGH MII MANAGEMENT MODULE");
1690 181 mohor
 
1691
    // set address
1692
    reg_addr = 5'h0; // control register
1693
    // write request
1694
    phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
1695
    #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1696
    check_mii_busy; // wait for write to finish
1697
    // read request
1698
    #Tp mii_read_req(phy_addr, reg_addr);
1699
    check_mii_busy; // wait for read to finish
1700
    // read data
1701 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1702 181 mohor
    if (phy_data !== tmp_data)
1703
    begin
1704
      test_fail("Data was not correctly written into OR read from writable PHY register - control register");
1705
      fail = fail + 1;
1706
    end
1707
    // set reset bit - selfclearing bit in PHY
1708
    phy_data = phy_data | 16'h8000;
1709
    // write request
1710
    #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1711
    check_mii_busy; // wait for write to finish
1712
    // read request
1713
    #Tp mii_read_req(phy_addr, reg_addr);
1714
    check_mii_busy; // wait for read to finish
1715
    // read data
1716 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1717 181 mohor
    // check self clearing of reset bit
1718
    if (tmp_data[15] !== 1'b0)
1719
    begin
1720
      test_fail("Reset bit should be self cleared - control register");
1721
      fail = fail + 1;
1722
    end
1723
    // check reset value of control register
1724
    if (tmp_data !== {2'h0, (`LED_CFG1 || `LED_CFG2), `LED_CFG1, 3'h0, `LED_CFG3, 8'h0})
1725
    begin
1726
      test_fail("PHY was not reset correctly AND/OR reset bit not self cleared");
1727
      fail = fail + 1;
1728
    end
1729
    if(fail == 0)
1730
      test_ok;
1731
    else
1732
      fail = 0;
1733 169 mohor
  end
1734
 
1735
 
1736 181 mohor
  ////////////////////////////////////////////////////////////////////
1737
  ////                                                            ////
1738
  ////  Test 'walking one' across phy address (with and without   ////
1739
  ////  preamble)                                                 ////
1740
  ////                                                            ////
1741
  ////////////////////////////////////////////////////////////////////
1742
  if (test_num == 4) // 
1743 169 mohor
  begin
1744 194 tadej
    // TEST 4: 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )
1745
    test_name   = "TEST 4: 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )";
1746
    `TIME; $display("  TEST 4: 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )");
1747 181 mohor
 
1748
    // set PHY to test mode
1749
    #Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
1750
    for (i = 0; i <= 1; i = i + 1)
1751 169 mohor
    begin
1752 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
1753
      #Tp eth_phy.clear_test_regs;
1754
      // MII mode register
1755
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}), 4'hF, 1, wbm_init_waits,
1756
                wbm_subseq_waits);
1757
      // walk one across phy address
1758
      for (phy_addr = 5'h1; phy_addr > 5'h0; phy_addr = phy_addr << 1)
1759 169 mohor
      begin
1760 181 mohor
        reg_addr = $random;
1761
        tmp_data = $random;
1762
        // write request
1763
        #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1764
        check_mii_busy; // wait for write to finish
1765
        // read request
1766
        #Tp mii_read_req(phy_addr, reg_addr);
1767
        check_mii_busy; // wait for read to finish
1768
        // read data
1769 274 tadejm
        wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1770 181 mohor
        #Tp;
1771
        if (phy_data !== tmp_data)
1772
        begin
1773
          if (i)
1774
            test_fail("Data was not correctly written into OR read from test registers (without preamble)");
1775
          else
1776
            test_fail("Data was not correctly written into OR read from test registers (with preamble)");
1777
          fail = fail + 1;
1778
        end
1779
        @(posedge wb_clk);
1780
        #Tp;
1781 169 mohor
      end
1782
    end
1783 181 mohor
    // set PHY to normal mode
1784
    #Tp eth_phy.test_regs(0);
1785
    #Tp eth_phy.preamble_suppresed(0);
1786
    // MII mode register
1787
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1788
    if(fail == 0)
1789
      test_ok;
1790
    else
1791
      fail = 0;
1792 169 mohor
  end
1793
 
1794
 
1795 181 mohor
  ////////////////////////////////////////////////////////////////////
1796
  ////                                                            ////
1797
  ////  Test 'walking one' across phy's register address (with    ////
1798
  ////  and without preamble)                                     ////
1799
  ////                                                            ////
1800
  ////////////////////////////////////////////////////////////////////
1801
  if (test_num == 5) // 
1802 169 mohor
  begin
1803 194 tadej
    // TEST 5: 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )
1804
    test_name   = "TEST 5: 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )";
1805
    `TIME; $display("  TEST 5: 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )");
1806 181 mohor
 
1807
    // set PHY to test mode
1808
    #Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
1809
    for (i = 0; i <= 1; i = i + 1)
1810 169 mohor
    begin
1811 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
1812
      #Tp eth_phy.clear_test_regs;
1813
      // MII mode register
1814
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}), 4'hF, 1, wbm_init_waits,
1815
                wbm_subseq_waits);
1816
      // walk one across reg address
1817
      for (reg_addr = 5'h1; reg_addr > 5'h0; reg_addr = reg_addr << 1)
1818 169 mohor
      begin
1819 181 mohor
        phy_addr = $random;
1820
        tmp_data = $random;
1821
        // write request
1822
        #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1823
        check_mii_busy; // wait for write to finish
1824
        // read request
1825
        #Tp mii_read_req(phy_addr, reg_addr);
1826
        check_mii_busy; // wait for read to finish
1827
        // read data
1828 274 tadejm
        wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1829 181 mohor
        #Tp;
1830
        if (phy_data !== tmp_data)
1831
        begin
1832
          if (i)
1833
            test_fail("Data was not correctly written into OR read from test registers (without preamble)");
1834
          else
1835
            test_fail("Data was not correctly written into OR read from test registers (with preamble)");
1836
          fail = fail + 1;
1837
        end
1838
        @(posedge wb_clk);
1839
        #Tp;
1840 169 mohor
      end
1841
    end
1842 181 mohor
    // set PHY to normal mode
1843
    #Tp eth_phy.test_regs(0);
1844
    #Tp eth_phy.preamble_suppresed(0);
1845
    // MII mode register
1846
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1847
    if(fail == 0)
1848
      test_ok;
1849
    else
1850
      fail = 0;
1851 169 mohor
  end
1852
 
1853
 
1854 181 mohor
  ////////////////////////////////////////////////////////////////////
1855
  ////                                                            ////
1856
  ////  Test 'walking one' across phy's data (with and without    ////
1857
  ////  preamble)                                                 ////
1858
  ////                                                            ////
1859
  ////////////////////////////////////////////////////////////////////
1860
  if (test_num == 6) // 
1861 169 mohor
  begin
1862 194 tadej
    // TEST 6: 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )
1863
    test_name   = "TEST 6: 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )";
1864
    `TIME; $display("  TEST 6: 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )");
1865 181 mohor
 
1866
    // set PHY to test mode
1867
    #Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
1868
    for (i = 0; i <= 1; i = i + 1)
1869 169 mohor
    begin
1870 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
1871
      #Tp eth_phy.clear_test_regs;
1872
      // MII mode register
1873
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}), 4'hF, 1, wbm_init_waits,
1874
                wbm_subseq_waits);
1875
      // walk one across data
1876
      for (tmp_data = 16'h1; tmp_data > 16'h0; tmp_data = tmp_data << 1)
1877 169 mohor
      begin
1878 181 mohor
        phy_addr = $random;
1879
        reg_addr = $random;
1880
        // write request
1881
        #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1882
        check_mii_busy; // wait for write to finish
1883
        // read request
1884
        #Tp mii_read_req(phy_addr, reg_addr);
1885
        check_mii_busy; // wait for read to finish
1886
        // read data
1887 274 tadejm
        wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1888 181 mohor
        #Tp;
1889
        if (phy_data !== tmp_data)
1890
        begin
1891
          if (i)
1892
            test_fail("Data was not correctly written into OR read from test registers (without preamble)");
1893
          else
1894
            test_fail("Data was not correctly written into OR read from test registers (with preamble)");
1895
          fail = fail + 1;
1896
        end
1897
        @(posedge wb_clk);
1898
        #Tp;
1899 169 mohor
      end
1900
    end
1901 181 mohor
    // set PHY to normal mode
1902
    #Tp eth_phy.test_regs(0);
1903
    #Tp eth_phy.preamble_suppresed(0);
1904
    // MII mode register
1905
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1906
    if(fail == 0)
1907
      test_ok;
1908
    else
1909
      fail = 0;
1910 169 mohor
  end
1911
 
1912
 
1913 181 mohor
  ////////////////////////////////////////////////////////////////////
1914
  ////                                                            ////
1915
  ////  Test reading from phy with wrong phy address (host        ////
1916
  ////  reading high 'z' data)                                    ////
1917
  ////                                                            ////
1918
  ////////////////////////////////////////////////////////////////////
1919
  if (test_num == 7) // 
1920 169 mohor
  begin
1921 194 tadej
    // TEST 7: READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )
1922
    test_name   = "TEST 7: READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )";
1923
    `TIME; $display("  TEST 7: READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )");
1924 181 mohor
 
1925
    phy_addr = 5'h2; // wrong PHY address
1926
    // read request
1927
    #Tp mii_read_req(phy_addr, reg_addr);
1928
    check_mii_busy; // wait for read to finish
1929
    // read data
1930
    $display("  => Two errors will be displayed from WB Bus Monitor, because correct HIGH Z data was read");
1931 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1932 181 mohor
    if (tmp_data !== 16'hzzzz)
1933
    begin
1934
      test_fail("Data was read from PHY register with wrong PHY address - control register");
1935
      fail = fail + 1;
1936
    end
1937
    if(fail == 0)
1938
      test_ok;
1939
    else
1940
      fail = 0;
1941 169 mohor
  end
1942
 
1943
 
1944 181 mohor
  ////////////////////////////////////////////////////////////////////
1945
  ////                                                            ////
1946
  ////  Test writing to phy with wrong phy address and reading    ////
1947
  ////  from correct one                                          ////
1948
  ////                                                            ////
1949
  ////////////////////////////////////////////////////////////////////
1950
  if (test_num == 8) // 
1951 169 mohor
  begin
1952 194 tadej
    // TEST 8: WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE
1953
    test_name   = "TEST 8: WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE";
1954
    `TIME; $display("  TEST 8: WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE");
1955 181 mohor
 
1956
    // set address
1957
    reg_addr = 5'h0; // control register
1958
    phy_addr = 5'h2; // wrong PHY address
1959
    // write request
1960
    phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
1961
    #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1962
    check_mii_busy; // wait for write to finish
1963
 
1964
    phy_addr = 5'h1; // correct PHY address
1965
    // read request
1966
    #Tp mii_read_req(phy_addr, reg_addr);
1967
    check_mii_busy; // wait for read to finish
1968
    // read data
1969 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1970 181 mohor
    if (phy_data === tmp_data)
1971
    begin
1972
      test_fail("Data was written into PHY register with wrong PHY address - control register");
1973
      fail = fail + 1;
1974
    end
1975
    if(fail == 0)
1976
      test_ok;
1977
    else
1978
      fail = 0;
1979 169 mohor
  end
1980
 
1981
 
1982 181 mohor
  ////////////////////////////////////////////////////////////////////
1983
  ////                                                            ////
1984
  ////  Test sliding stop scan command immediately after read     ////
1985
  ////  request (with and without preamble)                       ////
1986
  ////                                                            ////
1987
  ////////////////////////////////////////////////////////////////////
1988
  if (test_num == 9) // 
1989 169 mohor
  begin
1990 194 tadej
    // TEST 9: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )
1991
    test_name = "TEST 9: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )";
1992 181 mohor
    `TIME;
1993 194 tadej
    $display("  TEST 9: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )");
1994 181 mohor
 
1995
    for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
1996 169 mohor
    begin
1997 181 mohor
      #Tp eth_phy.preamble_suppresed(i2);
1998
      // MII mode register
1999
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
2000
               wbm_subseq_waits);
2001
      i = 0;
2002
      cnt = 0;
2003
      while (i < 80) // delay for sliding of writing a STOP SCAN command
2004 169 mohor
      begin
2005 181 mohor
        for (i3 = 0; i3 <= 1; i3 = i3 + 1) // choose read or write after read will be finished
2006
        begin
2007
          // set address
2008
          reg_addr = 5'h0; // control register
2009
          phy_addr = 5'h1; // correct PHY address
2010
          cnt = 0;
2011
          // read request
2012
          #Tp mii_read_req(phy_addr, reg_addr);
2013
          fork
2014
            begin
2015
              repeat(i) @(posedge Mdc_O);
2016
              // write command 0x0 into MII command register
2017
              // MII command written while read in progress
2018
              wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2019
              @(posedge wb_clk);
2020
              #Tp check_mii_busy; // wait for read to finish
2021
            end
2022
            begin
2023
              // wait for serial bus to become active
2024
              wait(Mdio_IO !== 1'bz);
2025
              // count transfer length
2026
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
2027
              begin
2028
                @(posedge Mdc_O);
2029
                #Tp cnt = cnt + 1;
2030
              end
2031
            end
2032
          join
2033
          // check transfer length
2034
          if (i2) // without preamble
2035 169 mohor
          begin
2036 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
2037
            begin
2038
              test_fail("Read request did not proceed correctly, while SCAN STOP command was written");
2039
              fail = fail + 1;
2040
            end
2041 169 mohor
          end
2042 181 mohor
          else // with preamble
2043 169 mohor
          begin
2044 181 mohor
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
2045
            begin
2046
              test_fail("Read request did not proceed correctly, while SCAN STOP command was written");
2047
              fail = fail + 1;
2048
            end
2049
          end
2050
          // check the BUSY signal to see if the bus is still IDLE
2051
          for (i1 = 0; i1 < 8; i1 = i1 + 1)
2052
            check_mii_busy; // wait for bus to become idle
2053
 
2054
          // try normal write or read after read was finished
2055
          #Tp phy_data = {8'h7D, (i[7:0] + 1)};
2056
          #Tp cnt = 0;
2057
          if (i3 == 0) // write after read
2058
          begin
2059
            // write request
2060
            #Tp mii_write_req(phy_addr, reg_addr, phy_data);
2061 169 mohor
            // wait for serial bus to become active
2062
            wait(Mdio_IO !== 1'bz);
2063
            // count transfer length
2064 181 mohor
            while(Mdio_IO !== 1'bz)
2065 169 mohor
            begin
2066
              @(posedge Mdc_O);
2067
              #Tp cnt = cnt + 1;
2068
            end
2069 181 mohor
            @(posedge Mdc_O);
2070
            // read request
2071
            #Tp mii_read_req(phy_addr, reg_addr);
2072
            check_mii_busy; // wait for read to finish
2073
            // read and check data
2074 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2075 181 mohor
            if (phy_data !== tmp_data)
2076
            begin
2077
              test_fail("Data was not correctly written into OR read from PHY register - control register");
2078
              fail = fail + 1;
2079
            end
2080 169 mohor
          end
2081 181 mohor
          else // read after read
2082 169 mohor
          begin
2083 181 mohor
            // read request
2084
            #Tp mii_read_req(phy_addr, reg_addr);
2085
            // wait for serial bus to become active
2086
            wait(Mdio_IO !== 1'bz);
2087
            // count transfer length
2088
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
2089
            begin
2090
              @(posedge Mdc_O);
2091
              #Tp cnt = cnt + 1;
2092
            end
2093 169 mohor
            @(posedge Mdc_O);
2094 181 mohor
            check_mii_busy; // wait for read to finish
2095
            // read and check data
2096 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2097 181 mohor
            if (phy_data !== tmp_data)
2098
            begin
2099
              test_fail("Data was not correctly written into OR read from PHY register - control register");
2100
              fail = fail + 1;
2101
            end
2102 169 mohor
          end
2103 181 mohor
          // check if transfer was a proper length
2104
          if (i2) // without preamble
2105 169 mohor
          begin
2106 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
2107
            begin
2108
              test_fail("New request did not proceed correctly, after read request");
2109
              fail = fail + 1;
2110
            end
2111 169 mohor
          end
2112 181 mohor
          else // with preamble
2113 169 mohor
          begin
2114 181 mohor
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
2115
            begin
2116
              test_fail("New request did not proceed correctly, after read request");
2117
              fail = fail + 1;
2118
            end
2119 169 mohor
          end
2120
        end
2121 181 mohor
        #Tp;
2122
        // set delay of writing the command
2123 169 mohor
        if (i2) // without preamble
2124
        begin
2125 181 mohor
          case(i)
2126
            0, 1:               i = i + 1;
2127
            18, 19, 20, 21, 22,
2128
            23, 24, 25, 26, 27,
2129
            28, 29, 30, 31, 32,
2130
            33, 34, 35:         i = i + 1;
2131
            36:                 i = 80;
2132
            default:            i = 18;
2133
          endcase
2134 169 mohor
        end
2135
        else // with preamble
2136
        begin
2137 181 mohor
          case(i)
2138
            0, 1:               i = i + 1;
2139
            50, 51, 52, 53, 54,
2140
            55, 56, 57, 58, 59,
2141
            60, 61, 62, 63, 64,
2142
            65, 66, 67:         i = i + 1;
2143
            68:                 i = 80;
2144
            default:            i = 50;
2145
          endcase
2146 169 mohor
        end
2147 181 mohor
        @(posedge wb_clk);
2148 169 mohor
      end
2149
    end
2150 181 mohor
    // set PHY to normal mode
2151
    #Tp eth_phy.preamble_suppresed(0);
2152
    // MII mode register
2153
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2154
    if(fail == 0)
2155
      test_ok;
2156
    else
2157
      fail = 0;
2158 169 mohor
  end
2159
 
2160
 
2161 181 mohor
  ////////////////////////////////////////////////////////////////////
2162
  ////                                                            ////
2163
  ////  Test sliding stop scan command immediately after write    ////
2164
  ////  request (with and without preamble)                       ////
2165
  ////                                                            ////
2166
  ////////////////////////////////////////////////////////////////////
2167
  if (test_num == 10) // 
2168 169 mohor
  begin
2169 194 tadej
    // TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )
2170
    test_name = "TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )";
2171 181 mohor
    `TIME;
2172 194 tadej
    $display("  TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )");
2173 181 mohor
 
2174
    for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
2175 169 mohor
    begin
2176 181 mohor
      #Tp eth_phy.preamble_suppresed(i2);
2177
      // MII mode register
2178
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
2179
                wbm_subseq_waits);
2180
      i = 0;
2181
      cnt = 0;
2182
      while (i < 80) // delay for sliding of writing a STOP SCAN command
2183 169 mohor
      begin
2184 181 mohor
        for (i3 = 0; i3 <= 1; i3 = i3 + 1) // choose read or write after write will be finished
2185
        begin
2186
          // set address
2187
          reg_addr = 5'h0; // control register
2188
          phy_addr = 5'h1; // correct PHY address
2189
          cnt = 0;
2190
          // write request
2191
          phy_data = {8'h75, (i[7:0] + 1)};
2192
          #Tp mii_write_req(phy_addr, reg_addr, phy_data);
2193
          fork
2194
            begin
2195
              repeat(i) @(posedge Mdc_O);
2196
              // write command 0x0 into MII command register
2197
              // MII command written while read in progress
2198
              wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2199
              @(posedge wb_clk);
2200
              #Tp check_mii_busy; // wait for write to finish
2201
            end
2202
            begin
2203
              // wait for serial bus to become active
2204
              wait(Mdio_IO !== 1'bz);
2205
              // count transfer length
2206
              while(Mdio_IO !== 1'bz)
2207
              begin
2208
                @(posedge Mdc_O);
2209
                #Tp cnt = cnt + 1;
2210
              end
2211
            end
2212
          join
2213
          // check transfer length
2214
          if (i2) // without preamble
2215 169 mohor
          begin
2216 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
2217
            begin
2218
              test_fail("Write request did not proceed correctly, while SCAN STOP command was written");
2219
              fail = fail + 1;
2220
            end
2221 169 mohor
          end
2222 181 mohor
          else // with preamble
2223 169 mohor
          begin
2224 181 mohor
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
2225
            begin
2226
              test_fail("Write request did not proceed correctly, while SCAN STOP command was written");
2227
              fail = fail + 1;
2228
            end
2229
          end
2230
          // check the BUSY signal to see if the bus is still IDLE
2231
          for (i1 = 0; i1 < 8; i1 = i1 + 1)
2232
            check_mii_busy; // wait for bus to become idle
2233
 
2234
          // try normal write or read after write was finished
2235
          #Tp cnt = 0;
2236
          if (i3 == 0) // write after write
2237
          begin
2238
            phy_data = {8'h7A, (i[7:0] + 1)};
2239
            // write request
2240
            #Tp mii_write_req(phy_addr, reg_addr, phy_data);
2241 169 mohor
            // wait for serial bus to become active
2242
            wait(Mdio_IO !== 1'bz);
2243
            // count transfer length
2244
            while(Mdio_IO !== 1'bz)
2245
            begin
2246
              @(posedge Mdc_O);
2247
              #Tp cnt = cnt + 1;
2248
            end
2249 181 mohor
            @(posedge Mdc_O);
2250
            // read request
2251
            #Tp mii_read_req(phy_addr, reg_addr);
2252
            check_mii_busy; // wait for read to finish
2253
            // read and check data
2254 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, tmp_data , 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2255 181 mohor
            if (phy_data !== tmp_data)
2256
            begin
2257
              test_fail("Data was not correctly written into OR read from PHY register - control register");
2258
              fail = fail + 1;
2259
            end
2260 169 mohor
          end
2261 181 mohor
          else // read after write
2262 169 mohor
          begin
2263 181 mohor
            // read request
2264
            #Tp mii_read_req(phy_addr, reg_addr);
2265
            // wait for serial bus to become active
2266
            wait(Mdio_IO !== 1'bz);
2267
            // count transfer length
2268
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
2269
            begin
2270
              @(posedge Mdc_O);
2271
              #Tp cnt = cnt + 1;
2272
            end
2273 169 mohor
            @(posedge Mdc_O);
2274 181 mohor
            check_mii_busy; // wait for read to finish
2275
            // read and check data
2276 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, tmp_data , 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2277 181 mohor
            if (phy_data !== tmp_data)
2278
            begin
2279
              test_fail("Data was not correctly written into OR read from PHY register - control register");
2280
              fail = fail + 1;
2281
            end
2282 169 mohor
          end
2283 181 mohor
          // check if transfer was a proper length
2284
          if (i2) // without preamble
2285 169 mohor
          begin
2286 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
2287
            begin
2288
              test_fail("New request did not proceed correctly, after write request");
2289
              fail = fail + 1;
2290
            end
2291 169 mohor
          end
2292 181 mohor
          else // with preamble
2293 169 mohor
          begin
2294 181 mohor
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
2295
            begin
2296
              test_fail("New request did not proceed correctly, after write request");
2297
              fail = fail + 1;
2298
            end
2299 169 mohor
          end
2300
        end
2301 181 mohor
        #Tp;
2302
        // set delay of writing the command
2303 169 mohor
        if (i2) // without preamble
2304
        begin
2305 181 mohor
          case(i)
2306
            0, 1:               i = i + 1;
2307
            18, 19, 20, 21, 22,
2308
            23, 24, 25, 26, 27,
2309
            28, 29, 30, 31, 32,
2310
            33, 34, 35:         i = i + 1;
2311
            36:                 i = 80;
2312
            default:            i = 18;
2313
          endcase
2314 169 mohor
        end
2315
        else // with preamble
2316
        begin
2317 181 mohor
          case(i)
2318
            0, 1:               i = i + 1;
2319
            50, 51, 52, 53, 54,
2320
            55, 56, 57, 58, 59,
2321
            60, 61, 62, 63, 64,
2322
            65, 66, 67:         i = i + 1;
2323
            68:                 i = 80;
2324
            default:            i = 50;
2325
          endcase
2326 169 mohor
        end
2327 181 mohor
        @(posedge wb_clk);
2328 169 mohor
      end
2329
    end
2330 181 mohor
    // set PHY to normal mode
2331
    #Tp eth_phy.preamble_suppresed(0);
2332
    // MII mode register
2333
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2334
    if(fail == 0)
2335
      test_ok;
2336
    else
2337
      fail = 0;
2338 169 mohor
  end
2339
 
2340
 
2341 181 mohor
  ////////////////////////////////////////////////////////////////////
2342
  ////                                                            ////
2343
  ////  Test busy and nvalid status durations during write (with  ////
2344
  ////  and without preamble)                                     ////
2345
  ////                                                            ////
2346
  ////////////////////////////////////////////////////////////////////
2347
  if (test_num == 11) // 
2348 169 mohor
  begin
2349 194 tadej
    // TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )
2350
    test_name   = "TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )";
2351
    `TIME; $display("  TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )");
2352 181 mohor
 
2353
    reset_mii; // reset MII
2354
    // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2355
    #Tp eth_phy.link_up_down(1);
2356
    // set the MII
2357
    clk_div = 64;
2358
    mii_set_clk_div(clk_div[7:0]);
2359
    // set address
2360
    reg_addr = 5'h1; // status register
2361
    phy_addr = 5'h1; // correct PHY address
2362
 
2363
    for (i = 0; i <= 1; i = i + 1)
2364 169 mohor
    begin
2365 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
2366
      // MII mode register
2367
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2368
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2369
      @(posedge Mdc_O);
2370
      // write request
2371
      #Tp mii_write_req(phy_addr, reg_addr, 16'h5A5A);
2372
      // read data from MII status register - Busy and Nvalid bits
2373 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2374 181 mohor
 
2375
      // check MII IO signal and Busy and Nvalid bits
2376
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2377 169 mohor
      begin
2378 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");
2379
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2380
        begin
2381
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2382
          fail = fail + 1;
2383
        end
2384
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2385
        begin
2386
          test_fail("Nvalid signal was set during write");
2387
          fail = fail + 1;
2388
        end
2389 169 mohor
      end
2390 181 mohor
      else // Busy bit should already be set to '1', due to reads from MII status register
2391 169 mohor
      begin
2392 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2393
        begin
2394
          test_fail("Busy signal should be set after write, due to reads from MII status register");
2395
          fail = fail + 1;
2396
        end
2397
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2398
        begin
2399
          test_fail("Nvalid signal was set during write");
2400
          fail = fail + 1;
2401
        end
2402 169 mohor
      end
2403 181 mohor
 
2404
      // wait for serial bus to become active
2405
      wait(Mdio_IO !== 1'bz);
2406
      // count transfer bits
2407
      if (i)
2408 169 mohor
      begin
2409 181 mohor
        repeat(32) @(posedge Mdc_O);
2410 169 mohor
      end
2411 181 mohor
      else
2412 169 mohor
      begin
2413 181 mohor
        repeat(64) @(posedge Mdc_O);
2414 169 mohor
      end
2415 181 mohor
      // read data from MII status register - Busy and Nvalid bits
2416 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2417 181 mohor
 
2418
      // check MII IO signal and Busy and Nvalid bits
2419
      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2420 169 mohor
      begin
2421 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2422
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2423
        begin
2424
          test_fail("Busy signal should be set while MII IO signal is not active anymore");
2425
          fail = fail + 1;
2426
        end
2427
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2428
        begin
2429
          test_fail("Nvalid signal was set during write");
2430
          fail = fail + 1;
2431
        end
2432 169 mohor
      end
2433 181 mohor
      else // Busy bit should still be set to '1'
2434 169 mohor
      begin
2435 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2436
        begin
2437
          test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2438
          fail = fail + 1;
2439
        end
2440
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2441
        begin
2442
          test_fail("Nvalid signal was set during write");
2443
          fail = fail + 1;
2444
        end
2445 169 mohor
      end
2446 181 mohor
 
2447
      // wait for next negative clock edge
2448
      @(negedge Mdc_O);
2449 169 mohor
      // read data from MII status register - Busy and Nvalid bits
2450 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2451 181 mohor
 
2452 169 mohor
      // check MII IO signal and Busy and Nvalid bits
2453
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2454
      begin
2455
        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2456
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2457
        begin
2458
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2459
          fail = fail + 1;
2460
        end
2461
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2462
        begin
2463
          test_fail("Nvalid signal was set during write");
2464
          fail = fail + 1;
2465
        end
2466
      end
2467 181 mohor
      else // Busy bit should still be set to '1'
2468 169 mohor
      begin
2469
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2470
        begin
2471 181 mohor
          test_fail("Busy signal should be set after MII IO signal become HIGH Z");
2472
          fail = fail + 1;
2473 169 mohor
        end
2474 181 mohor
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2475 169 mohor
        begin
2476 181 mohor
          test_fail("Nvalid signal was set during write");
2477
          fail = fail + 1;
2478
        end
2479
      end
2480
 
2481
      // wait for Busy to become inactive
2482
      i1 = 0;
2483
      while (i1 <= 2)
2484
      begin
2485
        // wait for next positive clock edge
2486
        @(posedge Mdc_O);
2487
        // read data from MII status register - Busy and Nvalid bits
2488 274 tadejm
        wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2489 181 mohor
 
2490
        // check MII IO signal and Busy and Nvalid bits
2491
        if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2492
        begin
2493
          test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2494
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2495 169 mohor
          begin
2496 181 mohor
            test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2497 169 mohor
            fail = fail + 1;
2498
          end
2499 181 mohor
          if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2500
          begin
2501
            test_fail("Nvalid signal was set during write");
2502
            fail = fail + 1;
2503
          end
2504 169 mohor
        end
2505 181 mohor
        else // wait for Busy bit to be set to '0'
2506 169 mohor
        begin
2507 181 mohor
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2508
          begin
2509
            i1 = 3; // end of Busy checking
2510
          end
2511
          else
2512
          begin
2513
            if (i1 == 2)
2514
            begin
2515
              test_fail("Busy signal should be cleared after 2 periods after MII IO signal become HIGH Z");
2516
              fail = fail + 1;
2517
            end
2518
            #Tp i1 = i1 + 1;
2519
          end
2520
          if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2521
          begin
2522
            test_fail("Nvalid signal was set after write");
2523
            fail = fail + 1;
2524
          end
2525 169 mohor
        end
2526
      end
2527
    end
2528 181 mohor
    // set PHY to normal mode
2529
    #Tp eth_phy.preamble_suppresed(0);
2530
    // MII mode register
2531
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2532
    if(fail == 0)
2533
      test_ok;
2534
    else
2535
      fail = 0;
2536 116 mohor
  end
2537
 
2538
 
2539 181 mohor
  ////////////////////////////////////////////////////////////////////
2540
  ////                                                            ////
2541
  ////  Test busy and nvalid status durations during write (with  ////
2542
  ////  and without preamble)                                     ////
2543
  ////                                                            ////
2544
  ////////////////////////////////////////////////////////////////////
2545
  if (test_num == 12) // 
2546 169 mohor
  begin
2547 194 tadej
    // TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )
2548
    test_name   = "TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )";
2549
    `TIME; $display("  TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )");
2550 181 mohor
 
2551
    reset_mii; // reset MII
2552
    // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2553
    #Tp eth_phy.link_up_down(1);
2554
    // set the MII
2555
    clk_div = 64;
2556
    mii_set_clk_div(clk_div[7:0]);
2557
    // set address
2558
    reg_addr = 5'h1; // status register
2559
    phy_addr = 5'h1; // correct PHY address
2560
 
2561
    for (i = 0; i <= 1; i = i + 1)
2562 169 mohor
    begin
2563 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
2564
      // MII mode register
2565
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2566
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2567 169 mohor
      @(posedge Mdc_O);
2568 181 mohor
      // read request
2569
      #Tp mii_read_req(phy_addr, reg_addr);
2570 169 mohor
      // read data from MII status register - Busy and Nvalid bits
2571 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2572 181 mohor
 
2573 169 mohor
      // check MII IO signal and Busy and Nvalid bits
2574
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2575
      begin
2576 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");
2577 169 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2578
        begin
2579 181 mohor
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2580 169 mohor
          fail = fail + 1;
2581
        end
2582
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2583
        begin
2584
          test_fail("Nvalid signal was set during read");
2585
          fail = fail + 1;
2586
        end
2587
      end
2588 181 mohor
      else // Busy bit should already be set to '1', due to reads from MII status register
2589 169 mohor
      begin
2590
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2591
        begin
2592 181 mohor
          test_fail("Busy signal should be set after read, due to reads from MII status register");
2593
          fail = fail + 1;
2594 169 mohor
        end
2595
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2596
        begin
2597 181 mohor
          test_fail("Nvalid signal was set during read");
2598 169 mohor
          fail = fail + 1;
2599
        end
2600
      end
2601 181 mohor
 
2602
      // wait for serial bus to become active
2603
      wait(Mdio_IO !== 1'bz);
2604
      // count transfer bits
2605
      if (i)
2606 169 mohor
      begin
2607 181 mohor
        repeat(31) @(posedge Mdc_O);
2608 169 mohor
      end
2609 181 mohor
      else
2610 169 mohor
      begin
2611 181 mohor
        repeat(63) @(posedge Mdc_O);
2612 169 mohor
      end
2613 181 mohor
      // wait for next negative clock edge
2614
      @(negedge Mdc_O);
2615
      // read data from MII status register - Busy and Nvalid bits
2616 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2617 181 mohor
 
2618
      // check MII IO signal and Busy and Nvalid bits
2619
      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2620 169 mohor
      begin
2621 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2622
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2623
        begin
2624
          test_fail("Busy signal should be set while MII IO signal is not active anymore");
2625
          fail = fail + 1;
2626
        end
2627
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2628
        begin
2629
          test_fail("Nvalid signal was set during read");
2630
          fail = fail + 1;
2631
        end
2632 169 mohor
      end
2633 181 mohor
      else // Busy bit should still be set to '1'
2634 169 mohor
      begin
2635 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2636
        begin
2637
          test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2638
          fail = fail + 1;
2639
        end
2640
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2641
        begin
2642
          test_fail("Nvalid signal was set during read");
2643
          fail = fail + 1;
2644
        end
2645 169 mohor
      end
2646 181 mohor
 
2647 169 mohor
      // wait for next positive clock edge
2648
      @(posedge Mdc_O);
2649
      // read data from MII status register - Busy and Nvalid bits
2650 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2651 181 mohor
 
2652 169 mohor
      // check MII IO signal and Busy and Nvalid bits
2653
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2654
      begin
2655
        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2656 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2657 169 mohor
        begin
2658 181 mohor
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2659
          fail = fail + 1;
2660
        end
2661
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2662
        begin
2663
          test_fail("Nvalid signal was set during read");
2664
          fail = fail + 1;
2665
        end
2666
      end
2667
      else // Busy bit should still be set to '1'
2668
      begin
2669
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2670
        begin
2671
          test_fail("Busy signal should be set after MII IO signal become HIGH Z");
2672
          fail = fail + 1;
2673
        end
2674
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2675
        begin
2676
          test_fail("Nvalid signal was set during read");
2677
          fail = fail + 1;
2678
        end
2679
      end
2680
 
2681
      // wait for Busy to become inactive
2682
      i1 = 0;
2683
      while (i1 <= 2)
2684
      begin
2685
        // wait for next positive clock edge
2686
        @(posedge Mdc_O);
2687
        // read data from MII status register - Busy and Nvalid bits
2688 274 tadejm
        wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2689 181 mohor
 
2690
        // check MII IO signal and Busy and Nvalid bits
2691
        if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2692
        begin
2693
          test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2694 169 mohor
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2695
          begin
2696
            test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2697
            fail = fail + 1;
2698
          end
2699 181 mohor
          if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2700 169 mohor
          begin
2701 181 mohor
            test_fail("Nvalid signal was set during read");
2702 169 mohor
            fail = fail + 1;
2703
          end
2704
        end
2705 181 mohor
        else // wait for Busy bit to be set to '0'
2706 169 mohor
        begin
2707
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2708
          begin
2709
            i1 = 3; // end of Busy checking
2710
          end
2711
          else
2712
          begin
2713
            if (i1 == 2)
2714
            begin
2715
              test_fail("Busy signal should be cleared after 2 periods after MII IO signal become HIGH Z");
2716
              fail = fail + 1;
2717
            end
2718
            #Tp i1 = i1 + 1;
2719
          end
2720 181 mohor
          if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2721 169 mohor
          begin
2722 181 mohor
            test_fail("Nvalid signal was set after read");
2723 169 mohor
            fail = fail + 1;
2724
          end
2725
        end
2726
      end
2727
    end
2728 181 mohor
    // set PHY to normal mode
2729
    #Tp eth_phy.preamble_suppresed(0);
2730
    // MII mode register
2731
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2732
    if(fail == 0)
2733
      test_ok;
2734
    else
2735
      fail = 0;
2736 169 mohor
  end
2737
 
2738
 
2739 181 mohor
  ////////////////////////////////////////////////////////////////////
2740
  ////                                                            ////
2741
  ////  Test busy and nvalid status durations during scan (with   ////
2742
  ////  and without preamble)                                     ////
2743
  ////                                                            ////
2744
  ////////////////////////////////////////////////////////////////////
2745
  if (test_num == 13) // 
2746 169 mohor
  begin
2747 194 tadej
    // TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )
2748
    test_name   = "TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )";
2749
    `TIME; $display("  TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )");
2750 181 mohor
 
2751
    reset_mii; // reset MII
2752
    // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2753
    #Tp eth_phy.link_up_down(1);
2754
    // set the MII
2755
    clk_div = 64;
2756
    mii_set_clk_div(clk_div[7:0]);
2757
    // set address
2758
    reg_addr = 5'h1; // status register
2759
    phy_addr = 5'h1; // correct PHY address
2760
 
2761
    for (i = 0; i <= 1; i = i + 1)
2762 169 mohor
    begin
2763 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
2764
      // MII mode register
2765
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2766
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2767
      @(posedge Mdc_O);
2768
      // scan request
2769
      #Tp mii_scan_req(phy_addr, reg_addr);
2770
      // read data from MII status register - Busy and Nvalid bits
2771 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2772 181 mohor
 
2773
      // check MII IO signal and Busy and Nvalid bits
2774
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2775 169 mohor
      begin
2776 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");
2777
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2778
        begin
2779
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2780
          fail = fail + 1;
2781
        end
2782
        if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2783
        begin
2784
          test_fail("Nvalid signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2785
          fail = fail + 1;
2786
        end
2787 169 mohor
      end
2788 181 mohor
      else // Busy bit should already be set to '1', due to reads from MII status register
2789 169 mohor
      begin
2790 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2791
        begin
2792
          test_fail("Busy signal should be set after scan, due to reads from MII status register");
2793
          fail = fail + 1;
2794
        end
2795
        if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2796
        begin
2797
          test_fail("Nvalid signal should be set after scan, due to reads from MII status register");
2798
          fail = fail + 1;
2799
        end
2800 169 mohor
      end
2801 181 mohor
 
2802
      // wait for serial bus to become active
2803 169 mohor
      wait(Mdio_IO !== 1'bz);
2804 181 mohor
      // count transfer bits
2805
      if (i)
2806 169 mohor
      begin
2807 181 mohor
        repeat(21) @(posedge Mdc_O);
2808 169 mohor
      end
2809 181 mohor
      else
2810 169 mohor
      begin
2811 181 mohor
        repeat(53) @(posedge Mdc_O);
2812 169 mohor
      end
2813 181 mohor
      // stop scan
2814
      #Tp mii_scan_finish; // finish scan operation
2815
 
2816
      // wait for next positive clock edge
2817
      repeat(10) @(posedge Mdc_O);
2818
      // read data from MII status register - Busy and Nvalid bits
2819 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2820 181 mohor
 
2821
      // check MII IO signal and Busy and Nvalid bits
2822
      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2823 169 mohor
      begin
2824 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2825
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2826 169 mohor
        begin
2827 181 mohor
          test_fail("Busy signal should be set while MII IO signal is not active anymore");
2828 169 mohor
          fail = fail + 1;
2829
        end
2830 181 mohor
        // Nvalid signal can be cleared here - it is still Testbench error
2831 169 mohor
      end
2832 181 mohor
      else // Busy bit should still be set to '1', Nvalid bit should still be set to '1'
2833 169 mohor
      begin
2834 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2835 169 mohor
        begin
2836 181 mohor
          test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2837 169 mohor
          fail = fail + 1;
2838
        end
2839 181 mohor
        if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2840 169 mohor
        begin
2841 181 mohor
          test_fail("Nvalid signal should be set while MII IO signal not HIGH Z");
2842 169 mohor
          fail = fail + 1;
2843
        end
2844 181 mohor
      end
2845
 
2846
      // wait for next negative clock edge
2847
      @(negedge Mdc_O);
2848
      // read data from MII status register - Busy and Nvalid bits
2849 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2850 181 mohor
 
2851
      // check MII IO signal and Busy and Nvalid bits
2852
      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2853
      begin
2854
        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2855
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2856 169 mohor
        begin
2857 181 mohor
          test_fail("Busy signal should be set while MII IO signal is not active anymore");
2858
          fail = fail + 1;
2859 169 mohor
        end
2860 181 mohor
        // Nvalid signal can be cleared here - it is still Testbench error
2861 169 mohor
      end
2862 181 mohor
      else // Busy bit should still be set to '1', Nvalid bit should still be set to '1'
2863 169 mohor
      begin
2864 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2865 169 mohor
        begin
2866 181 mohor
          test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2867
          fail = fail + 1;
2868 169 mohor
        end
2869 181 mohor
        if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2870 169 mohor
        begin
2871 181 mohor
          test_fail("Nvalid signal should be set while MII IO signal not HIGH Z");
2872
          fail = fail + 1;
2873 169 mohor
        end
2874
      end
2875 181 mohor
 
2876
      // wait for next negative clock edge
2877
      @(posedge Mdc_O);
2878
      // read data from MII status register - Busy and Nvalid bits
2879 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2880 181 mohor
 
2881
      // check MII IO signal and Busy and Nvalid bits
2882
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2883 169 mohor
      begin
2884 181 mohor
        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2885
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2886 169 mohor
        begin
2887 181 mohor
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2888 169 mohor
          fail = fail + 1;
2889
        end
2890 181 mohor
        if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2891 169 mohor
        begin
2892 181 mohor
          test_fail("Nvalid signal was not set while MII IO signal is not HIGH Z");
2893 169 mohor
          fail = fail + 1;
2894
        end
2895
      end
2896 181 mohor
      else // Busy bit should still be set to '1', Nvalid bit can be set to '0'
2897 169 mohor
      begin
2898 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2899 169 mohor
        begin
2900 181 mohor
          test_fail("Busy signal should be set after MII IO signal become HIGH Z");
2901
          fail = fail + 1;
2902 169 mohor
        end
2903 181 mohor
        if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2904 169 mohor
        begin
2905 181 mohor
          i2 = 1; // check finished
2906 169 mohor
        end
2907 181 mohor
        else
2908 169 mohor
        begin
2909 181 mohor
          i2 = 0; // check must continue
2910 169 mohor
        end
2911
      end
2912 181 mohor
 
2913
      // wait for Busy to become inactive
2914
      i1 = 0;
2915
      while ((i1 <= 2) || (i2 == 0))
2916
      begin
2917
        // wait for next positive clock edge
2918
        @(posedge Mdc_O);
2919
        // read data from MII status register - Busy and Nvalid bits
2920 274 tadejm
        wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2921 181 mohor
 
2922
        // check MII IO signal and Busy and Nvalid bits
2923
        if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2924 169 mohor
        begin
2925 181 mohor
          test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2926
          if (i1 <= 2)
2927 169 mohor
          begin
2928 181 mohor
            if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2929 169 mohor
            begin
2930 181 mohor
              test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2931 169 mohor
              fail = fail + 1;
2932
            end
2933
          end
2934 181 mohor
          if (i2 == 0)
2935 169 mohor
          begin
2936 181 mohor
            if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2937 169 mohor
            begin
2938 181 mohor
              test_fail("Nvalid signal was not set while MII IO signal is not HIGH Z");
2939 169 mohor
              fail = fail + 1;
2940
            end
2941
          end
2942
        end
2943 181 mohor
        else // wait for Busy bit to be set to '0'
2944 169 mohor
        begin
2945 181 mohor
          if (i1 <= 2)
2946 169 mohor
          begin
2947 181 mohor
            if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2948 169 mohor
            begin
2949 181 mohor
              i1 = 3; // end of Busy checking
2950 169 mohor
            end
2951 181 mohor
            else
2952 169 mohor
            begin
2953 181 mohor
              if (i1 == 2)
2954 169 mohor
              begin
2955 181 mohor
                test_fail("Busy signal should be cleared after 2 periods after MII IO signal become HIGH Z");
2956 169 mohor
                fail = fail + 1;
2957
              end
2958 181 mohor
              #Tp i1 = i1 + 1;
2959 169 mohor
            end
2960 181 mohor
          end
2961
          if (i2 == 0)
2962
          begin
2963
            if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2964 169 mohor
            begin
2965 181 mohor
              i2 = 1;
2966 169 mohor
            end
2967 181 mohor
            else
2968
            begin
2969
              test_fail("Nvalid signal should be cleared after MII IO signal become HIGH Z");
2970
              fail = fail + 1;
2971
            end
2972 169 mohor
          end
2973
        end
2974 181 mohor
      end
2975
    end
2976
    // set PHY to normal mode
2977
    #Tp eth_phy.preamble_suppresed(0);
2978
    // MII mode register
2979
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2980
    if(fail == 0)
2981
      test_ok;
2982
    else
2983
      fail = 0;
2984
  end
2985
 
2986
 
2987
  ////////////////////////////////////////////////////////////////////
2988
  ////                                                            ////
2989
  ////  Test scan status from phy with detecting link-fail bit    ////
2990
  ////  (with and without preamble)                               ////
2991
  ////                                                            ////
2992
  ////////////////////////////////////////////////////////////////////
2993
  if (test_num == 14) // 
2994
  begin
2995 194 tadej
    // TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )
2996
    test_name   = "TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )";
2997
    `TIME; $display("  TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )");
2998 181 mohor
 
2999
    reset_mii; // reset MII
3000
    // set link up, if it wasn't due to previous tests, since there weren't PHY registers
3001
    #Tp eth_phy.link_up_down(1);
3002
    // set MII speed
3003
    clk_div = 6;
3004
    mii_set_clk_div(clk_div[7:0]);
3005
    // set address
3006
    reg_addr = 5'h1; // status register
3007
    phy_addr = 5'h1; // correct PHY address
3008
 
3009
    // read request
3010
    #Tp mii_read_req(phy_addr, reg_addr);
3011
    check_mii_busy; // wait for read to finish
3012
    // read data from PHY status register - remember LINK-UP status
3013 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3014 181 mohor
 
3015
    for (i = 0; i <= 1; i = i + 1)
3016
    begin
3017
      #Tp eth_phy.preamble_suppresed(i);
3018
      // MII mode register
3019
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
3020
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3021
      if (i)
3022
      begin
3023
        // change saved data when preamble is suppressed
3024
        #Tp tmp_data = tmp_data | 16'h0040; // put bit 6 to ONE
3025
      end
3026
 
3027
      // scan request
3028
      #Tp mii_scan_req(phy_addr, reg_addr);
3029
      check_mii_scan_valid; // wait for scan to make first data valid
3030
 
3031 169 mohor
      fork
3032 181 mohor
      begin
3033 169 mohor
        repeat(2) @(posedge Mdc_O);
3034
        // read data from PHY status register
3035 274 tadejm
        wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3036 181 mohor
        if (phy_data !== tmp_data)
3037 169 mohor
        begin
3038 181 mohor
          test_fail("Data was not correctly scaned from status register");
3039 169 mohor
          fail = fail + 1;
3040
        end
3041
        // read data from MII status register
3042 274 tadejm
        wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3043 181 mohor
        if (phy_data[0] !== 1'b0)
3044 169 mohor
        begin
3045 181 mohor
          test_fail("Link FAIL bit was set in the MII status register");
3046 169 mohor
          fail = fail + 1;
3047
        end
3048
      end
3049
      begin
3050 181 mohor
      // Completely check second scan
3051 169 mohor
        #Tp cnt = 0;
3052
        // wait for serial bus to become active - second scan
3053
        wait(Mdio_IO !== 1'bz);
3054
        // count transfer length
3055 181 mohor
        while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i == 0)) || ((cnt == 15) && (i == 1)) )
3056 169 mohor
        begin
3057
          @(posedge Mdc_O);
3058
          #Tp cnt = cnt + 1;
3059
        end
3060
        // check transfer length
3061 181 mohor
        if (i) // without preamble
3062 169 mohor
        begin
3063
          if (cnt != 33) // at this value Mdio_IO is HIGH Z
3064
          begin
3065 181 mohor
            test_fail("Second scan request did not proceed correctly");
3066 169 mohor
            fail = fail + 1;
3067
          end
3068
        end
3069
        else // with preamble
3070
        begin
3071
          if (cnt != 65) // at this value Mdio_IO is HIGH Z
3072
          begin
3073 181 mohor
            test_fail("Second scan request did not proceed correctly");
3074 169 mohor
            fail = fail + 1;
3075
          end
3076
        end
3077
      end
3078
      join
3079 181 mohor
      // check third to fifth scans
3080
      for (i3 = 0; i3 <= 2; i3 = i3 + 1)
3081
      begin
3082
        fork
3083 169 mohor
        begin
3084
          repeat(2) @(posedge Mdc_O);
3085
          // read data from PHY status register
3086 274 tadejm
          wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3087 181 mohor
          if (phy_data !== tmp_data)
3088 169 mohor
          begin
3089 181 mohor
            test_fail("Data was not correctly scaned from status register");
3090
            fail = fail + 1;
3091 169 mohor
          end
3092
          // read data from MII status register
3093 274 tadejm
          wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3094 181 mohor
          if (phy_data[0] !== 1'b0)
3095 169 mohor
          begin
3096 181 mohor
            test_fail("Link FAIL bit was set in the MII status register");
3097
            fail = fail + 1;
3098 169 mohor
          end
3099 181 mohor
          if (i3 == 2) // after fourth scan read
3100 169 mohor
          begin
3101 181 mohor
            @(posedge Mdc_O);
3102
            // change saved data
3103
            #Tp tmp_data = tmp_data & 16'hFFFB; // put bit 3 to ZERO
3104
            // set link down
3105
            #Tp eth_phy.link_up_down(0);
3106 169 mohor
          end
3107
        end
3108
        begin
3109 181 mohor
        // Completely check scans
3110
          #Tp cnt = 0;
3111
          // wait for serial bus to become active - second scan
3112
          wait(Mdio_IO !== 1'bz);
3113
          // count transfer length
3114
          while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i == 0)) || ((cnt == 15) && (i == 1)) )
3115 169 mohor
          begin
3116 181 mohor
            @(posedge Mdc_O);
3117
            #Tp cnt = cnt + 1;
3118
          end
3119
          // check transfer length
3120
          if (i) // without preamble
3121
          begin
3122
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
3123 169 mohor
            begin
3124 181 mohor
              test_fail("Fifth scan request did not proceed correctly");
3125
              fail = fail + 1;
3126 169 mohor
            end
3127 181 mohor
          end
3128
          else // with preamble
3129
          begin
3130
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
3131 169 mohor
            begin
3132 181 mohor
              test_fail("Fifth scan request did not proceed correctly");
3133
              fail = fail + 1;
3134 169 mohor
            end
3135
          end
3136
        end
3137 181 mohor
        join
3138
      end
3139
 
3140
      fork
3141
      begin
3142
        repeat(2) @(posedge Mdc_O);
3143
        // read data from PHY status register
3144 274 tadejm
        wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3145 181 mohor
        if (phy_data !== tmp_data)
3146
        begin
3147
          test_fail("Data was not correctly scaned from status register");
3148
          fail = fail + 1;
3149
        end
3150
        // read data from MII status register
3151 274 tadejm
        wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3152 181 mohor
        if (phy_data[0] === 1'b0)
3153
        begin
3154
          test_fail("Link FAIL bit was not set in the MII status register");
3155
          fail = fail + 1;
3156
        end
3157
        // wait to see if data stayed latched
3158
        repeat(4) @(posedge Mdc_O);
3159
        // read data from PHY status register
3160 274 tadejm
        wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3161 181 mohor
        if (phy_data !== tmp_data)
3162
        begin
3163
          test_fail("Data was not latched correctly in status register");
3164
          fail = fail + 1;
3165
        end
3166
        // read data from MII status register
3167 274 tadejm
        wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3168 181 mohor
        if (phy_data[0] === 1'b0)
3169
        begin
3170
          test_fail("Link FAIL bit was not set in the MII status register");
3171
          fail = fail + 1;
3172
        end
3173
        // change saved data
3174
        #Tp tmp_data = tmp_data | 16'h0004; // put bit 2 to ONE
3175
        // set link up
3176
        #Tp eth_phy.link_up_down(1);
3177
      end
3178
      begin
3179
      // Wait for sixth scan
3180
        // wait for serial bus to become active - sixth scan
3181
        wait(Mdio_IO !== 1'bz);
3182
        // wait for serial bus to become inactive - turn-around cycle in sixth scan
3183
        wait(Mdio_IO === 1'bz);
3184
        // wait for serial bus to become active - end of turn-around cycle in sixth scan
3185
        wait(Mdio_IO !== 1'bz);
3186
        // wait for serial bus to become inactive - end of sixth scan
3187
        wait(Mdio_IO === 1'bz);
3188
      end
3189 169 mohor
      join
3190 181 mohor
 
3191
      @(posedge Mdc_O);
3192 169 mohor
      // read data from PHY status register
3193 274 tadejm
      wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3194 169 mohor
      if (phy_data !== tmp_data)
3195
      begin
3196 181 mohor
        test_fail("Data was not correctly scaned from status register");
3197 169 mohor
        fail = fail + 1;
3198
      end
3199
      // read data from MII status register
3200 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3201 169 mohor
      if (phy_data[0] !== 1'b0)
3202
      begin
3203
        test_fail("Link FAIL bit was set in the MII status register");
3204
        fail = fail + 1;
3205
      end
3206 181 mohor
      // wait to see if data stayed latched
3207
      repeat(4) @(posedge Mdc_O);
3208
      // read data from PHY status register
3209 274 tadejm
      wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3210 181 mohor
      if (phy_data !== tmp_data)
3211 169 mohor
      begin
3212 181 mohor
        test_fail("Data was not correctly scaned from status register");
3213
        fail = fail + 1;
3214 169 mohor
      end
3215 181 mohor
      // read data from MII status register
3216 274 tadejm
      wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3217 181 mohor
      if (phy_data[0] !== 1'b0)
3218 169 mohor
      begin
3219 181 mohor
        test_fail("Link FAIL bit was set in the MII status register");
3220
        fail = fail + 1;
3221 169 mohor
      end
3222 181 mohor
 
3223
      // STOP SCAN
3224
      #Tp mii_scan_finish; // finish scan operation
3225
      #Tp check_mii_busy; // wait for scan to finish
3226 169 mohor
    end
3227 181 mohor
    // set PHY to normal mode
3228
    #Tp eth_phy.preamble_suppresed(0);
3229
    // MII mode register
3230
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3231
    if(fail == 0)
3232
      test_ok;
3233
    else
3234
      fail = 0;
3235 169 mohor
  end
3236
 
3237
 
3238 181 mohor
  ////////////////////////////////////////////////////////////////////
3239
  ////                                                            ////
3240
  ////  Test scan status from phy with sliding link-fail bit      ////
3241
  ////  (with and without preamble)                               ////
3242
  ////                                                            ////
3243
  ////////////////////////////////////////////////////////////////////
3244
  if (test_num == 15) // 
3245 169 mohor
  begin
3246 194 tadej
    // TEST 15: SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )
3247
    test_name   = "TEST 15: SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )";
3248
    `TIME; $display("  TEST 15: SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )");
3249 181 mohor
 
3250
    // set address
3251
    reg_addr = 5'h1; // status register
3252
    phy_addr = 5'h1; // correct PHY address
3253
 
3254
    // read request
3255
    #Tp mii_read_req(phy_addr, reg_addr);
3256
    check_mii_busy; // wait for read to finish
3257
    // read data from PHY status register - remember LINK-UP status
3258 274 tadejm
    wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3259 181 mohor
 
3260
    for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
3261 169 mohor
    begin
3262 181 mohor
      #Tp eth_phy.preamble_suppresed(i2);
3263
      // MII mode register
3264
      #Tp wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
3265
                    wbm_subseq_waits);
3266
      if (i2)
3267 169 mohor
      begin
3268 181 mohor
        // change saved data when preamble is suppressed
3269
        #Tp tmp_data = tmp_data | 16'h0040; // put bit 6 to ONE
3270
      end
3271
 
3272
      i = 0;
3273
      while (i < 80) // delay for sliding of LinkFail bit
3274
      begin
3275
        // first there are two scans
3276
        #Tp cnt = 0;
3277 169 mohor
        // scan request
3278
        #Tp mii_scan_req(phy_addr, reg_addr);
3279 181 mohor
        #Tp check_mii_scan_valid; // wait for scan to make first data valid
3280
 
3281
        // check second scan
3282 169 mohor
        fork
3283 181 mohor
        begin
3284
          repeat(4) @(posedge Mdc_O);
3285
          // read data from PHY status register
3286 274 tadejm
          wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3287 181 mohor
          if (phy_data !== tmp_data)
3288 169 mohor
          begin
3289 181 mohor
            test_fail("Second data was not correctly scaned from status register");
3290
            fail = fail + 1;
3291 169 mohor
          end
3292 181 mohor
          // read data from MII status register
3293 274 tadejm
          wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3294 181 mohor
          if (phy_data[0] !== 1'b0)
3295
          begin
3296
            test_fail("Link FAIL bit was set in the MII status register");
3297
            fail = fail + 1;
3298
          end
3299
        end
3300
        begin
3301
        // Completely check scan
3302
          #Tp cnt = 0;
3303
          // wait for serial bus to become active - second scan
3304
          wait(Mdio_IO !== 1'bz);
3305
          // count transfer length
3306
          while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3307
          begin
3308
            @(posedge Mdc_O);
3309
            #Tp cnt = cnt + 1;
3310
          end
3311
          // check transfer length
3312
          if (i2) // without preamble
3313
          begin
3314
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
3315 169 mohor
            begin
3316 181 mohor
              test_fail("Second scan request did not proceed correctly");
3317
              fail = fail + 1;
3318 169 mohor
            end
3319 181 mohor
          end
3320
          else // with preamble
3321
          begin
3322
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
3323
            begin
3324
              test_fail("Second scan request did not proceed correctly");
3325
              fail = fail + 1;
3326
            end
3327
          end
3328
        end
3329
        join
3330
        // reset counter 
3331
        #Tp cnt = 0;
3332
        // SLIDING LINK DOWN and CHECK
3333
        fork
3334
          begin
3335
          // set link down
3336
            repeat(i) @(posedge Mdc_O);
3337
            // set link down
3338
            #Tp eth_phy.link_up_down(0);
3339
          end
3340
          begin
3341
          // check data in MII registers after each scan in this fork statement
3342 169 mohor
            if (i2) // without preamble
3343 181 mohor
              wait (cnt == 32);
3344
            else // with preamble
3345
              wait (cnt == 64);
3346
            repeat(3) @(posedge Mdc_O);
3347
            // read data from PHY status register
3348 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3349 181 mohor
            if ( ((i < 49) && !i2) || ((i < 17) && i2) )
3350 169 mohor
            begin
3351 181 mohor
              if (phy_data !== (tmp_data & 16'hFFFB)) // bit 3 is ZERO
3352 169 mohor
              begin
3353 181 mohor
                test_fail("Third data was not correctly scaned from status register");
3354 169 mohor
                fail = fail + 1;
3355
              end
3356
            end
3357 181 mohor
            else
3358 169 mohor
            begin
3359 181 mohor
              if (phy_data !== tmp_data)
3360 169 mohor
              begin
3361 181 mohor
                test_fail("Third data was not correctly scaned from status register");
3362 169 mohor
                fail = fail + 1;
3363
              end
3364
            end
3365 181 mohor
            // read data from MII status register
3366 274 tadejm
            wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3367 181 mohor
            if ( ((i < 49) && !i2) || ((i < 17) && i2) )
3368 169 mohor
            begin
3369 181 mohor
              if (phy_data[0] === 1'b0)
3370
              begin
3371
                test_fail("Link FAIL bit was not set in the MII status register");
3372
                fail = fail + 1;
3373
              end
3374 169 mohor
            end
3375 181 mohor
            else
3376 169 mohor
            begin
3377 181 mohor
              if (phy_data[0] !== 1'b0)
3378 169 mohor
              begin
3379 181 mohor
                test_fail("Link FAIL bit was set in the MII status register");
3380 169 mohor
                fail = fail + 1;
3381
              end
3382
            end
3383 181 mohor
          end
3384
          begin
3385
          // check length
3386
            for (i3 = 0; i3 <= 1; i3 = i3 + 1) // two scans
3387 169 mohor
            begin
3388 181 mohor
              #Tp cnt = 0;
3389
              // wait for serial bus to become active if there is more than one scan
3390
              wait(Mdio_IO !== 1'bz);
3391
              // count transfer length
3392
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3393 169 mohor
              begin
3394 181 mohor
                @(posedge Mdc_O);
3395
                #Tp cnt = cnt + 1;
3396 169 mohor
              end
3397 181 mohor
              // check transfer length
3398
              if (i2) // without preamble
3399
              begin
3400
                if (cnt != 33) // at this value Mdio_IO is HIGH Z
3401
                begin
3402
                  test_fail("3. or 4. scan request did not proceed correctly, while SCAN STOP was written");
3403
                  fail = fail + 1;
3404
                end
3405
              end
3406
              else // with preamble
3407
              begin
3408
                if (cnt != 65) // at this value Mdio_IO is HIGH Z
3409
                begin
3410
                  test_fail("3. or 4. scan request did not proceed correctly, while SCAN STOP was written");
3411
                  fail = fail + 1;
3412
                end
3413
              end
3414 169 mohor
            end
3415
          end
3416
        join
3417 181 mohor
        // reset counter
3418
        #Tp cnt = 0;
3419
        // check fifth scan and data from fourth scan
3420
        fork
3421 169 mohor
        begin
3422 181 mohor
          repeat(2) @(posedge Mdc_O);
3423
          // read data from PHY status register
3424 274 tadejm
          wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3425 181 mohor
          if (phy_data !== (tmp_data & 16'hFFFB)) // bit 3 is ZERO
3426 169 mohor
          begin
3427 181 mohor
            test_fail("4. data was not correctly scaned from status register");
3428
            fail = fail + 1;
3429 169 mohor
          end
3430 181 mohor
          // read data from MII status register
3431 274 tadejm
          wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3432 181 mohor
          if (phy_data[0] === 1'b0)
3433 169 mohor
          begin
3434 181 mohor
            test_fail("Link FAIL bit was not set in the MII status register");
3435 169 mohor
            fail = fail + 1;
3436
          end
3437
        end
3438
        begin
3439 181 mohor
        // Completely check intermediate scan
3440
          #Tp cnt = 0;
3441
          // wait for serial bus to become active - second scan
3442 169 mohor
          wait(Mdio_IO !== 1'bz);
3443
          // count transfer length
3444
          while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3445
          begin
3446
            @(posedge Mdc_O);
3447
            #Tp cnt = cnt + 1;
3448
          end
3449 181 mohor
          // check transfer length
3450
          if (i2) // without preamble
3451 169 mohor
          begin
3452 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
3453
            begin
3454
              test_fail("Fifth scan request did not proceed correctly");
3455
              fail = fail + 1;
3456
            end
3457 169 mohor
          end
3458 181 mohor
          else // with preamble
3459
          begin
3460
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
3461
            begin
3462
              test_fail("Fifth scan request did not proceed correctly");
3463
              fail = fail + 1;
3464
            end
3465
          end
3466 169 mohor
        end
3467 181 mohor
        join
3468
        // reset counter 
3469
        #Tp cnt = 0;
3470
        // SLIDING LINK UP and CHECK
3471
        fork
3472 169 mohor
          begin
3473 181 mohor
          // set link up
3474
            repeat(i) @(posedge Mdc_O);
3475
            // set link up
3476
            #Tp eth_phy.link_up_down(1);
3477 169 mohor
          end
3478 181 mohor
          begin
3479
          // check data in MII registers after each scan in this fork statement
3480
            repeat(2) @(posedge Mdc_O);
3481
            if (i2) // without preamble
3482
              wait (cnt == 32);
3483
            else // with preamble
3484
              wait (cnt == 64);
3485
            repeat(3) @(posedge Mdc_O);
3486
            // read data from PHY status register
3487 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3488 181 mohor
            if ( ((i < 49) && !i2) || ((i < 17) && i2) )
3489
            begin
3490
              if (phy_data !== tmp_data)
3491
              begin
3492
                test_fail("6. data was not correctly scaned from status register");
3493
                fail = fail + 1;
3494
              end
3495
            end
3496
            else
3497
            begin
3498
              if (phy_data !== (tmp_data & 16'hFFFB)) // bit 3 is ZERO
3499
              begin
3500
                test_fail("6. data was not correctly scaned from status register");
3501
                fail = fail + 1;
3502
              end
3503
            end
3504
            // read data from MII status register
3505 274 tadejm
            wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3506 181 mohor
            if ( ((i < 49) && !i2) || ((i < 17) && i2) )
3507
            begin
3508
              if (phy_data[0] !== 1'b0)
3509
              begin
3510
                test_fail("Link FAIL bit was set in the MII status register");
3511
                fail = fail + 1;
3512
              end
3513
            end
3514
            else
3515
            begin
3516
              if (phy_data[0] === 1'b0)
3517
              begin
3518
                test_fail("Link FAIL bit was not set in the MII status register");
3519
                fail = fail + 1;
3520
              end
3521
            end
3522
          end
3523
          begin
3524
          // check length
3525
            for (i3 = 0; i3 <= 1; i3 = i3 + 1) // two scans
3526
            begin
3527
              #Tp cnt = 0;
3528
              // wait for serial bus to become active if there is more than one scan
3529
              wait(Mdio_IO !== 1'bz);
3530
              // count transfer length
3531
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3532
              begin
3533
                @(posedge Mdc_O);
3534
                #Tp cnt = cnt + 1;
3535
              end
3536
              // check transfer length
3537
              if (i2) // without preamble
3538
              begin
3539
                if (cnt != 33) // at this value Mdio_IO is HIGH Z
3540
                begin
3541
                  test_fail("Scan request did not proceed correctly, while SCAN STOP was written");
3542
                  fail = fail + 1;
3543
                end
3544
              end
3545
              else // with preamble
3546
              begin
3547
                if (cnt != 65) // at this value Mdio_IO is HIGH Z
3548
                begin
3549
                  test_fail("Scan request did not proceed correctly, while SCAN STOP was written");
3550
                  fail = fail + 1;
3551
                end
3552
              end
3553
            end
3554
          end
3555
        join
3556
        // check last scan 
3557
        repeat(4) @(posedge Mdc_O);
3558
        // read data from PHY status register
3559 274 tadejm
        wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3560 181 mohor
        if (phy_data !== tmp_data)
3561
        begin
3562
          test_fail("7. data was not correctly scaned from status register");
3563
          fail = fail + 1;
3564 169 mohor
        end
3565 181 mohor
        // read data from MII status register
3566 274 tadejm
        wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3567 181 mohor
        if (phy_data[0] !== 1'b0)
3568
        begin
3569
          test_fail("Link FAIL bit was set in the MII status register");
3570
          fail = fail + 1;
3571
        end
3572
 
3573
        #Tp mii_scan_finish; // finish scan operation
3574
        #Tp check_mii_busy; // wait for scan to finish
3575
        #Tp;
3576
        // set delay of writing the command
3577
        if (i2) // without preamble
3578
        begin
3579
          case(i)
3580
            0,  1,  2,  3,  4:  i = i + 1;
3581
            13, 14, 15, 16, 17,
3582
            18, 19, 20, 21, 22,
3583
            23, 24, 25, 26, 27,
3584
            28, 29, 30, 31, 32,
3585
            33, 34, 35:         i = i + 1;
3586
            36:                 i = 80;
3587
            default:            i = 13;
3588
          endcase
3589
        end
3590 169 mohor
        else // with preamble
3591
        begin
3592 181 mohor
          case(i)
3593
            0,  1,  2,  3,  4:  i = i + 1;
3594
            45, 46, 47, 48, 49,
3595
            50, 51, 52, 53, 54,
3596
            55, 56, 57, 58, 59,
3597
            60, 61, 62, 63, 64,
3598
            65, 66, 67:         i = i + 1;
3599
            68:                 i = 80;
3600
            default:            i = 45;
3601
          endcase
3602 169 mohor
        end
3603 181 mohor
        @(posedge wb_clk);
3604
        #Tp;
3605 169 mohor
      end
3606
    end
3607 181 mohor
    // set PHY to normal mode
3608
    #Tp eth_phy.preamble_suppresed(0);
3609
    // MII mode register
3610
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3611
    if(fail == 0)
3612
      test_ok;
3613
    else
3614
      fail = 0;
3615 169 mohor
  end
3616
 
3617
 
3618 181 mohor
  ////////////////////////////////////////////////////////////////////
3619
  ////                                                            ////
3620
  ////  Test sliding stop scan command immediately after scan     ////
3621
  ////  request (with and without preamble)                       ////
3622
  ////                                                            ////
3623
  ////////////////////////////////////////////////////////////////////
3624
  if (test_num == 16) // 
3625 116 mohor
  begin
3626 194 tadej
    // TEST 16: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )
3627
    test_name = "TEST 16: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )";
3628 181 mohor
    `TIME;
3629 194 tadej
    $display("  TEST 16: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )");
3630 181 mohor
 
3631
    for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
3632 169 mohor
    begin
3633 181 mohor
      #Tp eth_phy.preamble_suppresed(i2);
3634
      // MII mode register
3635
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
3636
                wbm_subseq_waits);
3637
      i = 0;
3638
      cnt = 0;
3639
      while (i < 80) // delay for sliding of writing a STOP SCAN command
3640 169 mohor
      begin
3641 181 mohor
        for (i3 = 0; i3 <= 1; i3 = i3 + 1) // choose read or write after scan will be finished
3642 169 mohor
        begin
3643 181 mohor
          // set address
3644
          reg_addr = 5'h0; // control register
3645
          phy_addr = 5'h1; // correct PHY address
3646
          cnt = 0;
3647
          // scan request
3648
          #Tp mii_scan_req(phy_addr, reg_addr);
3649
          fork
3650
            begin
3651
              repeat(i) @(posedge Mdc_O);
3652
              // write command 0x0 into MII command register
3653
              // MII command written while scan in progress
3654
              wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3655
              @(posedge wb_clk);
3656
              #Tp check_mii_busy; // wait for scan to finish
3657
              @(posedge wb_clk);
3658
              disable check;
3659
            end
3660
            begin: check
3661
              // wait for serial bus to become active
3662
              wait(Mdio_IO !== 1'bz);
3663
              // count transfer length
3664
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3665
              begin
3666
                @(posedge Mdc_O);
3667
                #Tp cnt = cnt + 1;
3668
              end
3669
              // check transfer length
3670
              if (i2) // without preamble
3671
              begin
3672
                if (cnt != 33) // at this value Mdio_IO is HIGH Z
3673
                begin
3674
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3675
                  fail = fail + 1;
3676
                end
3677
              end
3678
              else // with preamble
3679
              begin
3680
                if (cnt != 65) // at this value Mdio_IO is HIGH Z
3681
                begin
3682
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3683
                  fail = fail + 1;
3684
                end
3685
              end
3686
              cnt = 0;
3687
              // wait for serial bus to become active if there is more than one scan
3688
              wait(Mdio_IO !== 1'bz);
3689
              // count transfer length
3690
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3691
              begin
3692
                @(posedge Mdc_O);
3693
                #Tp cnt = cnt + 1;
3694
              end
3695
              // check transfer length
3696
              if (i2) // without preamble
3697
              begin
3698
                if (cnt != 33) // at this value Mdio_IO is HIGH Z
3699
                begin
3700
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3701
                  fail = fail + 1;
3702
                end
3703
              end
3704
              else // with preamble
3705
              begin
3706
                if (cnt != 65) // at this value Mdio_IO is HIGH Z
3707
                begin
3708
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3709
                  fail = fail + 1;
3710
                end
3711
              end
3712
            end
3713
          join
3714
          // check the BUSY signal to see if the bus is still IDLE
3715
          for (i1 = 0; i1 < 8; i1 = i1 + 1)
3716
            check_mii_busy; // wait for bus to become idle
3717
 
3718
          // try normal write or read after scan was finished
3719
          phy_data = {8'h7D, (i[7:0] + 1)};
3720
          cnt = 0;
3721
          if (i3 == 0) // write after scan
3722 169 mohor
          begin
3723 181 mohor
            // write request
3724
            #Tp mii_write_req(phy_addr, reg_addr, phy_data);
3725
            // wait for serial bus to become active
3726
            wait(Mdio_IO !== 1'bz);
3727
            // count transfer length
3728
            while(Mdio_IO !== 1'bz)
3729
            begin
3730
              @(posedge Mdc_O);
3731
              #Tp cnt = cnt + 1;
3732
            end
3733 169 mohor
            @(posedge Mdc_O);
3734 181 mohor
            // read request
3735
            #Tp mii_read_req(phy_addr, reg_addr);
3736
            check_mii_busy; // wait for read to finish
3737
            // read and check data
3738 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3739 181 mohor
            if (phy_data !== tmp_data)
3740 169 mohor
            begin
3741 181 mohor
              test_fail("Data was not correctly written into OR read from PHY register - control register");
3742 169 mohor
              fail = fail + 1;
3743
            end
3744
          end
3745 181 mohor
          else // read after scan
3746 169 mohor
          begin
3747 181 mohor
            // read request
3748
            #Tp mii_read_req(phy_addr, reg_addr);
3749
            // wait for serial bus to become active
3750
            wait(Mdio_IO !== 1'bz);
3751
            // count transfer length
3752
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3753 169 mohor
            begin
3754 181 mohor
              @(posedge Mdc_O);
3755
              #Tp cnt = cnt + 1;
3756
            end
3757
            @(posedge Mdc_O);
3758
            check_mii_busy; // wait for read to finish
3759
            // read and check data
3760 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3761 181 mohor
            if (phy_data !== tmp_data)
3762
            begin
3763
              test_fail("Data was not correctly written into OR read from PHY register - control register");
3764 169 mohor
              fail = fail + 1;
3765
            end
3766
          end
3767 181 mohor
          // check if transfer was a proper length
3768 169 mohor
          if (i2) // without preamble
3769
          begin
3770
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
3771
            begin
3772 181 mohor
              test_fail("New request did not proceed correctly, after scan request");
3773 169 mohor
              fail = fail + 1;
3774
            end
3775
          end
3776
          else // with preamble
3777
          begin
3778
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
3779
            begin
3780 181 mohor
              test_fail("New request did not proceed correctly, after scan request");
3781 169 mohor
              fail = fail + 1;
3782
            end
3783
          end
3784
        end
3785 181 mohor
        #Tp;
3786
        // set delay of writing the command
3787
        if (i2) // without preamble
3788
        begin
3789
          case(i)
3790
            0, 1:               i = i + 1;
3791
            18, 19, 20, 21, 22,
3792
            23, 24, 25, 26, 27,
3793
            28, 29, 30, 31, 32,
3794
            33, 34, 35:         i = i + 1;
3795
            36:                 i = 80;
3796
            default:            i = 18;
3797
          endcase
3798
        end
3799
        else // with preamble
3800
        begin
3801
          case(i)
3802
            0, 1:               i = i + 1;
3803
            50, 51, 52, 53, 54,
3804
            55, 56, 57, 58, 59,
3805
            60, 61, 62, 63, 64,
3806
            65, 66, 67:         i = i + 1;
3807
            68:                 i = 80;
3808
            default:            i = 50;
3809
          endcase
3810
        end
3811
        @(posedge wb_clk);
3812
      end
3813
    end
3814
    // set PHY to normal mode
3815
    #Tp eth_phy.preamble_suppresed(0);
3816
    // MII mode register
3817
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3818
    if(fail == 0)
3819
      test_ok;
3820
    else
3821
      fail = 0;
3822
  end
3823 169 mohor
 
3824 181 mohor
 
3825
  ////////////////////////////////////////////////////////////////////
3826
  ////                                                            ////
3827
  ////  Test sliding stop scan command after 2. scan (with and    ////
3828
  ////  without preamble)                                         ////
3829
  ////                                                            ////
3830
  ////////////////////////////////////////////////////////////////////
3831
  if (test_num == 17) // 
3832
  begin
3833 194 tadej
    // TEST 17: SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )
3834
    test_name = "TEST 17: SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )";
3835
    `TIME; $display("  TEST 17: SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )");
3836 181 mohor
 
3837
    for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
3838
    begin
3839
      #Tp eth_phy.preamble_suppresed(i2);
3840
      // MII mode register
3841
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
3842
                wbm_subseq_waits);
3843
 
3844
      i = 0;
3845
      cnt = 0;
3846
      while (i < 80) // delay for sliding of writing a STOP SCAN command
3847
      begin
3848
        for (i3 = 0; i3 <= 1; i3 = i3 + 1) // choose read or write after scan will be finished
3849
        begin
3850
          // first there are two scans
3851
          // set address
3852
          reg_addr = 5'h0; // control register
3853
          phy_addr = 5'h1; // correct PHY address
3854
          cnt = 0;
3855
          // scan request
3856
          #Tp mii_scan_req(phy_addr, reg_addr);
3857
          // wait and check first 2 scans
3858 169 mohor
          begin
3859
            // wait for serial bus to become active
3860
            wait(Mdio_IO !== 1'bz);
3861
            // count transfer length
3862
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3863
            begin
3864
              @(posedge Mdc_O);
3865
              #Tp cnt = cnt + 1;
3866
            end
3867
            // check transfer length
3868
            if (i2) // without preamble
3869
            begin
3870
              if (cnt != 33) // at this value Mdio_IO is HIGH Z
3871
              begin
3872
                test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3873
                fail = fail + 1;
3874
              end
3875
            end
3876
            else // with preamble
3877
            begin
3878
              if (cnt != 65) // at this value Mdio_IO is HIGH Z
3879
              begin
3880
                test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3881
                fail = fail + 1;
3882
              end
3883
            end
3884
            cnt = 0;
3885
            // wait for serial bus to become active if there is more than one scan
3886
            wait(Mdio_IO !== 1'bz);
3887
            // count transfer length
3888
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3889
            begin
3890
              @(posedge Mdc_O);
3891
              #Tp cnt = cnt + 1;
3892
            end
3893
            // check transfer length
3894
            if (i2) // without preamble
3895
            begin
3896
              if (cnt != 33) // at this value Mdio_IO is HIGH Z
3897
              begin
3898
                test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3899
                fail = fail + 1;
3900
              end
3901
            end
3902
            else // with preamble
3903
            begin
3904
              if (cnt != 65) // at this value Mdio_IO is HIGH Z
3905
              begin
3906
                test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3907
                fail = fail + 1;
3908
              end
3909
            end
3910
          end
3911
 
3912 181 mohor
          // reset counter 
3913
          cnt = 0;
3914
          fork
3915
            begin
3916
              repeat(i) @(posedge Mdc_O);
3917
              // write command 0x0 into MII command register
3918
              // MII command written while scan in progress
3919
              wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3920
              @(posedge wb_clk);
3921
              #Tp check_mii_busy; // wait for scan to finish
3922
              @(posedge wb_clk);
3923
              disable check_3;
3924
            end
3925
            begin: check_3
3926
              // wait for serial bus to become active
3927
              wait(Mdio_IO !== 1'bz);
3928
              // count transfer length
3929
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3930
              begin
3931
                @(posedge Mdc_O);
3932
                #Tp cnt = cnt + 1;
3933
              end
3934
              // check transfer length
3935
              if (i2) // without preamble
3936
              begin
3937
                if (cnt != 33) // at this value Mdio_IO is HIGH Z
3938
                begin
3939
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3940
                  fail = fail + 1;
3941
                end
3942
              end
3943
              else // with preamble
3944
              begin
3945
                if (cnt != 65) // at this value Mdio_IO is HIGH Z
3946
                begin
3947
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3948
                  fail = fail + 1;
3949
                end
3950
              end
3951
              cnt = 0;
3952
              // wait for serial bus to become active if there is more than one scan
3953
              wait(Mdio_IO !== 1'bz);
3954
              // count transfer length
3955
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3956
              begin
3957
                @(posedge Mdc_O);
3958
                #Tp cnt = cnt + 1;
3959
              end
3960
              // check transfer length
3961
              if (i2) // without preamble
3962
              begin
3963
                if (cnt != 33) // at this value Mdio_IO is HIGH Z
3964
                begin
3965
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3966
                  fail = fail + 1;
3967
                end
3968
              end
3969
              else // with preamble
3970
              begin
3971
                if (cnt != 65) // at this value Mdio_IO is HIGH Z
3972
                begin
3973
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3974
                  fail = fail + 1;
3975
                end
3976
              end
3977
            end
3978
          join
3979
          // check the BUSY signal to see if the bus is still IDLE
3980
          for (i1 = 0; i1 < 8; i1 = i1 + 1)
3981
            check_mii_busy; // wait for bus to become idle
3982
 
3983
          // try normal write or read after scan was finished
3984
          phy_data = {8'h7D, (i[7:0] + 1)};
3985
          cnt = 0;
3986
          if (i3 == 0) // write after scan
3987 169 mohor
          begin
3988 181 mohor
            // write request
3989
            #Tp mii_write_req(phy_addr, reg_addr, phy_data);
3990
            // wait for serial bus to become active
3991
            wait(Mdio_IO !== 1'bz);
3992
            // count transfer length
3993
            while(Mdio_IO !== 1'bz)
3994
            begin
3995
              @(posedge Mdc_O);
3996
              #Tp cnt = cnt + 1;
3997
            end
3998 169 mohor
            @(posedge Mdc_O);
3999 181 mohor
            // read request
4000
            #Tp mii_read_req(phy_addr, reg_addr);
4001
            check_mii_busy; // wait for read to finish
4002
            // read and check data
4003 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4004 181 mohor
            if (phy_data !== tmp_data)
4005
            begin
4006
              test_fail("Data was not correctly written into OR read from PHY register - control register");
4007
              fail = fail + 1;
4008
            end
4009 169 mohor
          end
4010 181 mohor
          else // read after scan
4011 169 mohor
          begin
4012 181 mohor
            // read request
4013
            #Tp mii_read_req(phy_addr, reg_addr);
4014
            // wait for serial bus to become active
4015
            wait(Mdio_IO !== 1'bz);
4016
            // count transfer length
4017
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
4018
            begin
4019
              @(posedge Mdc_O);
4020
              #Tp cnt = cnt + 1;
4021
            end
4022
            @(posedge Mdc_O);
4023
            check_mii_busy; // wait for read to finish
4024
            // read and check data
4025 274 tadejm
            wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4026 181 mohor
            if (phy_data !== tmp_data)
4027
            begin
4028
              test_fail("Data was not correctly written into OR read from PHY register - control register");
4029
              fail = fail + 1;
4030
            end
4031 169 mohor
          end
4032 181 mohor
          // check if transfer was a proper length
4033
          if (i2) // without preamble
4034 169 mohor
          begin
4035 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
4036
            begin
4037
              test_fail("New request did not proceed correctly, after scan request");
4038
              fail = fail + 1;
4039
            end
4040 169 mohor
          end
4041 181 mohor
          else // with preamble
4042 169 mohor
          begin
4043 181 mohor
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
4044
            begin
4045
              test_fail("New request did not proceed correctly, after scan request");
4046
              fail = fail + 1;
4047
            end
4048 169 mohor
          end
4049
        end
4050 181 mohor
        #Tp;
4051
        // set delay of writing the command
4052 169 mohor
        if (i2) // without preamble
4053
        begin
4054 181 mohor
          case(i)
4055
            0, 1:               i = i + 1;
4056
            18, 19, 20, 21, 22,
4057
            23, 24, 25, 26, 27,
4058
            28, 29, 30, 31, 32,
4059
            33, 34, 35:         i = i + 1;
4060
            36:                 i = 80;
4061
            default:            i = 18;
4062
          endcase
4063 169 mohor
        end
4064
        else // with preamble
4065
        begin
4066 181 mohor
          case(i)
4067
            0, 1:               i = i + 1;
4068
            50, 51, 52, 53, 54,
4069
            55, 56, 57, 58, 59,
4070
            60, 61, 62, 63, 64,
4071
            65, 66, 67:         i = i + 1;
4072
            68:                 i = 80;
4073
            default:            i = 50;
4074
          endcase
4075 169 mohor
        end
4076 181 mohor
        @(posedge wb_clk);
4077 116 mohor
      end
4078
    end
4079 181 mohor
    // set PHY to normal mode
4080
    #Tp eth_phy.preamble_suppresed(0);
4081
    // MII mode register
4082
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4083
    if(fail == 0)
4084
      test_ok;
4085
    else
4086
      fail = 0;
4087 169 mohor
  end
4088 116 mohor
 
4089 181 mohor
end   //  for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
4090
 
4091 169 mohor
end
4092
endtask // test_mii
4093
 
4094
 
4095
task test_mac_full_duplex_transmit;
4096
  input  [31:0]  start_task;
4097
  input  [31:0]  end_task;
4098
  integer        bit_start_1;
4099
  integer        bit_end_1;
4100
  integer        bit_start_2;
4101
  integer        bit_end_2;
4102
  integer        num_of_reg;
4103 209 tadejm
  integer        num_of_frames;
4104
  integer        num_of_bd;
4105 169 mohor
  integer        i_addr;
4106
  integer        i_data;
4107
  integer        i_length;
4108 209 tadejm
  integer        tmp_len;
4109
  integer        tmp_bd;
4110
  integer        tmp_bd_num;
4111 169 mohor
  integer        tmp_data;
4112 209 tadejm
  integer        tmp_ipgt;
4113 194 tadej
  integer        test_num;
4114 169 mohor
  reg    [31:0]  tx_bd_num;
4115
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
4116
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
4117
  integer        i;
4118
  integer        i1;
4119
  integer        i2;
4120
  integer        i3;
4121
  integer        fail;
4122
  integer        speed;
4123 279 mohor
  reg            no_underrun;
4124 209 tadejm
  reg            frame_started;
4125
  reg            frame_ended;
4126
  reg            wait_for_frame;
4127 169 mohor
  reg    [31:0]  addr;
4128
  reg    [31:0]  data;
4129
  reg    [31:0]  tmp;
4130
  reg    [ 7:0]  st_data;
4131
  reg    [15:0]  max_tmp;
4132
  reg    [15:0]  min_tmp;
4133 279 mohor
 
4134 169 mohor
begin
4135
// MAC FULL DUPLEX TRANSMIT TEST
4136
test_heading("MAC FULL DUPLEX TRANSMIT TEST");
4137
$display(" ");
4138
$display("MAC FULL DUPLEX TRANSMIT TEST");
4139
fail = 0;
4140
 
4141
// reset MAC registers
4142
hard_reset;
4143
// reset MAC and MII LOGIC with soft reset
4144 274 tadejm
//reset_mac;
4145
//reset_mii;
4146 169 mohor
// set wb slave response
4147
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
4148
 
4149
  /*
4150
  TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
4151
  -------------------------------------------------------------------------------------
4152
  set_tx_bd
4153
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0], len[15:0], irq, pad, crc, txpnt[31:0]);
4154
  set_tx_bd_wrap
4155
    (tx_bd_num_end[6:0]);
4156
  set_tx_bd_ready
4157
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
4158
  check_tx_bd
4159
    (tx_bd_num_start[6:0], tx_bd_status[31:0]);
4160
  clear_tx_bd
4161
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
4162
 
4163
  TASKS for set and control RX buffer descriptors:
4164
  ------------------------------------------------
4165
  set_rx_bd
4166
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0], irq, rxpnt[31:0]);
4167
  set_rx_bd_wrap
4168
    (rx_bd_num_end[6:0]);
4169
  set_rx_bd_empty
4170
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
4171
  check_rx_bd
4172
    (rx_bd_num_end[6:0], rx_bd_status);
4173
  clear_rx_bd
4174
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
4175
 
4176
  TASKS for set and check TX packets:
4177
  -----------------------------------
4178
  set_tx_packet
4179
    (txpnt[31:0], len[15:0], eth_start_data[7:0]);
4180
  check_tx_packet
4181
    (txpnt_wb[31:0], txpnt_phy[31:0], len[15:0], failure[31:0]);
4182
 
4183
  TASKS for set and check RX packets:
4184
  -----------------------------------
4185
  set_rx_packet
4186
    (rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
4187
  check_rx_packet
4188
    (rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
4189
 
4190
  TASKS for append and check CRC to/of TX packet:
4191
  -----------------------------------------------
4192
  append_tx_crc
4193
    (txpnt_wb[31:0], len[15:0], negated_crc);
4194
  check_tx_crc
4195
    (txpnt_phy[31:0], len[15:0], negated_crc, failure[31:0]);
4196
 
4197
  TASK for append CRC to RX packet (CRC is checked together with check_rx_packet):
4198
  --------------------------------------------------------------------------------
4199
  append_rx_crc
4200
    (rxpnt_phy[31:0], len[15:0], plus_nibble, negated_crc);
4201
  */
4202
 
4203 194 tadej
//////////////////////////////////////////////////////////////////////
4204
////                                                              ////
4205
////  test_mac_full_duplex_transmit:                              ////
4206
////                                                              ////
4207
////  0: Test no transmit when all buffers are RX ( 10Mbps ).     ////
4208
////  1: Test no transmit when all buffers are RX ( 100Mbps ).    ////
4209
////  2: Test transmit packets form MINFL to MAXFL sizes at       ////
4210
////     one TX buffer decriptor ( 10Mbps ).                      ////
4211
////  3: Test transmit packets form MINFL to MAXFL sizes at       ////
4212
////     one TX buffer decriptor ( 100Mbps ).                     ////
4213
////                                                              ////
4214
//////////////////////////////////////////////////////////////////////
4215
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
4216 169 mohor
begin
4217
 
4218 194 tadej
  ////////////////////////////////////////////////////////////////////
4219
  ////                                                            ////
4220
  ////  Test no transmit when all buffers are RX ( 10Mbps ).      ////
4221
  ////                                                            ////
4222
  ////////////////////////////////////////////////////////////////////
4223
  if (test_num == 0) // Test no transmit when all buffers are RX ( 10Mbps ).
4224 169 mohor
  begin
4225 194 tadej
    // TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )
4226
    test_name   = "TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )";
4227
    `TIME; $display("  TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )");
4228
 
4229
    // unmask interrupts
4230 209 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
4231 194 tadej
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4232
    // set all buffer descriptors to RX - must be set before TX enable
4233 274 tadejm
    wait (wbm_working == 0);
4234 194 tadej
    wbm_write(`ETH_TX_BD_NUM, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4235
    // enable TX, set full-duplex mode, padding and CRC appending
4236 274 tadejm
    wait (wbm_working == 0);
4237 194 tadej
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4238
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4239
 
4240
    // write to phy's control register for 10Mbps
4241
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
4242
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
4243
    speed = 10;
4244
 
4245
    i = 0;
4246
    while (i < 128)
4247 169 mohor
    begin
4248 194 tadej
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
4249 169 mohor
      begin
4250 194 tadej
        set_tx_packet((`MEMORY_BASE + (i1 * 200)), 100, 0);
4251
        set_tx_bd(i1, i1, 100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + (i1 * 200)));
4252 169 mohor
      end
4253 194 tadej
      set_tx_bd_wrap(i);
4254
      fork
4255
        begin
4256
          set_tx_bd_ready(0, i);
4257
          repeat(20) @(negedge mtx_clk);
4258
          #1 disable check_tx_en10;
4259
        end
4260
        begin: check_tx_en10
4261
          wait (MTxEn === 1'b1);
4262
          test_fail("Tramsmit should not start at all");
4263
          fail = fail + 1;
4264
          `TIME; $display("*E Transmit of %d packets should not start at all - active MTxEn", i);
4265
        end
4266
      join
4267
      for (i2 = 0; i2 < 20; i2 = i2 + 1)
4268 169 mohor
      begin
4269 194 tadej
        check_tx_bd(0, tmp);
4270
        #1;
4271
        if (tmp[15] === 1'b0)
4272
        begin
4273
          test_fail("Tramsmit should not start at all");
4274
          fail = fail + 1;
4275
          `TIME; $display("*E Transmit of %d packets should not start at all - ready is 0", i);
4276
        end
4277
        if (tmp[8:0] !== 0)
4278
        begin
4279
          test_fail("Tramsmit should not be finished since it should not start at all");
4280
          fail = fail + 1;
4281
          `TIME; $display("*E Transmit of should not be finished since it should not start at all");
4282
        end
4283
        @(posedge wb_clk);
4284 169 mohor
      end
4285 274 tadejm
      wait (wbm_working == 0);
4286 194 tadej
      wbm_read(`ETH_INT, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4287
      if (tmp[6:0] !== 0)
4288 169 mohor
      begin
4289 194 tadej
        test_fail("Tramsmit should not get INT since it should not start at all");
4290 169 mohor
        fail = fail + 1;
4291 194 tadej
        `TIME; $display("*E Transmit of should not get INT since it should not start at all");
4292 169 mohor
      end
4293 194 tadej
      clear_tx_bd(0, i);
4294
      if ((i < 5) || (i > 124))
4295
        i = i + 1;
4296
      else
4297
        i = i + 120;
4298 116 mohor
    end
4299 194 tadej
    // disable TX
4300 274 tadejm
    wait (wbm_working == 0);
4301 194 tadej
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4302
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4303
    if(fail == 0)
4304
      test_ok;
4305 116 mohor
    else
4306 194 tadej
      fail = 0;
4307 169 mohor
  end
4308 116 mohor
 
4309
 
4310 194 tadej
  ////////////////////////////////////////////////////////////////////
4311
  ////                                                            ////
4312
  ////  Test no transmit when all buffers are RX ( 100Mbps ).     ////
4313
  ////                                                            ////
4314
  ////////////////////////////////////////////////////////////////////
4315
  if (test_num == 1) // Test no transmit when all buffers are RX ( 100Mbps ).
4316 169 mohor
  begin
4317 194 tadej
    // TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )
4318
    test_name   = "TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )";
4319
    `TIME; $display("  TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )");
4320
 
4321
    // unmask interrupts
4322 274 tadejm
    wait (wbm_working == 0);
4323 209 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
4324 194 tadej
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4325
    // set all buffer descriptors to RX - must be set before TX enable
4326 274 tadejm
    wait (wbm_working == 0);
4327 194 tadej
    wbm_write(`ETH_TX_BD_NUM, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4328
    // enable TX, set full-duplex mode, padding and CRC appending
4329 274 tadejm
    wait (wbm_working == 0);
4330 194 tadej
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4331
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4332
 
4333
    // write to phy's control register for 100Mbps
4334
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
4335
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
4336
    speed = 100;
4337
 
4338
    i = 0;
4339
    while (i < 128)
4340 169 mohor
    begin
4341 194 tadej
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
4342 169 mohor
      begin
4343 194 tadej
        set_tx_packet((`MEMORY_BASE + (i1 * 200)), 100, 0);
4344
        set_tx_bd(i1, i1, 100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + (i1 * 200)));
4345 169 mohor
      end
4346 194 tadej
      set_tx_bd_wrap(i);
4347
      fork
4348
        begin
4349
          set_tx_bd_ready(0, i);
4350
          repeat(20) @(negedge mtx_clk);
4351
          #1 disable check_tx_en100;
4352
        end
4353
        begin: check_tx_en100
4354
          wait (MTxEn === 1'b1);
4355
          test_fail("Tramsmit should not start at all");
4356
          fail = fail + 1;
4357
          `TIME; $display("*E Transmit of %d packets should not start at all - active MTxEn", i);
4358
        end
4359
      join
4360
      for (i2 = 0; i2 < 20; i2 = i2 + 1)
4361 169 mohor
      begin
4362 194 tadej
        check_tx_bd(0, tmp);
4363
        #1;
4364
        if (tmp[15] === 1'b0)
4365
        begin
4366
          test_fail("Tramsmit should not start at all");
4367
          fail = fail + 1;
4368
          `TIME; $display("*E Transmit of %d packets should not start at all - ready is 0", i);
4369
        end
4370
        if (tmp[8:0] !== 0)
4371
        begin
4372
          test_fail("Tramsmit should not be finished since it should not start at all");
4373
          fail = fail + 1;
4374
          `TIME; $display("*E Transmit of should not be finished since it should not start at all");
4375
        end
4376
        @(posedge wb_clk);
4377 169 mohor
      end
4378 274 tadejm
      wait (wbm_working == 0);
4379 194 tadej
      wbm_read(`ETH_INT, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4380
      if (tmp[6:0] !== 0)
4381 169 mohor
      begin
4382 194 tadej
        test_fail("Tramsmit should not get INT since it should not start at all");
4383 169 mohor
        fail = fail + 1;
4384 194 tadej
        `TIME; $display("*E Transmit of should not get INT since it should not start at all");
4385 169 mohor
      end
4386 194 tadej
      clear_tx_bd(0, i);
4387
      if ((i < 5) || (i > 124))
4388
        i = i + 1;
4389
      else
4390
        i = i + 120;
4391 169 mohor
    end
4392 194 tadej
    // disable TX
4393 274 tadejm
    wait (wbm_working == 0);
4394 194 tadej
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4395
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4396
    if(fail == 0)
4397
      test_ok;
4398 169 mohor
    else
4399 194 tadej
      fail = 0;
4400 169 mohor
  end
4401
 
4402
 
4403 194 tadej
  ////////////////////////////////////////////////////////////////////
4404
  ////                                                            ////
4405
  ////  Test transmit packets form MINFL to MAXFL sizes at        ////
4406
  ////  one TX buffer decriptor ( 10Mbps ).                       ////
4407
  ////                                                            ////
4408
  ////////////////////////////////////////////////////////////////////
4409 209 tadejm
  if (test_num == 2) // without and with padding
4410 169 mohor
  begin
4411 194 tadej
    // TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )
4412
    test_name = "TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )";
4413
    `TIME; $display("  TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )");
4414
 
4415
    max_tmp = 0;
4416
    min_tmp = 0;
4417
    // set one TX buffer descriptor - must be set before TX enable
4418 274 tadejm
    wait (wbm_working == 0);
4419 194 tadej
    wbm_write(`ETH_TX_BD_NUM, 32'h1, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4420 209 tadejm
    // enable TX, set full-duplex mode, NO padding and CRC appending
4421 274 tadejm
    wait (wbm_working == 0);
4422 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
4423 194 tadej
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4424
    // prepare two packets of MAXFL length
4425 274 tadejm
    wait (wbm_working == 0);
4426 194 tadej
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4427
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
4428
    min_tmp = tmp[31:16];
4429 209 tadejm
    st_data = 8'h01;
4430
    set_tx_packet(`MEMORY_BASE, (max_tmp), st_data); // length without CRC
4431 194 tadej
    st_data = 8'h10;
4432 209 tadejm
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp), st_data); // length without CRC
4433 194 tadej
    // check WB INT signal
4434
    if (wb_int !== 1'b0)
4435 169 mohor
    begin
4436 194 tadej
      test_fail("WB INT signal should not be set");
4437
      fail = fail + 1;
4438 169 mohor
    end
4439 194 tadej
 
4440
    // write to phy's control register for 10Mbps
4441
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
4442
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
4443
    speed = 10;
4444
 
4445
    i_length = (min_tmp - 4);
4446
    while (i_length <= (max_tmp - 4))
4447 169 mohor
    begin
4448 194 tadej
      // choose generating carrier sense and collision for first and last 64 lengths of frames
4449
      case (i_length[1:0])
4450
      2'h0: // Interrupt is generated
4451 169 mohor
      begin
4452 194 tadej
        // enable interrupt generation
4453 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
4454 194 tadej
        // unmask interrupts
4455 274 tadejm
        wait (wbm_working == 0);
4456 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
4457 194 tadej
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4458
        // not detect carrier sense in FD and no collision
4459
        eth_phy.carrier_sense_tx_fd_detect(0);
4460
        eth_phy.collision(0);
4461 169 mohor
      end
4462 194 tadej
      2'h1: // Interrupt is not generated
4463 169 mohor
      begin
4464 194 tadej
        // enable interrupt generation
4465 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
4466 194 tadej
        // mask interrupts
4467 274 tadejm
        wait (wbm_working == 0);
4468 194 tadej
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4469
        // detect carrier sense in FD and no collision
4470
        eth_phy.carrier_sense_tx_fd_detect(1);
4471
        eth_phy.collision(0);
4472 169 mohor
      end
4473 194 tadej
      2'h2: // Interrupt is not generated
4474
      begin
4475
        // disable interrupt generation
4476 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
4477 194 tadej
        // unmask interrupts
4478 274 tadejm
        wait (wbm_working == 0);
4479 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
4480 194 tadej
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4481
        // not detect carrier sense in FD and set collision
4482
        eth_phy.carrier_sense_tx_fd_detect(0);
4483
        eth_phy.collision(1);
4484
      end
4485
      default: // 2'h3: // Interrupt is not generated
4486
      begin
4487
        // disable interrupt generation
4488 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
4489 194 tadej
        // mask interrupts
4490 274 tadejm
        wait (wbm_working == 0);
4491 194 tadej
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4492
        // detect carrier sense in FD and set collision
4493
        eth_phy.carrier_sense_tx_fd_detect(1);
4494
        eth_phy.collision(1);
4495
      end
4496
      endcase
4497
      eth_phy.set_tx_mem_addr(max_tmp);
4498
      // set wrap bit
4499
      set_tx_bd_wrap(0);
4500
      set_tx_bd_ready(0, 0);
4501 169 mohor
      #1 check_tx_bd(0, data);
4502 274 tadejm
 
4503
 
4504 194 tadej
      if (i_length < min_tmp) // just first four
4505 169 mohor
      begin
4506 194 tadej
        while (data[15] === 1)
4507
        begin
4508
          #1 check_tx_bd(0, data);
4509
          @(posedge wb_clk);
4510
        end
4511 209 tadejm
        repeat (1) @(posedge wb_clk);
4512 169 mohor
      end
4513 194 tadej
      else if (i_length > (max_tmp - 8)) // just last four
4514 192 tadej
      begin
4515 194 tadej
        tmp = 0;
4516
        wait (MTxEn === 1'b1); // start transmit
4517
        while (tmp < (i_length - 20))
4518
        begin
4519
          #1 tmp = tmp + 1;
4520
          @(posedge wb_clk);
4521
        end
4522
        #1 check_tx_bd(0, data);
4523
        while (data[15] === 1)
4524
        begin
4525
          #1 check_tx_bd(0, data);
4526
          @(posedge wb_clk);
4527
        end
4528 209 tadejm
        repeat (1) @(posedge wb_clk);
4529 192 tadej
      end
4530
      else
4531
      begin
4532 194 tadej
        wait (MTxEn === 1'b1); // start transmit
4533
        #1 check_tx_bd(0, data);
4534
        if (data[15] !== 1)
4535
        begin
4536
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
4537
          fail = fail + 1;
4538
        end
4539
        wait (MTxEn === 1'b0); // end transmit
4540
        while (data[15] === 1)
4541
        begin
4542
          #1 check_tx_bd(0, data);
4543
          @(posedge wb_clk);
4544
        end
4545
        repeat (1) @(posedge wb_clk);
4546 192 tadej
      end
4547 274 tadejm
 
4548 279 mohor
      repeat(5) @(posedge mtx_clk);  // Wait some time so PHY stores the CRC
4549 274 tadejm
 
4550 194 tadej
      // check length of a PACKET
4551
      if (eth_phy.tx_len != (i_length + 4))
4552 192 tadej
      begin
4553 194 tadej
        test_fail("Wrong length of the packet out from MAC");
4554 192 tadej
        fail = fail + 1;
4555
      end
4556 194 tadej
      // checking in the following if statement is performed only for first and last 64 lengths
4557
      if ( ((i_length + 4) <= (min_tmp + 64)) || ((i_length + 4) > (max_tmp - 64)) )
4558 192 tadej
      begin
4559 194 tadej
        // check transmitted TX packet data
4560
        if (i_length[0] == 0)
4561
        begin
4562 209 tadejm
          check_tx_packet((`MEMORY_BASE + i_length[1:0]), max_tmp, i_length, tmp);
4563 194 tadej
        end
4564
        else
4565
        begin
4566 209 tadejm
          check_tx_packet(((`MEMORY_BASE + i_length[1:0]) + max_tmp), max_tmp, i_length, tmp);
4567 194 tadej
        end
4568
        if (tmp > 0)
4569
        begin
4570
          test_fail("Wrong data of the transmitted packet");
4571
          fail = fail + 1;
4572
        end
4573
        // check transmited TX packet CRC
4574
        check_tx_crc(max_tmp, i_length, 1'b0, tmp); // length without CRC
4575 274 tadejm
 
4576 194 tadej
        if (tmp > 0)
4577
        begin
4578
          test_fail("Wrong CRC of the transmitted packet");
4579
          fail = fail + 1;
4580
        end
4581 192 tadej
      end
4582 194 tadej
      // check WB INT signal
4583
      if (i_length[1:0] == 2'h0)
4584 192 tadej
      begin
4585 194 tadej
        if (wb_int !== 1'b1)
4586
        begin
4587
          `TIME; $display("*E WB INT signal should be set");
4588
          test_fail("WB INT signal should be set");
4589
          fail = fail + 1;
4590
        end
4591 192 tadej
      end
4592 194 tadej
      else
4593 192 tadej
      begin
4594 194 tadej
        if (wb_int !== 1'b0)
4595
        begin
4596
          `TIME; $display("*E WB INT signal should not be set");
4597
          test_fail("WB INT signal should not be set");
4598
          fail = fail + 1;
4599
        end
4600 192 tadej
      end
4601 194 tadej
      // check TX buffer descriptor of a packet
4602
      check_tx_bd(0, data);
4603
      if (i_length[1] == 1'b0) // interrupt enabled
4604 192 tadej
      begin
4605 194 tadej
        if (data[15:0] !== 16'h7800)
4606
        begin
4607
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
4608
          test_fail("TX buffer descriptor status is not correct");
4609
          fail = fail + 1;
4610
        end
4611 192 tadej
      end
4612 194 tadej
      else // interrupt not enabled
4613 192 tadej
      begin
4614 194 tadej
        if (data[15:0] !== 16'h3800)
4615
        begin
4616
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
4617
          test_fail("TX buffer descriptor status is not correct");
4618
          fail = fail + 1;
4619
        end
4620 192 tadej
      end
4621 194 tadej
      // clear TX buffer descriptor
4622
      clear_tx_bd(0, 0);
4623
      // check interrupts
4624 274 tadejm
      wait (wbm_working == 0);
4625 194 tadej
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4626
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
4627 192 tadej
      begin
4628 194 tadej
        if ((data & `ETH_INT_TXB) !== 1'b1)
4629
        begin
4630
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
4631
          test_fail("Interrupt Transmit Buffer was not set");
4632
          fail = fail + 1;
4633
        end
4634
        if ((data & (~`ETH_INT_TXB)) !== 0)
4635
        begin
4636
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
4637
          test_fail("Other interrupts (except Transmit Buffer) were set");
4638
          fail = fail + 1;
4639
        end
4640 192 tadej
      end
4641 194 tadej
      else
4642 192 tadej
      begin
4643 194 tadej
        if (data !== 0)
4644
        begin
4645
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
4646
          test_fail("Any of interrupts (except Transmit Buffer) was set");
4647
          fail = fail + 1;
4648
        end
4649 192 tadej
      end
4650 194 tadej
      // clear interrupts
4651 274 tadejm
      wait (wbm_working == 0);
4652 194 tadej
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4653
      // check WB INT signal
4654
      if (wb_int !== 1'b0)
4655 192 tadej
      begin
4656 194 tadej
        test_fail("WB INT signal should not be set");
4657 192 tadej
        fail = fail + 1;
4658
      end
4659 194 tadej
      // INTERMEDIATE DISPLAYS
4660
      if ((i_length + 4) == (min_tmp + 64))
4661 209 tadejm
      begin
4662 194 tadej
        // starting length is min_tmp, ending length is (min_tmp + 64)
4663 209 tadejm
        $display("    pads appending to packets is NOT selected");
4664
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
4665 194 tadej
                 min_tmp, (min_tmp + 64));
4666 209 tadejm
        // set padding, remain the rest
4667 274 tadejm
        wait (wbm_working == 0);
4668 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4669
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4670
      end
4671 194 tadej
      else if ((i_length + 4) == (max_tmp - 16))
4672 209 tadejm
      begin
4673 194 tadej
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
4674 209 tadejm
        $display("    pads appending to packets is selected");
4675
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
4676 194 tadej
                 (min_tmp + 64 + 128), tmp_data);
4677 209 tadejm
        // reset padding, remain the rest
4678 274 tadejm
        wait (wbm_working == 0);
4679 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
4680
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4681
      end
4682 194 tadej
      else if ((i_length + 4) == max_tmp)
4683 209 tadejm
      begin
4684
        $display("    pads appending to packets is NOT selected");
4685
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
4686 194 tadej
                 (max_tmp - (4 + 16)), max_tmp);
4687 209 tadejm
      end
4688 194 tadej
      // set length (loop variable)
4689
      if ((i_length + 4) < (min_tmp + 64))
4690
        i_length = i_length + 1;
4691
      else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
4692
      begin
4693
        i_length = i_length + 128;
4694
        tmp_data = i_length + 4; // last tmp_data is ending length
4695
      end
4696
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
4697
        i_length = max_tmp - (4 + 16);
4698
      else if ((i_length + 4) >= (max_tmp - 16))
4699
        i_length = i_length + 1;
4700
      else
4701
      begin
4702
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
4703
        #10 $stop;
4704
      end
4705 192 tadej
    end
4706 194 tadej
    // disable TX
4707 274 tadejm
    wait (wbm_working == 0);
4708 194 tadej
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4709
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4710
    if(fail == 0)
4711
      test_ok;
4712
    else
4713
      fail = 0;
4714
  end
4715
 
4716
 
4717
  ////////////////////////////////////////////////////////////////////
4718
  ////                                                            ////
4719
  ////  Test transmit packets form MINFL to MAXFL sizes at        ////
4720
  ////  one TX buffer decriptor ( 100Mbps ).                      ////
4721
  ////                                                            ////
4722
  ////////////////////////////////////////////////////////////////////
4723 209 tadejm
  if (test_num == 3) // with and without padding
4724 194 tadej
  begin
4725
    // TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )
4726
    test_name = "TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )";
4727
    `TIME; $display("  TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )");
4728
 
4729
    max_tmp = 0;
4730
    min_tmp = 0;
4731
    // set one TX buffer descriptor - must be set before TX enable
4732 274 tadejm
    wait (wbm_working == 0);
4733 194 tadej
    wbm_write(`ETH_TX_BD_NUM, 32'h1, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4734 209 tadejm
    // enable TX, set full-duplex mode, NO padding and CRC appending
4735 274 tadejm
    wait (wbm_working == 0);
4736 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
4737 194 tadej
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4738
    // prepare two packets of MAXFL length
4739 274 tadejm
    wait (wbm_working == 0);
4740 194 tadej
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4741
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
4742
    min_tmp = tmp[31:16];
4743
    st_data = 8'h5A;
4744 209 tadejm
    set_tx_packet(`MEMORY_BASE, (max_tmp), st_data); // length without CRC
4745 194 tadej
    st_data = 8'h10;
4746 209 tadejm
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp), st_data); // length without CRC
4747 169 mohor
    // check WB INT signal
4748 192 tadej
    if (wb_int !== 1'b0)
4749 169 mohor
    begin
4750
      test_fail("WB INT signal should not be set");
4751
      fail = fail + 1;
4752
    end
4753 194 tadej
 
4754
    // write to phy's control register for 100Mbps
4755
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
4756
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
4757
    speed = 100;
4758 192 tadej
 
4759 194 tadej
    i_length = (min_tmp - 4);
4760
    while (i_length <= (max_tmp - 4))
4761 192 tadej
    begin
4762 194 tadej
      // choose generating carrier sense and collision
4763
      case (i_length[1:0])
4764
      2'h0: // Interrupt is generated
4765 192 tadej
      begin
4766 194 tadej
        // enable interrupt generation
4767 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
4768 194 tadej
        // unmask interrupts
4769 274 tadejm
        wait (wbm_working == 0);
4770 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
4771 194 tadej
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4772
        // not detect carrier sense in FD and no collision
4773
        eth_phy.carrier_sense_tx_fd_detect(0);
4774
        eth_phy.collision(0);
4775 192 tadej
      end
4776 194 tadej
      2'h1: // Interrupt is not generated
4777 192 tadej
      begin
4778 194 tadej
        // enable interrupt generation
4779 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
4780 194 tadej
        // mask interrupts
4781 274 tadejm
        wait (wbm_working == 0);
4782 194 tadej
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4783
        // detect carrier sense in FD and no collision
4784
        eth_phy.carrier_sense_tx_fd_detect(1);
4785
        eth_phy.collision(0);
4786 192 tadej
      end
4787 194 tadej
      2'h2: // Interrupt is not generated
4788
      begin
4789
        // disable interrupt generation
4790 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
4791 194 tadej
        // unmask interrupts
4792 274 tadejm
        wait (wbm_working == 0);
4793 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
4794 194 tadej
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4795
        // not detect carrier sense in FD and set collision
4796
        eth_phy.carrier_sense_tx_fd_detect(0);
4797
        eth_phy.collision(1);
4798
      end
4799
      default: // 2'h3: // Interrupt is not generated
4800
      begin
4801
        // disable interrupt generation
4802 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
4803 194 tadej
        // mask interrupts
4804 274 tadejm
        wait (wbm_working == 0);
4805 194 tadej
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4806
        // detect carrier sense in FD and set collision
4807
        eth_phy.carrier_sense_tx_fd_detect(1);
4808
        eth_phy.collision(1);
4809
      end
4810
      endcase
4811
      eth_phy.set_tx_mem_addr(max_tmp);
4812
      // set wrap bit
4813
      set_tx_bd_wrap(0);
4814
      set_tx_bd_ready(0, 0);
4815 192 tadej
      #1 check_tx_bd(0, data);
4816 194 tadej
      if (i_length < min_tmp) // just first four
4817 192 tadej
      begin
4818 194 tadej
        while (data[15] === 1)
4819
        begin
4820
          #1 check_tx_bd(0, data);
4821
          @(posedge wb_clk);
4822
        end
4823 209 tadejm
        repeat (1) @(posedge wb_clk);
4824 194 tadej
      end
4825
      else if (i_length > (max_tmp - 8)) // just last four
4826
      begin
4827
        tmp = 0;
4828
        wait (MTxEn === 1'b1); // start transmit
4829
        while (tmp < (i_length - 20))
4830
        begin
4831
          #1 tmp = tmp + 1;
4832
          @(posedge wb_clk);
4833
        end
4834 192 tadej
        #1 check_tx_bd(0, data);
4835 194 tadej
        while (data[15] === 1)
4836
        begin
4837
          #1 check_tx_bd(0, data);
4838
          @(posedge wb_clk);
4839
        end
4840 209 tadejm
        repeat (1) @(posedge wb_clk);
4841 192 tadej
      end
4842 194 tadej
      else
4843
      begin
4844
        wait (MTxEn === 1'b1); // start transmit
4845
        #1 check_tx_bd(0, data);
4846
        if (data[15] !== 1)
4847
        begin
4848
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
4849
          fail = fail + 1;
4850
        end
4851
        wait (MTxEn === 1'b0); // end transmit
4852
        while (data[15] === 1)
4853
        begin
4854
          #1 check_tx_bd(0, data);
4855
          @(posedge wb_clk);
4856
        end
4857
        repeat (1) @(posedge wb_clk);
4858
      end
4859
      // check length of a PACKET
4860
      if (eth_phy.tx_len != (i_length + 4))
4861
      begin
4862
        test_fail("Wrong length of the packet out from MAC");
4863
        fail = fail + 1;
4864
      end
4865 192 tadej
      // check transmitted TX packet data
4866
      if (i_length[0] == 0)
4867
      begin
4868 209 tadejm
        check_tx_packet((`MEMORY_BASE + i_length[1:0]), max_tmp, i_length, tmp);
4869 192 tadej
      end
4870
      else
4871
      begin
4872 209 tadejm
        check_tx_packet(((`MEMORY_BASE + i_length[1:0]) + max_tmp), max_tmp, i_length, tmp);
4873 192 tadej
      end
4874
      if (tmp > 0)
4875
      begin
4876
        test_fail("Wrong data of the transmitted packet");
4877
        fail = fail + 1;
4878
      end
4879
      // check transmited TX packet CRC
4880
      check_tx_crc(max_tmp, i_length, 1'b0, tmp); // length without CRC
4881
      if (tmp > 0)
4882
      begin
4883
        test_fail("Wrong CRC of the transmitted packet");
4884
        fail = fail + 1;
4885
      end
4886 194 tadej
      // check WB INT signal
4887
      if (i_length[1:0] == 2'h0)
4888 192 tadej
      begin
4889 194 tadej
        if (wb_int !== 1'b1)
4890
        begin
4891
          `TIME; $display("*E WB INT signal should be set");
4892
          test_fail("WB INT signal should be set");
4893
          fail = fail + 1;
4894
        end
4895 192 tadej
      end
4896 194 tadej
      else
4897 192 tadej
      begin
4898 194 tadej
        if (wb_int !== 1'b0)
4899
        begin
4900
          `TIME; $display("*E WB INT signal should not be set");
4901
          test_fail("WB INT signal should not be set");
4902
          fail = fail + 1;
4903
        end
4904 192 tadej
      end
4905 194 tadej
      // check TX buffer descriptor of a packet
4906
      check_tx_bd(0, data);
4907
      if (i_length[1] == 1'b0) // interrupt enabled
4908 192 tadej
      begin
4909 194 tadej
        if (data[15:0] !== 16'h7800)
4910
        begin
4911
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
4912
          test_fail("TX buffer descriptor status is not correct");
4913
          fail = fail + 1;
4914
        end
4915 192 tadej
      end
4916 194 tadej
      else // interrupt not enabled
4917 192 tadej
      begin
4918 194 tadej
        if (data[15:0] !== 16'h3800)
4919
        begin
4920
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
4921
          test_fail("TX buffer descriptor status is not correct");
4922
          fail = fail + 1;
4923
        end
4924 192 tadej
      end
4925 194 tadej
      // clear TX buffer descriptor
4926
      clear_tx_bd(0, 0);
4927
      // check interrupts
4928 274 tadejm
      wait (wbm_working == 0);
4929 194 tadej
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4930
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
4931 192 tadej
      begin
4932 194 tadej
        if ((data & `ETH_INT_TXB) !== 1'b1)
4933
        begin
4934
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
4935
          test_fail("Interrupt Transmit Buffer was not set");
4936
          fail = fail + 1;
4937
        end
4938
        if ((data & (~`ETH_INT_TXB)) !== 0)
4939
        begin
4940
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
4941
          test_fail("Other interrupts (except Transmit Buffer) were set");
4942
          fail = fail + 1;
4943
        end
4944 192 tadej
      end
4945 194 tadej
      else
4946 192 tadej
      begin
4947 194 tadej
        if (data !== 0)
4948
        begin
4949
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h", data);
4950
          test_fail("Any of interrupts (except Transmit Buffer) was set");
4951
          fail = fail + 1;
4952
        end
4953 192 tadej
      end
4954 194 tadej
      // clear interrupts
4955 274 tadejm
      wait (wbm_working == 0);
4956 194 tadej
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4957
      // check WB INT signal
4958
      if (wb_int !== 1'b0)
4959 192 tadej
      begin
4960 194 tadej
        test_fail("WB INT signal should not be set");
4961 192 tadej
        fail = fail + 1;
4962
      end
4963 194 tadej
      // INTERMEDIATE DISPLAYS
4964
      if ((i_length + 4) == (min_tmp + 64))
4965 209 tadejm
      begin
4966 194 tadej
        // starting length is min_tmp, ending length is (min_tmp + 64)
4967 209 tadejm
        $display("    pads appending to packets is NOT selected");
4968
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
4969 194 tadej
                 min_tmp, (min_tmp + 64));
4970 209 tadejm
        // set padding, remain the rest
4971 274 tadejm
        wait (wbm_working == 0);
4972 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4973
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4974
      end
4975 194 tadej
      else if ((i_length + 4) == (max_tmp - 16))
4976 209 tadejm
      begin
4977 194 tadej
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
4978 209 tadejm
        $display("    pads appending to packets is selected");
4979
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
4980 194 tadej
                 (min_tmp + 64 + 128), tmp_data);
4981 209 tadejm
        // reset padding, remain the rest
4982 274 tadejm
        wait (wbm_working == 0);
4983 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
4984
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4985
      end
4986 194 tadej
      else if ((i_length + 4) == max_tmp)
4987 209 tadejm
      begin
4988
        $display("    pads appending to packets is NOT selected");
4989
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
4990 194 tadej
                 (max_tmp - (4 + 16)), max_tmp);
4991 209 tadejm
      end
4992 194 tadej
      // set length (loop variable)
4993
      if ((i_length + 4) < (min_tmp + 64))
4994
        i_length = i_length + 1;
4995
      else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
4996
      begin
4997
        i_length = i_length + 128;
4998
        tmp_data = i_length + 4; // last tmp_data is ending length
4999
      end
5000
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
5001
        i_length = max_tmp - (4 + 16);
5002
      else if ((i_length + 4) >= (max_tmp - 16))
5003
        i_length = i_length + 1;
5004 192 tadej
      else
5005 194 tadej
      begin
5006
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
5007
        #10 $stop;
5008
      end
5009 179 mohor
    end
5010 194 tadej
    // disable TX
5011 274 tadejm
    wait (wbm_working == 0);
5012 194 tadej
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
5013
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5014
    if(fail == 0)
5015
      test_ok;
5016
    else
5017
      fail = 0;
5018 169 mohor
  end
5019
 
5020
 
5021 209 tadejm
  ////////////////////////////////////////////////////////////////////
5022
  ////                                                            ////
5023
  ////  Test transmit packets form MINFL to MAXFL sizes at        ////
5024
  ////  maximum TX buffer decriptors ( 10Mbps ).                  ////
5025
  ////                                                            ////
5026
  ////////////////////////////////////////////////////////////////////
5027
  if (test_num == 4) // without and with padding
5028
  begin
5029
    // TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps )
5030
    test_name = "TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps )";
5031
    `TIME; $display("  TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps )");
5032
 
5033
    // reset MAC registers
5034
    hard_reset;
5035
    // reset MAC and MII LOGIC with soft reset
5036 274 tadejm
//    reset_mac;
5037
//    reset_mii;
5038 209 tadejm
    // set wb slave response
5039
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
5040 192 tadej
 
5041 209 tadejm
    max_tmp = 0;
5042
    min_tmp = 0;
5043
    num_of_frames = 0;
5044
    num_of_bd = 0;
5045
    // set maximum TX buffer descriptors (128) - must be set before TX enable
5046 274 tadejm
    wait (wbm_working == 0);
5047 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5048
    // enable TX, set full-duplex mode, NO padding and CRC appending
5049 274 tadejm
    wait (wbm_working == 0);
5050 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
5051
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5052
    // prepare two packets of MAXFL length
5053 274 tadejm
    wait (wbm_working == 0);
5054 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5055
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
5056
    min_tmp = tmp[31:16];
5057
    st_data = 8'hA3;
5058
    set_tx_packet(`MEMORY_BASE, (max_tmp), st_data); // length without CRC
5059
    st_data = 8'h81;
5060
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp), st_data); // length without CRC
5061
    // check WB INT signal
5062
    if (wb_int !== 1'b0)
5063
    begin
5064
      test_fail("WB INT signal should not be set");
5065
      fail = fail + 1;
5066
    end
5067
 
5068
    // write to phy's control register for 10Mbps
5069
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
5070
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
5071
    speed = 10;
5072
 
5073
    i_length = (min_tmp - 4);
5074
    while (i_length <= (max_tmp - 4))
5075
    begin
5076
      // choose generating carrier sense and collision
5077
      case (i_length[1:0])
5078
      2'h0: // Interrupt is generated
5079
      begin
5080
        // Reset_tx_bd nable interrupt generation
5081
        // unmask interrupts
5082 274 tadejm
        wait (wbm_working == 0);
5083 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
5084
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5085
        // not detect carrier sense in FD and no collision
5086
        eth_phy.carrier_sense_tx_fd_detect(0);
5087
        eth_phy.collision(0);
5088
      end
5089
      2'h1: // Interrupt is not generated
5090
      begin
5091
        // set_tx_bd enable interrupt generation
5092
        // mask interrupts
5093 274 tadejm
        wait (wbm_working == 0);
5094 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5095
        // detect carrier sense in FD and no collision
5096
        eth_phy.carrier_sense_tx_fd_detect(1);
5097
        eth_phy.collision(0);
5098
      end
5099
      2'h2: // Interrupt is not generated
5100
      begin
5101
        // set_tx_bd disable the interrupt generation
5102
        // unmask interrupts
5103 274 tadejm
        wait (wbm_working == 0);
5104 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
5105
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5106
        // not detect carrier sense in FD and set collision
5107
        eth_phy.carrier_sense_tx_fd_detect(0);
5108
        eth_phy.collision(1);
5109
      end
5110
      default: // 2'h3: // Interrupt is not generated
5111
      begin
5112
        // set_tx_bd disable the interrupt generation
5113
        // mask interrupts
5114 274 tadejm
        wait (wbm_working == 0);
5115 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5116
        // detect carrier sense in FD and set collision
5117
        eth_phy.carrier_sense_tx_fd_detect(1);
5118
        eth_phy.collision(1);
5119
      end
5120
      endcase
5121
      // first destination address on ethernet PHY
5122
      if (i_length[0] == 0)
5123
        eth_phy.set_tx_mem_addr(0);
5124
      else
5125
        eth_phy.set_tx_mem_addr(max_tmp);
5126
      // first 8 frames are transmitted with TX BD 0 (wrap bit on TX BD 0)
5127
      // number of all frames is 154 (146 without first 8)
5128
      if (num_of_frames < 8)
5129
      begin
5130
        case (i_length[1:0])
5131
        2'h0: // Interrupt is generated
5132
        begin
5133
          // enable interrupt generation
5134
          set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
5135
          // interrupts are unmasked
5136
        end
5137
        2'h1: // Interrupt is not generated
5138
        begin
5139
          // enable interrupt generation
5140
          set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
5141
          // interrupts are masked
5142
        end
5143
        2'h2: // Interrupt is not generated
5144
        begin
5145
          // disable interrupt generation
5146
          set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
5147
          // interrupts are unmasked
5148
        end
5149
        default: // 2'h3: // Interrupt is not generated
5150
        begin
5151
          // disable interrupt generation
5152
          set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
5153
          // interrupts are masked
5154
        end
5155
        endcase
5156
        // set wrap bit
5157
        set_tx_bd_wrap(0);
5158
      end
5159
      // after first 8 number of frames, 128 frames form TX BD 0 to 127 will be transmitted
5160
      else if ((num_of_frames - 8) == 0)
5161
      begin
5162
        tmp_len = i_length; // length of frame
5163
        tmp_bd_num = 0; // TX BD number
5164
        while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
5165
        begin
5166
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
5167
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
5168
          if (tmp_len[0] == 0)
5169
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
5170
          else
5171
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
5172
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
5173
          if ((tmp_len + 4) < (min_tmp + 128))
5174
            tmp_len = tmp_len + 1;
5175
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5176
            tmp_len = 256;
5177
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5178
            tmp_len = tmp_len + 128;
5179
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
5180
            tmp_len = max_tmp - (4 + 16);
5181
          else if ((tmp_len + 4) >= (max_tmp - 16))
5182
            tmp_len = tmp_len + 1;
5183
          // set TX BD number
5184
          tmp_bd_num = tmp_bd_num + 1;
5185
        end
5186
        // set wrap bit
5187
        set_tx_bd_wrap(127);
5188
      end
5189
      // after 128 + first 8 number of frames, 19 frames form TX BD 0 to 18 will be transmitted
5190
      else if ((num_of_frames - 8) == 20) // 128
5191
      begin
5192
        tmp_len = tmp_len; // length of frame remaines from previous settings
5193
        tmp_bd_num = 0; // TX BD number
5194
        while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
5195
        begin
5196
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
5197
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
5198
          if (tmp_len[0] == 0)
5199
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
5200
          else
5201
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
5202
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
5203
          if ((tmp_len + 4) < (min_tmp + 128))
5204
            tmp_len = tmp_len + 1;
5205
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5206
            tmp_len = 256;
5207
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5208
            tmp_len = tmp_len + 128;
5209
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
5210
            tmp_len = max_tmp - (4 + 16);
5211
          else if ((tmp_len + 4) >= (max_tmp - 16))
5212
            tmp_len = tmp_len + 1;
5213
          // set TX BD number
5214
          tmp_bd_num = tmp_bd_num + 1;
5215
        end
5216
      end
5217
      // set ready bit
5218
      if (num_of_frames < 8)
5219
        set_tx_bd_ready(0, 0);
5220
      else if ((num_of_frames - 8) < 128)
5221
        set_tx_bd_ready((num_of_frames - 8), (num_of_frames - 8));
5222
      else if ((num_of_frames - 136) < 19)
5223
        set_tx_bd_ready((num_of_frames - 136), (num_of_frames - 136));
5224
      // CHECK END OF TRANSMITION
5225
      #1 check_tx_bd(num_of_bd, data);
5226
      if (i_length < min_tmp) // just first four
5227
      begin
5228
        while (data[15] === 1)
5229
        begin
5230
          #1 check_tx_bd(num_of_bd, data);
5231
          @(posedge wb_clk);
5232
        end
5233
        repeat (1) @(posedge wb_clk);
5234
      end
5235
      else if (i_length > (max_tmp - 8)) // just last four
5236
      begin
5237
        tmp = 0;
5238
        wait (MTxEn === 1'b1); // start transmit
5239
        while (tmp < (i_length - 20))
5240
        begin
5241
          #1 tmp = tmp + 1;
5242
          @(posedge wb_clk);
5243
        end
5244
        #1 check_tx_bd(num_of_bd, data);
5245
        while (data[15] === 1)
5246
        begin
5247
          #1 check_tx_bd(num_of_bd, data);
5248
          @(posedge wb_clk);
5249
        end
5250
        repeat (1) @(posedge wb_clk);
5251
      end
5252
      else
5253
      begin
5254
        wait (MTxEn === 1'b1); // start transmit
5255
        #1 check_tx_bd(num_of_bd, data);
5256
        if (data[15] !== 1)
5257
        begin
5258
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
5259
          fail = fail + 1;
5260
        end
5261
        wait (MTxEn === 1'b0); // end transmit
5262
        while (data[15] === 1)
5263
        begin
5264
          #1 check_tx_bd(num_of_bd, data);
5265
          @(posedge wb_clk);
5266
        end
5267
        repeat (1) @(posedge wb_clk);
5268
      end
5269
      // check length of a PACKET
5270
      if (eth_phy.tx_len != (i_length + 4))
5271
      begin
5272
        test_fail("Wrong length of the packet out from MAC");
5273
        fail = fail + 1;
5274
      end
5275
        // check transmitted TX packet data
5276
        if (i_length[0] == 0)
5277
        begin
5278
          check_tx_packet((`MEMORY_BASE + i_length[1:0]), 0, i_length, tmp);
5279
        end
5280
        else
5281
        begin
5282
          check_tx_packet(((`MEMORY_BASE + i_length[1:0]) + max_tmp), max_tmp, i_length, tmp);
5283
        end
5284
        if (tmp > 0)
5285
        begin
5286
          test_fail("Wrong data of the transmitted packet");
5287
          fail = fail + 1;
5288
        end
5289
        // check transmited TX packet CRC
5290
        if (i_length[0] == 0)
5291
          check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
5292
        else
5293
          check_tx_crc(max_tmp, i_length, 1'b0, tmp); // length without CRC
5294
        if (tmp > 0)
5295
        begin
5296
          test_fail("Wrong CRC of the transmitted packet");
5297
          fail = fail + 1;
5298
        end
5299
      // check WB INT signal
5300
      if (i_length[1:0] == 2'h0)
5301
      begin
5302
        if (wb_int !== 1'b1)
5303
        begin
5304
          `TIME; $display("*E WB INT signal should be set");
5305
          test_fail("WB INT signal should be set");
5306
          fail = fail + 1;
5307
        end
5308
      end
5309
      else
5310
      begin
5311
        if (wb_int !== 1'b0)
5312
        begin
5313
          `TIME; $display("*E WB INT signal should not be set");
5314
          test_fail("WB INT signal should not be set");
5315
          fail = fail + 1;
5316
        end
5317
      end
5318
      // check TX buffer descriptor of a packet
5319
      check_tx_bd(num_of_bd, data);
5320
      if (i_length[1] == 1'b0) // interrupt enabled
5321
      begin
5322
        if ( ((data[15:0] !== 16'h7800) && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
5323
             ((data[15:0] !== 16'h5800) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
5324
        begin
5325
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
5326
          test_fail("TX buffer descriptor status is not correct");
5327
          fail = fail + 1;
5328
        end
5329
      end
5330
      else // interrupt not enabled
5331
      begin
5332
        if ( ((data[15:0] !== 16'h3800)  && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
5333
             ((data[15:0] !== 16'h1800) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
5334
        begin
5335
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
5336
          test_fail("TX buffer descriptor status is not correct");
5337
          fail = fail + 1;
5338
        end
5339
      end
5340
      // clear first half of 8 frames from TX buffer descriptor 0
5341
      if (num_of_frames < 4)
5342
        clear_tx_bd(num_of_bd, num_of_bd);
5343
      // clear BD with wrap bit
5344
      if (num_of_frames == 140)
5345
        clear_tx_bd(127, 127);
5346
      // check interrupts
5347 274 tadejm
      wait (wbm_working == 0);
5348 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5349
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
5350
      begin
5351
        if ((data & `ETH_INT_TXB) !== 1'b1)
5352
        begin
5353
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
5354
          test_fail("Interrupt Transmit Buffer was not set");
5355
          fail = fail + 1;
5356
        end
5357
        if ((data & (~`ETH_INT_TXB)) !== 0)
5358
        begin
5359
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
5360
          test_fail("Other interrupts (except Transmit Buffer) were set");
5361
          fail = fail + 1;
5362
        end
5363
      end
5364
      else
5365
      begin
5366
        if (data !== 0)
5367
        begin
5368
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
5369
          test_fail("Any of interrupts (except Transmit Buffer) was set");
5370
          fail = fail + 1;
5371
        end
5372
      end
5373
      // clear interrupts
5374 274 tadejm
      wait (wbm_working == 0);
5375 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5376
      // check WB INT signal
5377
      if (wb_int !== 1'b0)
5378
      begin
5379
        test_fail("WB INT signal should not be set");
5380
        fail = fail + 1;
5381
      end
5382
      // INTERMEDIATE DISPLAYS
5383
      if ((i_length + 4) == (min_tmp + 7))
5384
      begin
5385
        // starting length is min_tmp, ending length is (min_tmp + 128)
5386
        $display("    pads appending to packets is NOT selected");
5387
        $display("    using only TX BD 0 out of 128 BDs assigned to TX (wrap at first BD - TX BD 0)");
5388
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
5389
                 min_tmp, (min_tmp + 7));
5390
        $display("    ->all packets were send from TX BD 0");
5391
        // set padding, remain the rest
5392 274 tadejm
        wait (wbm_working == 0);
5393 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
5394
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5395
      end
5396
      else if ((i_length + 4) == (min_tmp + 128))
5397
      begin
5398
        // starting length is min_tmp, ending length is (min_tmp + 128)
5399
        $display("    pads appending to packets is NOT selected");
5400
        $display("    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)");
5401
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
5402
                 (min_tmp + 8), (min_tmp + 128));
5403
        $display("    ->packets were send from TX BD %0d to TX BD %0d respectively",
5404
                 1'b0, num_of_bd);
5405
        tmp_bd = num_of_bd + 1;
5406
        // set padding, remain the rest
5407 274 tadejm
        wait (wbm_working == 0);
5408 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
5409
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5410
      end
5411
      else if ((i_length + 4) == (max_tmp - 16))
5412
      begin
5413
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
5414
        $display("    pads appending to packets is selected");
5415
        $display("    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)");
5416
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
5417
                 (min_tmp + 64 + 128), tmp_data);
5418
        if (tmp_bd > num_of_bd)
5419
          $display("    ->packets were send from TX BD %0d to TX BD 127 and from TX BD 0 to TX BD %0d respectively",
5420
                   tmp_bd, num_of_bd);
5421
        else
5422
          $display("    ->packets were send from TX BD %0d to TX BD %0d respectively",
5423
                   tmp_bd, num_of_bd);
5424
        tmp_bd = num_of_bd + 1;
5425
        // reset padding, remain the rest
5426 274 tadejm
        wait (wbm_working == 0);
5427 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
5428
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5429
      end
5430
      else if ((i_length + 4) == max_tmp)
5431
      begin
5432
        $display("    pads appending to packets is NOT selected");
5433
        $display("    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)");
5434
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
5435
                 (max_tmp - (4 + 16)), max_tmp);
5436
        if (tmp_bd > num_of_bd)
5437
          $display("    ->packets were send from TX BD %0d to TX BD 127 and from TX BD 0 to TX BD %0d respectively",
5438
                   tmp_bd, num_of_bd);
5439
        else
5440
          $display("    ->packets were send from TX BD %0d to TX BD %0d respectively",
5441
                   tmp_bd, num_of_bd);
5442
      end
5443
      // set length (loop variable)
5444
      if ((i_length + 4) < (min_tmp + 128))
5445
        i_length = i_length + 1;
5446
      else if ( ((i_length + 4) == (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
5447
        i_length = 256;
5448
      else if ( ((i_length + 4) > (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
5449
      begin
5450
        i_length = i_length + 128;
5451
        tmp_data = i_length + 4; // last tmp_data is ending length
5452
      end
5453
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
5454
        i_length = max_tmp - (4 + 16);
5455
      else if ((i_length + 4) >= (max_tmp - 16))
5456
        i_length = i_length + 1;
5457
      else
5458
      begin
5459
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
5460
        #10 $stop;
5461
      end
5462
      // the number of frame transmitted
5463
      num_of_frames = num_of_frames + 1;
5464
      if ((num_of_frames <= 8) || ((num_of_frames - 8) == 128))
5465
        num_of_bd = 0;
5466
      else
5467
        num_of_bd = num_of_bd + 1;
5468
    end
5469
    // disable TX
5470 274 tadejm
    wait (wbm_working == 0);
5471 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
5472
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5473
    @(posedge wb_clk);
5474
    if(fail == 0)
5475
      test_ok;
5476
    else
5477
      fail = 0;
5478
  end
5479
 
5480
 
5481
  ////////////////////////////////////////////////////////////////////
5482
  ////                                                            ////
5483
  ////  Test transmit packets form MINFL to MAXFL sizes at        ////
5484
  ////  maximum TX buffer decriptors ( 100Mbps ).                 ////
5485
  ////                                                            ////
5486
  ////////////////////////////////////////////////////////////////////
5487
  if (test_num == 5) // with and without padding
5488
  begin
5489
    // TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps )
5490
    test_name = "TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps )";
5491
    `TIME; $display("  TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps )");
5492
 
5493
    // reset MAC registers
5494
    hard_reset;
5495
    // reset MAC and MII LOGIC with soft reset
5496 274 tadejm
//    reset_mac;
5497
//    reset_mii;
5498 209 tadejm
    // set wb slave response
5499
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
5500
 
5501
    max_tmp = 0;
5502
    min_tmp = 0;
5503
    num_of_frames = 0;
5504
    num_of_bd = 0;
5505
    // set maximum TX buffer descriptors (128) - must be set before TX enable
5506 274 tadejm
    wait (wbm_working == 0);
5507 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5508
    // enable TX, set full-duplex mode, NO padding and CRC appending
5509 274 tadejm
    wait (wbm_working == 0);
5510 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
5511
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5512
    // prepare two packets of MAXFL length
5513 274 tadejm
    wait (wbm_working == 0);
5514 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5515
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
5516
    min_tmp = tmp[31:16];
5517
    st_data = 8'hA5;
5518
    set_tx_packet(`MEMORY_BASE, (max_tmp), st_data); // length without CRC
5519
    st_data = 8'h71;
5520
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp), st_data); // length without CRC
5521
    // check WB INT signal
5522
    if (wb_int !== 1'b0)
5523
    begin
5524
      test_fail("WB INT signal should not be set");
5525
      fail = fail + 1;
5526
    end
5527
 
5528
    // write to phy's control register for 100Mbps
5529
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
5530
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
5531
    speed = 100;
5532
 
5533
    i_length = (min_tmp - 4);
5534
    while (i_length <= (max_tmp - 4))
5535
    begin
5536
      // choose generating carrier sense and collision
5537
      case (i_length[1:0])
5538
      2'h0: // Interrupt is generated
5539
      begin
5540
        // Reset_tx_bd nable interrupt generation
5541
        // unmask interrupts
5542 274 tadejm
        wait (wbm_working == 0);
5543 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
5544
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5545
        // not detect carrier sense in FD and no collision
5546
        eth_phy.carrier_sense_tx_fd_detect(0);
5547
        eth_phy.collision(0);
5548
      end
5549
      2'h1: // Interrupt is not generated
5550
      begin
5551
        // set_tx_bd enable interrupt generation
5552
        // mask interrupts
5553 274 tadejm
        wait (wbm_working == 0);
5554 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5555
        // detect carrier sense in FD and no collision
5556
        eth_phy.carrier_sense_tx_fd_detect(1);
5557
        eth_phy.collision(0);
5558
      end
5559
      2'h2: // Interrupt is not generated
5560
      begin
5561
        // set_tx_bd disable the interrupt generation
5562
        // unmask interrupts
5563 274 tadejm
        wait (wbm_working == 0);
5564 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
5565
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5566
        // not detect carrier sense in FD and set collision
5567
        eth_phy.carrier_sense_tx_fd_detect(0);
5568
        eth_phy.collision(1);
5569
      end
5570
      default: // 2'h3: // Interrupt is not generated
5571
      begin
5572
        // set_tx_bd disable the interrupt generation
5573
        // mask interrupts
5574 274 tadejm
        wait (wbm_working == 0);
5575 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5576
        // detect carrier sense in FD and set collision
5577
        eth_phy.carrier_sense_tx_fd_detect(1);
5578
        eth_phy.collision(1);
5579
      end
5580
      endcase
5581
      // first destination address on ethernet PHY
5582
      if (i_length[0] == 0)
5583
        eth_phy.set_tx_mem_addr(0);
5584
      else
5585
        eth_phy.set_tx_mem_addr(max_tmp);
5586
      // first 8 frames are transmitted with TX BD 0 (wrap bit on TX BD 0)
5587
      // number of all frames is 154 (146 without first 8)
5588
      if (num_of_frames < 8)
5589
      begin
5590
        case (i_length[1:0])
5591
        2'h0: // Interrupt is generated
5592
        begin
5593
          // enable interrupt generation
5594
          set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
5595
          // interrupts are unmasked
5596
        end
5597
        2'h1: // Interrupt is not generated
5598
        begin
5599
          // enable interrupt generation
5600
          set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
5601
          // interrupts are masked
5602
        end
5603
        2'h2: // Interrupt is not generated
5604
        begin
5605
          // disable interrupt generation
5606
          set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
5607
          // interrupts are unmasked
5608
        end
5609
        default: // 2'h3: // Interrupt is not generated
5610
        begin
5611
          // disable interrupt generation
5612
          set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
5613
          // interrupts are masked
5614
        end
5615
        endcase
5616
        // set wrap bit
5617
        set_tx_bd_wrap(0);
5618
      end
5619
      // after first 8 number of frames, 128 frames form TX BD 0 to 127 will be transmitted
5620
      else if ((num_of_frames - 8) == 0)
5621
      begin
5622
        tmp_len = i_length; // length of frame
5623
        tmp_bd_num = 0; // TX BD number
5624
        while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
5625
        begin
5626
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
5627
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
5628
          if (tmp_len[0] == 0)
5629
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
5630
          else
5631
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
5632
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
5633
          if ((tmp_len + 4) < (min_tmp + 128))
5634
            tmp_len = tmp_len + 1;
5635
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5636
            tmp_len = 256;
5637
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5638
            tmp_len = tmp_len + 128;
5639
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
5640
            tmp_len = max_tmp - (4 + 16);
5641
          else if ((tmp_len + 4) >= (max_tmp - 16))
5642
            tmp_len = tmp_len + 1;
5643
          // set TX BD number
5644
          tmp_bd_num = tmp_bd_num + 1;
5645
        end
5646
        // set wrap bit
5647
        set_tx_bd_wrap(127);
5648
      end
5649
      // after 128 + first 8 number of frames, 19 frames form TX BD 0 to 18 will be transmitted
5650
      else if ((num_of_frames - 8) == 20) // 128
5651
      begin
5652
        tmp_len = tmp_len; // length of frame remaines from previous settings
5653
        tmp_bd_num = 0; // TX BD number
5654
        while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
5655
        begin
5656
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
5657
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
5658
          if (tmp_len[0] == 0)
5659
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
5660
          else
5661
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
5662
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
5663
          if ((tmp_len + 4) < (min_tmp + 128))
5664
            tmp_len = tmp_len + 1;
5665
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5666
            tmp_len = 256;
5667
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5668
            tmp_len = tmp_len + 128;
5669
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
5670
            tmp_len = max_tmp - (4 + 16);
5671
          else if ((tmp_len + 4) >= (max_tmp - 16))
5672
            tmp_len = tmp_len + 1;
5673
          // set TX BD number
5674
          tmp_bd_num = tmp_bd_num + 1;
5675
        end
5676
      end
5677
      // set ready bit
5678
      if (num_of_frames < 8)
5679
        set_tx_bd_ready(0, 0);
5680
      else if ((num_of_frames - 8) < 128)
5681
        set_tx_bd_ready((num_of_frames - 8), (num_of_frames - 8));
5682
      else if ((num_of_frames - 136) < 19)
5683
        set_tx_bd_ready((num_of_frames - 136), (num_of_frames - 136));
5684
      // CHECK END OF TRANSMITION
5685
      #1 check_tx_bd(num_of_bd, data);
5686
      if (i_length < min_tmp) // just first four
5687
      begin
5688
        while (data[15] === 1)
5689
        begin
5690
          #1 check_tx_bd(num_of_bd, data);
5691
          @(posedge wb_clk);
5692
        end
5693
        repeat (1) @(posedge wb_clk);
5694
      end
5695
      else if (i_length > (max_tmp - 8)) // just last four
5696
      begin
5697
        tmp = 0;
5698
        wait (MTxEn === 1'b1); // start transmit
5699
        while (tmp < (i_length - 20))
5700
        begin
5701
          #1 tmp = tmp + 1;
5702
          @(posedge wb_clk);
5703
        end
5704
        #1 check_tx_bd(num_of_bd, data);
5705
        while (data[15] === 1)
5706
        begin
5707
          #1 check_tx_bd(num_of_bd, data);
5708
          @(posedge wb_clk);
5709
        end
5710
        repeat (1) @(posedge wb_clk);
5711
      end
5712
      else
5713
      begin
5714
        wait (MTxEn === 1'b1); // start transmit
5715
        #1 check_tx_bd(num_of_bd, data);
5716
        if (data[15] !== 1)
5717
        begin
5718
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
5719
          fail = fail + 1;
5720
        end
5721
        wait (MTxEn === 1'b0); // end transmit
5722
        while (data[15] === 1)
5723
        begin
5724
          #1 check_tx_bd(num_of_bd, data);
5725
          @(posedge wb_clk);
5726
        end
5727
        repeat (1) @(posedge wb_clk);
5728
      end
5729
      // check length of a PACKET
5730
      if (eth_phy.tx_len != (i_length + 4))
5731
      begin
5732
        test_fail("Wrong length of the packet out from MAC");
5733
        fail = fail + 1;
5734
      end
5735
      // checking in the following if statement is performed only for first and last 64 lengths
5736
        // check transmitted TX packet data
5737
        if (i_length[0] == 0)
5738
        begin
5739
          check_tx_packet((`MEMORY_BASE + i_length[1:0]), 0, i_length, tmp);
5740
        end
5741
        else
5742
        begin
5743
          check_tx_packet(((`MEMORY_BASE + i_length[1:0]) + max_tmp), max_tmp, i_length, tmp);
5744
        end
5745
        if (tmp > 0)
5746
        begin
5747
          test_fail("Wrong data of the transmitted packet");
5748
          fail = fail + 1;
5749
        end
5750
        // check transmited TX packet CRC
5751
        if (i_length[0] == 0)
5752
          check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
5753
        else
5754
          check_tx_crc(max_tmp, i_length, 1'b0, tmp); // length without CRC
5755
        if (tmp > 0)
5756
        begin
5757
          test_fail("Wrong CRC of the transmitted packet");
5758
          fail = fail + 1;
5759
        end
5760
      // check WB INT signal
5761
      if (i_length[1:0] == 2'h0)
5762
      begin
5763
        if (wb_int !== 1'b1)
5764
        begin
5765
          `TIME; $display("*E WB INT signal should be set");
5766
          test_fail("WB INT signal should be set");
5767
          fail = fail + 1;
5768
        end
5769
      end
5770
      else
5771
      begin
5772
        if (wb_int !== 1'b0)
5773
        begin
5774
          `TIME; $display("*E WB INT signal should not be set");
5775
          test_fail("WB INT signal should not be set");
5776
          fail = fail + 1;
5777
        end
5778
      end
5779
      // check TX buffer descriptor of a packet
5780
      check_tx_bd(num_of_bd, data);
5781
      if (i_length[1] == 1'b0) // interrupt enabled
5782
      begin
5783
        if ( ((data[15:0] !== 16'h7800) && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
5784
             ((data[15:0] !== 16'h5800) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
5785
        begin
5786
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
5787
          test_fail("TX buffer descriptor status is not correct");
5788
          fail = fail + 1;
5789
        end
5790
      end
5791
      else // interrupt not enabled
5792
      begin
5793
        if ( ((data[15:0] !== 16'h3800)  && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
5794
             ((data[15:0] !== 16'h1800) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
5795
        begin
5796
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
5797
          test_fail("TX buffer descriptor status is not correct");
5798
          fail = fail + 1;
5799
        end
5800
      end
5801
      // clear first half of 8 frames from TX buffer descriptor 0
5802
      if (num_of_frames < 4)
5803
        clear_tx_bd(num_of_bd, num_of_bd);
5804
      // clear BD with wrap bit
5805
      if (num_of_frames == 140)
5806
        clear_tx_bd(127, 127);
5807
      // check interrupts
5808 274 tadejm
      wait (wbm_working == 0);
5809 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5810
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
5811
      begin
5812
        if ((data & `ETH_INT_TXB) !== 1'b1)
5813
        begin
5814
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
5815
          test_fail("Interrupt Transmit Buffer was not set");
5816
          fail = fail + 1;
5817
        end
5818
        if ((data & (~`ETH_INT_TXB)) !== 0)
5819
        begin
5820
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
5821
          test_fail("Other interrupts (except Transmit Buffer) were set");
5822
          fail = fail + 1;
5823
        end
5824
      end
5825
      else
5826
      begin
5827
        if (data !== 0)
5828
        begin
5829
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
5830
          test_fail("Any of interrupts (except Transmit Buffer) was set");
5831
          fail = fail + 1;
5832
        end
5833
      end
5834
      // clear interrupts
5835 274 tadejm
      wait (wbm_working == 0);
5836 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5837
      // check WB INT signal
5838
      if (wb_int !== 1'b0)
5839
      begin
5840
        test_fail("WB INT signal should not be set");
5841
        fail = fail + 1;
5842
      end
5843
      // INTERMEDIATE DISPLAYS
5844
      if ((i_length + 4) == (min_tmp + 7))
5845
      begin
5846
        // starting length is min_tmp, ending length is (min_tmp + 128)
5847
        $display("    pads appending to packets is NOT selected");
5848
        $display("    using only TX BD 0 out of 128 BDs assigned to TX (wrap at first BD - TX BD 0)");
5849
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
5850
                 min_tmp, (min_tmp + 7));
5851
        $display("    ->all packets were send from TX BD 0");
5852
        // set padding, remain the rest
5853 274 tadejm
        wait (wbm_working == 0);
5854 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
5855
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5856
      end
5857
      else if ((i_length + 4) == (min_tmp + 128))
5858
      begin
5859
        // starting length is min_tmp, ending length is (min_tmp + 128)
5860
        $display("    pads appending to packets is NOT selected");
5861
        $display("    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)");
5862
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
5863
                 (min_tmp + 8), (min_tmp + 128));
5864
        $display("    ->packets were send from TX BD %0d to TX BD %0d respectively",
5865
                 1'b0, num_of_bd);
5866
        tmp_bd = num_of_bd + 1;
5867
        // set padding, remain the rest
5868 274 tadejm
        wait (wbm_working == 0);
5869 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
5870
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5871
      end
5872
      else if ((i_length + 4) == (max_tmp - 16))
5873
      begin
5874
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
5875
        $display("    pads appending to packets is selected");
5876
        $display("    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)");
5877
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
5878
                 (min_tmp + 64 + 128), tmp_data);
5879
        if (tmp_bd > num_of_bd)
5880
          $display("    ->packets were send from TX BD %0d to TX BD 127 and from TX BD 0 to TX BD %0d respectively",
5881
                   tmp_bd, num_of_bd);
5882
        else
5883
          $display("    ->packets were send from TX BD %0d to TX BD %0d respectively",
5884
                   tmp_bd, num_of_bd);
5885
        tmp_bd = num_of_bd + 1;
5886
        // reset padding, remain the rest
5887 274 tadejm
        wait (wbm_working == 0);
5888 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
5889
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5890
      end
5891
      else if ((i_length + 4) == max_tmp)
5892
      begin
5893
        $display("    pads appending to packets is NOT selected");
5894
        $display("    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)");
5895
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
5896
                 (max_tmp - (4 + 16)), max_tmp);
5897
        if (tmp_bd > num_of_bd)
5898
          $display("    ->packets were send from TX BD %0d to TX BD 127 and from TX BD 0 to TX BD %0d respectively",
5899
                   tmp_bd, num_of_bd);
5900
        else
5901
          $display("    ->packets were send from TX BD %0d to TX BD %0d respectively",
5902
                   tmp_bd, num_of_bd);
5903
      end
5904
      // set length (loop variable)
5905
      if ((i_length + 4) < (min_tmp + 128))
5906
        i_length = i_length + 1;
5907
      else if ( ((i_length + 4) == (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
5908
        i_length = 256;
5909
      else if ( ((i_length + 4) > (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
5910
      begin
5911
        i_length = i_length + 128;
5912
        tmp_data = i_length + 4; // last tmp_data is ending length
5913
      end
5914
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
5915
        i_length = max_tmp - (4 + 16);
5916
      else if ((i_length + 4) >= (max_tmp - 16))
5917
        i_length = i_length + 1;
5918
      else
5919
      begin
5920
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
5921
        #10 $stop;
5922
      end
5923
      // the number of frame transmitted
5924
      num_of_frames = num_of_frames + 1;
5925
      if ((num_of_frames <= 8) || ((num_of_frames - 8) == 128))
5926
        num_of_bd = 0;
5927
      else
5928
        num_of_bd = num_of_bd + 1;
5929
    end
5930
    // disable TX
5931 274 tadejm
    wait (wbm_working == 0);
5932 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
5933
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5934
    @(posedge wb_clk);
5935
    if(fail == 0)
5936
      test_ok;
5937
    else
5938
      fail = 0;
5939
  end
5940
 
5941
 
5942
  ////////////////////////////////////////////////////////////////////
5943
  ////                                                            ////
5944
  ////  Test transmit packets form 0 to (MINFL - 1) sizes at      ////
5945
  ////  8 TX buffer decriptors ( 10Mbps ).                        ////
5946
  ////                                                            ////
5947
  ////////////////////////////////////////////////////////////////////
5948
  if (test_num == 6) // 
5949
  begin
5950
    // TEST 6: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )
5951
    test_name = "TEST 6: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )";
5952
    `TIME; $display("  TEST 6: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )");
5953
 
5954
    // reset MAC registers
5955
    hard_reset;
5956
    // reset MAC and MII LOGIC with soft reset
5957 274 tadejm
//    reset_mac;
5958
//    reset_mii;
5959 209 tadejm
    // set wb slave response
5960
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
5961
 
5962
    max_tmp = 0;
5963
    min_tmp = 0;
5964
    // set 8 TX buffer descriptors - must be set before TX enable
5965 274 tadejm
    wait (wbm_working == 0);
5966 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h8, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5967
    // enable TX, set full-duplex mode, padding and CRC appending
5968 274 tadejm
    wait (wbm_working == 0);
5969 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
5970
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5971
    // prepare two packets of MAXFL length
5972 274 tadejm
    wait (wbm_working == 0);
5973 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5974
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
5975
    min_tmp = tmp[31:16];
5976
    st_data = 8'h12;
5977
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
5978
    st_data = 8'h34;
5979
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp - 4), st_data); // length without CRC
5980
    // check WB INT signal
5981
    if (wb_int !== 1'b0)
5982
    begin
5983
      test_fail("WB INT signal should not be set");
5984
      fail = fail + 1;
5985
    end
5986
 
5987
    // write to phy's control register for 10Mbps
5988
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
5989
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
5990
    speed = 10;
5991
 
5992
    frame_started = 0;
5993
    num_of_frames = 0;
5994
    num_of_bd = 0;
5995
    i_length = 0; // 0;
5996
    while (i_length < 70) // (min_tmp - 4))
5997
    begin
5998
      #1;
5999
      // choose generating carrier sense and collision
6000
      case (i_length[1:0])
6001
      2'h0: // Interrupt is generated
6002
      begin
6003
        // Reset_tx_bd nable interrupt generation
6004
        // unmask interrupts
6005 274 tadejm
        wait (wbm_working == 0);
6006 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
6007
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6008
        // not detect carrier sense in FD and no collision
6009
        eth_phy.carrier_sense_tx_fd_detect(0);
6010
        eth_phy.collision(0);
6011
      end
6012
      2'h1: // Interrupt is not generated
6013
      begin
6014
        // set_tx_bd enable interrupt generation
6015
        // mask interrupts
6016 274 tadejm
        wait (wbm_working == 0);
6017 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6018
        // detect carrier sense in FD and no collision
6019
        eth_phy.carrier_sense_tx_fd_detect(1);
6020
        eth_phy.collision(0);
6021
      end
6022
      2'h2: // Interrupt is not generated
6023
      begin
6024
        // set_tx_bd disable the interrupt generation
6025
        // unmask interrupts
6026 274 tadejm
        wait (wbm_working == 0);
6027 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
6028
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6029
        // not detect carrier sense in FD and set collision
6030
        eth_phy.carrier_sense_tx_fd_detect(0);
6031
        eth_phy.collision(1);
6032
      end
6033
      default: // 2'h3: // Interrupt is not generated
6034
      begin
6035
        // set_tx_bd disable the interrupt generation
6036
        // mask interrupts
6037 274 tadejm
        wait (wbm_working == 0);
6038 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6039
        // detect carrier sense in FD and set collision
6040
        eth_phy.carrier_sense_tx_fd_detect(1);
6041
        eth_phy.collision(1);
6042
      end
6043
      endcase
6044
      #1;
6045
      // first destination address on ethernet PHY
6046
      eth_phy.set_tx_mem_addr(num_of_frames * 16);
6047
      // SET packets and wrap bit
6048
      // num_of_frames <= 9 => wrap set to TX BD 0
6049
      if (num_of_frames <= 9)
6050
      begin
6051
        tmp_len = i_length; // length of frame
6052
        tmp_bd_num = 0; // TX BD number
6053
        // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6054
        // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6055
        if (tmp_len[0] == 0)
6056
          set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6057
        else
6058
          set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6059
        // set wrap bit
6060
        set_tx_bd_wrap(0);
6061
      end
6062
      // 10 <= num_of_frames < 18 => wrap set to TX BD 3
6063
      else if ((num_of_frames == 10) || (num_of_frames == 14))
6064
      begin
6065
        tmp_len = i_length; // length of frame
6066
        tmp_bd_num = 0; // TX BD number
6067
        while (tmp_bd_num < 4) //
6068
        begin
6069
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6070
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6071
          if (tmp_len[0] == 0)
6072
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6073
          else
6074
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6075
          tmp_len = tmp_len + 1;
6076
          // set TX BD number
6077
          tmp_bd_num = tmp_bd_num + 1;
6078
        end
6079
        // set wrap bit
6080
        set_tx_bd_wrap(3);
6081
      end
6082
      // 18 <= num_of_frames < 28 => wrap set to TX BD 4
6083
      else if ((num_of_frames == 18) || (num_of_frames == 23))
6084
      begin
6085
        tmp_len = i_length; // length of frame
6086
        tmp_bd_num = 0; // TX BD number
6087
        while (tmp_bd_num < 5) //
6088
        begin
6089
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6090
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6091
          if (tmp_len[0] == 0)
6092
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6093
          else
6094
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6095
          tmp_len = tmp_len + 1;
6096
          // set TX BD number
6097
          tmp_bd_num = tmp_bd_num + 1;
6098
        end
6099
        // set wrap bit
6100
        set_tx_bd_wrap(4);
6101
      end
6102
      // 28 <= num_of_frames < 40 => wrap set to TX BD 5
6103
      else if ((num_of_frames == 28) || (num_of_frames == 34))
6104
      begin
6105
        tmp_len = i_length; // length of frame
6106
        tmp_bd_num = 0; // TX BD number
6107
        while (tmp_bd_num < 6) //
6108
        begin
6109
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6110
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6111
          if (tmp_len[0] == 0)
6112
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6113
          else
6114
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6115
          tmp_len = tmp_len + 1;
6116
          // set TX BD number
6117
          tmp_bd_num = tmp_bd_num + 1;
6118
        end
6119
        // set wrap bit
6120
        set_tx_bd_wrap(5);
6121
      end
6122
      // 40 <= num_of_frames < 54 => wrap set to TX BD 6
6123
      else if ((num_of_frames == 40) || (num_of_frames == 47))
6124
      begin
6125
        tmp_len = i_length; // length of frame
6126
        tmp_bd_num = 0; // TX BD number
6127
        while (tmp_bd_num < 7) //
6128
        begin
6129
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6130
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6131
          if (tmp_len[0] == 0)
6132
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6133
          else
6134
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6135
          tmp_len = tmp_len + 1;
6136
          // set TX BD number
6137
          tmp_bd_num = tmp_bd_num + 1;
6138
        end
6139
        // set wrap bit
6140
        set_tx_bd_wrap(6);
6141
      end
6142
      // 54 <= num_of_frames < 70 => wrap set to TX BD 7
6143
      else if ((num_of_frames == 54) || (num_of_frames == 62))
6144
      begin
6145
        tmp_len = i_length; // length of frame
6146
        tmp_bd_num = 0; // TX BD number
6147
        while (tmp_bd_num < 8) //
6148
        begin
6149
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6150
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6151
          if (tmp_len[0] == 0)
6152
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6153
          else
6154
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6155
          tmp_len = tmp_len + 1;
6156
          // set TX BD number
6157
          tmp_bd_num = tmp_bd_num + 1;
6158
        end
6159
        // set wrap bit
6160
        set_tx_bd_wrap(7);
6161
      end
6162
      #1;
6163
      // SET ready bit
6164
      if (num_of_frames < 10)
6165
        set_tx_bd_ready(0, 0);
6166
      else if (num_of_frames < 14)
6167
        set_tx_bd_ready((num_of_frames - 10), (num_of_frames - 10));
6168
      else if (num_of_frames < 18)
6169
        set_tx_bd_ready((num_of_frames - 14), (num_of_frames - 14));
6170
      else if (num_of_frames < 23)
6171
        set_tx_bd_ready((num_of_frames - 18), (num_of_frames - 18));
6172
      else if (num_of_frames < 28)
6173
        set_tx_bd_ready((num_of_frames - 23), (num_of_frames - 23));
6174
      else if (num_of_frames < 34)
6175
        set_tx_bd_ready((num_of_frames - 28), (num_of_frames - 28));
6176
      else if (num_of_frames < 40)
6177
        set_tx_bd_ready((num_of_frames - 34), (num_of_frames - 34));
6178
      else if (num_of_frames < 47)
6179
        set_tx_bd_ready((num_of_frames - 40), (num_of_frames - 40));
6180
      else if (num_of_frames < 54)
6181
        set_tx_bd_ready((num_of_frames - 47), (num_of_frames - 47));
6182
      else if (num_of_frames < 62)
6183
        set_tx_bd_ready((num_of_frames - 54), (num_of_frames - 54));
6184
      else if (num_of_frames < 70)
6185
        set_tx_bd_ready((num_of_frames - 62), (num_of_frames - 62));
6186
      // CHECK END OF TRANSMITION
6187
      frame_started = 0;
6188
      if (num_of_frames >= 5)
6189
        #1 check_tx_bd(num_of_bd, data);
6190
      fork
6191
      begin: fr_st
6192
        wait (MTxEn === 1'b1); // start transmit
6193
        frame_started = 1;
6194
      end
6195
      begin
6196
        repeat (30) @(posedge mtx_clk);
6197
        if (num_of_frames < 5)
6198
        begin
6199
          if (frame_started == 1)
6200
          begin
6201
            `TIME; $display("*E Frame should NOT start!");
6202
          end
6203
          disable fr_st;
6204
        end
6205
        else
6206
        begin
6207
          if (frame_started == 0)
6208
          begin
6209
            `TIME; $display("*W Frame should start!");
6210
            disable fr_st;
6211
          end
6212
        end
6213
      end
6214
      join
6215
      // check packets larger than 4 bytes
6216
      if (num_of_frames >= 5)
6217
      begin
6218
        wait (MTxEn === 1'b0); // end transmit
6219
        while (data[15] === 1)
6220
        begin
6221
          #1 check_tx_bd(num_of_bd, data);
6222
          @(posedge wb_clk);
6223
        end
6224
        repeat (1) @(posedge wb_clk);
6225
        // check length of a PACKET
6226
        if (i_length <= (min_tmp - 4))
6227
        begin
6228
          if (eth_phy.tx_len != min_tmp)
6229
          begin
6230
            test_fail("Wrong length of the packet out from MAC");
6231
            fail = fail + 1;
6232
          end
6233
        end
6234
        else
6235
        begin
6236
          if (eth_phy.tx_len != (i_length + 4))
6237
          begin
6238
            test_fail("Wrong length of the packet out from MAC");
6239
            fail = fail + 1;
6240
          end
6241
        end
6242
        // check transmitted TX packet data
6243
        if (i_length[0] == 0)
6244
        begin
6245
          #1 check_tx_packet(`MEMORY_BASE, (num_of_frames * 16), i_length, tmp);
6246
        end
6247
        else
6248
        begin
6249
          #1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
6250
        end
6251
        if (tmp > 0)
6252
        begin
6253
          test_fail("Wrong data of the transmitted packet");
6254
          fail = fail + 1;
6255
        end
6256
        // check transmited TX packet CRC
6257
        if (num_of_frames < (min_tmp - 4))
6258
          #1 check_tx_crc((num_of_frames * 16), (min_tmp - 4), 1'b0, tmp); // length without CRC
6259
        else
6260
          #1 check_tx_crc((num_of_frames * 16), i_length, 1'b0, tmp); // length without CRC
6261
        if (tmp > 0)
6262
        begin
6263
          test_fail("Wrong CRC of the transmitted packet");
6264
          fail = fail + 1;
6265
        end
6266
      end
6267
      // check WB INT signal
6268
      if ((i_length[1:0] == 2'h0) && (num_of_frames >= 5))
6269
      begin
6270
        if (wb_int !== 1'b1)
6271
        begin
6272
          `TIME; $display("*E WB INT signal should be set");
6273
          test_fail("WB INT signal should be set");
6274
          fail = fail + 1;
6275
        end
6276
      end
6277
      else
6278
      begin
6279
        if (wb_int !== 1'b0)
6280
        begin
6281
          `TIME; $display("*E WB INT signal should not be set");
6282
          test_fail("WB INT signal should not be set");
6283
          fail = fail + 1;
6284
        end
6285
      end
6286
      // check TX buffer descriptor of a packet
6287
      check_tx_bd(num_of_bd, data);
6288
      if (num_of_frames >= 5)
6289
      begin
6290
        if (i_length[1] == 1'b0) // interrupt enabled
6291
        begin
6292
          if ( (data[15:0] !== 16'h7800) && // wrap bit
6293
               (data[15:0] !== 16'h5800) ) // without wrap bit
6294
          begin
6295
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
6296
            test_fail("TX buffer descriptor status is not correct");
6297
            fail = fail + 1;
6298
          end
6299
        end
6300
        else // interrupt not enabled
6301
        begin
6302
          if ( (data[15:0] !== 16'h3800) && // wrap bit
6303
               (data[15:0] !== 16'h1800) ) // without wrap bit
6304
          begin
6305
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
6306
            test_fail("TX buffer descriptor status is not correct");
6307
            fail = fail + 1;
6308
          end
6309
        end
6310
      end
6311
      else
6312
      begin
6313
        if (data[15] !== 1'b1)
6314
        begin
6315
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
6316
          test_fail("TX buffer descriptor status is not correct");
6317
          fail = fail + 1;
6318
        end
6319
      end
6320
      // clear TX BD with wrap bit
6321
      if (num_of_frames == 63)
6322
        clear_tx_bd(16, 16);
6323
      // check interrupts
6324 274 tadejm
      wait (wbm_working == 0);
6325 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6326
      if ( ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1)) && (num_of_frames >= 5) )
6327
      begin
6328
        if ((data & `ETH_INT_TXB) !== 1'b1)
6329
        begin
6330
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
6331
          test_fail("Interrupt Transmit Buffer was not set");
6332
          fail = fail + 1;
6333
        end
6334
        if ((data & (~`ETH_INT_TXB)) !== 0)
6335
        begin
6336
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
6337
          test_fail("Other interrupts (except Transmit Buffer) were set");
6338
          fail = fail + 1;
6339
        end
6340
      end
6341
      else
6342
      begin
6343
        if (data !== 0)
6344
        begin
6345
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
6346
          test_fail("Any of interrupts (except Transmit Buffer) was set");
6347
          fail = fail + 1;
6348
        end
6349
      end
6350
      // clear interrupts
6351 274 tadejm
      wait (wbm_working == 0);
6352 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6353
      // check WB INT signal
6354
      if (wb_int !== 1'b0)
6355
      begin
6356
        test_fail("WB INT signal should not be set");
6357
        fail = fail + 1;
6358
      end
6359
      // INTERMEDIATE DISPLAYS
6360
      if (i_length == 3)
6361
      begin
6362
        $display("    pads appending to packets is selected");
6363
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
6364
        $display("    ->packets with lengths from %0d to %0d are not transmitted (length increasing by 1 byte)",
6365
                 0, 3);
6366
      end
6367
      else if (i_length == 9)
6368
      begin
6369
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
6370
        $display("    ->packet with length 4 is not transmitted (length increasing by 1 byte)");
6371
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6372
                 5, 9);
6373
      end
6374
      else if (i_length == 17)
6375
      begin
6376
        $display("    using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3)");
6377
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6378
                 10, 17);
6379
      end
6380
      else if (i_length == 27)
6381
      begin
6382
        $display("    using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4)");
6383
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6384
                 18, 27);
6385
      end
6386
      else if (i_length == 40)
6387
      begin
6388
        $display("    using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5)");
6389
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6390
                 28, 40);
6391
      end
6392
      else if (i_length == 54)
6393
      begin
6394
        $display("    using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6)");
6395
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6396
                 41, 54);
6397
      end
6398
      else if (i_length == 69)
6399
      begin
6400
        $display("    using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7)");
6401
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6402
                 55, 69);
6403
      end
6404
      // set length (loop variable)
6405
      i_length = i_length + 1;
6406
      // the number of frame transmitted
6407
      num_of_frames = num_of_frames + 1;
6408
      if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
6409
          (num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
6410
          (num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
6411
          (num_of_frames == 54) || (num_of_frames == 62))
6412
        num_of_bd = 0;
6413
      else
6414
        num_of_bd = num_of_bd + 1;
6415
    end
6416
    // disable TX
6417 274 tadejm
    wait (wbm_working == 0);
6418 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
6419
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6420
    @(posedge wb_clk);
6421
    if(fail == 0)
6422
      test_ok;
6423
    else
6424
      fail = 0;
6425
  end
6426
 
6427
 
6428
  ////////////////////////////////////////////////////////////////////
6429
  ////                                                            ////
6430
  ////  Test transmit packets form 0 to (MINFL - 1) sizes at      ////
6431
  ////  8 TX buffer decriptors ( 100Mbps ).                       ////
6432
  ////                                                            ////
6433
  ////////////////////////////////////////////////////////////////////
6434
  if (test_num == 7) // 
6435
  begin
6436
    // TEST 7: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )
6437
    test_name = "TEST 7: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )";
6438
    `TIME; $display("  TEST 7: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )");
6439
 
6440
    // reset MAC registers
6441
    hard_reset;
6442
    // reset MAC and MII LOGIC with soft reset
6443 274 tadejm
//    reset_mac;
6444
//    reset_mii;
6445 209 tadejm
    // set wb slave response
6446
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
6447
 
6448
    max_tmp = 0;
6449
    min_tmp = 0;
6450
    // set 8 TX buffer descriptors - must be set before TX enable
6451 274 tadejm
    wait (wbm_working == 0);
6452 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h8, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6453
    // enable TX, set full-duplex mode, padding and CRC appending
6454 274 tadejm
    wait (wbm_working == 0);
6455 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
6456
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6457
    // prepare two packets of MAXFL length
6458 274 tadejm
    wait (wbm_working == 0);
6459 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6460
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
6461
    min_tmp = tmp[31:16];
6462
    st_data = 8'h12;
6463
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
6464
    st_data = 8'h34;
6465
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp - 4), st_data); // length without CRC
6466
    // check WB INT signal
6467
    if (wb_int !== 1'b0)
6468
    begin
6469
      test_fail("WB INT signal should not be set");
6470
      fail = fail + 1;
6471
    end
6472
 
6473
    // write to phy's control register for 100Mbps
6474
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
6475
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
6476
    speed = 100;
6477
 
6478
    frame_started = 0;
6479
    num_of_frames = 0;
6480
    num_of_bd = 0;
6481
    i_length = 0; // 0;
6482
    while (i_length < 70) // (min_tmp - 4))
6483
    begin
6484
      #1;
6485
      // choose generating carrier sense and collision
6486
      case (i_length[1:0])
6487
      2'h0: // Interrupt is generated
6488
      begin
6489
        // Reset_tx_bd nable interrupt generation
6490
        // unmask interrupts
6491 274 tadejm
        wait (wbm_working == 0);
6492 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
6493
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6494
        // not detect carrier sense in FD and no collision
6495
        eth_phy.carrier_sense_tx_fd_detect(0);
6496
        eth_phy.collision(0);
6497
      end
6498
      2'h1: // Interrupt is not generated
6499
      begin
6500
        // set_tx_bd enable interrupt generation
6501
        // mask interrupts
6502 274 tadejm
        wait (wbm_working == 0);
6503 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6504
        // detect carrier sense in FD and no collision
6505
        eth_phy.carrier_sense_tx_fd_detect(1);
6506
        eth_phy.collision(0);
6507
      end
6508
      2'h2: // Interrupt is not generated
6509
      begin
6510
        // set_tx_bd disable the interrupt generation
6511
        // unmask interrupts
6512 274 tadejm
        wait (wbm_working == 0);
6513 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
6514
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6515
        // not detect carrier sense in FD and set collision
6516
        eth_phy.carrier_sense_tx_fd_detect(0);
6517
        eth_phy.collision(1);
6518
      end
6519
      default: // 2'h3: // Interrupt is not generated
6520
      begin
6521
        // set_tx_bd disable the interrupt generation
6522
        // mask interrupts
6523 274 tadejm
        wait (wbm_working == 0);
6524 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6525
        // detect carrier sense in FD and set collision
6526
        eth_phy.carrier_sense_tx_fd_detect(1);
6527
        eth_phy.collision(1);
6528
      end
6529
      endcase
6530
      #1;
6531
      // first destination address on ethernet PHY
6532
      eth_phy.set_tx_mem_addr(num_of_frames * 16);
6533
      // SET packets and wrap bit
6534
      // num_of_frames <= 9 => wrap set to TX BD 0
6535
      if (num_of_frames <= 9)
6536
      begin
6537
        tmp_len = i_length; // length of frame
6538
        tmp_bd_num = 0; // TX BD number
6539
        // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6540
        // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6541
        if (tmp_len[0] == 0)
6542
          set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6543
        else
6544
          set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6545
        // set wrap bit
6546
        set_tx_bd_wrap(0);
6547
      end
6548
      // 10 <= num_of_frames < 18 => wrap set to TX BD 3
6549
      else if ((num_of_frames == 10) || (num_of_frames == 14))
6550
      begin
6551
        tmp_len = i_length; // length of frame
6552
        tmp_bd_num = 0; // TX BD number
6553
        while (tmp_bd_num < 4) //
6554
        begin
6555
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6556
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6557
          if (tmp_len[0] == 0)
6558
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6559
          else
6560
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6561
          tmp_len = tmp_len + 1;
6562
          // set TX BD number
6563
          tmp_bd_num = tmp_bd_num + 1;
6564
        end
6565
        // set wrap bit
6566
        set_tx_bd_wrap(3);
6567
      end
6568
      // 18 <= num_of_frames < 28 => wrap set to TX BD 4
6569
      else if ((num_of_frames == 18) || (num_of_frames == 23))
6570
      begin
6571
        tmp_len = i_length; // length of frame
6572
        tmp_bd_num = 0; // TX BD number
6573
        while (tmp_bd_num < 5) //
6574
        begin
6575
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6576
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6577
          if (tmp_len[0] == 0)
6578
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6579
          else
6580
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6581
          tmp_len = tmp_len + 1;
6582
          // set TX BD number
6583
          tmp_bd_num = tmp_bd_num + 1;
6584
        end
6585
        // set wrap bit
6586
        set_tx_bd_wrap(4);
6587
      end
6588
      // 28 <= num_of_frames < 40 => wrap set to TX BD 5
6589
      else if ((num_of_frames == 28) || (num_of_frames == 34))
6590
      begin
6591
        tmp_len = i_length; // length of frame
6592
        tmp_bd_num = 0; // TX BD number
6593
        while (tmp_bd_num < 6) //
6594
        begin
6595
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6596
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6597
          if (tmp_len[0] == 0)
6598
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6599
          else
6600
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6601
          tmp_len = tmp_len + 1;
6602
          // set TX BD number
6603
          tmp_bd_num = tmp_bd_num + 1;
6604
        end
6605
        // set wrap bit
6606
        set_tx_bd_wrap(5);
6607
      end
6608
      // 40 <= num_of_frames < 54 => wrap set to TX BD 6
6609
      else if ((num_of_frames == 40) || (num_of_frames == 47))
6610
      begin
6611
        tmp_len = i_length; // length of frame
6612
        tmp_bd_num = 0; // TX BD number
6613
        while (tmp_bd_num < 7) //
6614
        begin
6615
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6616
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6617
          if (tmp_len[0] == 0)
6618
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6619
          else
6620
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6621
          tmp_len = tmp_len + 1;
6622
          // set TX BD number
6623
          tmp_bd_num = tmp_bd_num + 1;
6624
        end
6625
        // set wrap bit
6626
        set_tx_bd_wrap(6);
6627
      end
6628
      // 54 <= num_of_frames < 70 => wrap set to TX BD 7
6629
      else if ((num_of_frames == 54) || (num_of_frames == 62))
6630
      begin
6631
        tmp_len = i_length; // length of frame
6632
        tmp_bd_num = 0; // TX BD number
6633
        while (tmp_bd_num < 8) //
6634
        begin
6635
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6636
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6637
          if (tmp_len[0] == 0)
6638
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6639
          else
6640
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6641
          tmp_len = tmp_len + 1;
6642
          // set TX BD number
6643
          tmp_bd_num = tmp_bd_num + 1;
6644
        end
6645
        // set wrap bit
6646
        set_tx_bd_wrap(7);
6647
      end
6648
      #1;
6649
      // SET ready bit
6650
      if (num_of_frames < 10)
6651
        set_tx_bd_ready(0, 0);
6652
      else if (num_of_frames < 14)
6653
        set_tx_bd_ready((num_of_frames - 10), (num_of_frames - 10));
6654
      else if (num_of_frames < 18)
6655
        set_tx_bd_ready((num_of_frames - 14), (num_of_frames - 14));
6656
      else if (num_of_frames < 23)
6657
        set_tx_bd_ready((num_of_frames - 18), (num_of_frames - 18));
6658
      else if (num_of_frames < 28)
6659
        set_tx_bd_ready((num_of_frames - 23), (num_of_frames - 23));
6660
      else if (num_of_frames < 34)
6661
        set_tx_bd_ready((num_of_frames - 28), (num_of_frames - 28));
6662
      else if (num_of_frames < 40)
6663
        set_tx_bd_ready((num_of_frames - 34), (num_of_frames - 34));
6664
      else if (num_of_frames < 47)
6665
        set_tx_bd_ready((num_of_frames - 40), (num_of_frames - 40));
6666
      else if (num_of_frames < 54)
6667
        set_tx_bd_ready((num_of_frames - 47), (num_of_frames - 47));
6668
      else if (num_of_frames < 62)
6669
        set_tx_bd_ready((num_of_frames - 54), (num_of_frames - 54));
6670
      else if (num_of_frames < 70)
6671
        set_tx_bd_ready((num_of_frames - 62), (num_of_frames - 62));
6672
      // CHECK END OF TRANSMITION
6673
      frame_started = 0;
6674
      if (num_of_frames >= 5)
6675
        #1 check_tx_bd(num_of_bd, data);
6676
      fork
6677
      begin: fr_st1
6678
        wait (MTxEn === 1'b1); // start transmit
6679
        frame_started = 1;
6680
      end
6681
      begin
6682 279 mohor
        repeat (50) @(posedge mtx_clk);     // Increased from 30 to 50
6683 209 tadejm
        if (num_of_frames < 5)
6684
        begin
6685
          if (frame_started == 1)
6686
          begin
6687
            `TIME; $display("*E Frame should NOT start!");
6688
          end
6689
          disable fr_st1;
6690
        end
6691
        else
6692
        begin
6693
          if (frame_started == 0)
6694
          begin
6695
            `TIME; $display("*W Frame should start!");
6696
            disable fr_st1;
6697
          end
6698
        end
6699
      end
6700
      join
6701
      // check packets larger than 4 bytes
6702
      if (num_of_frames >= 5)
6703
      begin
6704
        wait (MTxEn === 1'b0); // end transmit
6705
        while (data[15] === 1)
6706
        begin
6707
          #1 check_tx_bd(num_of_bd, data);
6708
          @(posedge wb_clk);
6709
        end
6710
        repeat (1) @(posedge wb_clk);
6711
        // check length of a PACKET
6712
        if (i_length <= (min_tmp - 4))
6713
        begin
6714
          if (eth_phy.tx_len != min_tmp)
6715
          begin
6716
            test_fail("Wrong length of the packet out from MAC");
6717
            fail = fail + 1;
6718
          end
6719
        end
6720
        else
6721
        begin
6722
          if (eth_phy.tx_len != (i_length + 4))
6723
          begin
6724
            test_fail("Wrong length of the packet out from MAC");
6725
            fail = fail + 1;
6726
          end
6727
        end
6728
        // check transmitted TX packet data
6729
        if (i_length[0] == 0)
6730
        begin
6731
          #1 check_tx_packet(`MEMORY_BASE, (num_of_frames * 16), i_length, tmp);
6732
        end
6733
        else
6734
        begin
6735
          #1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
6736
        end
6737
        if (tmp > 0)
6738
        begin
6739
          test_fail("Wrong data of the transmitted packet");
6740
          fail = fail + 1;
6741
        end
6742
        // check transmited TX packet CRC
6743
        if (num_of_frames < (min_tmp - 4))
6744
          #1 check_tx_crc((num_of_frames * 16), (min_tmp - 4), 1'b0, tmp); // length without CRC
6745
        else
6746
          #1 check_tx_crc((num_of_frames * 16), i_length, 1'b0, tmp); // length without CRC
6747
        if (tmp > 0)
6748
        begin
6749
          test_fail("Wrong CRC of the transmitted packet");
6750
          fail = fail + 1;
6751
        end
6752
      end
6753
      // check WB INT signal
6754
      if ((i_length[1:0] == 2'h0) && (num_of_frames >= 5))
6755
      begin
6756
        if (wb_int !== 1'b1)
6757
        begin
6758
          `TIME; $display("*E WB INT signal should be set");
6759
          test_fail("WB INT signal should be set");
6760
          fail = fail + 1;
6761
        end
6762
      end
6763
      else
6764
      begin
6765
        if (wb_int !== 1'b0)
6766
        begin
6767
          `TIME; $display("*E WB INT signal should not be set");
6768
          test_fail("WB INT signal should not be set");
6769
          fail = fail + 1;
6770
        end
6771
      end
6772
      // check TX buffer descriptor of a packet
6773
      check_tx_bd(num_of_bd, data);
6774
      if (num_of_frames >= 5)
6775
      begin
6776
        if (i_length[1] == 1'b0) // interrupt enabled
6777
        begin
6778
          if ( (data[15:0] !== 16'h7800) && // wrap bit
6779
               (data[15:0] !== 16'h5800) ) // without wrap bit
6780
          begin
6781
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
6782
            test_fail("TX buffer descriptor status is not correct");
6783
            fail = fail + 1;
6784
          end
6785
        end
6786
        else // interrupt not enabled
6787
        begin
6788
          if ( (data[15:0] !== 16'h3800) && // wrap bit
6789
               (data[15:0] !== 16'h1800) ) // without wrap bit
6790
          begin
6791
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
6792
            test_fail("TX buffer descriptor status is not correct");
6793
            fail = fail + 1;
6794
          end
6795
        end
6796
      end
6797
      else
6798
      begin
6799
        if (data[15] !== 1'b1)
6800
        begin
6801
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
6802
          test_fail("TX buffer descriptor status is not correct");
6803
          fail = fail + 1;
6804
        end
6805
      end
6806
      // clear TX BD with wrap bit
6807
      if (num_of_frames == 63)
6808
        clear_tx_bd(16, 16);
6809
      // check interrupts
6810 274 tadejm
      wait (wbm_working == 0);
6811 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6812
      if ( ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1)) && (num_of_frames >= 5) )
6813
      begin
6814
        if ((data & `ETH_INT_TXB) !== 1'b1)
6815
        begin
6816
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
6817
          test_fail("Interrupt Transmit Buffer was not set");
6818
          fail = fail + 1;
6819
        end
6820
        if ((data & (~`ETH_INT_TXB)) !== 0)
6821
        begin
6822
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
6823
          test_fail("Other interrupts (except Transmit Buffer) were set");
6824
          fail = fail + 1;
6825
        end
6826
      end
6827
      else
6828
      begin
6829
        if (data !== 0)
6830
        begin
6831
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
6832
          test_fail("Any of interrupts (except Transmit Buffer) was set");
6833
          fail = fail + 1;
6834
        end
6835
      end
6836
      // clear interrupts
6837 274 tadejm
      wait (wbm_working == 0);
6838 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6839
      // check WB INT signal
6840
      if (wb_int !== 1'b0)
6841
      begin
6842
        test_fail("WB INT signal should not be set");
6843
        fail = fail + 1;
6844
      end
6845
      // INTERMEDIATE DISPLAYS
6846
      if (i_length == 3)
6847
      begin
6848
        $display("    pads appending to packets is selected");
6849
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
6850
        $display("    ->packets with lengths from %0d to %0d are not transmitted (length increasing by 1 byte)",
6851
                 0, 3);
6852
      end
6853
      else if (i_length == 9)
6854
      begin
6855
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
6856
        $display("    ->packet with length 4 is not transmitted (length increasing by 1 byte)");
6857
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6858
                 5, 9);
6859
      end
6860
      else if (i_length == 17)
6861
      begin
6862
        $display("    using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3)");
6863
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6864
                 10, 17);
6865
      end
6866
      else if (i_length == 27)
6867
      begin
6868
        $display("    using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4)");
6869
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6870
                 18, 27);
6871
      end
6872
      else if (i_length == 40)
6873
      begin
6874
        $display("    using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5)");
6875
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6876
                 28, 40);
6877
      end
6878
      else if (i_length == 54)
6879
      begin
6880
        $display("    using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6)");
6881
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6882
                 41, 54);
6883
      end
6884
      else if (i_length == 69)
6885
      begin
6886
        $display("    using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7)");
6887
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6888
                 55, 69);
6889
      end
6890
      // set length (loop variable)
6891
      i_length = i_length + 1;
6892
      // the number of frame transmitted
6893
      num_of_frames = num_of_frames + 1;
6894
      if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
6895
          (num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
6896
          (num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
6897
          (num_of_frames == 54) || (num_of_frames == 62))
6898
        num_of_bd = 0;
6899
      else
6900
        num_of_bd = num_of_bd + 1;
6901
    end
6902
    // disable TX
6903
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
6904
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6905
    @(posedge wb_clk);
6906
    if(fail == 0)
6907
      test_ok;
6908
    else
6909
      fail = 0;
6910
  end
6911
 
6912
 
6913
  ////////////////////////////////////////////////////////////////////
6914
  ////                                                            ////
6915 243 tadejm
  ////  Test transmit packets (no pads) from 0 to (MINFL - 1)     ////
6916 209 tadejm
  ////  sizes at 8 TX buffer decriptors ( 10Mbps ).               ////
6917
  ////                                                            ////
6918
  ////////////////////////////////////////////////////////////////////
6919
  if (test_num == 8) // 
6920
  begin
6921 243 tadejm
    // TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )
6922
    test_name = "TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )";
6923
    `TIME; $display("  TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )");
6924 279 mohor
 
6925 209 tadejm
    // reset MAC registers
6926
    hard_reset;
6927
    // reset MAC and MII LOGIC with soft reset
6928 274 tadejm
//    reset_mac;
6929
//    reset_mii;
6930 209 tadejm
    // set wb slave response
6931
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
6932
 
6933
    max_tmp = 0;
6934
    min_tmp = 0;
6935
    // set 8 TX buffer descriptors - must be set before TX enable
6936 274 tadejm
    wait (wbm_working == 0);
6937 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h8, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6938
    // enable TX, set full-duplex mode, padding and CRC appending
6939 274 tadejm
    wait (wbm_working == 0);
6940 243 tadejm
//    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
6941
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD,
6942 209 tadejm
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6943
    // prepare two packets of MAXFL length
6944 274 tadejm
    wait (wbm_working == 0);
6945 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6946
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
6947
    min_tmp = tmp[31:16];
6948
    st_data = 8'h12;
6949
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
6950
    st_data = 8'h34;
6951
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp - 4), st_data); // length without CRC
6952
    // check WB INT signal
6953
    if (wb_int !== 1'b0)
6954
    begin
6955
      test_fail("WB INT signal should not be set");
6956
      fail = fail + 1;
6957
    end
6958
 
6959
    // write to phy's control register for 10Mbps
6960
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
6961
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
6962
    speed = 10;
6963
 
6964
    frame_started = 0;
6965
    num_of_frames = 0;
6966
    num_of_bd = 0;
6967
    i_length = 0; // 0;
6968
    while (i_length < 70) // (min_tmp - 4))
6969
    begin
6970
      #1;
6971
      // choose generating carrier sense and collision
6972
      case (i_length[1:0])
6973
      2'h0: // Interrupt is generated
6974
      begin
6975
        // Reset_tx_bd nable interrupt generation
6976
        // unmask interrupts
6977 274 tadejm
        wait (wbm_working == 0);
6978 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
6979
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6980
        // not detect carrier sense in FD and no collision
6981
        eth_phy.carrier_sense_tx_fd_detect(0);
6982
        eth_phy.collision(0);
6983
      end
6984
      2'h1: // Interrupt is not generated
6985
      begin
6986
        // set_tx_bd enable interrupt generation
6987
        // mask interrupts
6988 274 tadejm
        wait (wbm_working == 0);
6989 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6990
        // detect carrier sense in FD and no collision
6991
        eth_phy.carrier_sense_tx_fd_detect(1);
6992
        eth_phy.collision(0);
6993
      end
6994
      2'h2: // Interrupt is not generated
6995
      begin
6996
        // set_tx_bd disable the interrupt generation
6997
        // unmask interrupts
6998 274 tadejm
        wait (wbm_working == 0);
6999 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
7000
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7001
        // not detect carrier sense in FD and set collision
7002
        eth_phy.carrier_sense_tx_fd_detect(0);
7003
        eth_phy.collision(1);
7004
      end
7005
      default: // 2'h3: // Interrupt is not generated
7006
      begin
7007
        // set_tx_bd disable the interrupt generation
7008
        // mask interrupts
7009 274 tadejm
        wait (wbm_working == 0);
7010 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7011
        // detect carrier sense in FD and set collision
7012
        eth_phy.carrier_sense_tx_fd_detect(1);
7013
        eth_phy.collision(1);
7014
      end
7015
      endcase
7016 243 tadejm
//      // append CRC
7017
//      if ((i_length[0] == 1'b0) && (num_of_frames >= 6))
7018
//      begin
7019
//        append_tx_crc(`MEMORY_BASE, i_length, 1'b0);
7020
//      end
7021 209 tadejm
      #1;
7022
      // first destination address on ethernet PHY
7023
      eth_phy.set_tx_mem_addr(num_of_frames * 16);
7024
      // SET packets and wrap bit
7025
      // num_of_frames <= 9 => wrap set to TX BD 0
7026 243 tadejm
      if (num_of_frames <= 5)
7027
        begin
7028
          tmp_len = i_length; // length of frame
7029
          tmp_bd_num = 0; // TX BD number
7030
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7031
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7032 274 tadejm
 
7033 243 tadejm
          if (tmp_len[0] == 0) // CRC appended by 'HARDWARE'
7034 279 mohor
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, `MEMORY_BASE);
7035 243 tadejm
          else
7036 279 mohor
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
7037 243 tadejm
          // set wrap bit
7038
          set_tx_bd_wrap(0);
7039
        end
7040
        else if (num_of_frames <= 9)
7041
        begin
7042
          tmp_len = i_length; // length of frame
7043
          tmp_bd_num = 0; // TX BD number
7044
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7045
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7046
          if (tmp_len[0] == 0) // CRC appended by 'SOFTWARE'
7047 279 mohor
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
7048 243 tadejm
          else
7049
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
7050
          // set wrap bit
7051
          set_tx_bd_wrap(0);
7052 279 mohor
        end
7053
        // 10 <= num_of_frames < 18 => wrap set to TX BD 3
7054
        else if ((num_of_frames == 10) || (num_of_frames == 14))
7055 209 tadejm
        begin
7056 279 mohor
          tmp_len = i_length; // length of frame
7057
          tmp_bd_num = 0; // TX BD number
7058
          while (tmp_bd_num < 4)
7059
          begin
7060
            // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7061
            // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7062
            if (tmp_len[0] == 0)
7063
              set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
7064
            else
7065
              set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
7066
            tmp_len = tmp_len + 1;
7067
            // set TX BD number
7068
            tmp_bd_num = tmp_bd_num + 1;
7069
          end
7070
          // set wrap bit
7071
          set_tx_bd_wrap(3);
7072 209 tadejm
        end
7073
      // 18 <= num_of_frames < 28 => wrap set to TX BD 4
7074
      else if ((num_of_frames == 18) || (num_of_frames == 23))
7075
      begin
7076
        tmp_len = i_length; // length of frame
7077
        tmp_bd_num = 0; // TX BD number
7078
        while (tmp_bd_num < 5) //
7079
        begin
7080
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7081
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7082
          if (tmp_len[0] == 0)
7083 279 mohor
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
7084 243 tadejm
          else // when (num_of_frames == 23), (i_length == 23) and therefor i_length[0] == 1 !!!
7085
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1],
7086
                      ((num_of_frames == 23) && (tmp_bd_num == 0)), 1'b1, (`MEMORY_BASE + max_tmp));
7087 279 mohor
 
7088 209 tadejm
          tmp_len = tmp_len + 1;
7089
          // set TX BD number
7090
          tmp_bd_num = tmp_bd_num + 1;
7091
        end
7092
        // set wrap bit
7093
        set_tx_bd_wrap(4);
7094
      end
7095
      // 28 <= num_of_frames < 40 => wrap set to TX BD 5
7096
      else if ((num_of_frames == 28) || (num_of_frames == 34))
7097
      begin
7098
        tmp_len = i_length; // length of frame
7099
        tmp_bd_num = 0; // TX BD number
7100
        while (tmp_bd_num < 6) //
7101
        begin
7102
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7103
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7104
          if (tmp_len[0] == 0)
7105 279 mohor
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
7106 209 tadejm
          else
7107 243 tadejm
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
7108 209 tadejm
          tmp_len = tmp_len + 1;
7109
          // set TX BD number
7110
          tmp_bd_num = tmp_bd_num + 1;
7111
        end
7112
        // set wrap bit
7113
        set_tx_bd_wrap(5);
7114
      end
7115
      // 40 <= num_of_frames < 54 => wrap set to TX BD 6
7116
      else if ((num_of_frames == 40) || (num_of_frames == 47))
7117
      begin
7118
        tmp_len = i_length; // length of frame
7119
        tmp_bd_num = 0; // TX BD number
7120
        while (tmp_bd_num < 7) //
7121
        begin
7122
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7123
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7124
          if (tmp_len[0] == 0)
7125 279 mohor
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
7126 209 tadejm
          else
7127 243 tadejm
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
7128 209 tadejm
          tmp_len = tmp_len + 1;
7129
          // set TX BD number
7130
          tmp_bd_num = tmp_bd_num + 1;
7131
        end
7132
        // set wrap bit
7133
        set_tx_bd_wrap(6);
7134
      end
7135
      // 54 <= num_of_frames < 70 => wrap set to TX BD 7
7136
      else if ((num_of_frames == 54) || (num_of_frames == 62))
7137
      begin
7138
        tmp_len = i_length; // length of frame
7139
        tmp_bd_num = 0; // TX BD number
7140
        while (tmp_bd_num < 8) //
7141
        begin
7142
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7143
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7144
          if (tmp_len[0] == 0)
7145 279 mohor
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
7146 209 tadejm
          else
7147 243 tadejm
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
7148 209 tadejm
          tmp_len = tmp_len + 1;
7149
          // set TX BD number
7150
          tmp_bd_num = tmp_bd_num + 1;
7151
        end
7152
        // set wrap bit
7153
        set_tx_bd_wrap(7);
7154
      end
7155
      #1;
7156
      // SET ready bit
7157
      if (num_of_frames < 10)
7158
        set_tx_bd_ready(0, 0);
7159
      else if (num_of_frames < 14)
7160
        set_tx_bd_ready((num_of_frames - 10), (num_of_frames - 10));
7161
      else if (num_of_frames < 18)
7162
        set_tx_bd_ready((num_of_frames - 14), (num_of_frames - 14));
7163
      else if (num_of_frames < 23)
7164
        set_tx_bd_ready((num_of_frames - 18), (num_of_frames - 18));
7165
      else if (num_of_frames < 28)
7166
        set_tx_bd_ready((num_of_frames - 23), (num_of_frames - 23));
7167
      else if (num_of_frames < 34)
7168
        set_tx_bd_ready((num_of_frames - 28), (num_of_frames - 28));
7169
      else if (num_of_frames < 40)
7170
        set_tx_bd_ready((num_of_frames - 34), (num_of_frames - 34));
7171
      else if (num_of_frames < 47)
7172
        set_tx_bd_ready((num_of_frames - 40), (num_of_frames - 40));
7173
      else if (num_of_frames < 54)
7174
        set_tx_bd_ready((num_of_frames - 47), (num_of_frames - 47));
7175
      else if (num_of_frames < 62)
7176
        set_tx_bd_ready((num_of_frames - 54), (num_of_frames - 54));
7177
      else if (num_of_frames < 70)
7178
        set_tx_bd_ready((num_of_frames - 62), (num_of_frames - 62));
7179
      // CHECK END OF TRANSMITION
7180
      frame_started = 0;
7181
      if (num_of_frames >= 5)
7182
        #1 check_tx_bd(num_of_bd, data);
7183
      fork
7184
      begin: fr_st2
7185
        wait (MTxEn === 1'b1); // start transmit
7186
        frame_started = 1;
7187
      end
7188
      begin
7189
        repeat (30) @(posedge mtx_clk);
7190
        if (num_of_frames < 5)
7191
        begin
7192
          if (frame_started == 1)
7193
          begin
7194
            `TIME; $display("*E Frame should NOT start!");
7195
          end
7196
          disable fr_st2;
7197
        end
7198
        else
7199
        begin
7200
          if (frame_started == 0)
7201
          begin
7202
            `TIME; $display("*W Frame should start!");
7203
            disable fr_st2;
7204
          end
7205
        end
7206
      end
7207
      join
7208 279 mohor
 
7209
 
7210 209 tadejm
      // check packets larger than 4 bytes
7211
      if (num_of_frames >= 5)
7212
      begin
7213
        wait (MTxEn === 1'b0); // end transmit
7214
        while (data[15] === 1)
7215
        begin
7216
          #1 check_tx_bd(num_of_bd, data);
7217
          @(posedge wb_clk);
7218
        end
7219
        repeat (1) @(posedge wb_clk);
7220 274 tadejm
 
7221
 
7222 279 mohor
        // check length of a PACKET     // Check this if it is OK igor
7223
        if (num_of_frames < 6)
7224
          begin
7225
            if (eth_phy.tx_len != (i_length + 4))
7226
              begin
7227
                `TIME; $display("*E Wrong length of the packet out from MAC");
7228
                test_fail("Wrong length of the packet out from MAC");
7229
                fail = fail + 1;
7230
              end
7231
          end
7232
        else if (num_of_frames != 23) // 6 - 53 except 23
7233
          begin
7234
            if (i_length[0] == 1'b0)
7235
              begin
7236
                if (eth_phy.tx_len != i_length)
7237
                  begin
7238
                    `TIME; $display("*E Wrong length of the packet out from MAC");
7239
                    test_fail("Wrong length of the packet out from MAC");
7240
                    fail = fail + 1;
7241
                  end
7242
              end
7243
            else
7244
              begin
7245
                if (eth_phy.tx_len != (i_length + 4))
7246
                  begin
7247
                    `TIME; $display("*E Wrong length of the packet out from MAC");
7248
                    test_fail("Wrong length of the packet out from MAC");
7249
                    fail = fail + 1;
7250
                  end
7251
              end
7252
          end
7253
        else // num_of_frames == 23
7254
          begin
7255
            if (data[12]) // Padding
7256
              begin
7257
                if (eth_phy.tx_len != (64))
7258
                  begin
7259
                    `TIME; $display("*E Wrong length of the packet out from MAC");
7260
                    test_fail("Wrong length of the packet out from MAC");
7261
                    fail = fail + 1;
7262
                  end
7263
              end
7264
            else
7265
              begin
7266
                if (eth_phy.tx_len != (i_length + 4))
7267
                  begin
7268
                    `TIME; $display("*E Wrong length of the packet out from MAC");
7269
                    test_fail("Wrong length of the packet out from MAC");
7270
                    fail = fail + 1;
7271
                  end
7272
              end
7273
          end
7274
 
7275 209 tadejm
        // check transmitted TX packet data
7276
        if (i_length[0] == 0)
7277
        begin
7278
          #1 check_tx_packet(`MEMORY_BASE, (num_of_frames * 16), i_length, tmp);
7279
        end
7280 243 tadejm
        else if (num_of_frames == 23) // i_length[0] == 1 here
7281
        begin
7282 279 mohor
          #1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
7283
          #1 check_tx_packet( 0, (num_of_frames * 16 + i_length), (min_tmp - i_length - 4), tmp);
7284 243 tadejm
        end
7285 209 tadejm
        else
7286
        begin
7287
          #1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
7288
        end
7289
        if (tmp > 0)
7290
        begin
7291
          test_fail("Wrong data of the transmitted packet");
7292
          fail = fail + 1;
7293
        end
7294
        // check transmited TX packet CRC
7295 243 tadejm
        #1;
7296
        if ((i_length[0] == 1'b0) && (num_of_frames >= 6))
7297
        begin
7298
        end
7299
        else
7300
          check_tx_crc((num_of_frames * 16), (eth_phy.tx_len - 4), 1'b0, tmp); // length without CRC
7301 209 tadejm
        if (tmp > 0)
7302
        begin
7303
          test_fail("Wrong CRC of the transmitted packet");
7304
          fail = fail + 1;
7305
        end
7306
      end
7307
      // check WB INT signal
7308
      if ((i_length[1:0] == 2'h0) && (num_of_frames >= 5))
7309
      begin
7310
        if (wb_int !== 1'b1)
7311
        begin
7312
          `TIME; $display("*E WB INT signal should be set");
7313
          test_fail("WB INT signal should be set");
7314
          fail = fail + 1;
7315
        end
7316
      end
7317
      else
7318
      begin
7319
        if (wb_int !== 1'b0)
7320
        begin
7321
          `TIME; $display("*E WB INT signal should not be set");
7322
          test_fail("WB INT signal should not be set");
7323
          fail = fail + 1;
7324
        end
7325
      end
7326
      // check TX buffer descriptor of a packet
7327
      check_tx_bd(num_of_bd, data);
7328 279 mohor
 
7329 209 tadejm
      if (num_of_frames >= 5)
7330
      begin
7331 243 tadejm
        if ((i_length[1] == 1'b0) && (i_length[0] == 1'b0)) // interrupt enabled
7332 209 tadejm
        begin
7333 243 tadejm
          if ( (data[15:0] !== 16'h6000) &&  // wrap bit
7334
               (data[15:0] !== 16'h4000) )  // without wrap bit
7335 209 tadejm
          begin
7336 279 mohor
            `TIME; $display("*E TX buffer descriptor status is not correct 1: %0h", data[15:0]);
7337 209 tadejm
            test_fail("TX buffer descriptor status is not correct");
7338
            fail = fail + 1;
7339
          end
7340
        end
7341 243 tadejm
        else if ((i_length[1] == 1'b1) && (i_length[0] == 1'b0)) // interrupt not enabled
7342 209 tadejm
        begin
7343 243 tadejm
          if ( (data[15:0] !== 16'h2000) && // wrap bit
7344
               (data[15:0] !== 16'h0000) ) // without wrap bit
7345
          begin
7346 279 mohor
            `TIME; $display("*E TX buffer descriptor status is not correct 2: %0h", data[15:0]);
7347 243 tadejm
            test_fail("TX buffer descriptor status is not correct");
7348
            fail = fail + 1;
7349
          end
7350
        end
7351
        else if ((i_length[1] == 1'b0) && (i_length[0] == 1'b1)) // interrupt enabled
7352
        begin
7353
          if ( (data[15:0] !== 16'h6800) && // wrap bit
7354
               (data[15:0] !== 16'h4800) ) // without wrap bit
7355
          begin
7356 279 mohor
            `TIME; $display("*E TX buffer descriptor status is not correct 3: %0h", data[15:0]);
7357 243 tadejm
            test_fail("TX buffer descriptor status is not correct");
7358
            fail = fail + 1;
7359
          end
7360
        end
7361
        else if (num_of_frames != 23) // ((i_length[1] == 1'b1) && (i_length[0] == 1'b1)) // interrupt not enabled
7362
        begin
7363
          if ( (data[15:0] !== 16'h2800) && // wrap bit
7364
               (data[15:0] !== 16'h0800) ) // without wrap bit
7365
          begin
7366 279 mohor
            `TIME; $display("*E TX buffer descriptor status is not correct 4: %0h", data[15:0]);
7367 243 tadejm
            test_fail("TX buffer descriptor status is not correct");
7368
            fail = fail + 1;
7369
          end
7370
        end
7371
        else // ((num_of_frames != 23) && (i_length[1] == 1'b1) && (i_length[0] == 1'b1)) // interrupt not enabled
7372
        begin
7373 209 tadejm
          if ( (data[15:0] !== 16'h3800) && // wrap bit
7374
               (data[15:0] !== 16'h1800) ) // without wrap bit
7375
          begin
7376 279 mohor
            `TIME; $display("*E TX buffer descriptor status is not correct 5: %0h", data[15:0]);
7377 209 tadejm
            test_fail("TX buffer descriptor status is not correct");
7378
            fail = fail + 1;
7379
          end
7380
        end
7381
      end
7382
      else
7383
      begin
7384
        if (data[15] !== 1'b1)
7385
        begin
7386
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
7387
          test_fail("TX buffer descriptor status is not correct");
7388
          fail = fail + 1;
7389
        end
7390
      end
7391
      // clear TX BD with wrap bit
7392
      if (num_of_frames == 63)
7393
        clear_tx_bd(16, 16);
7394
      // check interrupts
7395 274 tadejm
      wait (wbm_working == 0);
7396 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7397
      if ( ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1)) && (num_of_frames >= 5) )
7398
      begin
7399
        if ((data & `ETH_INT_TXB) !== 1'b1)
7400
        begin
7401
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
7402
          test_fail("Interrupt Transmit Buffer was not set");
7403
          fail = fail + 1;
7404
        end
7405
        if ((data & (~`ETH_INT_TXB)) !== 0)
7406
        begin
7407
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
7408
          test_fail("Other interrupts (except Transmit Buffer) were set");
7409
          fail = fail + 1;
7410
        end
7411
      end
7412
      else
7413
      begin
7414
        if (data !== 0)
7415
        begin
7416
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
7417
          test_fail("Any of interrupts (except Transmit Buffer) was set");
7418
          fail = fail + 1;
7419
        end
7420
      end
7421
      // clear interrupts
7422 274 tadejm
      wait (wbm_working == 0);
7423 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7424
      // check WB INT signal
7425
      if (wb_int !== 1'b0)
7426
      begin
7427
        test_fail("WB INT signal should not be set");
7428
        fail = fail + 1;
7429
      end
7430
      // INTERMEDIATE DISPLAYS
7431
      if (i_length == 3)
7432
      begin
7433 279 mohor
        $display("    pads appending to packets is not selected (except for 0x23)");
7434 209 tadejm
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
7435
        $display("    ->packets with lengths from %0d to %0d are not transmitted (length increasing by 1 byte)",
7436
                 0, 3);
7437
      end
7438
      else if (i_length == 9)
7439
      begin
7440
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
7441
        $display("    ->packet with length 4 is not transmitted (length increasing by 1 byte)");
7442
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7443
                 5, 9);
7444
      end
7445
      else if (i_length == 17)
7446
      begin
7447
        $display("    using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3)");
7448
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7449
                 10, 17);
7450
      end
7451
      else if (i_length == 27)
7452
      begin
7453
        $display("    using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4)");
7454
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7455
                 18, 27);
7456
      end
7457
      else if (i_length == 40)
7458
      begin
7459
        $display("    using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5)");
7460
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7461
                 28, 40);
7462
      end
7463
      else if (i_length == 54)
7464
      begin
7465
        $display("    using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6)");
7466
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7467
                 41, 54);
7468
      end
7469
      else if (i_length == 69)
7470
      begin
7471
        $display("    using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7)");
7472
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7473
                 55, 69);
7474
      end
7475
      // set length (loop variable)
7476
      i_length = i_length + 1;
7477
      // the number of frame transmitted
7478
      num_of_frames = num_of_frames + 1;
7479
      if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
7480
          (num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
7481
          (num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
7482
          (num_of_frames == 54) || (num_of_frames == 62))
7483
        num_of_bd = 0;
7484
      else
7485
        num_of_bd = num_of_bd + 1;
7486
    end
7487
    // disable TX
7488 274 tadejm
    wait (wbm_working == 0);
7489 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
7490
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7491
    @(posedge wb_clk);
7492
    if(fail == 0)
7493
      test_ok;
7494
    else
7495
      fail = 0;
7496
  end
7497
 
7498
 
7499
  ////////////////////////////////////////////////////////////////////
7500
  ////                                                            ////
7501 243 tadejm
  ////  Test transmit packets (no pads) form 0 to (MINFL - 1)     ////
7502 209 tadejm
  ////  sizes at 8 TX buffer decriptors ( 100Mbps ).              ////
7503
  ////                                                            ////
7504
  ////////////////////////////////////////////////////////////////////
7505
  if (test_num == 9) // 
7506
  begin
7507 243 tadejm
    // TEST 9: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )
7508
    test_name = "TEST 9: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )";
7509
    `TIME; $display("  TEST 9: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )");
7510 209 tadejm
 
7511
    // reset MAC registers
7512
    hard_reset;
7513
    // reset MAC and MII LOGIC with soft reset
7514 274 tadejm
//    reset_mac;
7515
//    reset_mii;
7516 209 tadejm
    // set wb slave response
7517
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
7518
 
7519
    max_tmp = 0;
7520
    min_tmp = 0;
7521
    // set 8 TX buffer descriptors - must be set before TX enable
7522 274 tadejm
    wait (wbm_working == 0);
7523 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h8, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7524
    // enable TX, set full-duplex mode, padding and CRC appending
7525 274 tadejm
    wait (wbm_working == 0);
7526 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
7527
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7528
    // prepare two packets of MAXFL length
7529 274 tadejm
    wait (wbm_working == 0);
7530 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7531
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
7532
    min_tmp = tmp[31:16];
7533
    st_data = 8'h12;
7534
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
7535
    st_data = 8'h34;
7536
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp - 4), st_data); // length without CRC
7537
    // check WB INT signal
7538
    if (wb_int !== 1'b0)
7539
    begin
7540
      test_fail("WB INT signal should not be set");
7541
      fail = fail + 1;
7542
    end
7543
 
7544
    // write to phy's control register for 100Mbps
7545
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
7546
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
7547
    speed = 100;
7548
 
7549
    frame_started = 0;
7550
    num_of_frames = 0;
7551
    num_of_bd = 0;
7552
    i_length = 0; // 0;
7553
    while (i_length < 70) // (min_tmp - 4))
7554
    begin
7555
      #1;
7556
      // choose generating carrier sense and collision
7557
      case (i_length[1:0])
7558
      2'h0: // Interrupt is generated
7559
      begin
7560
        // Reset_tx_bd nable interrupt generation
7561
        // unmask interrupts
7562 274 tadejm
        wait (wbm_working == 0);
7563 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
7564
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7565
        // not detect carrier sense in FD and no collision
7566
        eth_phy.carrier_sense_tx_fd_detect(0);
7567
        eth_phy.collision(0);
7568
      end
7569
      2'h1: // Interrupt is not generated
7570
      begin
7571
        // set_tx_bd enable interrupt generation
7572
        // mask interrupts
7573 274 tadejm
        wait (wbm_working == 0);
7574 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7575
        // detect carrier sense in FD and no collision
7576
        eth_phy.carrier_sense_tx_fd_detect(1);
7577
        eth_phy.collision(0);
7578
      end
7579
      2'h2: // Interrupt is not generated
7580
      begin
7581
        // set_tx_bd disable the interrupt generation
7582
        // unmask interrupts
7583 274 tadejm
        wait (wbm_working == 0);
7584 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
7585
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7586
        // not detect carrier sense in FD and set collision
7587
        eth_phy.carrier_sense_tx_fd_detect(0);
7588
        eth_phy.collision(1);
7589
      end
7590
      default: // 2'h3: // Interrupt is not generated
7591
      begin
7592
        // set_tx_bd disable the interrupt generation
7593
        // mask interrupts
7594 274 tadejm
        wait (wbm_working == 0);
7595 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7596
        // detect carrier sense in FD and set collision
7597
        eth_phy.carrier_sense_tx_fd_detect(1);
7598
        eth_phy.collision(1);
7599
      end
7600
      endcase
7601
      #1;
7602
      // first destination address on ethernet PHY
7603
      eth_phy.set_tx_mem_addr(num_of_frames * 16);
7604
      // SET packets and wrap bit
7605
      // num_of_frames <= 9 => wrap set to TX BD 0
7606
      if (num_of_frames <= 9)
7607
      begin
7608
        tmp_len = i_length; // length of frame
7609
        tmp_bd_num = 0; // TX BD number
7610
        // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7611
        // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7612
        if (tmp_len[0] == 0)
7613
          set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
7614
        else
7615
          set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
7616
        // set wrap bit
7617
        set_tx_bd_wrap(0);
7618
      end
7619
      // 10 <= num_of_frames < 18 => wrap set to TX BD 3
7620
      else if ((num_of_frames == 10) || (num_of_frames == 14))
7621
      begin
7622
        tmp_len = i_length; // length of frame
7623
        tmp_bd_num = 0; // TX BD number
7624
        while (tmp_bd_num < 4) //
7625
        begin
7626
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7627
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7628
          if (tmp_len[0] == 0)
7629
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
7630
          else
7631
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
7632
          tmp_len = tmp_len + 1;
7633
          // set TX BD number
7634
          tmp_bd_num = tmp_bd_num + 1;
7635
        end
7636
        // set wrap bit
7637
        set_tx_bd_wrap(3);
7638
      end
7639
      // 18 <= num_of_frames < 28 => wrap set to TX BD 4
7640
      else if ((num_of_frames == 18) || (num_of_frames == 23))
7641
      begin
7642
        tmp_len = i_length; // length of frame
7643
        tmp_bd_num = 0; // TX BD number
7644
        while (tmp_bd_num < 5) //
7645
        begin
7646
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7647
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7648
          if (tmp_len[0] == 0)
7649
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
7650
          else
7651
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
7652
          tmp_len = tmp_len + 1;
7653
          // set TX BD number
7654
          tmp_bd_num = tmp_bd_num + 1;
7655
        end
7656
        // set wrap bit
7657
        set_tx_bd_wrap(4);
7658
      end
7659
      // 28 <= num_of_frames < 40 => wrap set to TX BD 5
7660
      else if ((num_of_frames == 28) || (num_of_frames == 34))
7661
      begin
7662
        tmp_len = i_length; // length of frame
7663
        tmp_bd_num = 0; // TX BD number
7664
        while (tmp_bd_num < 6) //
7665
        begin
7666
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7667
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7668
          if (tmp_len[0] == 0)
7669
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
7670
          else
7671
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
7672
          tmp_len = tmp_len + 1;
7673
          // set TX BD number
7674
          tmp_bd_num = tmp_bd_num + 1;
7675
        end
7676
        // set wrap bit
7677
        set_tx_bd_wrap(5);
7678
      end
7679
      // 40 <= num_of_frames < 54 => wrap set to TX BD 6
7680
      else if ((num_of_frames == 40) || (num_of_frames == 47))
7681
      begin
7682
        tmp_len = i_length; // length of frame
7683
        tmp_bd_num = 0; // TX BD number
7684
        while (tmp_bd_num < 7) //
7685
        begin
7686
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7687
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7688
          if (tmp_len[0] == 0)
7689
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
7690
          else
7691
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
7692
          tmp_len = tmp_len + 1;
7693
          // set TX BD number
7694
          tmp_bd_num = tmp_bd_num + 1;
7695
        end
7696
        // set wrap bit
7697
        set_tx_bd_wrap(6);
7698
      end
7699
      // 54 <= num_of_frames < 70 => wrap set to TX BD 7
7700
      else if ((num_of_frames == 54) || (num_of_frames == 62))
7701
      begin
7702
        tmp_len = i_length; // length of frame
7703
        tmp_bd_num = 0; // TX BD number
7704
        while (tmp_bd_num < 8) //
7705
        begin
7706
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7707
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7708
          if (tmp_len[0] == 0)
7709
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
7710
          else
7711
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
7712
          tmp_len = tmp_len + 1;
7713
          // set TX BD number
7714
          tmp_bd_num = tmp_bd_num + 1;
7715
        end
7716
        // set wrap bit
7717
        set_tx_bd_wrap(7);
7718
      end
7719
      #1;
7720
      // SET ready bit
7721
      if (num_of_frames < 10)
7722
        set_tx_bd_ready(0, 0);
7723
      else if (num_of_frames < 14)
7724
        set_tx_bd_ready((num_of_frames - 10), (num_of_frames - 10));
7725
      else if (num_of_frames < 18)
7726
        set_tx_bd_ready((num_of_frames - 14), (num_of_frames - 14));
7727
      else if (num_of_frames < 23)
7728
        set_tx_bd_ready((num_of_frames - 18), (num_of_frames - 18));
7729
      else if (num_of_frames < 28)
7730
        set_tx_bd_ready((num_of_frames - 23), (num_of_frames - 23));
7731
      else if (num_of_frames < 34)
7732
        set_tx_bd_ready((num_of_frames - 28), (num_of_frames - 28));
7733
      else if (num_of_frames < 40)
7734
        set_tx_bd_ready((num_of_frames - 34), (num_of_frames - 34));
7735
      else if (num_of_frames < 47)
7736
        set_tx_bd_ready((num_of_frames - 40), (num_of_frames - 40));
7737
      else if (num_of_frames < 54)
7738
        set_tx_bd_ready((num_of_frames - 47), (num_of_frames - 47));
7739
      else if (num_of_frames < 62)
7740
        set_tx_bd_ready((num_of_frames - 54), (num_of_frames - 54));
7741
      else if (num_of_frames < 70)
7742
        set_tx_bd_ready((num_of_frames - 62), (num_of_frames - 62));
7743
      // CHECK END OF TRANSMITION
7744
      frame_started = 0;
7745
      if (num_of_frames >= 5)
7746
        #1 check_tx_bd(num_of_bd, data);
7747
      fork
7748
      begin: fr_st3
7749
        wait (MTxEn === 1'b1); // start transmit
7750
        frame_started = 1;
7751
      end
7752
      begin
7753 279 mohor
        repeat (50) @(posedge mtx_clk);
7754
$display("(%0t) num_of_frames = 0x%0x", $time, num_of_frames);
7755 209 tadejm
        if (num_of_frames < 5)
7756
        begin
7757
          if (frame_started == 1)
7758
          begin
7759
            `TIME; $display("*E Frame should NOT start!");
7760
          end
7761
          disable fr_st3;
7762
        end
7763
        else
7764
        begin
7765
          if (frame_started == 0)
7766
          begin
7767
            `TIME; $display("*W Frame should start!");
7768 279 mohor
#500 $stop;
7769 209 tadejm
            disable fr_st3;
7770
          end
7771
        end
7772
      end
7773
      join
7774
      // check packets larger than 4 bytes
7775
      if (num_of_frames >= 5)
7776
      begin
7777
        wait (MTxEn === 1'b0); // end transmit
7778
        while (data[15] === 1)
7779
        begin
7780
          #1 check_tx_bd(num_of_bd, data);
7781
          @(posedge wb_clk);
7782
        end
7783
        repeat (1) @(posedge wb_clk);
7784
        // check length of a PACKET
7785 279 mohor
        if ((num_of_frames + 4) < 64)
7786
          begin
7787
            if (eth_phy.tx_len != 64)
7788
            begin
7789
              `TIME; $display("*E Wrong length of the packet out from MAC");
7790
              test_fail("Wrong length of the packet out from MAC");
7791
              fail = fail + 1;
7792
            end
7793
          end
7794
        else
7795
          begin
7796 209 tadejm
        if (eth_phy.tx_len != (i_length + 4))
7797
        begin
7798
          `TIME; $display("*E Wrong length of the packet out from MAC");
7799
          test_fail("Wrong length of the packet out from MAC");
7800
          fail = fail + 1;
7801
        end
7802 279 mohor
          end
7803 209 tadejm
        // check transmitted TX packet data
7804
        if (i_length[0] == 0)
7805
        begin
7806
          #1 check_tx_packet(`MEMORY_BASE, (num_of_frames * 16), i_length, tmp);
7807
        end
7808
        else
7809
        begin
7810
          #1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
7811
        end
7812
        if (tmp > 0)
7813
        begin
7814
          test_fail("Wrong data of the transmitted packet");
7815
          fail = fail + 1;
7816
        end
7817
        // check transmited TX packet CRC
7818
        #1 check_tx_crc((num_of_frames * 16), (eth_phy.tx_len - 4), 1'b0, tmp); // length without CRC
7819
        if (tmp > 0)
7820
        begin
7821
          test_fail("Wrong CRC of the transmitted packet");
7822
          fail = fail + 1;
7823
        end
7824
      end
7825
      // check WB INT signal
7826
      if ((i_length[1:0] == 2'h0) && (num_of_frames >= 5))
7827
      begin
7828
        if (wb_int !== 1'b1)
7829
        begin
7830
          `TIME; $display("*E WB INT signal should be set");
7831
          test_fail("WB INT signal should be set");
7832
          fail = fail + 1;
7833
        end
7834
      end
7835
      else
7836
      begin
7837
        if (wb_int !== 1'b0)
7838
        begin
7839
          `TIME; $display("*E WB INT signal should not be set");
7840
          test_fail("WB INT signal should not be set");
7841
          fail = fail + 1;
7842
        end
7843
      end
7844
      // check TX buffer descriptor of a packet
7845
      check_tx_bd(num_of_bd, data);
7846
      if (num_of_frames >= 5)
7847
      begin
7848
        if (i_length[1] == 1'b0) // interrupt enabled
7849
        begin
7850
          if ( (data[15:0] !== 16'h7800) && // wrap bit
7851
               (data[15:0] !== 16'h5800) ) // without wrap bit
7852
          begin
7853
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
7854
            test_fail("TX buffer descriptor status is not correct");
7855
            fail = fail + 1;
7856
          end
7857
        end
7858
        else // interrupt not enabled
7859
        begin
7860
          if ( (data[15:0] !== 16'h3800) && // wrap bit
7861
               (data[15:0] !== 16'h1800) ) // without wrap bit
7862
          begin
7863
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
7864
            test_fail("TX buffer descriptor status is not correct");
7865
            fail = fail + 1;
7866
          end
7867
        end
7868
      end
7869
      else
7870
      begin
7871
        if (data[15] !== 1'b1)
7872
        begin
7873
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
7874
          test_fail("TX buffer descriptor status is not correct");
7875
          fail = fail + 1;
7876
        end
7877
      end
7878
      // clear TX BD with wrap bit
7879
      if (num_of_frames == 63)
7880
        clear_tx_bd(16, 16);
7881
      // check interrupts
7882 274 tadejm
      wait (wbm_working == 0);
7883 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7884
      if ( ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1)) && (num_of_frames >= 5) )
7885
      begin
7886
        if ((data & `ETH_INT_TXB) !== 1'b1)
7887
        begin
7888
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
7889
          test_fail("Interrupt Transmit Buffer was not set");
7890
          fail = fail + 1;
7891
        end
7892
        if ((data & (~`ETH_INT_TXB)) !== 0)
7893
        begin
7894
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
7895
          test_fail("Other interrupts (except Transmit Buffer) were set");
7896
          fail = fail + 1;
7897
        end
7898
      end
7899
      else
7900
      begin
7901
        if (data !== 0)
7902
        begin
7903
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
7904
          test_fail("Any of interrupts (except Transmit Buffer) was set");
7905
          fail = fail + 1;
7906
        end
7907
      end
7908
      // clear interrupts
7909 274 tadejm
      wait (wbm_working == 0);
7910 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7911
      // check WB INT signal
7912
      if (wb_int !== 1'b0)
7913
      begin
7914
        test_fail("WB INT signal should not be set");
7915
        fail = fail + 1;
7916
      end
7917
      // INTERMEDIATE DISPLAYS
7918
      if (i_length == 3)
7919
      begin
7920
        $display("    pads appending to packets is selected");
7921
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
7922
        $display("    ->packets with lengths from %0d to %0d are not transmitted (length increasing by 1 byte)",
7923
                 0, 3);
7924
      end
7925
      else if (i_length == 9)
7926
      begin
7927
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
7928
        $display("    ->packet with length 4 is not transmitted (length increasing by 1 byte)");
7929
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7930
                 5, 9);
7931
      end
7932
      else if (i_length == 17)
7933
      begin
7934
        $display("    using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3)");
7935
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7936
                 10, 17);
7937
      end
7938
      else if (i_length == 27)
7939
      begin
7940
        $display("    using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4)");
7941
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7942
                 18, 27);
7943
      end
7944
      else if (i_length == 40)
7945
      begin
7946
        $display("    using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5)");
7947
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7948
                 28, 40);
7949
      end
7950
      else if (i_length == 54)
7951
      begin
7952
        $display("    using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6)");
7953
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7954
                 41, 54);
7955
      end
7956
      else if (i_length == 69)
7957
      begin
7958
        $display("    using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7)");
7959
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7960
                 55, 69);
7961
      end
7962
      // set length (loop variable)
7963
      i_length = i_length + 1;
7964
      // the number of frame transmitted
7965
      num_of_frames = num_of_frames + 1;
7966
      if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
7967
          (num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
7968
          (num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
7969
          (num_of_frames == 54) || (num_of_frames == 62))
7970
        num_of_bd = 0;
7971
      else
7972
        num_of_bd = num_of_bd + 1;
7973
    end
7974
    // disable TX
7975 274 tadejm
    wait (wbm_working == 0);
7976 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
7977
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7978
    @(posedge wb_clk);
7979
    if(fail == 0)
7980
      test_ok;
7981
    else
7982
      fail = 0;
7983
  end
7984
 
7985
 
7986
  ////////////////////////////////////////////////////////////////////
7987
  ////                                                            ////
7988
  ////  Test transmit packets across MAXFL value at               ////
7989
  ////  13 TX buffer decriptors ( 10Mbps ).                       ////
7990
  ////                                                            ////
7991
  ////////////////////////////////////////////////////////////////////
7992
  if (test_num == 10) // without and with padding
7993
  begin
7994
    // TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )
7995
    test_name = "TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )";
7996
    `TIME; $display("  TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )");
7997
 
7998
    // reset MAC registers
7999
    hard_reset;
8000
    // set wb slave response
8001
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
8002
 
8003
    max_tmp = 0;
8004
    min_tmp = 0;
8005
    num_of_frames = 0;
8006
    num_of_bd = 0;
8007
    // set 13 TX buffer descriptors - must be set before TX enable
8008 274 tadejm
    wait (wbm_working == 0);
8009 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'hD, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8010
    // enable TX, set full-duplex mode, NO padding and CRC appending
8011 274 tadejm
    wait (wbm_working == 0);
8012 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
8013
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8014
    // prepare a packet of MAXFL + 10 length
8015 274 tadejm
    wait (wbm_working == 0);
8016 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8017
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
8018
    min_tmp = tmp[31:16];
8019
    st_data = 8'hA3;
8020
    set_tx_packet(`MEMORY_BASE, (max_tmp + 10), st_data); // length without CRC
8021
    // check WB INT signal
8022
    if (wb_int !== 1'b0)
8023
    begin
8024
      test_fail("WB INT signal should not be set");
8025
      fail = fail + 1;
8026
    end
8027
 
8028
    // write to phy's control register for 10Mbps
8029
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
8030
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
8031
    speed = 10;
8032
 
8033
    i_length = (max_tmp - 5);
8034 279 mohor
    while (num_of_bd <= 3)
8035 209 tadejm
    begin
8036 279 mohor
      // unmask interrupts
8037
      wait (wbm_working == 0);
8038
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
8039
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8040
      // not detect carrier sense in FD and no collision
8041
      eth_phy.carrier_sense_tx_fd_detect(0);
8042
      eth_phy.collision(0);
8043 209 tadejm
      // first destination address on ethernet PHY
8044
      eth_phy.set_tx_mem_addr(0);
8045
 
8046 279 mohor
      if (num_of_bd == 0)
8047
      begin
8048
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8049
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8050
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8051
        set_tx_bd_wrap(2);
8052
        set_tx_bd_ready(0, 0);
8053
      end
8054
      else if (num_of_bd == 1)
8055
        set_tx_bd_ready(1, 1);
8056
      else if (num_of_bd == 2)
8057
        set_tx_bd_ready(2, 2);
8058
      else if (num_of_bd == 3)
8059
      begin
8060
        set_tx_bd(0, 0, 100, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8061
        set_tx_bd_wrap(2);
8062
        set_tx_bd_ready(0, 0);
8063
        i_length = 96;
8064
      end
8065
 
8066 209 tadejm
 
8067
      // CHECK END OF TRANSMITION
8068 279 mohor
      check_tx_bd(num_of_bd, data);
8069
      wait (MTxEn === 1'b1); // start transmit
8070
      check_tx_bd(num_of_bd, data);
8071
      if (data[15] !== 1)
8072
      begin
8073
        test_fail("Wrong buffer descriptor's ready bit read out from MAC");
8074
        fail = fail + 1;
8075
      end
8076
      wait (MTxEn === 1'b0); // end transmit
8077
      while (data[15] === 1)
8078
      begin
8079
        check_tx_bd(num_of_bd, data);
8080
        @(posedge wb_clk);
8081
      end
8082
      repeat (1) @(posedge wb_clk);
8083 209 tadejm
      // check length of a PACKET
8084 279 mohor
      tmp_len = eth_phy.tx_len;
8085
      #1;
8086
      if (tmp_len != (i_length + 4))
8087 209 tadejm
      begin
8088
        test_fail("Wrong length of the packet out from MAC");
8089
        fail = fail + 1;
8090
      end
8091 279 mohor
 
8092
      // check transmitted TX packet data
8093
      if ((i_length + 4) == 100)
8094
        check_tx_packet(`MEMORY_BASE, 0, 100 - 4, tmp);
8095
      else if ((i_length + 4) <= max_tmp)
8096
        check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
8097
      else
8098
        check_tx_packet(`MEMORY_BASE, 0, max_tmp - 4, tmp);
8099
 
8100
      if (tmp > 0)
8101
      begin
8102
        test_fail("Wrong data of the transmitted packet");
8103
        fail = fail + 1;
8104
      end
8105
 
8106
      // check transmited TX packet CRC
8107
      if ((i_length + 4) == 100)
8108
        check_tx_crc(0, 100, 1'b0, tmp); // length without CRC
8109
      else if ((i_length + 4) <= max_tmp)
8110
        check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
8111
 
8112
      if (tmp > 0)
8113
      begin
8114
        test_fail("Wrong CRC of the transmitted packet");
8115
        fail = fail + 1;
8116
      end
8117
 
8118
      if (wb_int !== 1'b1)
8119
      begin
8120
        `TIME; $display("*E WB INT signal should be set");
8121
        test_fail("WB INT signal should be set");
8122
        fail = fail + 1;
8123
      end
8124
 
8125
      check_tx_bd(num_of_bd, data);
8126
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
8127
           ((data[15:0] !== 16'h5800) && (num_of_bd < 2)) )   // without wrap bit
8128
      begin
8129
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
8130
        test_fail("TX buffer descriptor status is not correct");
8131
        fail = fail + 1;
8132
      end
8133
 
8134 209 tadejm
      // check interrupts
8135 274 tadejm
      wait (wbm_working == 0);
8136 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8137 279 mohor
      if ((data & `ETH_INT_TXB) !== `ETH_INT_TXB)
8138
      begin
8139
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
8140
        test_fail("Interrupt Transmit Buffer was not set");
8141
        fail = fail + 1;
8142
      end
8143
      if ((data & (~`ETH_INT_TXB)) !== 0)
8144
      begin
8145
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
8146
        test_fail("Other interrupts (except Transmit Buffer) were set");
8147
        fail = fail + 1;
8148
      end
8149
 
8150 209 tadejm
      // clear interrupts
8151 274 tadejm
      wait (wbm_working == 0);
8152 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8153
      // check WB INT signal
8154
      if (wb_int !== 1'b0)
8155
      begin
8156
        test_fail("WB INT signal should not be set");
8157
        fail = fail + 1;
8158
      end
8159 279 mohor
 
8160 209 tadejm
      // INTERMEDIATE DISPLAYS
8161 279 mohor
      if (num_of_bd == 0)
8162
        $display("    ->packet with length %0d sent", (i_length + 4));
8163
      else if (num_of_bd == 1)
8164
        $display("    ->packet with length %0d sent", (i_length + 4));
8165
      else if (num_of_bd == 2)
8166
        $display("    ->packet with length %0d sent", (i_length + 4));
8167
      else if (num_of_bd == 3)
8168
        $display("    ->packet with length %0d sent", (104));
8169 209 tadejm
      // set length (loop variable)
8170
      i_length = i_length + 1;
8171
      // the number of frame transmitted
8172
      num_of_frames = num_of_frames + 1;
8173
      num_of_bd = num_of_bd + 1;
8174
      @(posedge wb_clk);
8175
    end
8176
    // disable TX
8177 274 tadejm
    wait (wbm_working == 0);
8178 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
8179
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8180
    @(posedge wb_clk);
8181
    if(fail == 0)
8182
      test_ok;
8183
    else
8184
      fail = 0;
8185
  end
8186
 
8187
 
8188
  ////////////////////////////////////////////////////////////////////
8189
  ////                                                            ////
8190
  ////  Test transmit packets across MAXFL value at               ////
8191 279 mohor
  ////  13 TX buffer decriptors ( 100Mbps ).                       ////
8192 209 tadejm
  ////                                                            ////
8193
  ////////////////////////////////////////////////////////////////////
8194
  if (test_num == 11) // without and with padding
8195
  begin
8196
    // TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )
8197
    test_name = "TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )";
8198
    `TIME; $display("  TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )");
8199 279 mohor
 
8200 209 tadejm
    // reset MAC registers
8201
    hard_reset;
8202
    // set wb slave response
8203
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
8204
 
8205
    max_tmp = 0;
8206
    min_tmp = 0;
8207
    num_of_frames = 0;
8208
    num_of_bd = 0;
8209
    // set 13 TX buffer descriptors - must be set before TX enable
8210 274 tadejm
    wait (wbm_working == 0);
8211 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'hD, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8212
    // enable TX, set full-duplex mode, NO padding and CRC appending
8213 274 tadejm
    wait (wbm_working == 0);
8214 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
8215
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8216
    // prepare a packet of MAXFL + 10 length
8217 274 tadejm
    wait (wbm_working == 0);
8218 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8219
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
8220
    min_tmp = tmp[31:16];
8221
    st_data = 8'hA3;
8222
    set_tx_packet(`MEMORY_BASE, (max_tmp + 10), st_data); // length without CRC
8223
    // check WB INT signal
8224
    if (wb_int !== 1'b0)
8225
    begin
8226
      test_fail("WB INT signal should not be set");
8227
      fail = fail + 1;
8228
    end
8229 279 mohor
 
8230
    // write to phy's control register for 10Mbps
8231
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 reset - speed 100
8232
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
8233 209 tadejm
    speed = 100;
8234
 
8235
    i_length = (max_tmp - 5);
8236 279 mohor
    while (num_of_bd <= 3)
8237 209 tadejm
    begin
8238
      // unmask interrupts
8239 274 tadejm
      wait (wbm_working == 0);
8240 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
8241
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8242
      // not detect carrier sense in FD and no collision
8243
      eth_phy.carrier_sense_tx_fd_detect(0);
8244
      eth_phy.collision(0);
8245
      // first destination address on ethernet PHY
8246
      eth_phy.set_tx_mem_addr(0);
8247 279 mohor
 
8248 209 tadejm
      if (num_of_bd == 0)
8249
      begin
8250
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8251
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8252
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8253
        set_tx_bd_wrap(2);
8254
        set_tx_bd_ready(0, 0);
8255
      end
8256
      else if (num_of_bd == 1)
8257
        set_tx_bd_ready(1, 1);
8258
      else if (num_of_bd == 2)
8259
        set_tx_bd_ready(2, 2);
8260 279 mohor
      else if (num_of_bd == 3)
8261
      begin
8262
        set_tx_bd(0, 0, 100, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8263
        set_tx_bd_wrap(2);
8264
        set_tx_bd_ready(0, 0);
8265
        i_length = 96;
8266
      end
8267
 
8268
 
8269 209 tadejm
      // CHECK END OF TRANSMITION
8270
      check_tx_bd(num_of_bd, data);
8271 279 mohor
      wait (MTxEn === 1'b1); // start transmit
8272 209 tadejm
      check_tx_bd(num_of_bd, data);
8273 279 mohor
      if (data[15] !== 1)
8274
      begin
8275
        test_fail("Wrong buffer descriptor's ready bit read out from MAC");
8276
        fail = fail + 1;
8277
      end
8278
      wait (MTxEn === 1'b0); // end transmit
8279
      while (data[15] === 1)
8280
      begin
8281
        check_tx_bd(num_of_bd, data);
8282
        @(posedge wb_clk);
8283
      end
8284
      repeat (1) @(posedge wb_clk);
8285
      repeat (10) @(posedge mtx_clk);
8286 209 tadejm
      // check length of a PACKET
8287
      tmp_len = eth_phy.tx_len;
8288
      #1;
8289
      if (tmp_len != (i_length + 4))
8290
      begin
8291
        test_fail("Wrong length of the packet out from MAC");
8292
        fail = fail + 1;
8293
      end
8294 279 mohor
 
8295
      // check transmitted TX packet data
8296
      if ((i_length + 4) == 100)
8297
        check_tx_packet(`MEMORY_BASE, 0, 100 - 4, tmp);
8298
      else if ((i_length + 4) <= max_tmp)
8299
        check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
8300
      else
8301
        check_tx_packet(`MEMORY_BASE, 0, max_tmp - 4, tmp);
8302
 
8303 209 tadejm
      if (tmp > 0)
8304
      begin
8305
        test_fail("Wrong data of the transmitted packet");
8306
        fail = fail + 1;
8307
      end
8308 279 mohor
 
8309 209 tadejm
      // check transmited TX packet CRC
8310 279 mohor
      if ((i_length + 4) == 100)
8311
        check_tx_crc(0, 100, 1'b0, tmp); // length without CRC
8312
      else if ((i_length + 4) <= max_tmp)
8313
        check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
8314
 
8315 209 tadejm
      if (tmp > 0)
8316
      begin
8317
        test_fail("Wrong CRC of the transmitted packet");
8318
        fail = fail + 1;
8319
      end
8320 279 mohor
 
8321 209 tadejm
      if (wb_int !== 1'b1)
8322
      begin
8323
        `TIME; $display("*E WB INT signal should be set");
8324
        test_fail("WB INT signal should be set");
8325
        fail = fail + 1;
8326
      end
8327 279 mohor
 
8328 209 tadejm
      check_tx_bd(num_of_bd, data);
8329
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
8330
           ((data[15:0] !== 16'h5800) && (num_of_bd < 2)) )   // without wrap bit
8331
      begin
8332
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
8333
        test_fail("TX buffer descriptor status is not correct");
8334
        fail = fail + 1;
8335
      end
8336 279 mohor
 
8337 209 tadejm
      // check interrupts
8338 274 tadejm
      wait (wbm_working == 0);
8339 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8340 279 mohor
      if ((data & `ETH_INT_TXB) !== `ETH_INT_TXB)
8341 209 tadejm
      begin
8342
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
8343
        test_fail("Interrupt Transmit Buffer was not set");
8344
        fail = fail + 1;
8345
      end
8346
      if ((data & (~`ETH_INT_TXB)) !== 0)
8347
      begin
8348
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
8349
        test_fail("Other interrupts (except Transmit Buffer) were set");
8350
        fail = fail + 1;
8351
      end
8352 279 mohor
 
8353 209 tadejm
      // clear interrupts
8354 274 tadejm
      wait (wbm_working == 0);
8355 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8356
      // check WB INT signal
8357
      if (wb_int !== 1'b0)
8358
      begin
8359
        test_fail("WB INT signal should not be set");
8360
        fail = fail + 1;
8361
      end
8362 279 mohor
 
8363 209 tadejm
      // INTERMEDIATE DISPLAYS
8364
      if (num_of_bd == 0)
8365
        $display("    ->packet with length %0d sent", (i_length + 4));
8366
      else if (num_of_bd == 1)
8367
        $display("    ->packet with length %0d sent", (i_length + 4));
8368
      else if (num_of_bd == 2)
8369
        $display("    ->packet with length %0d sent", (i_length + 4));
8370 279 mohor
      else if (num_of_bd == 3)
8371
        $display("    ->packet with length %0d sent", (104));
8372 209 tadejm
      // set length (loop variable)
8373
      i_length = i_length + 1;
8374
      // the number of frame transmitted
8375
      num_of_frames = num_of_frames + 1;
8376
      num_of_bd = num_of_bd + 1;
8377
      @(posedge wb_clk);
8378
    end
8379
    // disable TX
8380 274 tadejm
    wait (wbm_working == 0);
8381 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
8382
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8383
    @(posedge wb_clk);
8384
    if(fail == 0)
8385
      test_ok;
8386
    else
8387
      fail = 0;
8388
  end
8389
 
8390
 
8391 279 mohor
 
8392
 
8393 209 tadejm
  ////////////////////////////////////////////////////////////////////
8394
  ////                                                            ////
8395
  ////  Test transmit packets across changed MAXFL value at       ////
8396
  ////  47 TX buffer decriptors ( 10Mbps ).                       ////
8397
  ////                                                            ////
8398
  ////////////////////////////////////////////////////////////////////
8399
  if (test_num == 12) // without and with padding
8400
  begin
8401
    // TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )
8402
    test_name = "TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )";
8403
    `TIME; $display("  TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )");
8404
 
8405
    // reset MAC registers
8406
    hard_reset;
8407
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
8408
 
8409
    max_tmp = 0;
8410
    min_tmp = 0;
8411
    num_of_frames = 0;
8412
    num_of_bd = 0;
8413
    // set 47 TX buffer descriptors - must be set before TX enable
8414 274 tadejm
    wait (wbm_working == 0);
8415 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h2F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8416
    // prepare a packet of MAXFL + 10 length
8417 274 tadejm
    wait (wbm_working == 0);
8418 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8419
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
8420
    min_tmp = tmp[31:16];
8421
    // change MAXFL value
8422
    max_tmp = min_tmp + 53;
8423 274 tadejm
    wait (wbm_working == 0);
8424 209 tadejm
    wbm_write(`ETH_PACKETLEN, {min_tmp, max_tmp}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8425
    st_data = 8'h62;
8426
    set_tx_packet(`MEMORY_BASE, max_tmp, st_data); // length with CRC
8427 274 tadejm
    wait (wbm_working == 0);
8428 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD,
8429
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8430
    // check WB INT signal
8431
    if (wb_int !== 1'b0)
8432
    begin
8433
      test_fail("WB INT signal should not be set");
8434
      fail = fail + 1;
8435
    end
8436
 
8437
    // write to phy's control register for 10Mbps
8438
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
8439
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
8440
    speed = 10;
8441
 
8442
    i_length = (max_tmp - 5); // (max_tmp - 1); // not (max_tmp - 5) because NO automatic CRC appending
8443
    while (i_length <= (max_tmp - 3)) // (max_tmp + 1)) // (max_tmp) is the limit
8444
    begin
8445 274 tadejm
      wait (wbm_working == 0);
8446 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
8447
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8448
      // not detect carrier sense in FD and no collision
8449
      eth_phy.carrier_sense_tx_fd_detect(0);
8450
      eth_phy.collision(0);
8451
      // first destination address on ethernet PHY
8452
      eth_phy.set_tx_mem_addr(0);
8453
      // prepare BDs
8454
      if (num_of_bd == 0)
8455
      begin
8456
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8457
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8458
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8459
        set_tx_bd_wrap(2);
8460
        set_tx_bd_ready(0, 0);
8461
      end
8462
      else if (num_of_bd == 1)
8463
        set_tx_bd_ready(1, 1);
8464
      else if (num_of_bd == 2)
8465
        set_tx_bd_ready(2, 2);
8466
      // CHECK END OF TRANSMITION
8467
      check_tx_bd(num_of_bd, data);
8468
        wait (MTxEn === 1'b1); // start transmit
8469
      check_tx_bd(num_of_bd, data);
8470
        if (data[15] !== 1)
8471
        begin
8472
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
8473
          fail = fail + 1;
8474
        end
8475
        wait (MTxEn === 1'b0); // end transmit
8476
        while (data[15] === 1)
8477
        begin
8478
      check_tx_bd(num_of_bd, data);
8479
          @(posedge wb_clk);
8480
        end
8481 279 mohor
        repeat (5) @(posedge mtx_clk);
8482 209 tadejm
      // check length of a PACKET
8483
      tmp_len = eth_phy.tx_len;
8484
      #1;
8485
      if (tmp_len != (i_length + 4))
8486
      begin
8487
        test_fail("Wrong length of the packet out from MAC");
8488
        fail = fail + 1;
8489
      end
8490
      // checking packet
8491
      check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
8492
      if (tmp > 0)
8493
      begin
8494
        test_fail("Wrong data of the transmitted packet");
8495
        fail = fail + 1;
8496
      end
8497
      // check transmited TX packet CRC
8498 279 mohor
      if (num_of_bd !== 2)
8499
        check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
8500 209 tadejm
      if (tmp > 0)
8501
      begin
8502
        test_fail("Wrong CRC of the transmitted packet");
8503
        fail = fail + 1;
8504
      end
8505
      // check WB INT signal
8506
      if (wb_int !== 1'b1)
8507
      begin
8508
        `TIME; $display("*E WB INT signal should be set");
8509
        test_fail("WB INT signal should be set");
8510
        fail = fail + 1;
8511
      end
8512
      // check TX buffer descriptor of a packet
8513
      check_tx_bd(num_of_bd, data);
8514
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
8515
           ((data[15:0] !== 16'h5800) && (num_of_bd < 2)) )   // without wrap bit
8516
      begin
8517
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
8518
        test_fail("TX buffer descriptor status is not correct");
8519
        fail = fail + 1;
8520
      end
8521
      // check interrupts
8522 274 tadejm
      wait (wbm_working == 0);
8523 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8524
      if ((data & `ETH_INT_TXB) !== 1'b1)
8525
      begin
8526
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
8527
        test_fail("Interrupt Transmit Buffer was not set");
8528
        fail = fail + 1;
8529
      end
8530
      if ((data & (~`ETH_INT_TXB)) !== 0)
8531
      begin
8532
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
8533
        test_fail("Other interrupts (except Transmit Buffer) were set");
8534
        fail = fail + 1;
8535
      end
8536
      // clear interrupts
8537 274 tadejm
      wait (wbm_working == 0);
8538 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8539
      // check WB INT signal
8540
      if (wb_int !== 1'b0)
8541
      begin
8542
        test_fail("WB INT signal should not be set");
8543
        fail = fail + 1;
8544
      end
8545
      // INTERMEDIATE DISPLAYS
8546
      if (num_of_bd == 0)
8547
        $display("    ->packet with length %0d sent", (i_length + 4));
8548
      else if (num_of_bd == 1)
8549
        $display("    ->packet with length %0d sent", (i_length + 4));
8550
      else if (num_of_bd == 2)
8551
        $display("    ->packet with length %0d sent", (i_length + 4));
8552
      // set length (loop variable)
8553
      i_length = i_length + 1;
8554
      // the number of frame transmitted
8555
      num_of_frames = num_of_frames + 1;
8556
      num_of_bd = num_of_bd + 1;
8557
      @(posedge wb_clk);
8558
    end
8559
    // disable TX
8560 274 tadejm
    wait (wbm_working == 0);
8561 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
8562
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8563
    @(posedge wb_clk);
8564
    if(fail == 0)
8565
      test_ok;
8566
    else
8567
      fail = 0;
8568
  end
8569
 
8570
 
8571
  ////////////////////////////////////////////////////////////////////
8572
  ////                                                            ////
8573
  ////  Test transmit packets across changed MAXFL value at       ////
8574
  ////  47 TX buffer decriptors ( 100Mbps ).                      ////
8575
  ////                                                            ////
8576
  ////////////////////////////////////////////////////////////////////
8577
  if (test_num == 13) // without and with padding
8578
  begin
8579
    // TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )
8580
    test_name = "TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )";
8581
    `TIME; $display("  TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )");
8582
 
8583
    // reset MAC registers
8584
    hard_reset;
8585
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
8586
 
8587
    max_tmp = 0;
8588
    min_tmp = 0;
8589
    num_of_frames = 0;
8590
    num_of_bd = 0;
8591
    // set 47 TX buffer descriptors - must be set before TX enable
8592 274 tadejm
    wait (wbm_working == 0);
8593 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h2F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8594
    // prepare a packet of MAXFL + 10 length
8595 274 tadejm
    wait (wbm_working == 0);
8596 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8597
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
8598
    min_tmp = tmp[31:16];
8599
    // change MAXFL value
8600
    max_tmp = min_tmp + 53;
8601 274 tadejm
    wait (wbm_working == 0);
8602 209 tadejm
    wbm_write(`ETH_PACKETLEN, {min_tmp, max_tmp}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8603
    st_data = 8'h62;
8604
    set_tx_packet(`MEMORY_BASE, max_tmp, st_data); // length with CRC
8605 274 tadejm
    wait (wbm_working == 0);
8606 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD,
8607
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8608
    // check WB INT signal
8609
    if (wb_int !== 1'b0)
8610
    begin
8611
      test_fail("WB INT signal should not be set");
8612
      fail = fail + 1;
8613
    end
8614
 
8615 279 mohor
    // write to phy's control register for 10Mbps
8616
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 reset - speed 100
8617
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
8618 209 tadejm
    speed = 100;
8619
 
8620
    i_length = (max_tmp - 5); // (max_tmp - 1); // not (max_tmp - 5) because NO automatic CRC appending
8621
    while (i_length <= (max_tmp - 3)) // (max_tmp + 1)) // (max_tmp) is the limit
8622
    begin
8623 274 tadejm
      wait (wbm_working == 0);
8624 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
8625
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8626
      // not detect carrier sense in FD and no collision
8627
      eth_phy.carrier_sense_tx_fd_detect(0);
8628
      eth_phy.collision(0);
8629
      // first destination address on ethernet PHY
8630
      eth_phy.set_tx_mem_addr(0);
8631
      // prepare BDs
8632
      if (num_of_bd == 0)
8633
      begin
8634
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8635
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8636
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8637
        set_tx_bd_wrap(2);
8638
        set_tx_bd_ready(0, 0);
8639
      end
8640
      else if (num_of_bd == 1)
8641
        set_tx_bd_ready(1, 1);
8642
      else if (num_of_bd == 2)
8643
        set_tx_bd_ready(2, 2);
8644
      // CHECK END OF TRANSMITION
8645
      check_tx_bd(num_of_bd, data);
8646
        wait (MTxEn === 1'b1); // start transmit
8647
      check_tx_bd(num_of_bd, data);
8648
        if (data[15] !== 1)
8649
        begin
8650
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
8651
          fail = fail + 1;
8652
        end
8653
        wait (MTxEn === 1'b0); // end transmit
8654
        while (data[15] === 1)
8655
        begin
8656
      check_tx_bd(num_of_bd, data);
8657
          @(posedge wb_clk);
8658
        end
8659 279 mohor
        repeat (5) @(posedge mtx_clk);
8660 209 tadejm
      // check length of a PACKET
8661
      tmp_len = eth_phy.tx_len;
8662
      #1;
8663
      if (tmp_len != (i_length + 4))
8664
      begin
8665
        test_fail("Wrong length of the packet out from MAC");
8666
        fail = fail + 1;
8667
      end
8668
      // checking packet
8669
      check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
8670
      if (tmp > 0)
8671
      begin
8672
        test_fail("Wrong data of the transmitted packet");
8673
        fail = fail + 1;
8674
      end
8675
      // check transmited TX packet CRC
8676 279 mohor
      if (num_of_bd !== 2)
8677
        check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
8678 209 tadejm
      if (tmp > 0)
8679
      begin
8680
        test_fail("Wrong CRC of the transmitted packet");
8681
        fail = fail + 1;
8682
      end
8683
      // check WB INT signal
8684
      if (wb_int !== 1'b1)
8685
      begin
8686
        `TIME; $display("*E WB INT signal should be set");
8687
        test_fail("WB INT signal should be set");
8688
        fail = fail + 1;
8689
      end
8690
      // check TX buffer descriptor of a packet
8691
      check_tx_bd(num_of_bd, data);
8692
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
8693
           ((data[15:0] !== 16'h5800) && (num_of_bd < 2)) )   // without wrap bit
8694
      begin
8695
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
8696
        test_fail("TX buffer descriptor status is not correct");
8697
        fail = fail + 1;
8698
      end
8699
      // check interrupts
8700 274 tadejm
      wait (wbm_working == 0);
8701 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8702
      if ((data & `ETH_INT_TXB) !== 1'b1)
8703
      begin
8704
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
8705
        test_fail("Interrupt Transmit Buffer was not set");
8706
        fail = fail + 1;
8707
      end
8708
      if ((data & (~`ETH_INT_TXB)) !== 0)
8709
      begin
8710
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
8711
        test_fail("Other interrupts (except Transmit Buffer) were set");
8712
        fail = fail + 1;
8713
      end
8714
      // clear interrupts
8715 274 tadejm
      wait (wbm_working == 0);
8716 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8717
      // check WB INT signal
8718
      if (wb_int !== 1'b0)
8719
      begin
8720
        test_fail("WB INT signal should not be set");
8721
        fail = fail + 1;
8722
      end
8723
      // INTERMEDIATE DISPLAYS
8724
      if (num_of_bd == 0)
8725
        $display("    ->packet with length %0d sent", (i_length + 4));
8726
      else if (num_of_bd == 1)
8727
        $display("    ->packet with length %0d sent", (i_length + 4));
8728
      else if (num_of_bd == 2)
8729
        $display("    ->packet with length %0d sent", (i_length + 4));
8730
      // set length (loop variable)
8731
      i_length = i_length + 1;
8732
      // the number of frame transmitted
8733
      num_of_frames = num_of_frames + 1;
8734
      num_of_bd = num_of_bd + 1;
8735
      @(posedge wb_clk);
8736
    end
8737
    // disable TX
8738 274 tadejm
    wait (wbm_working == 0);
8739 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
8740
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8741
    @(posedge wb_clk);
8742
    if(fail == 0)
8743
      test_ok;
8744
    else
8745
      fail = 0;
8746
  end
8747
 
8748
 
8749
  ////////////////////////////////////////////////////////////////////
8750
  ////                                                            ////
8751
  ////  Test transmit packets across changed MINFL value at       ////
8752
  ////  7 TX buffer decriptors ( 10Mbps ).                        ////
8753
  ////                                                            ////
8754
  ////////////////////////////////////////////////////////////////////
8755
  if (test_num == 14) // without and with padding
8756
  begin
8757
    // TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )
8758
    test_name = "TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )";
8759
    `TIME; $display("  TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )");
8760
 
8761
    // reset MAC registers
8762
    hard_reset;
8763 279 mohor
 
8764 209 tadejm
    // set wb slave response
8765
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
8766
 
8767
    max_tmp = 0;
8768
    min_tmp = 0;
8769
    num_of_frames = 0;
8770
    num_of_bd = 0;
8771
    // set 7 TX buffer descriptors - must be set before TX enable
8772 274 tadejm
    wait (wbm_working == 0);
8773 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h7, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8774
    // prepare a packet of MAXFL + 10 length
8775 274 tadejm
    wait (wbm_working == 0);
8776 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8777
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
8778
    min_tmp = tmp[31:16];
8779 279 mohor
 
8780 209 tadejm
    // change MINFL value
8781
    min_tmp = max_tmp - 177;
8782 274 tadejm
    wait (wbm_working == 0);
8783 209 tadejm
    wbm_write(`ETH_PACKETLEN, {min_tmp, max_tmp}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8784
    st_data = 8'h62;
8785
    set_tx_packet(`MEMORY_BASE, min_tmp, st_data); // length without CRC
8786
    // enable TX, set full-duplex mode, padding and CRC appending
8787 274 tadejm
    wait (wbm_working == 0);
8788 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
8789
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8790
    // check WB INT signal
8791
    if (wb_int !== 1'b0)
8792
    begin
8793
      test_fail("WB INT signal should not be set");
8794
      fail = fail + 1;
8795
    end
8796
 
8797
    // write to phy's control register for 10Mbps
8798
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
8799
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
8800
    speed = 10;
8801
 
8802
    i_length = (min_tmp - 5);
8803
    while (i_length <= (min_tmp - 3)) // (min_tmp - 4) is the limit
8804
    begin
8805
      // Reset_tx_bd nable interrupt generation
8806
      // unmask interrupts
8807 274 tadejm
      wait (wbm_working == 0);
8808 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
8809
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8810
      // not detect carrier sense in FD and no collision
8811
      eth_phy.carrier_sense_tx_fd_detect(0);
8812
      eth_phy.collision(0);
8813
      // first destination address on ethernet PHY
8814
      eth_phy.set_tx_mem_addr(0);
8815
      // prepare BDs
8816
      if (num_of_bd == 0)
8817
      begin
8818
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8819
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8820
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8821
        set_tx_bd_wrap(2);
8822
        set_tx_bd_ready(0, 0);
8823
      end
8824
      else if (num_of_bd == 1)
8825
        set_tx_bd_ready(1, 1);
8826
      else if (num_of_bd == 2)
8827
        set_tx_bd_ready(2, 2);
8828
      // CHECK END OF TRANSMITION
8829
      check_tx_bd(num_of_bd, data);
8830
        wait (MTxEn === 1'b1); // start transmit
8831
      check_tx_bd(num_of_bd, data);
8832
        if (data[15] !== 1)
8833
        begin
8834
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
8835
          fail = fail + 1;
8836
        end
8837
        wait (MTxEn === 1'b0); // end transmit
8838
        while (data[15] === 1)
8839
        begin
8840
      check_tx_bd(num_of_bd, data);
8841
          @(posedge wb_clk);
8842
        end
8843
        repeat (1) @(posedge wb_clk);
8844
      // check length of a PACKET
8845
      tmp_len = eth_phy.tx_len;
8846
      #1;
8847
      if (tmp_len != (i_length + 4))
8848
      begin
8849
        test_fail("Wrong length of the packet out from MAC");
8850
        fail = fail + 1;
8851
      end
8852
      // checking packet
8853
      check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
8854
      if (tmp > 0)
8855
      begin
8856
        test_fail("Wrong data of the transmitted packet");
8857
        fail = fail + 1;
8858
      end
8859
      // check transmited TX packet CRC
8860 279 mohor
      if (num_of_bd !== 0)  // First packet is padded and CRC does not match.
8861
        check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
8862
      else
8863
        tmp = 0;
8864 209 tadejm
      if (tmp > 0)
8865
      begin
8866
        test_fail("Wrong CRC of the transmitted packet");
8867
        fail = fail + 1;
8868
      end
8869
      // check WB INT signal
8870
      if (wb_int !== 1'b1)
8871
      begin
8872
        `TIME; $display("*E WB INT signal should be set");
8873
        test_fail("WB INT signal should be set");
8874
        fail = fail + 1;
8875
      end
8876
      // check TX buffer descriptor of a packet
8877
      check_tx_bd(num_of_bd, data);
8878
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
8879
           ((data[15:0] !== 16'h5800) && (num_of_bd < 2)) )   // without wrap bit
8880
      begin
8881
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
8882
        test_fail("TX buffer descriptor status is not correct");
8883
        fail = fail + 1;
8884
      end
8885
      // check interrupts
8886 274 tadejm
      wait (wbm_working == 0);
8887 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8888
      if ((data & `ETH_INT_TXB) !== 1'b1)
8889
      begin
8890
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
8891
        test_fail("Interrupt Transmit Buffer was not set");
8892
        fail = fail + 1;
8893
      end
8894
      if ((data & (~`ETH_INT_TXB)) !== 0)
8895
      begin
8896
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
8897
        test_fail("Other interrupts (except Transmit Buffer) were set");
8898
        fail = fail + 1;
8899
      end
8900
      // clear interrupts
8901 274 tadejm
      wait (wbm_working == 0);
8902 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8903
      // check WB INT signal
8904
      if (wb_int !== 1'b0)
8905
      begin
8906
        test_fail("WB INT signal should not be set");
8907
        fail = fail + 1;
8908
      end
8909
      // INTERMEDIATE DISPLAYS
8910
      if (num_of_bd == 0)
8911
        $display("    ->packet with length %0d sent", (i_length + 4));
8912
      else if (num_of_bd == 1)
8913
        $display("    ->packet with length %0d sent", (i_length + 4));
8914
      else if (num_of_bd == 2)
8915
        $display("    ->packet with length %0d sent", (i_length + 4));
8916
      // set length (loop variable)
8917
      i_length = i_length + 1;
8918
      // the number of frame transmitted
8919
      num_of_frames = num_of_frames + 1;
8920
      num_of_bd = num_of_bd + 1;
8921
      @(posedge wb_clk);
8922
    end
8923
    // disable TX
8924 274 tadejm
    wait (wbm_working == 0);
8925 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
8926
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8927
    @(posedge wb_clk);
8928
    if(fail == 0)
8929
      test_ok;
8930
    else
8931
      fail = 0;
8932
  end
8933
 
8934
 
8935
  ////////////////////////////////////////////////////////////////////
8936
  ////                                                            ////
8937
  ////  Test transmit packets across changed MINFL value at       ////
8938
  ////  7 TX buffer decriptors ( 100Mbps ).                       ////
8939
  ////                                                            ////
8940
  ////////////////////////////////////////////////////////////////////
8941
  if (test_num == 15) // without and with padding
8942
  begin
8943
    // TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )
8944
    test_name = "TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )";
8945
    `TIME; $display("  TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )");
8946
 
8947
    hard_reset;
8948 279 mohor
 
8949 209 tadejm
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
8950
 
8951
    max_tmp = 0;
8952
    min_tmp = 0;
8953
    num_of_frames = 0;
8954
    num_of_bd = 0;
8955
    // set 7 TX buffer descriptors - must be set before TX enable
8956 274 tadejm
    wait (wbm_working == 0);
8957 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h7, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8958
    // prepare a packet of MAXFL + 10 length
8959 274 tadejm
    wait (wbm_working == 0);
8960 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8961
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
8962
    min_tmp = tmp[31:16];
8963
    // change MINFL value
8964
    min_tmp = max_tmp - 177;
8965 274 tadejm
    wait (wbm_working == 0);
8966 209 tadejm
    wbm_write(`ETH_PACKETLEN, {min_tmp, max_tmp}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8967
    st_data = 8'h62;
8968
    set_tx_packet(`MEMORY_BASE, min_tmp, st_data); // length without CRC
8969
    // enable TX, set full-duplex mode, padding and CRC appending
8970 274 tadejm
    wait (wbm_working == 0);
8971 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
8972
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8973
    // check WB INT signal
8974
    if (wb_int !== 1'b0)
8975
    begin
8976
      test_fail("WB INT signal should not be set");
8977
      fail = fail + 1;
8978
    end
8979
 
8980
    // write to phy's control register for 100Mbps
8981
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
8982
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
8983
    speed = 100;
8984
 
8985
    i_length = (min_tmp - 5);
8986
    while (i_length <= (min_tmp - 3)) // (min_tmp - 4) is the limit
8987
    begin
8988
      // Reset_tx_bd nable interrupt generation
8989
      // unmask interrupts
8990 274 tadejm
      wait (wbm_working == 0);
8991 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
8992
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8993
      // not detect carrier sense in FD and no collision
8994
      eth_phy.carrier_sense_tx_fd_detect(0);
8995
      eth_phy.collision(0);
8996
      // first destination address on ethernet PHY
8997
      eth_phy.set_tx_mem_addr(0);
8998
      // prepare BDs
8999
      if (num_of_bd == 0)
9000
      begin
9001
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9002
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9003
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9004
        set_tx_bd_wrap(2);
9005
        set_tx_bd_ready(0, 0);
9006
      end
9007
      else if (num_of_bd == 1)
9008
        set_tx_bd_ready(1, 1);
9009
      else if (num_of_bd == 2)
9010
        set_tx_bd_ready(2, 2);
9011
      // CHECK END OF TRANSMITION
9012
      check_tx_bd(num_of_bd, data);
9013
        wait (MTxEn === 1'b1); // start transmit
9014
      check_tx_bd(num_of_bd, data);
9015
        if (data[15] !== 1)
9016
        begin
9017
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
9018
          fail = fail + 1;
9019
        end
9020
        wait (MTxEn === 1'b0); // end transmit
9021
        while (data[15] === 1)
9022
        begin
9023
      check_tx_bd(num_of_bd, data);
9024
          @(posedge wb_clk);
9025
        end
9026
        repeat (1) @(posedge wb_clk);
9027
      // check length of a PACKET
9028
      tmp_len = eth_phy.tx_len;
9029
      #1;
9030
      if (tmp_len != (i_length + 4))
9031
      begin
9032
        test_fail("Wrong length of the packet out from MAC");
9033
        fail = fail + 1;
9034
      end
9035
      // checking packet
9036
      check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
9037
      if (tmp > 0)
9038
      begin
9039
        test_fail("Wrong data of the transmitted packet");
9040
        fail = fail + 1;
9041
      end
9042
      // check transmited TX packet CRC
9043 279 mohor
      if (num_of_bd !== 0)
9044
        check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
9045
      else
9046
        tmp = 0;
9047
 
9048 209 tadejm
      if (tmp > 0)
9049
      begin
9050
        test_fail("Wrong CRC of the transmitted packet");
9051
        fail = fail + 1;
9052
      end
9053
      // check WB INT signal
9054
      if (wb_int !== 1'b1)
9055
      begin
9056
        `TIME; $display("*E WB INT signal should be set");
9057
        test_fail("WB INT signal should be set");
9058
        fail = fail + 1;
9059
      end
9060
      // check TX buffer descriptor of a packet
9061
      check_tx_bd(num_of_bd, data);
9062
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
9063
           ((data[15:0] !== 16'h5800) && (num_of_bd < 2)) )   // without wrap bit
9064
      begin
9065
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
9066
        test_fail("TX buffer descriptor status is not correct");
9067
        fail = fail + 1;
9068
      end
9069
      // check interrupts
9070 274 tadejm
      wait (wbm_working == 0);
9071 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9072
      if ((data & `ETH_INT_TXB) !== 1'b1)
9073
      begin
9074
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
9075
        test_fail("Interrupt Transmit Buffer was not set");
9076
        fail = fail + 1;
9077
      end
9078
      if ((data & (~`ETH_INT_TXB)) !== 0)
9079
      begin
9080
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
9081
        test_fail("Other interrupts (except Transmit Buffer) were set");
9082
        fail = fail + 1;
9083
      end
9084
      // clear interrupts
9085 274 tadejm
      wait (wbm_working == 0);
9086 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9087
      // check WB INT signal
9088
      if (wb_int !== 1'b0)
9089
      begin
9090
        test_fail("WB INT signal should not be set");
9091
        fail = fail + 1;
9092
      end
9093
      // INTERMEDIATE DISPLAYS
9094
      if (num_of_bd == 0)
9095
        $display("    ->packet with length %0d sent", (i_length + 4));
9096
      else if (num_of_bd == 1)
9097
        $display("    ->packet with length %0d sent", (i_length + 4));
9098
      else if (num_of_bd == 2)
9099
        $display("    ->packet with length %0d sent", (i_length + 4));
9100
      // set length (loop variable)
9101
      i_length = i_length + 1;
9102
      // the number of frame transmitted
9103
      num_of_frames = num_of_frames + 1;
9104
      num_of_bd = num_of_bd + 1;
9105
      @(posedge wb_clk);
9106
    end
9107
    // disable TX
9108 274 tadejm
    wait (wbm_working == 0);
9109 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
9110
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9111
    @(posedge wb_clk);
9112
    if(fail == 0)
9113
      test_ok;
9114
    else
9115
      fail = 0;
9116
  end
9117
 
9118
 
9119
  ////////////////////////////////////////////////////////////////////
9120
  ////                                                            ////
9121
  ////  Test transmit packets across MAXFL with HUGEN at          ////
9122
  ////  19 TX buffer decriptors ( 10Mbps ).                       ////
9123
  ////                                                            ////
9124
  ////////////////////////////////////////////////////////////////////
9125
  if (test_num == 16) // without and with padding
9126
  begin
9127
    // TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps )
9128
    test_name = "TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps )";
9129
    `TIME; $display("  TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps )");
9130
 
9131
    // reset MAC registers
9132
    hard_reset;
9133
    // reset MAC and MII LOGIC with soft reset
9134 274 tadejm
//    reset_mac;
9135
//    reset_mii;
9136 209 tadejm
    // set wb slave response
9137
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
9138
 
9139
    max_tmp = 0;
9140
    min_tmp = 0;
9141
    num_of_frames = 0;
9142
    num_of_bd = 0;
9143
    // set 19 TX buffer descriptors - must be set before TX enable
9144 274 tadejm
    wait (wbm_working == 0);
9145 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h13, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9146
    // prepare a packet of 64k - 1 length (16'hFFFF)
9147 274 tadejm
    wait (wbm_working == 0);
9148 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9149
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
9150
    min_tmp = tmp[31:16];
9151
    st_data = 8'h8D;
9152
    set_tx_packet(`MEMORY_BASE, 16'hFFFF, st_data); // length with CRC
9153
    // enable TX, set full-duplex mode, NO padding, CRC appending and huge enabled
9154 274 tadejm
    wait (wbm_working == 0);
9155 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN | `ETH_MODER_HUGEN,
9156
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9157
    // check WB INT signal
9158
    if (wb_int !== 1'b0)
9159
    begin
9160
      test_fail("WB INT signal should not be set");
9161
      fail = fail + 1;
9162
    end
9163
 
9164
    // write to phy's control register for 10Mbps
9165
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
9166
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
9167
    speed = 10;
9168
 
9169
    i_length = (max_tmp - 5); // (max_tmp - 4) is the MAXFL limit
9170
    while (i_length <= (16'hFFFF - 4)) // (16'hFFFF - 4) is the limit
9171
    begin
9172
      $display("   i_length = %0d", i_length);
9173
      // Reset_tx_bd nable interrupt generation
9174
      // unmask interrupts
9175 274 tadejm
      wait (wbm_working == 0);
9176 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
9177
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9178
      // not detect carrier sense in FD and no collision
9179
      eth_phy.carrier_sense_tx_fd_detect(0);
9180
      eth_phy.collision(0);
9181
      // first destination address on ethernet PHY
9182
      eth_phy.set_tx_mem_addr(0);
9183
      // prepare BDs
9184
      if (num_of_bd == 0)
9185
      begin
9186
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9187
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9188
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9189
        set_tx_bd(3, 3, (16'hFFFF - 5), 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9190
        set_tx_bd(4, 4, (16'hFFFF - 4), 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9191
        set_tx_bd_wrap(4);
9192
        set_tx_bd_ready(0, 0);
9193
      end
9194
      else if (num_of_bd == 1)
9195
        set_tx_bd_ready(1, 1);
9196
      else if (num_of_bd == 2)
9197
        set_tx_bd_ready(2, 2);
9198
      else if (num_of_bd == 3)
9199
        set_tx_bd_ready(3, 3);
9200
      else if (num_of_bd == 4)
9201
        set_tx_bd_ready(4, 4);
9202
      // CHECK END OF TRANSMITION
9203
      check_tx_bd(num_of_bd, data);
9204
        wait (MTxEn === 1'b1); // start transmit
9205
      check_tx_bd(num_of_bd, data);
9206
        if (data[15] !== 1)
9207
        begin
9208
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
9209
          fail = fail + 1;
9210
        end
9211
        wait (MTxEn === 1'b0); // end transmit
9212
        while (data[15] === 1)
9213
        begin
9214
      check_tx_bd(num_of_bd, data);
9215
          @(posedge wb_clk);
9216
        end
9217
        repeat (1) @(posedge wb_clk);
9218
      // check length of a PACKET
9219
      $display("   eth_phy length = %0d", eth_phy.tx_len);
9220
      tmp_len = eth_phy.tx_len;
9221
      #1;
9222
      if (tmp_len != (i_length + 4))
9223
      begin
9224
        test_fail("Wrong length of the packet out from MAC");
9225
        fail = fail + 1;
9226
      end
9227
      // checking packet
9228
      check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
9229
      if (tmp > 0)
9230
      begin
9231
        test_fail("Wrong data of the transmitted packet");
9232
        fail = fail + 1;
9233
      end
9234
      // check transmited TX packet CRC
9235
      check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
9236
      if (tmp > 0)
9237
      begin
9238
        test_fail("Wrong CRC of the transmitted packet");
9239
        fail = fail + 1;
9240
      end
9241
      // check WB INT signal
9242
      if (wb_int !== 1'b1)
9243
      begin
9244
        `TIME; $display("*E WB INT signal should be set");
9245
        test_fail("WB INT signal should be set");
9246
        fail = fail + 1;
9247
      end
9248
      // check TX buffer descriptor of a packet
9249
      check_tx_bd(num_of_bd, data);
9250
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 4)) || // wrap bit
9251
           ((data[15:0] !== 16'h5800) && (num_of_bd < 4)) )   // without wrap bit
9252
      begin
9253
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
9254
        test_fail("TX buffer descriptor status is not correct");
9255
        fail = fail + 1;
9256
      end
9257
      // check interrupts
9258 274 tadejm
      wait (wbm_working == 0);
9259 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9260
      if ((data & `ETH_INT_TXB) !== 1'b1)
9261
      begin
9262
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
9263
        test_fail("Interrupt Transmit Buffer was not set");
9264
        fail = fail + 1;
9265
      end
9266
      if ((data & (~`ETH_INT_TXB)) !== 0)
9267
      begin
9268
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
9269
        test_fail("Other interrupts (except Transmit Buffer) were set");
9270
        fail = fail + 1;
9271
      end
9272
      // clear interrupts
9273 274 tadejm
      wait (wbm_working == 0);
9274 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9275
      // check WB INT signal
9276
      if (wb_int !== 1'b0)
9277
      begin
9278
        test_fail("WB INT signal should not be set");
9279
        fail = fail + 1;
9280
      end
9281
      // INTERMEDIATE DISPLAYS
9282
      $display("    ->packet with length %0d sent", (i_length + 4));
9283
      // set length (loop variable)
9284
      if ((num_of_bd < 2) || (num_of_bd >= 3))
9285
        i_length = i_length + 1;
9286
      else if (num_of_bd == 2)
9287
        i_length = (16'hFFFF - 5);
9288
      // the number of frame transmitted
9289
      num_of_frames = num_of_frames + 1;
9290
      num_of_bd = num_of_bd + 1;
9291
      @(posedge wb_clk);
9292
    end
9293
    // disable TX
9294 274 tadejm
    wait (wbm_working == 0);
9295 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
9296
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9297
    @(posedge wb_clk);
9298
    if(fail == 0)
9299
      test_ok;
9300
    else
9301
      fail = 0;
9302
  end
9303
 
9304
 
9305
  ////////////////////////////////////////////////////////////////////
9306
  ////                                                            ////
9307
  ////  Test transmit packets across MAXFL with HUGEN at          ////
9308
  ////  19 TX buffer decriptors ( 100Mbps ).                      ////
9309
  ////                                                            ////
9310
  ////////////////////////////////////////////////////////////////////
9311
  if (test_num == 17) // without and with padding
9312
  begin
9313
    // TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps )
9314
    test_name = "TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps )";
9315
    `TIME; $display("  TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps )");
9316
 
9317
    // reset MAC registers
9318
    hard_reset;
9319
    // reset MAC and MII LOGIC with soft reset
9320 274 tadejm
//    reset_mac;
9321
//    reset_mii;
9322 209 tadejm
    // set wb slave response
9323
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
9324
 
9325
    max_tmp = 0;
9326
    min_tmp = 0;
9327
    num_of_frames = 0;
9328
    num_of_bd = 0;
9329
    // set 19 TX buffer descriptors - must be set before TX enable
9330 274 tadejm
    wait (wbm_working == 0);
9331 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h13, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9332
    // prepare a packet of 64k - 1 length (16'hFFFF)
9333 274 tadejm
    wait (wbm_working == 0);
9334 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9335
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
9336
    min_tmp = tmp[31:16];
9337
    st_data = 8'h8D;
9338
    set_tx_packet(`MEMORY_BASE, 16'hFFFF, st_data); // length with CRC
9339
    // enable TX, set full-duplex mode, NO padding, CRC appending and huge enabled
9340 274 tadejm
    wait (wbm_working == 0);
9341 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN | `ETH_MODER_HUGEN,
9342
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9343
    // check WB INT signal
9344
    if (wb_int !== 1'b0)
9345
    begin
9346
      test_fail("WB INT signal should not be set");
9347
      fail = fail + 1;
9348
    end
9349
 
9350
    // write to phy's control register for 100Mbps
9351
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
9352
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
9353
    speed = 100;
9354
 
9355
    i_length = (max_tmp - 5); // (max_tmp - 4) is the MAXFL limit
9356
    while (i_length <= (16'hFFFF - 4)) // (16'hFFFF - 4) is the limit
9357
    begin
9358
      $display("   i_length = %0d", i_length);
9359
      // Reset_tx_bd nable interrupt generation
9360
      // unmask interrupts
9361 274 tadejm
      wait (wbm_working == 0);
9362 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
9363
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9364
      // not detect carrier sense in FD and no collision
9365
      eth_phy.carrier_sense_tx_fd_detect(0);
9366
      eth_phy.collision(0);
9367
      // first destination address on ethernet PHY
9368
      eth_phy.set_tx_mem_addr(0);
9369
      // prepare BDs
9370
      if (num_of_bd == 0)
9371
      begin
9372
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9373
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9374
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9375
        set_tx_bd(3, 3, (16'hFFFF - 5), 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9376
        set_tx_bd(4, 4, (16'hFFFF - 4), 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9377
        set_tx_bd_wrap(4);
9378
        set_tx_bd_ready(0, 0);
9379
      end
9380
      else if (num_of_bd == 1)
9381
        set_tx_bd_ready(1, 1);
9382
      else if (num_of_bd == 2)
9383
        set_tx_bd_ready(2, 2);
9384
      else if (num_of_bd == 3)
9385
        set_tx_bd_ready(3, 3);
9386
      else if (num_of_bd == 4)
9387
        set_tx_bd_ready(4, 4);
9388
      // CHECK END OF TRANSMITION
9389
      check_tx_bd(num_of_bd, data);
9390
        wait (MTxEn === 1'b1); // start transmit
9391
      check_tx_bd(num_of_bd, data);
9392
        if (data[15] !== 1)
9393
        begin
9394
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
9395
          fail = fail + 1;
9396
        end
9397
        wait (MTxEn === 1'b0); // end transmit
9398
        while (data[15] === 1)
9399
        begin
9400
      check_tx_bd(num_of_bd, data);
9401
          @(posedge wb_clk);
9402
        end
9403
        repeat (1) @(posedge wb_clk);
9404
      // check length of a PACKET
9405
      $display("   eth_phy length = %0d", eth_phy.tx_len);
9406
      tmp_len = eth_phy.tx_len;
9407
      #1;
9408
      if (tmp_len != (i_length + 4))
9409
      begin
9410
        test_fail("Wrong length of the packet out from MAC");
9411
        fail = fail + 1;
9412
      end
9413
      // checking packet
9414
      check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
9415
      if (tmp > 0)
9416
      begin
9417
        test_fail("Wrong data of the transmitted packet");
9418
        fail = fail + 1;
9419
      end
9420
      // check transmited TX packet CRC
9421
      check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
9422
      if (tmp > 0)
9423
      begin
9424
        test_fail("Wrong CRC of the transmitted packet");
9425
        fail = fail + 1;
9426
      end
9427
      // check WB INT signal
9428
      if (wb_int !== 1'b1)
9429
      begin
9430
        `TIME; $display("*E WB INT signal should be set");
9431
        test_fail("WB INT signal should be set");
9432
        fail = fail + 1;
9433
      end
9434
      // check TX buffer descriptor of a packet
9435
      check_tx_bd(num_of_bd, data);
9436
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 4)) || // wrap bit
9437
           ((data[15:0] !== 16'h5800) && (num_of_bd < 4)) )   // without wrap bit
9438
      begin
9439
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
9440
        test_fail("TX buffer descriptor status is not correct");
9441
        fail = fail + 1;
9442
      end
9443
      // check interrupts
9444 274 tadejm
      wait (wbm_working == 0);
9445 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9446
      if ((data & `ETH_INT_TXB) !== 1'b1)
9447
      begin
9448
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
9449
        test_fail("Interrupt Transmit Buffer was not set");
9450
        fail = fail + 1;
9451
      end
9452
      if ((data & (~`ETH_INT_TXB)) !== 0)
9453
      begin
9454
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
9455
        test_fail("Other interrupts (except Transmit Buffer) were set");
9456
        fail = fail + 1;
9457
      end
9458
      // clear interrupts
9459 274 tadejm
      wait (wbm_working == 0);
9460 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9461
      // check WB INT signal
9462
      if (wb_int !== 1'b0)
9463
      begin
9464
        test_fail("WB INT signal should not be set");
9465
        fail = fail + 1;
9466
      end
9467
      // INTERMEDIATE DISPLAYS
9468
      $display("    ->packet with length %0d sent", (i_length + 4));
9469
      // set length (loop variable)
9470
      if ((num_of_bd < 2) || (num_of_bd >= 3))
9471
        i_length = i_length + 1;
9472
      else if (num_of_bd == 2)
9473
        i_length = (16'hFFFF - 5);
9474
      // the number of frame transmitted
9475
      num_of_frames = num_of_frames + 1;
9476
      num_of_bd = num_of_bd + 1;
9477
      @(posedge wb_clk);
9478
    end
9479
    // disable TX
9480 274 tadejm
    wait (wbm_working == 0);
9481 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
9482
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9483
    @(posedge wb_clk);
9484
    if(fail == 0)
9485
      test_ok;
9486
    else
9487
      fail = 0;
9488
  end
9489
 
9490
 
9491
  ////////////////////////////////////////////////////////////////////
9492
  ////                                                            ////
9493
  ////  Test IPG during Back-to-Back transmit at                  ////
9494
  ////  88 TX buffer decriptors ( 10Mbps ).                       ////
9495
  ////                                                            ////
9496
  ////////////////////////////////////////////////////////////////////
9497
  if (test_num == 18) // without and with padding
9498
  begin
9499
    // TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps )
9500
    test_name = "TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps )";
9501
    `TIME; $display("  TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps )");
9502
 
9503
    // reset MAC registers
9504
    hard_reset;
9505
    // reset MAC and MII LOGIC with soft reset
9506 274 tadejm
//    reset_mac;
9507
//    reset_mii;
9508 209 tadejm
    // set wb slave response
9509
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
9510
 
9511
    max_tmp = 0;
9512
    min_tmp = 0;
9513
    num_of_frames = 0;
9514
    num_of_bd = 0;
9515
    tmp_ipgt = 0;
9516
    // set 88 TX buffer descriptors - must be set before TX enable
9517 274 tadejm
    wait (wbm_working == 0);
9518 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h58, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9519
    // enable TX, set full-duplex mode, NO padding and CRC appending
9520 274 tadejm
    wait (wbm_working == 0);
9521 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
9522
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9523
    // prepare two packets of MAXFL length
9524 274 tadejm
    wait (wbm_working == 0);
9525 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9526
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
9527
    min_tmp = tmp[31:16];
9528
    st_data = 8'h29;
9529
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
9530
    // check WB INT signal
9531
    if (wb_int !== 1'b0)
9532
    begin
9533
      test_fail("WB INT signal should not be set");
9534
      fail = fail + 1;
9535
    end
9536
 
9537
    // write to phy's control register for 10Mbps
9538
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
9539
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
9540
    speed = 10;
9541
 
9542
    i_length = (min_tmp - 4);
9543
    while (i_length < (max_tmp - 4))
9544
    begin
9545
      // disable TX, set full-duplex mode, NO padding and CRC appending
9546 274 tadejm
      wait (wbm_working == 0);
9547 209 tadejm
      wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
9548
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9549
      // set IPGT register
9550 274 tadejm
      wait (wbm_working == 0);
9551 209 tadejm
      wbm_write(`ETH_IPGT, tmp_ipgt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9552
      // enable TX, set full-duplex mode, NO padding and CRC appending
9553 274 tadejm
      wait (wbm_working == 0);
9554 209 tadejm
      wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
9555
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9556
      // Reset_tx_bd enable interrupt generation
9557
      // unmask interrupts
9558 274 tadejm
      wait (wbm_working == 0);
9559 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
9560
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9561
      // not detect carrier sense in FD and no collision
9562
      eth_phy.carrier_sense_tx_fd_detect(0);
9563
      eth_phy.collision(0);
9564
      // first destination address on ethernet PHY
9565
      eth_phy.set_tx_mem_addr(0);
9566
      // prepare BDs
9567
      if (num_of_bd == 0)
9568
      begin
9569
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9570
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9571
        set_tx_bd_wrap(1);
9572
        set_tx_bd_ready(0, 0);
9573
        set_tx_bd_ready(1, 1);
9574
      end
9575
      // CHECK END OF TWO TRANSMITIONs
9576
      // wait for first transmit to end
9577
      check_tx_bd(num_of_bd, data);
9578
      wait (MTxEn === 1'b1); // start transmit
9579
      if (data[15] !== 1)
9580
      begin
9581
        test_fail("Wrong buffer descriptor's ready bit read out from MAC");
9582
        fail = fail + 1;
9583
      end
9584
      wait (MTxEn === 1'b0); // end transmit
9585
      num_of_frames = num_of_frames + 1;
9586
      num_of_bd = num_of_bd + 1;
9587
      #Tp;
9588
      // destination address on ethernet PHY
9589
      eth_phy.set_tx_mem_addr(0);
9590
      i1 = 0;
9591
      i2 = 0;
9592
      // count IPG clock periods
9593
      fork
9594
        begin
9595
          wait (MTxEn === 1'b1); // start second transmit
9596
          #Tp;
9597
          disable count_rising;
9598
          disable count_falling;
9599
        end
9600
        begin: count_rising
9601
          forever
9602
          begin
9603
            @(posedge mtx_clk);
9604
            i1 = i1 + 1;
9605
            #Tp;
9606
          end
9607
        end
9608
        begin: count_falling
9609
          forever
9610
          begin
9611
            @(negedge mtx_clk);
9612
            i2 = i2 + 1;
9613
            #Tp;
9614
          end
9615
        end
9616
      join
9617
      // check IPG length - INTERMEDIATE DISPLAYS
9618
      if((i1 == i2) && (i1 >= (tmp_ipgt + 3)))
9619
      begin
9620
        $display("    ->IPG with %0d mtx_clk periods (min %0d) between packets with lengths %0d and %0d checked",
9621
                  i1, (tmp_ipgt + 3), (i_length + 4), (i_length + 4 + 1));
9622
      end
9623
      else
9624
      begin
9625
        `TIME; $display("*E IPG is not correct: (%0d + %0d) / 2, requested: %d", i1, i2, (tmp_ipgt + 3));
9626
        fail = fail + 1;
9627
        test_fail("IPG is not correct");
9628
      end
9629
      // wait for second transmit to end
9630
      wait (MTxEn === 1'b0); // end second transmit
9631
      while (data[15] === 1)
9632
      begin
9633
        check_tx_bd(num_of_bd, data);
9634
        @(posedge wb_clk);
9635
      end
9636
      repeat (1) @(posedge wb_clk);
9637
      // check length of a second PACKET
9638
      tmp_len = eth_phy.tx_len;
9639
      #1;
9640
      if (tmp_len != (i_length + 4 + 1))
9641
      begin
9642
        test_fail("Wrong length of second packet out from MAC");
9643
        fail = fail + 1;
9644
      end
9645
      // checking second packet
9646
      check_tx_packet(`MEMORY_BASE, 0, (i_length + 1), tmp);
9647
      if (tmp > 0)
9648
      begin
9649
        test_fail("Wrong data of second transmitted packet");
9650
        fail = fail + 1;
9651
      end
9652
      // check second transmited TX packet CRC
9653
      check_tx_crc(0, (i_length + 1), 1'b0, tmp); // length without CRC
9654
      if (tmp > 0)
9655
      begin
9656
        test_fail("Wrong CRC of second transmitted packet");
9657
        fail = fail + 1;
9658
      end
9659
      // check WB INT signal
9660
      if (wb_int !== 1'b1)
9661
      begin
9662
        `TIME; $display("*E WB INT signal should be set");
9663
        test_fail("WB INT signal should be set");
9664
        fail = fail + 1;
9665
      end
9666
      // check TX buffer descriptor of a packet
9667
      check_tx_bd(num_of_bd, data);
9668
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // wrap bit
9669
           ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // without wrap bit
9670
      begin
9671
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
9672
        test_fail("TX buffer descriptor status is not correct");
9673
        fail = fail + 1;
9674
      end
9675
      // check interrupts
9676 274 tadejm
      wait (wbm_working == 0);
9677 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9678
      if ((data & `ETH_INT_TXB) !== 1'b1)
9679
      begin
9680
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
9681
        test_fail("Interrupt Transmit Buffer was not set");
9682
        fail = fail + 1;
9683
      end
9684
      if ((data & (~`ETH_INT_TXB)) !== 0)
9685
      begin
9686
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
9687
        test_fail("Other interrupts (except Transmit Buffer) were set");
9688
        fail = fail + 1;
9689
      end
9690
      // clear interrupts
9691 274 tadejm
      wait (wbm_working == 0);
9692 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9693
      // check WB INT signal
9694
      if (wb_int !== 1'b0)
9695
      begin
9696
        test_fail("WB INT signal should not be set");
9697
        fail = fail + 1;
9698
      end
9699
      // set length (LOOP variable)
9700
      if ((tmp_ipgt + 3) < 130) // tmp_ipgt < 124
9701
        i_length = i_length + 2;
9702
      else
9703
        i_length = (max_tmp - 4);
9704
      // set IPGT
9705
      if ((tmp_ipgt + 3) < 10)
9706
        tmp_ipgt = tmp_ipgt + 1;
9707
      else if ((tmp_ipgt + 3) < 24)
9708
        tmp_ipgt = tmp_ipgt + 7;
9709
      else if ((tmp_ipgt + 3) == 24)
9710
        tmp_ipgt = 38 - 3;
9711
      else if ((tmp_ipgt + 3) == 38)
9712
        tmp_ipgt = 72 - 3;
9713
      else if ((tmp_ipgt + 3) == 72)
9714
        tmp_ipgt = 130 - 3; // 124 - 3
9715
      // the number of frame transmitted
9716
      num_of_frames = num_of_frames + 1;
9717
      num_of_bd = 0;
9718
      @(posedge wb_clk);
9719
    end
9720
    // disable TX
9721 274 tadejm
    wait (wbm_working == 0);
9722 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
9723
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9724
    @(posedge wb_clk);
9725
    if(fail == 0)
9726
      test_ok;
9727
    else
9728
      fail = 0;
9729
  end
9730
 
9731
 
9732
  ////////////////////////////////////////////////////////////////////
9733
  ////                                                            ////
9734
  ////  Test IPG during Back-to-Back transmit at                  ////
9735
  ////  88 TX buffer decriptors ( 100Mbps ).                      ////
9736
  ////                                                            ////
9737
  ////////////////////////////////////////////////////////////////////
9738
  if (test_num == 19) // without and with padding
9739
  begin
9740
    // TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps )
9741
    test_name = "TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps )";
9742
    `TIME; $display("  TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps )");
9743
 
9744
    // reset MAC registers
9745
    hard_reset;
9746
    // reset MAC and MII LOGIC with soft reset
9747 274 tadejm
//    reset_mac;
9748
//    reset_mii;
9749 209 tadejm
    // set wb slave response
9750
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
9751
 
9752
    max_tmp = 0;
9753
    min_tmp = 0;
9754
    num_of_frames = 0;
9755
    num_of_bd = 0;
9756
    tmp_ipgt = 0;
9757
    // set 88 TX buffer descriptors - must be set before TX enable
9758 274 tadejm
    wait (wbm_working == 0);
9759 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h58, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9760
    // enable TX, set full-duplex mode, NO padding and CRC appending
9761 274 tadejm
    wait (wbm_working == 0);
9762 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
9763
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9764
    // prepare two packets of MAXFL length
9765 274 tadejm
    wait (wbm_working == 0);
9766 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9767
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
9768
    min_tmp = tmp[31:16];
9769
    st_data = 8'h29;
9770
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
9771
    // check WB INT signal
9772
    if (wb_int !== 1'b0)
9773
    begin
9774
      test_fail("WB INT signal should not be set");
9775
      fail = fail + 1;
9776
    end
9777
 
9778
    // write to phy's control register for 100Mbps
9779
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
9780
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
9781
    speed = 100;
9782
 
9783
    i_length = (min_tmp - 4);
9784
    while (i_length < (max_tmp - 4))
9785
    begin
9786
      // disable TX, set full-duplex mode, NO padding and CRC appending
9787 274 tadejm
      wait (wbm_working == 0);
9788 209 tadejm
      wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
9789
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9790
      // set IPGT register
9791 274 tadejm
      wait (wbm_working == 0);
9792 209 tadejm
      wbm_write(`ETH_IPGT, tmp_ipgt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9793
      // enable TX, set full-duplex mode, NO padding and CRC appending
9794 274 tadejm
      wait (wbm_working == 0);
9795 209 tadejm
      wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
9796
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9797
      // Reset_tx_bd enable interrupt generation
9798
      // unmask interrupts
9799 274 tadejm
      wait (wbm_working == 0);
9800 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
9801
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9802
      // not detect carrier sense in FD and no collision
9803
      eth_phy.carrier_sense_tx_fd_detect(0);
9804
      eth_phy.collision(0);
9805
      // first destination address on ethernet PHY
9806
      eth_phy.set_tx_mem_addr(0);
9807
      // prepare BDs
9808
      if (num_of_bd == 0)
9809
      begin
9810
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9811
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9812
        set_tx_bd_wrap(1);
9813
        set_tx_bd_ready(0, 0);
9814
        set_tx_bd_ready(1, 1);
9815
      end
9816
      // CHECK END OF TWO TRANSMITIONs
9817
      // wait for first transmit to end
9818
      check_tx_bd(num_of_bd, data);
9819
      wait (MTxEn === 1'b1); // start transmit
9820
      if (data[15] !== 1)
9821
      begin
9822
        test_fail("Wrong buffer descriptor's ready bit read out from MAC");
9823
        fail = fail + 1;
9824
      end
9825
      wait (MTxEn === 1'b0); // end transmit
9826
      num_of_frames = num_of_frames + 1;
9827
      num_of_bd = num_of_bd + 1;
9828
      #Tp;
9829
      // destination address on ethernet PHY
9830
      eth_phy.set_tx_mem_addr(0);
9831
      i1 = 0;
9832
      i2 = 0;
9833
      // count IPG clock periods
9834
      fork
9835
        begin
9836
          wait (MTxEn === 1'b1); // start second transmit
9837
          #Tp;
9838
          disable count_rising1;
9839
          disable count_falling1;
9840
        end
9841
        begin: count_rising1
9842
          forever
9843
          begin
9844
            @(posedge mtx_clk);
9845
            i1 = i1 + 1;
9846
            #Tp;
9847
          end
9848
        end
9849
        begin: count_falling1
9850
          forever
9851
          begin
9852
            @(negedge mtx_clk);
9853
            i2 = i2 + 1;
9854
            #Tp;
9855
          end
9856
        end
9857
      join
9858
      // check IPG length - INTERMEDIATE DISPLAYS
9859
      if((i1 == i2) && (i1 >= (tmp_ipgt + 3)))
9860
      begin
9861
        $display("    ->IPG with %0d mtx_clk periods (min %0d) between packets with lengths %0d and %0d checked",
9862
                  i1, (tmp_ipgt + 3), (i_length + 4), (i_length + 4 + 1));
9863
      end
9864
      else
9865
      begin
9866
        `TIME; $display("*E IPG is not correct: (%0d + %0d) / 2, requested: %d", i1, i2, (tmp_ipgt + 3));
9867
        fail = fail + 1;
9868
        test_fail("IPG is not correct");
9869
      end
9870
      // wait for second transmit to end
9871
      wait (MTxEn === 1'b0); // end second transmit
9872
      while (data[15] === 1)
9873
      begin
9874
        check_tx_bd(num_of_bd, data);
9875
        @(posedge wb_clk);
9876
      end
9877
      repeat (1) @(posedge wb_clk);
9878
      // check length of a second PACKET
9879
      tmp_len = eth_phy.tx_len;
9880
      #1;
9881
      if (tmp_len != (i_length + 4 + 1))
9882
      begin
9883
        test_fail("Wrong length of second packet out from MAC");
9884
        fail = fail + 1;
9885
      end
9886
      // checking second packet
9887
      check_tx_packet(`MEMORY_BASE, 0, (i_length + 1), tmp);
9888
      if (tmp > 0)
9889
      begin
9890
        test_fail("Wrong data of second transmitted packet");
9891
        fail = fail + 1;
9892
      end
9893
      // check second transmited TX packet CRC
9894
      check_tx_crc(0, (i_length + 1), 1'b0, tmp); // length without CRC
9895
      if (tmp > 0)
9896
      begin
9897
        test_fail("Wrong CRC of second transmitted packet");
9898
        fail = fail + 1;
9899
      end
9900
      // check WB INT signal
9901
      if (wb_int !== 1'b1)
9902
      begin
9903
        `TIME; $display("*E WB INT signal should be set");
9904
        test_fail("WB INT signal should be set");
9905
        fail = fail + 1;
9906
      end
9907
      // check TX buffer descriptor of a packet
9908
      check_tx_bd(num_of_bd, data);
9909
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // wrap bit
9910
           ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // without wrap bit
9911
      begin
9912
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
9913
        test_fail("TX buffer descriptor status is not correct");
9914
        fail = fail + 1;
9915
      end
9916
      // check interrupts
9917 274 tadejm
      wait (wbm_working == 0);
9918 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9919
      if ((data & `ETH_INT_TXB) !== 1'b1)
9920
      begin
9921
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
9922
        test_fail("Interrupt Transmit Buffer was not set");
9923
        fail = fail + 1;
9924
      end
9925
      if ((data & (~`ETH_INT_TXB)) !== 0)
9926
      begin
9927
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
9928
        test_fail("Other interrupts (except Transmit Buffer) were set");
9929
        fail = fail + 1;
9930
      end
9931
      // clear interrupts
9932 274 tadejm
      wait (wbm_working == 0);
9933 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9934
      // check WB INT signal
9935
      if (wb_int !== 1'b0)
9936
      begin
9937
        test_fail("WB INT signal should not be set");
9938
        fail = fail + 1;
9939
      end
9940
      // set length (LOOP variable)
9941
      if ((tmp_ipgt + 3) < 130) // tmp_ipgt < 124
9942
        i_length = i_length + 2;
9943
      else
9944
        i_length = (max_tmp - 4);
9945
      // set IPGT
9946
      if ((tmp_ipgt + 3) < 10)
9947
        tmp_ipgt = tmp_ipgt + 1;
9948
      else if ((tmp_ipgt + 3) < 24)
9949
        tmp_ipgt = tmp_ipgt + 7;
9950
      else if ((tmp_ipgt + 3) == 24)
9951
        tmp_ipgt = 38 - 3;
9952
      else if ((tmp_ipgt + 3) == 38)
9953
        tmp_ipgt = 72 - 3;
9954
      else if ((tmp_ipgt + 3) == 72)
9955
        tmp_ipgt = 130 - 3; // 124 - 3
9956
      // the number of frame transmitted
9957
      num_of_frames = num_of_frames + 1;
9958
      num_of_bd = 0;
9959
      @(posedge wb_clk);
9960
    end
9961
    // disable TX
9962 274 tadejm
    wait (wbm_working == 0);
9963 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
9964
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9965
    @(posedge wb_clk);
9966
    if(fail == 0)
9967
      test_ok;
9968
    else
9969
      fail = 0;
9970
  end
9971
 
9972
 
9973
  ////////////////////////////////////////////////////////////////////
9974
  ////                                                            ////
9975
  ////  Test transmit packets after TX under-run on each packet's ////
9976
  ////  byte at 2 TX buffer decriptors ( 10Mbps ).                ////
9977
  ////                                                            ////
9978
  ////////////////////////////////////////////////////////////////////
9979
  if (test_num == 20) // without padding
9980
  begin
9981
    // TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps )
9982
    test_name = "TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps )";
9983
    `TIME;
9984
    $display("  TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps )");
9985
 
9986
    // reset MAC registers
9987
    hard_reset;
9988
    // set wb slave response
9989
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
9990
 
9991
    max_tmp = 0;
9992
    min_tmp = 0;
9993
    // set 2 TX buffer descriptors - must be set before TX enable
9994 274 tadejm
    wait (wbm_working == 0);
9995 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h2, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9996
    // enable TX, set full-duplex mode, NO padding and CRC appending
9997 274 tadejm
    wait (wbm_working == 0);
9998 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN |/* `ETH_MODER_PAD |*/ `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
9999
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10000
    // prepare a packet of MAXFL length
10001 274 tadejm
    wait (wbm_working == 0);
10002 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10003
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
10004
    min_tmp = tmp[31:16];
10005
    st_data = 8'h99;
10006
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
10007
    // read IPG value
10008 274 tadejm
    wait (wbm_working == 0);
10009 209 tadejm
    wbm_read(`ETH_IPGT, tmp_ipgt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10010
    // check WB INT signal
10011
    if (wb_int !== 1'b0)
10012
    begin
10013
      test_fail("WB INT signal should not be set");
10014
      fail = fail + 1;
10015
    end
10016
 
10017
    // write to phy's control register for 10Mbps
10018
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
10019
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
10020
    speed = 10;
10021
 
10022 279 mohor
    num_of_frames = 60; // (0..3) => start under-run on first word
10023 209 tadejm
    num_of_bd = 0;
10024
    i_data = 3; // (3) => one BYTE read in first word - FIRST byte
10025 279 mohor
    i_length = 80;
10026 209 tadejm
    while (i_length < (max_tmp - 4))
10027
    begin
10028
      // Reset_tx_bd enable interrupt generation
10029
      // unmask interrupts
10030 274 tadejm
      wait (wbm_working == 0);
10031 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
10032
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10033
      // not detect carrier sense in FD and no collision
10034
      eth_phy.carrier_sense_tx_fd_detect(0);
10035
      eth_phy.collision(0);
10036
      // first destination address on ethernet PHY
10037
      eth_phy.set_tx_mem_addr(0);
10038
      // prepare BDs
10039
      if (num_of_bd == 0)
10040
      begin
10041
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_data[1:0]));
10042
        set_tx_bd(1, 1, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
10043
        set_tx_bd_wrap(1);
10044
        // set wb slave response: ACK (response), wbs_waits[2:0] (waits before response), 
10045
        //                       wbs_retries[7:0] (RTYs before ACK if RTY response selected)
10046 223 tadejm
        #1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
10047 209 tadejm
        set_tx_bd_ready(1, 1);
10048
        set_tx_bd_ready(0, 0);
10049
      end
10050
      // frame under-run checking
10051
      frame_started = 0;
10052
      frame_ended = 0;
10053
      wait_for_frame = 0;
10054 279 mohor
      no_underrun = 0;
10055 209 tadejm
      fork
10056
        begin
10057
          // for every 4 frames bytes 1, 2, 3 and 4 respectively are read in first word => 1 ACK
10058
          // in other words 4 bytes are read, since length is MINFL => num_of_frames[31:2] ACKs
10059 279 mohor
          i = 0;
10060
          while (i <= (num_of_frames[31:2] + 1))
10061
          begin
10062
            @(negedge wb_clk);
10063
            if (eth_ma_wb_ack_i)
10064
            begin
10065
              i = i + 1;
10066
            end
10067
          end
10068 209 tadejm
          // set wb slave response: ACK (response), wbs_waits[2:0] (waits before response), 
10069
          //                       wbs_retries[7:0] (RTYs before ACK if RTY response selected)
10070 223 tadejm
          #1 wb_slave.cycle_response(`NO_RESPONSE, 3'h0, 8'hFF);
10071 209 tadejm
          // wait for synchronization and some additional clocks
10072
          wait_for_frame = 1;
10073
          // wait for frame
10074
          wait ((wait_for_frame == 0) || (frame_started == 1))
10075
          if ((wait_for_frame == 0) && (frame_started == 0)) // frame didn't start
10076
          begin
10077
            disable check_fr;
10078
          end
10079
          else if ((wait_for_frame == 1) && (frame_started == 1)) // frame started
10080
          begin
10081
            disable wait_fr;
10082 279 mohor
            if (frame_ended == 1)
10083
            begin
10084
              $display("(%0t) no under-run on %0d. byte, since length of frame (without CRC) is only %0d bytes",
10085
                        $time, ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])), i_length);
10086
              no_underrun = 1;
10087
            end
10088
            else
10089
            begin
10090
              wait (frame_ended == 1);
10091
              $display("(%0t) under-run on %0d. byte",
10092
                        $time, ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])));
10093
              no_underrun = 0;
10094
            end
10095 209 tadejm
          end
10096
          repeat (2) @(posedge wb_clk);
10097
          // set wb slave response: ACK (response), wbs_waits[2:0] (waits before response), 
10098
          //                       wbs_retries[7:0] (RTYs before ACK if RTY response selected)
10099 223 tadejm
          wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
10100 209 tadejm
        end
10101
        begin: wait_fr
10102
          wait (wait_for_frame == 1)
10103
          begin
10104
            // wait for synchronization and some additional clocks
10105
            repeat (3) @(posedge wb_clk);
10106
            repeat (2 * tmp_ipgt) @(posedge mtx_clk);
10107
            repeat (2) @(posedge wb_clk);
10108
            repeat (2) @(posedge mtx_clk);
10109
            wait_for_frame = 0;
10110
          end
10111
        end
10112
        begin: check_fr
10113
          // wait for frame to start
10114
          @(posedge MTxEn);
10115
          frame_started = 1;
10116
          // wait for frame to end due to under-run
10117
          @(negedge MTxEn);
10118
          frame_ended = 1;
10119
        end
10120
      join
10121 279 mohor
 
10122
      repeat (5) @ (posedge mtx_clk);
10123
 
10124 209 tadejm
      // wait for first transmit to end, if under-run didn't happen
10125
      if (frame_ended == 0)
10126
      begin
10127
        // WAIT FOR FIRST TRANSMIT
10128
        check_tx_bd(num_of_bd, data);
10129
        wait (MTxEn === 1'b1); // start first transmit
10130
        if (data[15] !== 1)
10131
        begin
10132
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
10133
          fail = fail + 1;
10134
        end
10135
        wait (MTxEn === 1'b0); // end first transmit
10136
        while (data[15] === 1)
10137
        begin
10138
          check_tx_bd(num_of_bd, data);
10139
          @(posedge wb_clk);
10140
        end
10141
        repeat (1) @(posedge wb_clk);
10142
        // CHECK FIRST FRAME
10143
        // check length of a first PACKET
10144
        tmp_len = eth_phy.tx_len;
10145 279 mohor
 
10146 209 tadejm
        #1;
10147
        if (tmp_len != (i_length + 4))
10148
        begin
10149 223 tadejm
          `TIME; $display("*E Wrong length of first packet out from MAC");
10150
          test_fail("Wrong length of first packet out from MAC");
10151 209 tadejm
          fail = fail + 1;
10152
        end
10153
        // checking first packet
10154
        check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (i_length), tmp);
10155
        if (tmp > 0)
10156
        begin
10157 223 tadejm
          `TIME; $display("*E Wrong data of first transmitted packet");
10158
          test_fail("Wrong data of first transmitted packet");
10159 209 tadejm
          fail = fail + 1;
10160
        end
10161
        // check first transmited TX packet CRC
10162
        check_tx_crc(0, (i_length), 1'b0, tmp); // length without CRC
10163
        if (tmp > 0)
10164
        begin
10165 223 tadejm
          `TIME; $display("*E Wrong CRC of first transmitted packet");
10166
          test_fail("Wrong CRC of first transmitted packet");
10167 209 tadejm
          fail = fail + 1;
10168
        end
10169
        // check WB INT signal
10170
        if (wb_int !== 1'b1)
10171
        begin
10172
          `TIME; $display("*E WB INT signal should be set");
10173
          test_fail("WB INT signal should be set");
10174
          fail = fail + 1;
10175
        end
10176
        // check TX buffer descriptor of a packet
10177
        check_tx_bd(num_of_bd, data);
10178
        if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // wrap bit
10179
             ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // without wrap bit
10180
        begin
10181
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
10182
          test_fail("TX buffer descriptor status is not correct");
10183
          fail = fail + 1;
10184
        end
10185
        // check interrupts
10186 274 tadejm
        wait (wbm_working == 0);
10187 209 tadejm
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10188
        if ((data & `ETH_INT_TXB) !== 1'b1)
10189
        begin
10190
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
10191
          test_fail("Interrupt Transmit Buffer was not set");
10192
          fail = fail + 1;
10193
        end
10194
        if ((data & (~`ETH_INT_TXB)) !== 0)
10195
        begin
10196
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
10197
          test_fail("Other interrupts (except Transmit Buffer) were set");
10198
          fail = fail + 1;
10199
        end
10200
        // clear interrupts
10201 274 tadejm
        wait (wbm_working == 0);
10202 209 tadejm
        wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10203
        // check WB INT signal
10204
        if (wb_int !== 1'b0)
10205
        begin
10206
          test_fail("WB INT signal should not be set");
10207
          fail = fail + 1;
10208
        end
10209
      end
10210 279 mohor
      else // if (frame_ended == 1)
10211 223 tadejm
      begin
10212
        // CHECK FIRST FRAME
10213
        // check length of a first PACKET
10214 279 mohor
 
10215
        if (no_underrun)
10216 223 tadejm
        begin
10217 279 mohor
          // CHECK FIRST FRAME, without under-run !!!
10218
          // check length of a first PACKET
10219
          tmp_len = eth_phy.tx_len;
10220
          #1;
10221
          if (tmp_len != (i_length + 4))
10222
          begin
10223
            `TIME; $display("*E Wrong length of first packet out from MAC (no under-run)");
10224
            test_fail("Wrong length of first packet out from MAC (no under-run)");
10225
            fail = fail + 1;
10226
          end
10227 223 tadejm
        end
10228 279 mohor
        else
10229
        begin
10230
          // CHECK FIRST FRAME, on which under-run occure !!!
10231
          // check length of a first PACKET
10232
          tmp_len = eth_phy.tx_len_err;
10233
          #1;
10234
          if (tmp_len != ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])))
10235
          begin
10236
            `TIME; $display("*E Wrong length of first packet out from MAC");
10237
            test_fail("Wrong length of first packet out from MAC");
10238
            fail = fail + 1;
10239
          end
10240
        end
10241 223 tadejm
        // checking first packet
10242 279 mohor
        if (no_underrun)
10243
          check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (i_length), tmp);    // only received are checked
10244
        else
10245
          check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (num_of_frames), tmp);
10246 223 tadejm
        if (tmp > 0)
10247
        begin
10248
          `TIME; $display("*E Wrong data of first transmitted packet");
10249
          test_fail("Wrong data of first transmitted packet");
10250
          fail = fail + 1;
10251
        end
10252
        // check WB INT signal
10253
        if (wb_int !== 1'b1)
10254
        begin
10255
          `TIME; $display("*E WB INT signal should be set");
10256
          test_fail("WB INT signal should be set");
10257
          fail = fail + 1;
10258
        end
10259 279 mohor
 
10260 223 tadejm
        // check TX buffer descriptor of a packet
10261
        check_tx_bd(num_of_bd, data);
10262 279 mohor
        if (no_underrun)
10263 223 tadejm
        begin
10264 279 mohor
          if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // under-run, wrap bit
10265
               ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // under-run, without wrap bit
10266
          begin
10267
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
10268
            test_fail("TX buffer descriptor status is not correct");
10269
            fail = fail + 1;
10270
          end
10271 223 tadejm
        end
10272 279 mohor
        else
10273
          if ( ((data[15:0] !== 16'h7900) && (num_of_bd == 1)) || // under-run, wrap bit
10274
               ((data[15:0] !== 16'h5900) && (num_of_bd < 1)) )   // under-run, without wrap bit
10275
          begin
10276
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
10277
            test_fail("TX buffer descriptor status is not correct");
10278
            fail = fail + 1;
10279
          end
10280
 
10281 223 tadejm
        // check interrupts
10282 274 tadejm
        wait (wbm_working == 0);
10283 223 tadejm
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10284 279 mohor
 
10285
        if (no_underrun)
10286 223 tadejm
        begin
10287 279 mohor
          if ((data & `ETH_INT_TXB) !== 2'b01)
10288
          begin
10289
            `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
10290
            test_fail("Interrupt Transmit Buffer was not set");
10291
            fail = fail + 1;
10292
          end
10293
          if ((data & (~`ETH_INT_TXB)) !== 0)
10294
          begin
10295
            `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
10296
            test_fail("Other interrupts (except Transmit Buffer) were set");
10297
            fail = fail + 1;
10298
          end
10299 223 tadejm
        end
10300 279 mohor
        else
10301 223 tadejm
        begin
10302 279 mohor
          if ((data & `ETH_INT_TXE) !== 2'b10)
10303
          begin
10304
            `TIME; $display("*E Interrupt Transmit Error was not set, interrupt reg: %0h", data);
10305
            test_fail("Interrupt Transmit Error was not set");
10306
            fail = fail + 1;
10307
          end
10308
          if ((data & (~`ETH_INT_TXE)) !== 0)
10309
          begin
10310
            `TIME; $display("*E Other interrupts (except Transmit Error) were set, interrupt reg: %0h", data);
10311
            test_fail("Other interrupts (except Transmit Buffer) were set");
10312
            fail = fail + 1;
10313
          end
10314 223 tadejm
        end
10315 279 mohor
 
10316 223 tadejm
        // clear interrupts
10317 274 tadejm
        wait (wbm_working == 0);
10318 223 tadejm
        wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10319
        // check WB INT signal
10320
        if (wb_int !== 1'b0)
10321
        begin
10322
          test_fail("WB INT signal should not be set");
10323
          fail = fail + 1;
10324
        end
10325
      end
10326 209 tadejm
      num_of_bd = num_of_bd + 1;
10327
      // destination address on ethernet PHY
10328
      eth_phy.set_tx_mem_addr(0);
10329 223 tadejm
      // WAIT FOR SECOND TRANSMIT
10330 209 tadejm
      check_tx_bd(num_of_bd, data);
10331
      wait (MTxEn === 1'b1); // start first transmit
10332
      if (data[15] !== 1)
10333
      begin
10334
        test_fail("Wrong buffer descriptor's ready bit read out from MAC");
10335
        fail = fail + 1;
10336
      end
10337
      wait (MTxEn === 1'b0); // end first transmit
10338
      while (data[15] === 1)
10339
      begin
10340
        check_tx_bd(num_of_bd, data);
10341
        @(posedge wb_clk);
10342
      end
10343
      repeat (1) @(posedge wb_clk);
10344
      // CHECK SECOND FRAME
10345
      // check length of a second PACKET
10346
      tmp_len = eth_phy.tx_len;
10347
      #1;
10348
      if (tmp_len != (i_length + 4))
10349
      begin
10350 223 tadejm
        `TIME; $display("*E Wrong length of second packet out from MAC");
10351 209 tadejm
        test_fail("Wrong length of second packet out from MAC");
10352
        fail = fail + 1;
10353
      end
10354
      // checking second packet
10355
      check_tx_packet(`MEMORY_BASE, 0, (i_length), tmp);
10356
      if (tmp > 0)
10357
      begin
10358 223 tadejm
        `TIME; $display("*E Wrong data of second transmitted packet");
10359 209 tadejm
        test_fail("Wrong data of second transmitted packet");
10360
        fail = fail + 1;
10361
      end
10362
      // check second transmited TX packet CRC
10363
      check_tx_crc(0, (i_length), 1'b0, tmp); // length without CRC
10364
      if (tmp > 0)
10365
      begin
10366 223 tadejm
        `TIME; $display("*E Wrong CRC of second transmitted packet");
10367 209 tadejm
        test_fail("Wrong CRC of second transmitted packet");
10368
        fail = fail + 1;
10369
      end
10370
      // check WB INT signal
10371
      if (wb_int !== 1'b1)
10372
      begin
10373
        `TIME; $display("*E WB INT signal should be set");
10374
        test_fail("WB INT signal should be set");
10375
        fail = fail + 1;
10376
      end
10377
      // check TX buffer descriptor of a packet
10378
      check_tx_bd(num_of_bd, data);
10379
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // wrap bit
10380
           ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // without wrap bit
10381
      begin
10382
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
10383
        test_fail("TX buffer descriptor status is not correct");
10384
        fail = fail + 1;
10385
      end
10386
      // check interrupts
10387 274 tadejm
      wait (wbm_working == 0);
10388 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10389
      if ((data & `ETH_INT_TXB) !== 1'b1)
10390
      begin
10391
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
10392
        test_fail("Interrupt Transmit Buffer was not set");
10393
        fail = fail + 1;
10394
      end
10395
      if ((data & (~`ETH_INT_TXB)) !== 0)
10396
      begin
10397
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
10398
        test_fail("Other interrupts (except Transmit Buffer) were set");
10399
        fail = fail + 1;
10400
      end
10401
      // clear interrupts
10402 274 tadejm
      wait (wbm_working == 0);
10403 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10404
      // check WB INT signal
10405
      if (wb_int !== 1'b0)
10406
      begin
10407
        test_fail("WB INT signal should not be set");
10408
        fail = fail + 1;
10409
      end
10410
      // set initial value
10411
      i_data = i_data - 1;
10412 279 mohor
      // the number of frames transmitted
10413 209 tadejm
      num_of_frames = num_of_frames + 1;
10414
      num_of_bd = 0;
10415
      // set length (LOOP variable)
10416 223 tadejm
      if (num_of_frames == i_length + 4) // 64 => this was last Byte (1st .. 64th) when i_length = min_tmp - 4
10417 209 tadejm
        i_length = (max_tmp - 4);
10418
      @(posedge wb_clk);
10419
    end
10420
    // disable TX
10421 274 tadejm
    wait (wbm_working == 0);
10422 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
10423
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10424
    @(posedge wb_clk);
10425
    if(fail == 0)
10426
      test_ok;
10427
    else
10428
      fail = 0;
10429
  end
10430
 
10431
 
10432
  ////////////////////////////////////////////////////////////////////
10433
  ////                                                            ////
10434
  ////  Test transmit packets after TX under-run on each packet's ////
10435
  ////  byte at 2 TX buffer decriptors ( 100Mbps ).               ////
10436
  ////                                                            ////
10437
  ////////////////////////////////////////////////////////////////////
10438
  if (test_num == 21) // without padding
10439
  begin
10440
    // TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps )
10441
    test_name = "TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps )";
10442
    `TIME;
10443
    $display("  TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps )");
10444
 
10445
    // reset MAC registers
10446
    hard_reset;
10447
    // set wb slave response
10448
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
10449
 
10450
    max_tmp = 0;
10451
    min_tmp = 0;
10452
    // set 2 TX buffer descriptors - must be set before TX enable
10453 274 tadejm
    wait (wbm_working == 0);
10454 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h2, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10455
    // enable TX, set full-duplex mode, NO padding and CRC appending
10456 274 tadejm
    wait (wbm_working == 0);
10457 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN |/* `ETH_MODER_PAD |*/ `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
10458
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10459
    // prepare a packet of MAXFL length
10460 274 tadejm
    wait (wbm_working == 0);
10461 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10462
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
10463
    min_tmp = tmp[31:16];
10464
    st_data = 8'h99;
10465
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
10466
    // read IPG value
10467 274 tadejm
    wait (wbm_working == 0);
10468 209 tadejm
    wbm_read(`ETH_IPGT, tmp_ipgt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10469
    // check WB INT signal
10470
    if (wb_int !== 1'b0)
10471
    begin
10472
      test_fail("WB INT signal should not be set");
10473
      fail = fail + 1;
10474
    end
10475
 
10476
    // write to phy's control register for 100Mbps
10477
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
10478 279 mohor
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
10479 209 tadejm
    speed = 100;
10480
 
10481 279 mohor
    num_of_frames = 60; // (0..3) => start under-run on first word
10482 209 tadejm
    num_of_bd = 0;
10483
    i_data = 3; // (3) => one BYTE read in first word - FIRST byte
10484 279 mohor
    i_length = 80;
10485 209 tadejm
    while (i_length < (max_tmp - 4))
10486
    begin
10487
      // Reset_tx_bd enable interrupt generation
10488
      // unmask interrupts
10489 274 tadejm
      wait (wbm_working == 0);
10490 209 tadejm
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
10491
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10492
      // not detect carrier sense in FD and no collision
10493
      eth_phy.carrier_sense_tx_fd_detect(0);
10494
      eth_phy.collision(0);
10495
      // first destination address on ethernet PHY
10496
      eth_phy.set_tx_mem_addr(0);
10497
      // prepare BDs
10498
      if (num_of_bd == 0)
10499
      begin
10500
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_data[1:0]));
10501
        set_tx_bd(1, 1, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
10502
        set_tx_bd_wrap(1);
10503
        // set wb slave response: ACK (response), wbs_waits[2:0] (waits before response), 
10504
        //                       wbs_retries[7:0] (RTYs before ACK if RTY response selected)
10505 279 mohor
        #1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
10506 209 tadejm
        set_tx_bd_ready(1, 1);
10507
        set_tx_bd_ready(0, 0);
10508
      end
10509
      // frame under-run checking
10510
      frame_started = 0;
10511
      frame_ended = 0;
10512
      wait_for_frame = 0;
10513 279 mohor
      no_underrun = 0;
10514 209 tadejm
      fork
10515
        begin
10516
          // for every 4 frames bytes 1, 2, 3 and 4 respectively are read in first word => 1 ACK
10517
          // in other words 4 bytes are read, since length is MINFL => num_of_frames[31:2] ACKs
10518 279 mohor
          i = 0;
10519
          while (i <= (num_of_frames[31:2] + 1))
10520
          begin
10521
            @(negedge wb_clk);
10522
            if (eth_ma_wb_ack_i)
10523
            begin
10524
              i = i + 1;
10525
            end
10526
          end
10527 209 tadejm
          // set wb slave response: ACK (response), wbs_waits[2:0] (waits before response), 
10528
          //                       wbs_retries[7:0] (RTYs before ACK if RTY response selected)
10529 279 mohor
          #1 wb_slave.cycle_response(`NO_RESPONSE, 3'h0, 8'hFF);
10530 209 tadejm
          // wait for synchronization and some additional clocks
10531
          wait_for_frame = 1;
10532
          // wait for frame
10533
          wait ((wait_for_frame == 0) || (frame_started == 1))
10534
          if ((wait_for_frame == 0) && (frame_started == 0)) // frame didn't start
10535
          begin
10536
            disable check_fr1;
10537
          end
10538
          else if ((wait_for_frame == 1) && (frame_started == 1)) // frame started
10539
          begin
10540
            disable wait_fr1;
10541 279 mohor
            if (frame_ended == 1)
10542
            begin
10543
              $display("(%0t) no under-run on %0d. byte, since length of frame (without CRC) is only %0d bytes",
10544
                        $time, ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])), i_length);
10545
              no_underrun = 1;
10546
            end
10547
            else
10548
            begin
10549
              wait (frame_ended == 1);
10550
              $display("(%0t) under-run on %0d. byte",
10551
                        $time, ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])));
10552
              no_underrun = 0;
10553
            end
10554 209 tadejm
          end
10555
          repeat (2) @(posedge wb_clk);
10556
          // set wb slave response: ACK (response), wbs_waits[2:0] (waits before response), 
10557
          //                       wbs_retries[7:0] (RTYs before ACK if RTY response selected)
10558 279 mohor
          wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
10559 209 tadejm
        end
10560
        begin: wait_fr1
10561
          wait (wait_for_frame == 1)
10562
          begin
10563
            // wait for synchronization and some additional clocks
10564
            repeat (3) @(posedge wb_clk);
10565
            repeat (2 * tmp_ipgt) @(posedge mtx_clk);
10566
            repeat (2) @(posedge wb_clk);
10567
            repeat (2) @(posedge mtx_clk);
10568
            wait_for_frame = 0;
10569
          end
10570
        end
10571
        begin: check_fr1
10572
          // wait for frame to start
10573
          @(posedge MTxEn);
10574
          frame_started = 1;
10575
          // wait for frame to end due to under-run
10576
          @(negedge MTxEn);
10577
          frame_ended = 1;
10578
        end
10579
      join
10580 279 mohor
 
10581
      repeat (5) @ (posedge mtx_clk);
10582
 
10583 209 tadejm
      // wait for first transmit to end, if under-run didn't happen
10584
      if (frame_ended == 0)
10585
      begin
10586
        // WAIT FOR FIRST TRANSMIT
10587
        check_tx_bd(num_of_bd, data);
10588
        wait (MTxEn === 1'b1); // start first transmit
10589
        if (data[15] !== 1)
10590
        begin
10591
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
10592
          fail = fail + 1;
10593
        end
10594
        wait (MTxEn === 1'b0); // end first transmit
10595
        while (data[15] === 1)
10596
        begin
10597
          check_tx_bd(num_of_bd, data);
10598
          @(posedge wb_clk);
10599
        end
10600 279 mohor
        repeat (10) @(posedge wb_clk);
10601 209 tadejm
        // CHECK FIRST FRAME
10602
        // check length of a first PACKET
10603
        tmp_len = eth_phy.tx_len;
10604 279 mohor
 
10605 209 tadejm
        #1;
10606
        if (tmp_len != (i_length + 4))
10607
        begin
10608 279 mohor
          `TIME; $display("*E Wrong length of first packet out from MAC");
10609
          test_fail("Wrong length of first packet out from MAC");
10610 209 tadejm
          fail = fail + 1;
10611
        end
10612
        // checking first packet
10613
        check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (i_length), tmp);
10614
        if (tmp > 0)
10615
        begin
10616 279 mohor
          `TIME; $display("*E Wrong data of first transmitted packet");
10617
          test_fail("Wrong data of first transmitted packet");
10618 209 tadejm
          fail = fail + 1;
10619
        end
10620
        // check first transmited TX packet CRC
10621
        check_tx_crc(0, (i_length), 1'b0, tmp); // length without CRC
10622
        if (tmp > 0)
10623
        begin
10624 279 mohor
          `TIME; $display("*E Wrong CRC of first transmitted packet");
10625
          test_fail("Wrong CRC of first transmitted packet");
10626 209 tadejm
          fail = fail + 1;
10627
        end
10628
        // check WB INT signal
10629
        if (wb_int !== 1'b1)
10630
        begin
10631
          `TIME; $display("*E WB INT signal should be set");
10632
          test_fail("WB INT signal should be set");
10633
          fail = fail + 1;
10634
        end
10635
        // check TX buffer descriptor of a packet
10636
        check_tx_bd(num_of_bd, data);
10637
        if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // wrap bit
10638
             ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // without wrap bit
10639
        begin
10640
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
10641
          test_fail("TX buffer descriptor status is not correct");
10642
          fail = fail + 1;
10643
        end
10644
        // check interrupts
10645 274 tadejm
        wait (wbm_working == 0);
10646 209 tadejm
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10647
        if ((data & `ETH_INT_TXB) !== 1'b1)
10648
        begin
10649
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
10650
          test_fail("Interrupt Transmit Buffer was not set");
10651
          fail = fail + 1;
10652
        end
10653
        if ((data & (~`ETH_INT_TXB)) !== 0)
10654
        begin
10655
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
10656
          test_fail("Other interrupts (except Transmit Buffer) were set");
10657
          fail = fail + 1;
10658
        end
10659
        // clear interrupts
10660 274 tadejm
        wait (wbm_working == 0);
10661 209 tadejm
        wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10662
        // check WB INT signal
10663
        if (wb_int !== 1'b0)
10664
        begin
10665
          test_fail("WB INT signal should not be set");
10666
          fail = fail + 1;
10667
        end
10668
      end
10669 279 mohor
      else // if (frame_ended == 1)
10670
      begin
10671
        // CHECK FIRST FRAME
10672
        // check length of a first PACKET
10673
 
10674
        if (no_underrun)
10675
        begin
10676
          // CHECK FIRST FRAME, without under-run !!!
10677
          // check length of a first PACKET
10678
          tmp_len = eth_phy.tx_len;
10679
          #1;
10680
          if (tmp_len != (i_length + 4))
10681
          begin
10682
            `TIME; $display("*E Wrong length of first packet out from MAC (no under-run)");
10683
            test_fail("Wrong length of first packet out from MAC (no under-run)");
10684
            fail = fail + 1;
10685
          end
10686
        end
10687
        else
10688
        begin
10689
          // CHECK FIRST FRAME, on which under-run occure !!!
10690
          // check length of a first PACKET
10691
          tmp_len = eth_phy.tx_len_err-1;   // -1 because synchronization at 100 Mbps is slover then at 10 Mbps (wb_clk remains the same)
10692
          #1;
10693
          if (tmp_len != ({num_of_frames[31:2], 2'h0} + (4 - i_data[1:0])))
10694
          begin
10695
            `TIME; $display("*E Wrong length of first packet out from MAC");
10696
            test_fail("Wrong length of first packet out from MAC");
10697
            fail = fail + 1;
10698
          end
10699
        end
10700
        // checking first packet
10701
        if (no_underrun)
10702
          check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (i_length), tmp);    // only received are checked
10703
        else
10704
          check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (num_of_frames), tmp);
10705
        if (tmp > 0)
10706
        begin
10707
          `TIME; $display("*E Wrong data of first transmitted packet");
10708
          test_fail("Wrong data of first transmitted packet");
10709
          fail = fail + 1;
10710
        end
10711
        // check WB INT signal
10712
        if (wb_int !== 1'b1)
10713
        begin
10714
          `TIME; $display("*E WB INT signal should be set");
10715
          test_fail("WB INT signal should be set");
10716
          fail = fail + 1;
10717
        end
10718
 
10719
        // check TX buffer descriptor of a packet
10720
        check_tx_bd(num_of_bd, data);
10721
        if (no_underrun)
10722
        begin
10723
          if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // under-run, wrap bit
10724
               ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // under-run, without wrap bit
10725
          begin
10726
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
10727
            test_fail("TX buffer descriptor status is not correct");
10728
            fail = fail + 1;
10729
          end
10730
        end
10731
        else
10732
          if ( ((data[15:0] !== 16'h7900) && (num_of_bd == 1)) || // under-run, wrap bit
10733
               ((data[15:0] !== 16'h5900) && (num_of_bd < 1)) )   // under-run, without wrap bit
10734
          begin
10735
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
10736
            test_fail("TX buffer descriptor status is not correct");
10737
            fail = fail + 1;
10738
          end
10739
 
10740
        // check interrupts
10741
        wait (wbm_working == 0);
10742
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10743
 
10744
        if (no_underrun)
10745
        begin
10746
          if ((data & `ETH_INT_TXB) !== 2'b01)
10747
          begin
10748
            `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
10749
            test_fail("Interrupt Transmit Buffer was not set");
10750
            fail = fail + 1;
10751
          end
10752
          if ((data & (~`ETH_INT_TXB)) !== 0)
10753
          begin
10754
            `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
10755
            test_fail("Other interrupts (except Transmit Buffer) were set");
10756
            fail = fail + 1;
10757
          end
10758
        end
10759
        else
10760
        begin
10761
          if ((data & `ETH_INT_TXE) !== 2'b10)
10762
          begin
10763
            `TIME; $display("*E Interrupt Transmit Error was not set, interrupt reg: %0h", data);
10764
            test_fail("Interrupt Transmit Error was not set");
10765
            fail = fail + 1;
10766
          end
10767
          if ((data & (~`ETH_INT_TXE)) !== 0)
10768
          begin
10769
            `TIME; $display("*E Other interrupts (except Transmit Error) were set, interrupt reg: %0h", data);
10770
            test_fail("Other interrupts (except Transmit Buffer) were set");
10771
            fail = fail + 1;
10772
          end
10773
        end
10774
 
10775
        // clear interrupts
10776
        wait (wbm_working == 0);
10777
        wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10778
        // check WB INT signal
10779
        if (wb_int !== 1'b0)
10780
        begin
10781
          test_fail("WB INT signal should not be set");
10782
          fail = fail + 1;
10783
        end
10784
      end
10785 209 tadejm
      num_of_bd = num_of_bd + 1;
10786
      // destination address on ethernet PHY
10787
      eth_phy.set_tx_mem_addr(0);
10788 279 mohor
      // WAIT FOR SECOND TRANSMIT
10789 209 tadejm
      check_tx_bd(num_of_bd, data);
10790
      wait (MTxEn === 1'b1); // start first transmit
10791
      if (data[15] !== 1)
10792
      begin
10793
        test_fail("Wrong buffer descriptor's ready bit read out from MAC");
10794
        fail = fail + 1;
10795
      end
10796
      wait (MTxEn === 1'b0); // end first transmit
10797
      while (data[15] === 1)
10798
      begin
10799
        check_tx_bd(num_of_bd, data);
10800
        @(posedge wb_clk);
10801
      end
10802
      repeat (1) @(posedge wb_clk);
10803
      // CHECK SECOND FRAME
10804
      // check length of a second PACKET
10805
      tmp_len = eth_phy.tx_len;
10806
      #1;
10807
      if (tmp_len != (i_length + 4))
10808
      begin
10809 279 mohor
        `TIME; $display("*E Wrong length of second packet out from MAC");
10810 209 tadejm
        test_fail("Wrong length of second packet out from MAC");
10811
        fail = fail + 1;
10812
      end
10813
      // checking second packet
10814
      check_tx_packet(`MEMORY_BASE, 0, (i_length), tmp);
10815
      if (tmp > 0)
10816
      begin
10817 279 mohor
        `TIME; $display("*E Wrong data of second transmitted packet");
10818 209 tadejm
        test_fail("Wrong data of second transmitted packet");
10819
        fail = fail + 1;
10820
      end
10821
      // check second transmited TX packet CRC
10822
      check_tx_crc(0, (i_length), 1'b0, tmp); // length without CRC
10823
      if (tmp > 0)
10824
      begin
10825 279 mohor
        `TIME; $display("*E Wrong CRC of second transmitted packet");
10826 209 tadejm
        test_fail("Wrong CRC of second transmitted packet");
10827
        fail = fail + 1;
10828
      end
10829
      // check WB INT signal
10830
      if (wb_int !== 1'b1)
10831
      begin
10832
        `TIME; $display("*E WB INT signal should be set");
10833
        test_fail("WB INT signal should be set");
10834
        fail = fail + 1;
10835
      end
10836
      // check TX buffer descriptor of a packet
10837
      check_tx_bd(num_of_bd, data);
10838
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // wrap bit
10839
           ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // without wrap bit
10840
      begin
10841
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
10842
        test_fail("TX buffer descriptor status is not correct");
10843
        fail = fail + 1;
10844
      end
10845
      // check interrupts
10846 274 tadejm
      wait (wbm_working == 0);
10847 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10848
      if ((data & `ETH_INT_TXB) !== 1'b1)
10849
      begin
10850
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
10851
        test_fail("Interrupt Transmit Buffer was not set");
10852
        fail = fail + 1;
10853
      end
10854
      if ((data & (~`ETH_INT_TXB)) !== 0)
10855
      begin
10856
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
10857
        test_fail("Other interrupts (except Transmit Buffer) were set");
10858
        fail = fail + 1;
10859
      end
10860
      // clear interrupts
10861 274 tadejm
      wait (wbm_working == 0);
10862 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10863
      // check WB INT signal
10864
      if (wb_int !== 1'b0)
10865
      begin
10866
        test_fail("WB INT signal should not be set");
10867
        fail = fail + 1;
10868
      end
10869
      // set initial value
10870
      i_data = i_data - 1;
10871 279 mohor
      // the number of frames transmitted
10872 209 tadejm
      num_of_frames = num_of_frames + 1;
10873
      num_of_bd = 0;
10874
      // set length (LOOP variable)
10875 279 mohor
      if (num_of_frames == i_length + 4) // 64 => this was last Byte (1st .. 64th) when i_length = min_tmp - 4
10876 209 tadejm
        i_length = (max_tmp - 4);
10877
      @(posedge wb_clk);
10878
    end
10879
    // disable TX
10880 274 tadejm
    wait (wbm_working == 0);
10881 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
10882
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10883
    @(posedge wb_clk);
10884
    if(fail == 0)
10885
      test_ok;
10886
    else
10887
      fail = 0;
10888
  end
10889
 
10890 194 tadej
end   //  for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
10891 169 mohor
 
10892
end
10893
endtask // test_mac_full_duplex_transmit
10894
 
10895
 
10896 209 tadejm
task test_mac_full_duplex_receive;
10897
  input  [31:0]  start_task;
10898
  input  [31:0]  end_task;
10899
  integer        bit_start_1;
10900
  integer        bit_end_1;
10901
  integer        bit_start_2;
10902
  integer        bit_end_2;
10903
  integer        num_of_reg;
10904
  integer        num_of_frames;
10905
  integer        num_of_bd;
10906
  integer        i_addr;
10907
  integer        i_data;
10908
  integer        i_length;
10909
  integer        tmp_len;
10910
  integer        tmp_bd;
10911
  integer        tmp_bd_num;
10912
  integer        tmp_data;
10913
  integer        tmp_ipgt;
10914
  integer        test_num;
10915
  reg    [31:0]  tx_bd_num;
10916
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
10917
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
10918
  integer        i;
10919
  integer        i1;
10920
  integer        i2;
10921
  integer        i3;
10922
  integer        fail;
10923
  integer        speed;
10924
  reg            frame_started;
10925
  reg            frame_ended;
10926
  reg            wait_for_frame;
10927 243 tadejm
  reg            check_frame;
10928
  reg            stop_checking_frame;
10929
  reg            first_fr_received;
10930 209 tadejm
  reg    [31:0]  addr;
10931
  reg    [31:0]  data;
10932
  reg    [31:0]  tmp;
10933
  reg    [ 7:0]  st_data;
10934
  reg    [15:0]  max_tmp;
10935
  reg    [15:0]  min_tmp;
10936
begin
10937
// MAC FULL DUPLEX RECEIVE TEST
10938
test_heading("MAC FULL DUPLEX RECEIVE TEST");
10939
$display(" ");
10940
$display("MAC FULL DUPLEX RECEIVE TEST");
10941
fail = 0;
10942
 
10943
// reset MAC registers
10944
hard_reset;
10945
// reset MAC and MII LOGIC with soft reset
10946 274 tadejm
//reset_mac;
10947
//reset_mii;
10948 209 tadejm
// set wb slave response
10949
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
10950
 
10951
  /*
10952
  TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
10953
  -------------------------------------------------------------------------------------
10954
  set_tx_bd
10955
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0], len[15:0], irq, pad, crc, txpnt[31:0]);
10956
  set_tx_bd_wrap
10957
    (tx_bd_num_end[6:0]);
10958
  set_tx_bd_ready
10959
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
10960
  check_tx_bd
10961
    (tx_bd_num_start[6:0], tx_bd_status[31:0]);
10962
  clear_tx_bd
10963
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
10964
 
10965
  TASKS for set and control RX buffer descriptors:
10966
  ------------------------------------------------
10967
  set_rx_bd
10968
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0], irq, rxpnt[31:0]);
10969
  set_rx_bd_wrap
10970
    (rx_bd_num_end[6:0]);
10971
  set_rx_bd_empty
10972
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
10973
  check_rx_bd
10974
    (rx_bd_num_end[6:0], rx_bd_status);
10975
  clear_rx_bd
10976
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
10977
 
10978
  TASKS for set and check TX packets:
10979
  -----------------------------------
10980
  set_tx_packet
10981
    (txpnt[31:0], len[15:0], eth_start_data[7:0]);
10982
  check_tx_packet
10983
    (txpnt_wb[31:0], txpnt_phy[31:0], len[15:0], failure[31:0]);
10984
 
10985
  TASKS for set and check RX packets:
10986
  -----------------------------------
10987
  set_rx_packet
10988
    (rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
10989
  check_rx_packet
10990
    (rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
10991
 
10992
  TASKS for append and check CRC to/of TX packet:
10993
  -----------------------------------------------
10994
  append_tx_crc
10995
    (txpnt_wb[31:0], len[15:0], negated_crc);
10996
  check_tx_crc
10997
    (txpnt_phy[31:0], len[15:0], negated_crc, failure[31:0]);
10998
 
10999
  TASK for append CRC to RX packet (CRC is checked together with check_rx_packet):
11000
  --------------------------------------------------------------------------------
11001
  append_rx_crc
11002
    (rxpnt_phy[31:0], len[15:0], plus_nibble, negated_crc);
11003
  */
11004
 
11005
//////////////////////////////////////////////////////////////////////
11006
////                                                              ////
11007
////  test_mac_full_duplex_receive:                               ////
11008
////                                                              ////
11009
////  0: Test no receive when all buffers are TX ( 10Mbps ).      ////
11010
////  1: Test no receive when all buffers are TX ( 100Mbps ).     ////
11011 243 tadejm
////  2: Test receive packet synchronization with receive         ////
11012
////     disable/enable ( 10Mbps ).                               ////
11013
////  3: Test receive packet synchronization with receive         ////
11014
////     disable/enable ( 100Mbps ).                              ////
11015
////  4: Test receive packets form MINFL to MAXFL sizes at        ////
11016 209 tadejm
////     one RX buffer decriptor ( 10Mbps ).                      ////
11017 243 tadejm
////  5: Test receive packets form MINFL to MAXFL sizes at        ////
11018 209 tadejm
////     one RX buffer decriptor ( 100Mbps ).                     ////
11019
////                                                              ////
11020
//////////////////////////////////////////////////////////////////////
11021
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
11022
begin
11023
 
11024
  ////////////////////////////////////////////////////////////////////
11025
  ////                                                            ////
11026
  ////  Test no receive when all buffers are TX ( 10Mbps ).       ////
11027
  ////                                                            ////
11028
  ////////////////////////////////////////////////////////////////////
11029
  if (test_num == 0) // Test no receive when all buffers are TX ( 10Mbps ).
11030
  begin
11031
    // TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )
11032
    test_name   = "TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )";
11033
    `TIME; $display("  TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )");
11034
 
11035
    // unmask interrupts
11036 274 tadejm
    wait (wbm_working == 0);
11037 209 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
11038
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11039
    // set all buffer descriptors to TX - must be set before RX enable
11040 274 tadejm
    wait (wbm_working == 0);
11041 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11042 223 tadejm
    // enable RX, set full-duplex mode, receive small, NO correct IFG
11043 274 tadejm
    wait (wbm_working == 0);
11044 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
11045
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11046
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11047
 
11048
    // write to phy's control register for 10Mbps
11049
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
11050
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
11051
    speed = 10;
11052
 
11053
    i = 0;
11054
    while (i < 128)
11055
    begin
11056
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
11057
      begin
11058
        set_rx_packet((i1 * 50), 10, 1'b0, 48'h1234_5678_8765, 48'h0011_2233_4455, 16'h0101, 8'h0);
11059
        append_rx_crc((i1 * 50), 10, 1'b0, 1'b0);
11060
        set_rx_bd(i1, i1, 1'b1, (`MEMORY_BASE + (i1 * 50)));
11061
      end
11062
      set_rx_bd_wrap(i);
11063
      set_rx_bd_empty(0, i);
11064
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
11065
      begin
11066
        #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, (i1 * 50), 14, 1'b0);
11067
        repeat(10) @(posedge mrx_clk);
11068
      end
11069
      @(posedge mrx_clk);
11070
      for (i2 = 0; i2 < 20; i2 = i2 + 1)
11071
      begin
11072
        check_rx_bd(0, tmp);
11073
        #1;
11074
        if (tmp[15] === 1'b0)
11075
        begin
11076
          test_fail("Receive should not start at all");
11077
          fail = fail + 1;
11078
          `TIME; $display("*E Receive of %d packets should not start at all - empty is 0", i);
11079
        end
11080
        if (tmp[7:0] !== 0)
11081
        begin
11082
          test_fail("Receive should not be finished since it should not start at all");
11083
          fail = fail + 1;
11084
          `TIME; $display("*E Receive of should not be finished since it should not start at all");
11085
        end
11086
        @(posedge wb_clk);
11087
      end
11088 274 tadejm
      wait (wbm_working == 0);
11089 209 tadejm
      wbm_read(`ETH_INT, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11090
      if (tmp[6:0] !== 0)
11091
      begin
11092
        test_fail("Receive should not get INT since it should not start at all");
11093
        fail = fail + 1;
11094
        `TIME; $display("*E Receive of should not get INT since it should not start at all");
11095
      end
11096
      clear_rx_bd(0, i);
11097
      if ((i < 5) || (i > 124))
11098
        i = i + 1;
11099
      else
11100
        i = i + 120;
11101
    end
11102
    // disable RX
11103 274 tadejm
    wait (wbm_working == 0);
11104 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
11105
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11106
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11107
    if(fail == 0)
11108
      test_ok;
11109
    else
11110
      fail = 0;
11111
  end
11112
 
11113
 
11114
  ////////////////////////////////////////////////////////////////////
11115
  ////                                                            ////
11116
  ////  Test no receive when all buffers are TX ( 100Mbps ).      ////
11117
  ////                                                            ////
11118
  ////////////////////////////////////////////////////////////////////
11119
  if (test_num == 1) // Test no receive when all buffers are TX ( 100Mbps ).
11120
  begin
11121
    // TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )
11122
    test_name   = "TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )";
11123
    `TIME; $display("  TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )");
11124
 
11125
    // unmask interrupts
11126 274 tadejm
    wait (wbm_working == 0);
11127 209 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
11128
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11129
    // set all buffer descriptors to TX - must be set before RX enable
11130 274 tadejm
    wait (wbm_working == 0);
11131 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11132 223 tadejm
    // enable RX, set full-duplex mode, receive small, NO correct IFG
11133 274 tadejm
    wait (wbm_working == 0);
11134 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
11135
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11136
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11137
 
11138
    // write to phy's control register for 100Mbps
11139
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
11140
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
11141
    speed = 100;
11142
 
11143
    i = 0;
11144
    while (i < 128)
11145
    begin
11146
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
11147
      begin
11148
        set_rx_packet((i1 * 50), 10, 1'b0, 48'h1234_5678_8765, 48'h0011_2233_4455, 16'h0101, 8'h0);
11149
        append_rx_crc((i1 * 50), 10, 1'b0, 1'b0);
11150
        set_rx_bd(i1, i1, 1'b1, (`MEMORY_BASE + (i1 * 50)));
11151
      end
11152
      set_rx_bd_wrap(i);
11153
      set_rx_bd_empty(0, i);
11154
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
11155
      begin
11156
        #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, (i1 * 50), 14, 1'b0);
11157
        repeat(10) @(posedge mrx_clk);
11158
      end
11159
      @(posedge mrx_clk);
11160
      for (i2 = 0; i2 < 20; i2 = i2 + 1)
11161
      begin
11162
        check_rx_bd(0, tmp);
11163
        #1;
11164
        if (tmp[15] === 1'b0)
11165
        begin
11166
          test_fail("Receive should not start at all");
11167
          fail = fail + 1;
11168
          `TIME; $display("*E Receive of %d packets should not start at all - empty is 0", i);
11169
        end
11170
        if (tmp[7:0] !== 0)
11171
        begin
11172
          test_fail("Receive should not be finished since it should not start at all");
11173
          fail = fail + 1;
11174
          `TIME; $display("*E Receive of should not be finished since it should not start at all");
11175
        end
11176
        @(posedge wb_clk);
11177
      end
11178 274 tadejm
      wait (wbm_working == 0);
11179 209 tadejm
      wbm_read(`ETH_INT, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11180
      if (tmp[6:0] !== 0)
11181
      begin
11182
        test_fail("Receive should not get INT since it should not start at all");
11183
        fail = fail + 1;
11184
        `TIME; $display("*E Receive of should not get INT since it should not start at all");
11185
      end
11186
      clear_rx_bd(0, i);
11187
      if ((i < 5) || (i > 124))
11188
        i = i + 1;
11189
      else
11190
        i = i + 120;
11191
    end
11192
    // disable RX
11193 274 tadejm
    wait (wbm_working == 0);
11194 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
11195
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11196
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11197
    if(fail == 0)
11198
      test_ok;
11199
    else
11200
      fail = 0;
11201
  end
11202
 
11203
 
11204
  ////////////////////////////////////////////////////////////////////
11205
  ////                                                            ////
11206 243 tadejm
  ////  Test receive packet synchronization with receive          ////
11207
  ////  disable/enable ( 10Mbps ).                                ////
11208
  ////                                                            ////
11209
  ////////////////////////////////////////////////////////////////////
11210
  if (test_num == 2) // Test no receive when all buffers are TX ( 10Mbps ).
11211
  begin
11212
    // TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
11213
    test_name   = "TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
11214
    `TIME; $display("  TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
11215
 
11216
    // unmask interrupts
11217 274 tadejm
    wait (wbm_working == 0);
11218 243 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
11219
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11220
    // set 10 RX buffer descriptor (8'h80 - 8'hA) - must be set before RX enable
11221 274 tadejm
    wait (wbm_working == 0);
11222 243 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h76, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11223
    // disable RX, set full-duplex mode, NO receive small, NO correct IFG
11224 274 tadejm
    wait (wbm_working == 0);
11225 243 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
11226
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11227
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11228
    // prepare two packets of MAXFL length
11229 274 tadejm
    wait (wbm_working == 0);
11230 243 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11231
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
11232
    min_tmp = tmp[31:16];
11233
    st_data = 8'h0F;
11234
    set_rx_packet(0, (min_tmp + 1), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
11235
    append_rx_crc(0, (min_tmp + 1), 1'b0, 1'b0);
11236
    st_data = 8'h1A;
11237
    set_rx_packet(max_tmp, (min_tmp + 1), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
11238
    append_rx_crc(max_tmp, (min_tmp + 1), 1'b0, 1'b0);
11239
    // check WB INT signal
11240
    if (wb_int !== 1'b0)
11241
    begin
11242
      test_fail("WB INT signal should not be set");
11243
      fail = fail + 1;
11244
    end
11245
 
11246
    // write to phy's control register for 10Mbps
11247
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
11248
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
11249
    speed = 10;
11250
 
11251
    frame_started = 0;
11252
    frame_ended = 0;
11253
    wait_for_frame = 0;
11254
    check_frame = 0;
11255
    stop_checking_frame = 0;
11256
    first_fr_received = 1; // at the beginning the first frame of each two will be received!
11257
 
11258
    num_of_frames = 0; // 
11259
    num_of_bd = 0;
11260
    i_length = (min_tmp + 1); // 5 bytes longer than MINFL
11261
    while (i_length < (max_tmp - 4))
11262
    begin
11263
      // choose generating carrier sense and collision 
11264
      case (num_of_frames[1:0])
11265
      2'h0: // Interrupt is generated
11266
      begin
11267
        // enable interrupt generation
11268
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
11269
        // not detect carrier sense in FD and no collision
11270
        eth_phy.no_carrier_sense_rx_fd_detect(0);
11271
        eth_phy.collision(0);
11272
      end
11273
      2'h1: // Interrupt is generated
11274
      begin
11275
        // enable interrupt generation
11276
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
11277
        // detect carrier sense in FD and no collision
11278
        eth_phy.no_carrier_sense_rx_fd_detect(1);
11279
        eth_phy.collision(0);
11280
      end
11281
      2'h2: // Interrupt is generated
11282
      begin
11283
        // disable interrupt generation
11284
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
11285
        // not detect carrier sense in FD and set collision
11286
        eth_phy.no_carrier_sense_rx_fd_detect(0);
11287
        eth_phy.collision(1);
11288
      end
11289
      default: // 2'h3: // Interrupt is generated
11290
      begin
11291
        // disable interrupt generation
11292
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
11293
        // detect carrier sense in FD and set collision
11294
        eth_phy.no_carrier_sense_rx_fd_detect(1);
11295
        eth_phy.collision(1);
11296
      end
11297
      endcase
11298
      // set wrap bit
11299
      set_rx_bd_wrap(118);
11300
      set_rx_bd_empty(118, 118);
11301
      check_frame = 0;
11302
      stop_checking_frame = 0;
11303
      tmp_data = 0;
11304
      fork
11305
        begin // enable RX MAC on first of each two packets - every second should be recived normaly
11306
          if (num_of_frames[0] == 1'b0)
11307
          begin
11308
            repeat(1) @(posedge wb_clk);
11309
            if (num_of_frames[1] == 1'b0)
11310
            begin
11311
              repeat (num_of_frames[31:2]) @(posedge mrx_clk); // for every (second) frame enable receiver one clock later
11312
            end
11313
            else
11314
            begin
11315
              @(posedge mrx_clk);
11316
              repeat (num_of_frames[31:2]) @(negedge mrx_clk); // for every (second) frame enable receiver one clock later
11317
            end
11318
            // enable RX, set full-duplex mode, NO receive small, NO correct IFG
11319
            wbm_init_waits = 4'h0;
11320
            wbm_subseq_waits = 4'h0;
11321 274 tadejm
            #1 wait (wbm_working == 0);
11322
            wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
11323 243 tadejm
                      `ETH_MODER_PRO | `ETH_MODER_BRO,
11324
                      4'hF, 1, wbm_init_waits, wbm_subseq_waits); // write ASAP
11325
          end
11326
        end
11327
        begin // send a packet from PHY RX
11328
          repeat(1) @(posedge wb_clk); // wait for WB write when it is without delays
11329
          if (num_of_frames[1] == 1'b0)
11330
          begin
11331
            set_rx_addr_type(0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E);
11332
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
11333
          end
11334
          else
11335
          begin
11336
            set_rx_addr_type((max_tmp), 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E);
11337
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
11338
          end
11339
        end
11340
        begin: send_packet0
11341
          wait (MRxDV === 1'b1); // start transmit
11342
          wait (MRxDV === 1'b0); // end transmit
11343
          check_frame = 1;
11344
          repeat(10) @(posedge mrx_clk);
11345
          repeat(15) @(posedge wb_clk);
11346
          stop_checking_frame = 1;
11347
        end
11348
        begin // count WB clocks between ACK (negedge) and RX_DV (posedge) or vice-versa
11349
          @(posedge eth_sl_wb_ack_o or posedge MRxDV);
11350
          if ((eth_sl_wb_ack_o === 1'b1) && (MRxDV === 1'b1))
11351
          begin
11352
            tmp_data = 32'h8000_0001; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
11353
          end
11354
          else if (MRxDV === 1'b1)
11355
          begin
11356
            while (eth_sl_wb_ack_o === 1'b0)
11357
            begin
11358
              @(posedge wb_clk);
11359
              tmp_data = tmp_data + 1;
11360
            end
11361
            tmp_data = tmp_data | 32'h8000_0000; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
11362
          end
11363
          else if (eth_sl_wb_ack_o === 1'b1)
11364
          begin
11365
            @(posedge wb_clk); // wait for one clock => tmp_data 'becomes' 0
11366
            while (MRxDV === 1'b0)
11367
            begin
11368
              @(posedge wb_clk);
11369
              tmp_data = tmp_data + 1; // bit[31]==0 => 'negedge eth_sl_wb_ack_o' was equal or before 'posedge MRxDV'
11370
            end
11371
          end
11372
        end
11373
        begin // check packet
11374
          wait (check_frame == 1);
11375
          check_rx_bd(118, tmp_bd);
11376
          while ((tmp_bd[15] === 1) && (stop_checking_frame == 0))
11377
          begin
11378
            #1 check_rx_bd(118, tmp_bd);
11379
            @(posedge wb_clk);
11380
          end
11381
          if (num_of_frames[0] == 1'b0)
11382
          begin
11383
            if (tmp_bd[15] === 1)
11384
            begin
11385
              if (first_fr_received == 1)
11386
              begin
11387
                first_fr_received = 0;
11388
                $display("    %0d packets (without this one) are checked - packets are received by two in a set",
11389
                         num_of_frames); // +1 due to start with 0 AND -1 because this packet is excluded
11390
                $display("    From this moment:");
11391
                $display("    first one of two packets (including this one) is not accepted due to late RX enable");
11392
                if (tmp_data[31])
11393
                  $display("    ->RX enable set %0d WB clks after RX_DV", tmp_data[30:0]);
11394
                else
11395
                  $display("    ->RX enable set %0d WB clks before RX_DV", tmp_data[30:0]);
11396
              end
11397
            end
11398
          end
11399
          if (stop_checking_frame == 0)
11400
            disable send_packet0;
11401
        end
11402
      join
11403
      // ONLY IF packet was received!
11404
      if (tmp_bd[15] === 0)
11405
      begin
11406
        // check length of a PACKET
11407
        if (tmp_bd[31:16] != (i_length + 4))
11408
        begin
11409
          `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
11410
                          tmp_bd[31:16], (i_length + 4));
11411
          test_fail("Wrong length of the packet out from PHY");
11412
          fail = fail + 1;
11413
        end
11414
        // check received RX packet data and CRC
11415
        if (first_fr_received == 0) // if PREVIOUS RX buffer descriptor was not ready, pointer address is -1
11416
        begin
11417
          if (num_of_frames[1] == 1'b0)
11418
          begin
11419
            check_rx_packet(0, (`MEMORY_BASE + num_of_frames[1:0] - 1'b1), (i_length + 4), 1'b0, 1'b0, tmp);
11420
          end
11421
          else
11422
          begin
11423
            check_rx_packet(max_tmp, (`MEMORY_BASE + num_of_frames[1:0] - 1'b1), (i_length + 4), 1'b0, 1'b0, tmp);
11424
          end
11425
          if (tmp > 0)
11426
          begin
11427
            `TIME; $display("*E Wrong data of the received packet");
11428
            test_fail("Wrong data of the received packet");
11429
            fail = fail + 1;
11430
          end
11431
        end
11432
        else // if PREVIOUS RX buffer descriptor was ready
11433
        begin
11434
          if (num_of_frames[1] == 1'b0)
11435
          begin
11436
            check_rx_packet(0, (`MEMORY_BASE + num_of_frames[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
11437
          end
11438
          else
11439
          begin
11440
            check_rx_packet(max_tmp, (`MEMORY_BASE + num_of_frames[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
11441
          end
11442
          if (tmp > 0)
11443
          begin
11444
            `TIME; $display("*E Wrong data of the received packet");
11445
            test_fail("Wrong data of the received packet");
11446
            fail = fail + 1;
11447
          end
11448
        end
11449
      end
11450
      // check WB INT signal
11451
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
11452
      begin
11453
        if (wb_int !== 1'b0)
11454
        begin
11455
          `TIME; $display("*E WB INT signal should not be set");
11456
          test_fail("WB INT signal should not be set");
11457
          fail = fail + 1;
11458
        end
11459
      end
11460
      else
11461
      begin
11462
        if (wb_int !== 1'b1)
11463
        begin
11464
          `TIME; $display("*E WB INT signal should be set");
11465
          test_fail("WB INT signal should be set");
11466
          fail = fail + 1;
11467
        end
11468
      end
11469
      // check RX buffer descriptor of a packet - only 15 LSBits
11470
      check_rx_bd(118, data);
11471
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
11472
      begin
11473
        if (data[15:0] !== 16'hE000)
11474
        begin
11475
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
11476
          test_fail("RX buffer descriptor status is not correct");
11477
          fail = fail + 1;
11478
        end
11479
      end
11480
      else // interrupt enabled
11481
      begin
11482 279 mohor
        if ((data[15:0] !== 16'h6000) && (data[15:0] !== 16'h6080)) // because of promiscuous
11483 243 tadejm
        begin
11484
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
11485
          test_fail("RX buffer descriptor status is not correct");
11486
          fail = fail + 1;
11487
        end
11488
      end
11489
      // check interrupts
11490 274 tadejm
      wait (wbm_working == 0);
11491 243 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11492
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
11493
      begin
11494
        if (data !== 0)
11495
        begin
11496
          `TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, num_of_frames[1:0]);
11497
          test_fail("Any of interrupts was set");
11498
          fail = fail + 1;
11499
        end
11500
      end
11501
      else
11502
      begin
11503
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
11504
        begin
11505
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
11506
          test_fail("Interrupt Receive Buffer was not set");
11507
          fail = fail + 1;
11508
        end
11509
        if ((data & (~`ETH_INT_RXB)) !== 0)
11510
        begin
11511
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
11512
          test_fail("Other interrupts (except Receive Buffer) were set");
11513
          fail = fail + 1;
11514
        end
11515
      end
11516
      // clear interrupts
11517 274 tadejm
      wait (wbm_working == 0);
11518 243 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11519
      // check WB INT signal
11520
      if (wb_int !== 1'b0)
11521
      begin
11522
        test_fail("WB INT signal should not be set");
11523
        fail = fail + 1;
11524
      end
11525
      // disable RX after two packets
11526
      if (num_of_frames[0] == 1'b1)
11527
      begin
11528
        // disable RX, set full-duplex mode, NO receive small, NO correct IFG
11529 274 tadejm
        wait (wbm_working == 0);
11530 243 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
11531
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
11532
                  4'hF, 1, 4'h0, 4'h0); // write ASAP
11533
      end
11534
      // the number of frame transmitted
11535
      num_of_frames = num_of_frames + 1;
11536
      num_of_bd = 0;
11537
      // set length (LOOP variable)
11538
      if (num_of_frames[31:2] == (i_length * 2 + 16)) // 64 => this vas last Byte (1st .. 64th) when i_length = min_tmp - 4
11539
        i_length = (max_tmp - 4);
11540
      @(posedge wb_clk);
11541
    end
11542
    // disable RX
11543 274 tadejm
    wait (wbm_working == 0);
11544 243 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
11545
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11546
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11547
    if(fail == 0)
11548
      test_ok;
11549
    else
11550
      fail = 0;
11551
  end
11552
 
11553
 
11554
  ////////////////////////////////////////////////////////////////////
11555
  ////                                                            ////
11556
  ////  Test receive packet synchronization with receive          ////
11557
  ////  disable/enable ( 100Mbps ).                               ////
11558
  ////                                                            ////
11559
  ////////////////////////////////////////////////////////////////////
11560
  if (test_num == 3) // Test no receive when all buffers are TX ( 100Mbps ).
11561
  begin
11562
    // TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )
11563
    test_name   = "TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )";
11564
    `TIME; $display("  TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )");
11565
 
11566
    // unmask interrupts
11567 274 tadejm
    wait (wbm_working == 0);
11568 243 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
11569
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11570
    // set 10 RX buffer descriptor (8'h80 - 8'hA) - must be set before RX enable
11571 274 tadejm
    wait (wbm_working == 0);
11572 243 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h76, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11573
    // disable RX, set full-duplex mode, NO receive small, NO correct IFG
11574 274 tadejm
    wait (wbm_working == 0);
11575 243 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
11576
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11577
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11578
    // prepare two packets of MAXFL length
11579 274 tadejm
    wait (wbm_working == 0);
11580 243 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11581
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
11582
    min_tmp = tmp[31:16];
11583
    st_data = 8'h0F;
11584
    set_rx_packet(0, (min_tmp + 1), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
11585
    append_rx_crc(0, (min_tmp + 1), 1'b0, 1'b0);
11586
    st_data = 8'h1A;
11587
    set_rx_packet(max_tmp, (min_tmp + 1), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
11588
    append_rx_crc(max_tmp, (min_tmp + 1), 1'b0, 1'b0);
11589
    // check WB INT signal
11590
    if (wb_int !== 1'b0)
11591
    begin
11592
      test_fail("WB INT signal should not be set");
11593
      fail = fail + 1;
11594
    end
11595
 
11596
    // write to phy's control register for 100Mbps
11597
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
11598
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
11599
    speed = 100;
11600
 
11601
    frame_started = 0;
11602
    frame_ended = 0;
11603
    wait_for_frame = 0;
11604
    check_frame = 0;
11605
    stop_checking_frame = 0;
11606
    first_fr_received = 1; // at the beginning the first frame of each two will be received!
11607
 
11608
    num_of_frames = 0; // 
11609
    num_of_bd = 0;
11610
    i_length = (min_tmp + 1); // 5 bytes longer than MINFL
11611
    while (i_length < (max_tmp - 4))
11612
    begin
11613
      // choose generating carrier sense and collision 
11614
      case (num_of_frames[1:0])
11615
      2'h0: // Interrupt is generated
11616
      begin
11617
        // enable interrupt generation
11618
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
11619
        // not detect carrier sense in FD and no collision
11620
        eth_phy.no_carrier_sense_rx_fd_detect(0);
11621
        eth_phy.collision(0);
11622
      end
11623
      2'h1: // Interrupt is generated
11624
      begin
11625
        // enable interrupt generation
11626
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
11627
        // detect carrier sense in FD and no collision
11628
        eth_phy.no_carrier_sense_rx_fd_detect(1);
11629
        eth_phy.collision(0);
11630
      end
11631
      2'h2: // Interrupt is generated
11632
      begin
11633
        // disable interrupt generation
11634
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
11635
        // not detect carrier sense in FD and set collision
11636
        eth_phy.no_carrier_sense_rx_fd_detect(0);
11637
        eth_phy.collision(1);
11638
      end
11639
      default: // 2'h3: // Interrupt is generated
11640
      begin
11641
        // disable interrupt generation
11642
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
11643
        // detect carrier sense in FD and set collision
11644
        eth_phy.no_carrier_sense_rx_fd_detect(1);
11645
        eth_phy.collision(1);
11646
      end
11647
      endcase
11648
//if (first_fr_received == 0)
11649
//begin
11650
//  check_rx_bd(118, data);
11651 274 tadejm
//  wait (wbm_working == 0);
11652 243 tadejm
//  wbm_read((`TX_BD_BASE + (118 * 8) + 4), tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11653
//  $display("RX BD set : %h, %h", data, tmp);
11654
//end
11655
      // set wrap bit
11656
      set_rx_bd_wrap(118);
11657
      set_rx_bd_empty(118, 118);
11658
      check_frame = 0;
11659
      stop_checking_frame = 0;
11660
      tmp_data = 0;
11661
      fork
11662
        begin // enable RX MAC on first of each two packets - every second should be recived normaly
11663
          if (num_of_frames[0] == 1'b0)
11664
          begin
11665
            repeat(1) @(posedge wb_clk);
11666
            if (num_of_frames[1] == 1'b0)
11667
            begin
11668
              repeat (num_of_frames[31:2]) @(posedge mrx_clk); // for every (second) frame enable receiver one clock later
11669
            end
11670
            else
11671
            begin
11672
              @(posedge mrx_clk);
11673
              repeat (num_of_frames[31:2]) @(negedge mrx_clk); // for every (second) frame enable receiver one clock later
11674
            end
11675
            // enable RX, set full-duplex mode, NO receive small, NO correct IFG
11676
            wbm_init_waits = 4'h0;
11677
            wbm_subseq_waits = 4'h0;
11678 274 tadejm
            #1 wait (wbm_working == 0);
11679
            wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
11680 243 tadejm
                      `ETH_MODER_PRO | `ETH_MODER_BRO,
11681
                      4'hF, 1, wbm_init_waits, wbm_subseq_waits); // write ASAP
11682
$display("mama 2, num_of_frames=%0h", num_of_frames);
11683
          end
11684
        end
11685
        begin // send a packet from PHY RX
11686
          repeat(1) @(posedge wb_clk); // wait for WB write when it is without delays
11687
          if (num_of_frames[1] == 1'b0)
11688
          begin
11689
            set_rx_addr_type(0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E);
11690
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
11691
          end
11692
          else
11693
          begin
11694
            set_rx_addr_type((max_tmp), 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E);
11695
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
11696
          end
11697
        end
11698
        begin: send_packet1
11699
          wait (MRxDV === 1'b1); // start transmit
11700
          wait (MRxDV === 1'b0); // end transmit
11701
          check_frame = 1;
11702
$display("mama 3");
11703
          repeat(10) @(posedge mrx_clk);
11704
          repeat(15) @(posedge wb_clk);
11705
          stop_checking_frame = 1;
11706
        end
11707
        begin // count WB clocks between ACK (negedge) and RX_DV (posedge) or vice-versa
11708
          @(posedge eth_sl_wb_ack_o or posedge MRxDV);
11709
$display("mama 4");
11710
          if ((eth_sl_wb_ack_o === 1'b1) && (MRxDV === 1'b1))
11711
          begin
11712
            tmp_data = 32'h8000_0001; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
11713
$display("mama 4_1");
11714
          end
11715
          else if (MRxDV === 1'b1)
11716
          begin
11717
            while (eth_sl_wb_ack_o === 1'b0)
11718
            begin
11719
              @(posedge wb_clk);
11720
              tmp_data = tmp_data + 1;
11721
            end
11722
            tmp_data = tmp_data | 32'h8000_0000; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
11723
$display("mama 4_2");
11724
          end
11725
          else if (eth_sl_wb_ack_o === 1'b1)
11726
          begin
11727
            @(posedge wb_clk); // wait for one clock => tmp_data 'becomes' 0
11728
            while (MRxDV === 1'b0)
11729
            begin
11730
              @(posedge wb_clk);
11731
              tmp_data = tmp_data + 1; // bit[31]==0 => 'negedge eth_sl_wb_ack_o' was equal or before 'posedge MRxDV'
11732
            end
11733
$display("mama 4_3");
11734
          end
11735
        end
11736
        begin // check packet
11737
          wait (check_frame == 1);
11738
          check_rx_bd(118, tmp_bd);
11739
          while ((tmp_bd[15] === 1) && (stop_checking_frame == 0))
11740
          begin
11741
            #1 check_rx_bd(118, tmp_bd);
11742
            @(posedge wb_clk);
11743
          end
11744
$display("mama 5, tmp_bd=%0h", tmp_bd);
11745
          if (num_of_frames[0] == 1'b0)
11746
          begin
11747
            if (tmp_bd[15] === 1)
11748
            begin
11749
              if (first_fr_received == 1)
11750
              begin
11751
                first_fr_received = 0;
11752
                $display("    %0d packets (without this one) are checked - packets are received by two in a set",
11753
                         num_of_frames); // +1 due to start with 0 AND -1 because this packet is excluded
11754
                $display("    From this moment:");
11755
                $display("    first one of two packets (including this one) is not accepted due to late RX enable");
11756
                if (tmp_data[31])
11757
                  $display("    ->RX enable set %0d WB clks after RX_DV", tmp_data[30:0]);
11758
                else
11759
                  $display("    ->RX enable set %0d WB clks before RX_DV", tmp_data[30:0]);
11760
              end
11761
              // check FB, etc.
11762
 
11763
            end
11764
            else // (tmp_bd[15] === 0)
11765
            begin // check FB, packet, etc.
11766
 
11767
            end
11768
$display("mama 5_1");
11769
          end
11770
          else // (num_of_frames[0] == 1'b1)
11771
          begin
11772
            if (tmp_bd[15] === 1) // ERROR, because second packet of each two frames should be received
11773
            begin // check NOTHING
11774
 
11775
            end
11776
            else // (tmp_bd[15] === 0)
11777
            begin // check FB, packet, etc.
11778
 
11779
            end
11780
$display("mama 5_2");
11781
          end
11782
          if (stop_checking_frame == 0)
11783
            disable send_packet1;
11784
        end
11785
      join
11786
      // ONLY IF packet was received!
11787
$display("mama 6");
11788
      if (tmp_bd[15] === 0)
11789
      begin
11790
        // check length of a PACKET
11791
        if (tmp_bd[31:16] != (i_length + 4))
11792
        begin
11793
          `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
11794
                          tmp_bd[31:16], (i_length + 4));
11795
          test_fail("Wrong length of the packet out from PHY");
11796
          fail = fail + 1;
11797
        end
11798
        // check received RX packet data and CRC
11799
        if (first_fr_received == 0) // if PREVIOUS RX buffer descriptor was not ready, pointer address is -1
11800
        begin
11801
          if (num_of_frames[1] == 1'b0)
11802
          begin
11803
            check_rx_packet(0, (`MEMORY_BASE + num_of_frames[1:0] - 1'b1), (i_length + 4), 1'b0, 1'b0, tmp);
11804
          end
11805
          else
11806
          begin
11807
            check_rx_packet(max_tmp, (`MEMORY_BASE + num_of_frames[1:0] - 1'b1), (i_length + 4), 1'b0, 1'b0, tmp);
11808
          end
11809
          if (tmp > 0)
11810
          begin
11811
            `TIME; $display("*E Wrong data of the received packet");
11812
            test_fail("Wrong data of the received packet");
11813
            fail = fail + 1;
11814
          end
11815
        end
11816
        else // if PREVIOUS RX buffer descriptor was ready
11817
        begin
11818
          if (num_of_frames[1] == 1'b0)
11819
          begin
11820
            check_rx_packet(0, (`MEMORY_BASE + num_of_frames[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
11821
          end
11822
          else
11823
          begin
11824
            check_rx_packet(max_tmp, (`MEMORY_BASE + num_of_frames[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
11825
          end
11826
          if (tmp > 0)
11827
          begin
11828
            `TIME; $display("*E Wrong data of the received packet");
11829
            test_fail("Wrong data of the received packet");
11830
            fail = fail + 1;
11831
          end
11832
        end
11833
      end
11834
      // check WB INT signal
11835
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
11836
      begin
11837
        if (wb_int !== 1'b0)
11838
        begin
11839
          `TIME; $display("*E WB INT signal should not be set");
11840
          test_fail("WB INT signal should not be set");
11841
          fail = fail + 1;
11842
        end
11843
      end
11844
      else
11845
      begin
11846
        if (wb_int !== 1'b1)
11847
        begin
11848
          `TIME; $display("*E WB INT signal should be set");
11849
          test_fail("WB INT signal should be set");
11850
          fail = fail + 1;
11851
        end
11852
      end
11853
      // check RX buffer descriptor of a packet - only 15 LSBits
11854
      check_rx_bd(118, data);
11855
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
11856
      begin
11857
        if (data[15:0] !== 16'hE000)
11858
        begin
11859
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
11860
          test_fail("RX buffer descriptor status is not correct");
11861
          fail = fail + 1;
11862
        end
11863
      end
11864
      else // interrupt enabled
11865
      begin
11866 279 mohor
        if ((data[15:0] !== 16'h6000) && (data[15:0] !== 16'h6080)) // because of promiscuous
11867 243 tadejm
        begin
11868
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
11869
          test_fail("RX buffer descriptor status is not correct");
11870
          fail = fail + 1;
11871
        end
11872
      end
11873
      // check interrupts
11874 274 tadejm
      wait (wbm_working == 0);
11875 243 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11876
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
11877
      begin
11878
        if (data !== 0)
11879
        begin
11880
          `TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, num_of_frames[1:0]);
11881
          test_fail("Any of interrupts was set");
11882
          fail = fail + 1;
11883
        end
11884
      end
11885
      else
11886
      begin
11887
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
11888
        begin
11889
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
11890
          test_fail("Interrupt Receive Buffer was not set");
11891
          fail = fail + 1;
11892
        end
11893
        if ((data & (~`ETH_INT_RXB)) !== 0)
11894
        begin
11895
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
11896
          test_fail("Other interrupts (except Receive Buffer) were set");
11897
          fail = fail + 1;
11898
        end
11899
      end
11900
      // clear interrupts
11901 274 tadejm
      wait (wbm_working == 0);
11902 243 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11903
      // check WB INT signal
11904
      if (wb_int !== 1'b0)
11905
      begin
11906
        test_fail("WB INT signal should not be set");
11907
        fail = fail + 1;
11908
      end
11909
      // disable RX after two packets
11910
      if (num_of_frames[0] == 1'b1)
11911
      begin
11912
        // disable RX, set full-duplex mode, NO receive small, NO correct IFG
11913 274 tadejm
        wait (wbm_working == 0);
11914 243 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
11915
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
11916
                  4'hF, 1, 4'h0, 4'h0); // write ASAP
11917
      end
11918
      // the number of frame transmitted
11919
      num_of_frames = num_of_frames + 1;
11920
      num_of_bd = 0;
11921
      // set length (LOOP variable)
11922
      if (num_of_frames[31:2] == (i_length * 2 + 16)) // 64 => this vas last Byte (1st .. 64th) when i_length = min_tmp - 4
11923
        i_length = (max_tmp - 4);
11924
      @(posedge wb_clk);
11925
    end
11926
    // disable RX
11927 274 tadejm
    wait (wbm_working == 0);
11928 243 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
11929
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11930
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11931
    if(fail == 0)
11932
      test_ok;
11933
    else
11934
      fail = 0;
11935
  end
11936
 
11937
 
11938
  ////////////////////////////////////////////////////////////////////
11939
  ////                                                            ////
11940 209 tadejm
  ////  Test receive packets form MINFL to MAXFL sizes at         ////
11941
  ////  one RX buffer decriptor ( 10Mbps ).                       ////
11942
  ////                                                            ////
11943
  ////////////////////////////////////////////////////////////////////
11944 243 tadejm
  if (test_num == 4) // 
11945 209 tadejm
  begin
11946 243 tadejm
    // TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )
11947
    test_name   = "TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )";
11948
    `TIME; $display("  TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )");
11949 209 tadejm
 
11950
    // unmask interrupts
11951 274 tadejm
    wait (wbm_working == 0);
11952 209 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
11953
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11954
    // set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
11955 274 tadejm
    wait (wbm_working == 0);
11956 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11957
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
11958 274 tadejm
    wait (wbm_working == 0);
11959 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
11960
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11961
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11962
    // prepare two packets of MAXFL length
11963 274 tadejm
    wait (wbm_working == 0);
11964 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11965
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
11966
    min_tmp = tmp[31:16];
11967
    st_data = 8'h0F;
11968
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
11969
    st_data = 8'h1A;
11970
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
11971
    // check WB INT signal
11972
    if (wb_int !== 1'b0)
11973
    begin
11974
      test_fail("WB INT signal should not be set");
11975
      fail = fail + 1;
11976
    end
11977
 
11978
    // write to phy's control register for 10Mbps
11979
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
11980
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
11981
    speed = 10;
11982
 
11983
    i_length = (min_tmp - 4);
11984
    while (i_length <= (max_tmp - 4))
11985
    begin
11986
      // choose generating carrier sense and collision for first and last 64 lengths of frames
11987
      case (i_length[1:0])
11988
      2'h0: // Interrupt is generated
11989
      begin
11990
        // enable interrupt generation
11991
        set_rx_bd(127, 127, 1'b1, (`MEMORY_BASE + i_length[1:0]));
11992
        // unmask interrupts
11993 274 tadejm
        wait (wbm_working == 0);
11994 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
11995
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11996
        // not detect carrier sense in FD and no collision
11997
        eth_phy.no_carrier_sense_rx_fd_detect(0);
11998
        eth_phy.collision(0);
11999
      end
12000
      2'h1: // Interrupt is not generated
12001
      begin
12002
        // enable interrupt generation
12003
        set_rx_bd(127, 127, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
12004
        // mask interrupts
12005 274 tadejm
        wait (wbm_working == 0);
12006 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12007
        // detect carrier sense in FD and no collision
12008
        eth_phy.no_carrier_sense_rx_fd_detect(1);
12009
        eth_phy.collision(0);
12010
      end
12011
      2'h2: // Interrupt is not generated
12012
      begin
12013
        // disable interrupt generation
12014
        set_rx_bd(127, 127, 1'b0, (`MEMORY_BASE + i_length[1:0]));
12015
        // unmask interrupts
12016 274 tadejm
        wait (wbm_working == 0);
12017 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
12018
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12019
        // not detect carrier sense in FD and set collision
12020
        eth_phy.no_carrier_sense_rx_fd_detect(0);
12021
        eth_phy.collision(1);
12022
      end
12023
      default: // 2'h3: // Interrupt is not generated
12024
      begin
12025
        // disable interrupt generation
12026
        set_rx_bd(127, 127, 1'b0, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
12027
        // mask interrupts
12028 274 tadejm
        wait (wbm_working == 0);
12029 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12030
        // detect carrier sense in FD and set collision
12031
        eth_phy.no_carrier_sense_rx_fd_detect(1);
12032
        eth_phy.collision(1);
12033
      end
12034
      endcase
12035
      if (i_length[0] == 1'b0)
12036
        append_rx_crc (0, i_length, 1'b0, 1'b0);
12037
      else
12038
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
12039
      // set wrap bit
12040
      set_rx_bd_wrap(127);
12041
      set_rx_bd_empty(127, 127);
12042
      fork
12043
        begin
12044
          if (i_length[0] == 1'b0)
12045
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
12046
          else
12047
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
12048
          repeat(10) @(posedge mrx_clk);
12049
        end
12050
        begin
12051
          #1 check_rx_bd(127, data);
12052
          if (i_length < min_tmp) // just first four
12053
          begin
12054
            while (data[15] === 1)
12055
            begin
12056
              #1 check_rx_bd(127, data);
12057
              @(posedge wb_clk);
12058
            end
12059
            repeat (1) @(posedge wb_clk);
12060
          end
12061
          else
12062
          begin
12063
            wait (MRxDV === 1'b1); // start transmit
12064
            #1 check_rx_bd(127, data);
12065
            if (data[15] !== 1)
12066
            begin
12067
              test_fail("Wrong buffer descriptor's ready bit read out from MAC");
12068
              fail = fail + 1;
12069
            end
12070
            wait (MRxDV === 1'b0); // end transmit
12071
            while (data[15] === 1)
12072
            begin
12073
              #1 check_rx_bd(127, data);
12074
              @(posedge wb_clk);
12075
            end
12076
            repeat (1) @(posedge wb_clk);
12077
          end
12078
        end
12079
      join
12080
      // check length of a PACKET
12081
      if (data[31:16] != (i_length + 4))
12082
      begin
12083
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
12084
                        data[31:16], (i_length + 4));
12085
        test_fail("Wrong length of the packet out from PHY");
12086
        fail = fail + 1;
12087
      end
12088
      // checking in the following if statement is performed only for first and last 64 lengths
12089
      // check received RX packet data and CRC
12090
      if (i_length[0] == 1'b0)
12091
      begin
12092
        check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
12093
      end
12094
      else
12095
      begin
12096
        check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
12097
      end
12098
      if (tmp > 0)
12099
      begin
12100
        `TIME; $display("*E Wrong data of the received packet");
12101
        test_fail("Wrong data of the received packet");
12102
        fail = fail + 1;
12103
      end
12104
      // check WB INT signal
12105
      if (i_length[1:0] == 2'h0)
12106
      begin
12107
        if (wb_int !== 1'b1)
12108
        begin
12109
          `TIME; $display("*E WB INT signal should be set");
12110
          test_fail("WB INT signal should be set");
12111
          fail = fail + 1;
12112
        end
12113
      end
12114
      else
12115
      begin
12116
        if (wb_int !== 1'b0)
12117
        begin
12118
          `TIME; $display("*E WB INT signal should not be set");
12119
          test_fail("WB INT signal should not be set");
12120
          fail = fail + 1;
12121
        end
12122
      end
12123
      // check RX buffer descriptor of a packet
12124
      check_rx_bd(127, data);
12125
      if (i_length[1] == 1'b0) // interrupt enabled no_carrier_sense_rx_fd_detect
12126
      begin
12127 281 mohor
        if ( ((data[15:0] !== 16'h6080) && (i_length[0] == 1'b0)) ||
12128
             ((data[15:0] !== 16'h6080) && (i_length[0] == 1'b1)) )
12129 209 tadejm
        begin
12130
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
12131
          test_fail("RX buffer descriptor status is not correct");
12132
          fail = fail + 1;
12133
        end
12134
      end
12135
      else // interrupt not enabled
12136
      begin
12137 281 mohor
        if ( ((data[15:0] !== 16'h2080) && (i_length[0] == 1'b0)) ||
12138
             ((data[15:0] !== 16'h2080) && (i_length[0] == 1'b1)) )
12139 209 tadejm
        begin
12140
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
12141
          test_fail("RX buffer descriptor status is not correct");
12142
          fail = fail + 1;
12143
        end
12144
      end
12145
      // clear RX buffer descriptor for first 4 frames
12146
      if (i_length < min_tmp)
12147
        clear_rx_bd(127, 127);
12148
      // check interrupts
12149 274 tadejm
      wait (wbm_working == 0);
12150 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12151
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
12152
      begin
12153
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
12154
        begin
12155
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
12156
          test_fail("Interrupt Receive Buffer was not set");
12157
          fail = fail + 1;
12158
        end
12159
        if ((data & (~`ETH_INT_RXB)) !== 0)
12160
        begin
12161
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
12162
          test_fail("Other interrupts (except Receive Buffer) were set");
12163
          fail = fail + 1;
12164
        end
12165
      end
12166
      else
12167
      begin
12168
        if (data !== 0)
12169
        begin
12170
          `TIME; $display("*E Any of interrupts (except Receive Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
12171
          test_fail("Any of interrupts (except Receive Buffer) was set");
12172
          fail = fail + 1;
12173
        end
12174
      end
12175
      // clear interrupts
12176 274 tadejm
      wait (wbm_working == 0);
12177 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12178
      // check WB INT signal
12179
      if (wb_int !== 1'b0)
12180
      begin
12181
        test_fail("WB INT signal should not be set");
12182
        fail = fail + 1;
12183
      end
12184
      // INTERMEDIATE DISPLAYS
12185
      if ((i_length + 4) == (min_tmp + 64))
12186
      begin
12187
        // starting length is min_tmp, ending length is (min_tmp + 64)
12188
        $display("    receive small packets is NOT selected");
12189
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
12190
                 min_tmp, (min_tmp + 64));
12191
        // set receive small, remain the rest
12192 274 tadejm
        wait (wbm_working == 0);
12193 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
12194
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12195
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12196
      end
12197
      else if ((i_length + 4) == (max_tmp - 16))
12198
      begin
12199
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
12200
        $display("    receive small packets is selected");
12201
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
12202
                 (min_tmp + 64 + 128), tmp_data);
12203
        // reset receive small, remain the rest
12204 274 tadejm
        wait (wbm_working == 0);
12205 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
12206
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12207
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12208
      end
12209
      else if ((i_length + 4) == max_tmp)
12210
      begin
12211
        $display("    receive small packets is NOT selected");
12212
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
12213
                 (max_tmp - (4 + 16)), max_tmp);
12214
      end
12215
      // set length (loop variable)
12216
      if ((i_length + 4) < (min_tmp + 64))
12217
        i_length = i_length + 1;
12218
      else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
12219
      begin
12220
        i_length = i_length + 128;
12221
        tmp_data = i_length + 4; // last tmp_data is ending length
12222
      end
12223
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
12224
        i_length = max_tmp - (4 + 16);
12225
      else if ((i_length + 4) >= (max_tmp - 16))
12226
        i_length = i_length + 1;
12227
      else
12228
      begin
12229
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
12230
        #10 $stop;
12231
      end
12232
    end
12233
    // disable RX
12234 274 tadejm
    wait (wbm_working == 0);
12235 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
12236
              `ETH_MODER_PRO | `ETH_MODER_BRO,
12237
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12238
    if(fail == 0)
12239
      test_ok;
12240
    else
12241
      fail = 0;
12242
  end
12243
 
12244
 
12245
  ////////////////////////////////////////////////////////////////////
12246
  ////                                                            ////
12247
  ////  Test receive packets form MINFL to MAXFL sizes at         ////
12248
  ////  one RX buffer decriptor ( 100Mbps ).                      ////
12249
  ////                                                            ////
12250
  ////////////////////////////////////////////////////////////////////
12251 243 tadejm
  if (test_num == 5) // Test no receive when all buffers are TX ( 100Mbps ).
12252 209 tadejm
  begin
12253 243 tadejm
    // TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )
12254
    test_name   = "TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )";
12255
    `TIME; $display("  TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )");
12256 209 tadejm
 
12257
    // unmask interrupts
12258 274 tadejm
    wait (wbm_working == 0);
12259 209 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
12260
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12261
    // set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
12262 274 tadejm
    wait (wbm_working == 0);
12263 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12264
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
12265 274 tadejm
    wait (wbm_working == 0);
12266 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
12267
              `ETH_MODER_PRO | `ETH_MODER_BRO,
12268
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12269
    // prepare two packets of MAXFL length
12270 274 tadejm
    wait (wbm_working == 0);
12271 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12272
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
12273
    min_tmp = tmp[31:16];
12274
    st_data = 8'h0F;
12275
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
12276
    st_data = 8'h1A;
12277
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
12278
    // check WB INT signal
12279
    if (wb_int !== 1'b0)
12280
    begin
12281
      test_fail("WB INT signal should not be set");
12282
      fail = fail + 1;
12283
    end
12284
 
12285
    // write to phy's control register for 100Mbps
12286
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
12287
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
12288
    speed = 100;
12289
 
12290
    i_length = (min_tmp - 4);
12291
    while (i_length <= (max_tmp - 4))
12292
    begin
12293
      // choose generating carrier sense and collision for first and last 64 lengths of frames
12294
      case (i_length[1:0])
12295
      2'h0: // Interrupt is generated
12296
      begin
12297
        // enable interrupt generation
12298
        set_rx_bd(127, 127, 1'b1, (`MEMORY_BASE + i_length[1:0]));
12299
        // unmask interrupts
12300 274 tadejm
        wait (wbm_working == 0);
12301 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
12302
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12303
        // not detect carrier sense in FD and no collision
12304
        eth_phy.no_carrier_sense_rx_fd_detect(0);
12305
        eth_phy.collision(0);
12306
      end
12307
      2'h1: // Interrupt is not generated
12308
      begin
12309
        // enable interrupt generation
12310
        set_rx_bd(127, 127, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
12311
        // mask interrupts
12312 274 tadejm
        wait (wbm_working == 0);
12313 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12314
        // detect carrier sense in FD and no collision
12315
        eth_phy.no_carrier_sense_rx_fd_detect(1);
12316
        eth_phy.collision(0);
12317
      end
12318
      2'h2: // Interrupt is not generated
12319
      begin
12320
        // disable interrupt generation
12321
        set_rx_bd(127, 127, 1'b0, (`MEMORY_BASE + i_length[1:0]));
12322
        // unmask interrupts
12323 274 tadejm
        wait (wbm_working == 0);
12324 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
12325
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12326
        // not detect carrier sense in FD and set collision
12327
        eth_phy.no_carrier_sense_rx_fd_detect(0);
12328
        eth_phy.collision(1);
12329
      end
12330
      default: // 2'h3: // Interrupt is not generated
12331
      begin
12332
        // disable interrupt generation
12333
        set_rx_bd(127, 127, 1'b0, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
12334
        // mask interrupts
12335 274 tadejm
        wait (wbm_working == 0);
12336 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12337
        // detect carrier sense in FD and set collision
12338
        eth_phy.no_carrier_sense_rx_fd_detect(1);
12339
        eth_phy.collision(1);
12340
      end
12341
      endcase
12342
      if (i_length[0] == 1'b0)
12343
        append_rx_crc (0, i_length, 1'b0, 1'b0);
12344
      else
12345
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
12346
      // set wrap bit
12347
      set_rx_bd_wrap(127);
12348
      set_rx_bd_empty(127, 127);
12349
      fork
12350
        begin
12351
          if (i_length[0] == 1'b0)
12352
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
12353
          else
12354
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
12355
          repeat(10) @(posedge mrx_clk);
12356
        end
12357
        begin
12358
          #1 check_rx_bd(127, data);
12359
          if (i_length < min_tmp) // just first four
12360
          begin
12361
            while (data[15] === 1)
12362
            begin
12363
              #1 check_rx_bd(127, data);
12364
              @(posedge wb_clk);
12365
            end
12366
            repeat (1) @(posedge wb_clk);
12367
          end
12368
          else
12369
          begin
12370
            wait (MRxDV === 1'b1); // start transmit
12371
            #1 check_rx_bd(127, data);
12372
            if (data[15] !== 1)
12373
            begin
12374
              test_fail("Wrong buffer descriptor's ready bit read out from MAC");
12375
              fail = fail + 1;
12376
            end
12377
            wait (MRxDV === 1'b0); // end transmit
12378
            while (data[15] === 1)
12379
            begin
12380
              #1 check_rx_bd(127, data);
12381
              @(posedge wb_clk);
12382
            end
12383
            repeat (1) @(posedge wb_clk);
12384
          end
12385
        end
12386
      join
12387
      // check length of a PACKET
12388
      if (data[31:16] != (i_length + 4))
12389
      begin
12390
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
12391
                        data[31:16], (i_length + 4));
12392
        test_fail("Wrong length of the packet out from PHY");
12393
        fail = fail + 1;
12394
      end
12395
      // checking in the following if statement is performed only for first and last 64 lengths
12396
      // check received RX packet data and CRC
12397
      if (i_length[0] == 1'b0)
12398
      begin
12399
        check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
12400
      end
12401
      else
12402
      begin
12403
        check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
12404
      end
12405
      if (tmp > 0)
12406
      begin
12407
        `TIME; $display("*E Wrong data of the received packet");
12408
        test_fail("Wrong data of the received packet");
12409
        fail = fail + 1;
12410
      end
12411
      // check WB INT signal
12412
      if (i_length[1:0] == 2'h0)
12413
      begin
12414
        if (wb_int !== 1'b1)
12415
        begin
12416
          `TIME; $display("*E WB INT signal should be set");
12417
          test_fail("WB INT signal should be set");
12418
          fail = fail + 1;
12419
        end
12420
      end
12421
      else
12422
      begin
12423
        if (wb_int !== 1'b0)
12424
        begin
12425
          `TIME; $display("*E WB INT signal should not be set");
12426
          test_fail("WB INT signal should not be set");
12427
          fail = fail + 1;
12428
        end
12429
      end
12430
      // check RX buffer descriptor of a packet
12431
      check_rx_bd(127, data);
12432
      if (i_length[1] == 1'b0) // interrupt enabled 
12433
      begin
12434 281 mohor
        if ( ((data[15:0] !== 16'h6080) && (i_length[0] == 1'b0)) ||
12435
             ((data[15:0] !== 16'h6080) && (i_length[0] == 1'b1)) )
12436 209 tadejm
        begin
12437
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
12438
          test_fail("RX buffer descriptor status is not correct");
12439
          fail = fail + 1;
12440
        end
12441
      end
12442
      else // interrupt not enabled
12443
      begin
12444 281 mohor
        if ( ((data[15:0] !== 16'h2080) && (i_length[0] == 1'b0)) ||
12445
             ((data[15:0] !== 16'h2080) && (i_length[0] == 1'b1)) )
12446 209 tadejm
        begin
12447
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
12448
          test_fail("RX buffer descriptor status is not correct");
12449
          fail = fail + 1;
12450
        end
12451
      end
12452
      // clear RX buffer descriptor for first 4 frames
12453
      if (i_length < min_tmp)
12454
        clear_rx_bd(127, 127);
12455
      // check interrupts
12456 274 tadejm
      wait (wbm_working == 0);
12457 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12458
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
12459
      begin
12460
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
12461
        begin
12462
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
12463
          test_fail("Interrupt Receive Buffer was not set");
12464
          fail = fail + 1;
12465
        end
12466
        if ((data & (~`ETH_INT_RXB)) !== 0)
12467
        begin
12468
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
12469
          test_fail("Other interrupts (except Receive Buffer) were set");
12470
          fail = fail + 1;
12471
        end
12472
      end
12473
      else
12474
      begin
12475
        if (data !== 0)
12476
        begin
12477
          `TIME; $display("*E Any of interrupts (except Receive Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
12478
          test_fail("Any of interrupts (except Receive Buffer) was set");
12479
          fail = fail + 1;
12480
        end
12481
      end
12482
      // clear interrupts
12483 274 tadejm
      wait (wbm_working == 0);
12484 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12485
      // check WB INT signal
12486
      if (wb_int !== 1'b0)
12487
      begin
12488
        test_fail("WB INT signal should not be set");
12489
        fail = fail + 1;
12490
      end
12491
      // INTERMEDIATE DISPLAYS
12492
      if ((i_length + 4) == (min_tmp + 64))
12493
      begin
12494
        // starting length is min_tmp, ending length is (min_tmp + 64)
12495
        $display("    receive small packets is NOT selected");
12496
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
12497
                 min_tmp, (min_tmp + 64));
12498
        // set receive small, remain the rest
12499 274 tadejm
        wait (wbm_working == 0);
12500 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
12501
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12502
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12503
      end
12504
      else if ((i_length + 4) == (max_tmp - 16))
12505
      begin
12506
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
12507
        $display("    receive small packets is selected");
12508
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
12509
                 (min_tmp + 64 + 128), tmp_data);
12510
        // reset receive small, remain the rest
12511 274 tadejm
        wait (wbm_working == 0);
12512 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
12513
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12514
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12515
      end
12516
      else if ((i_length + 4) == max_tmp)
12517
      begin
12518
        $display("    receive small packets is NOT selected");
12519
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
12520
                 (max_tmp - (4 + 16)), max_tmp);
12521
      end
12522
      // set length (loop variable)
12523
      if ((i_length + 4) < (min_tmp + 64))
12524
        i_length = i_length + 1;
12525
      else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
12526
      begin
12527
        i_length = i_length + 128;
12528
        tmp_data = i_length + 4; // last tmp_data is ending length
12529
      end
12530
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
12531
        i_length = max_tmp - (4 + 16);
12532
      else if ((i_length + 4) >= (max_tmp - 16))
12533
        i_length = i_length + 1;
12534
      else
12535
      begin
12536
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
12537
        #10 $stop;
12538
      end
12539
    end
12540
    // disable RX
12541 274 tadejm
    wait (wbm_working == 0);
12542 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
12543
              `ETH_MODER_PRO | `ETH_MODER_BRO,
12544
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12545
    if(fail == 0)
12546
      test_ok;
12547
    else
12548
      fail = 0;
12549
  end
12550
 
12551
 
12552
  ////////////////////////////////////////////////////////////////////
12553
  ////                                                            ////
12554
  ////  Test receive packets form MINFL to MAXFL sizes at         ////
12555
  ////  maximum RX buffer decriptors ( 10Mbps ).                  ////
12556
  ////                                                            ////
12557
  ////////////////////////////////////////////////////////////////////
12558 243 tadejm
  if (test_num == 6) // 
12559 209 tadejm
  begin
12560 243 tadejm
    // TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )
12561
    test_name = "TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )";
12562
    `TIME; $display("  TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )");
12563 209 tadejm
 
12564
    // reset MAC registers
12565
    hard_reset;
12566
    // reset MAC and MII LOGIC with soft reset
12567 274 tadejm
//    reset_mac;
12568
//    reset_mii;
12569 209 tadejm
    // set wb slave response
12570
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
12571
 
12572
    max_tmp = 0;
12573
    min_tmp = 0;
12574
    num_of_frames = 0;
12575
    num_of_bd = 0;
12576
    // set maximum RX buffer descriptors (128) - must be set before RX enable
12577 274 tadejm
    wait (wbm_working == 0);
12578 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12579
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
12580 274 tadejm
    wait (wbm_working == 0);
12581 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
12582
              `ETH_MODER_PRO | `ETH_MODER_BRO,
12583
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12584
    // prepare two packets of MAXFL length
12585 274 tadejm
    wait (wbm_working == 0);
12586 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12587
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
12588
    min_tmp = tmp[31:16];
12589
    st_data = 8'hAC;
12590
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
12591
    st_data = 8'h35;
12592
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
12593
    // check WB INT signal
12594
    if (wb_int !== 1'b0)
12595
    begin
12596
      test_fail("WB INT signal should not be set");
12597
      fail = fail + 1;
12598
    end
12599
 
12600
    // write to phy's control register for 10Mbps
12601
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
12602
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
12603
    speed = 10;
12604
 
12605
    i_length = (min_tmp - 4);
12606
    while (i_length <= (max_tmp - 4))
12607
    begin
12608
      // append CRC to packet
12609
      if (i_length[0] == 1'b0)
12610
        append_rx_crc (0, i_length, 1'b0, 1'b0);
12611
      else
12612
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
12613
      // choose generating carrier sense and collision
12614
      case (i_length[1:0])
12615
      2'h0: // Interrupt is generated
12616
      begin
12617
        // Reset_tx_bd nable interrupt generation
12618
        // unmask interrupts
12619 274 tadejm
        wait (wbm_working == 0);
12620 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
12621
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12622
        // not detect carrier sense in FD and no collision
12623
        eth_phy.no_carrier_sense_rx_fd_detect(0);
12624
        eth_phy.collision(0);
12625
      end
12626
      2'h1: // Interrupt is not generated
12627
      begin
12628
        // set_tx_bd enable interrupt generation
12629
        // mask interrupts
12630 274 tadejm
        wait (wbm_working == 0);
12631 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12632
        // detect carrier sense in FD and no collision
12633
        eth_phy.no_carrier_sense_rx_fd_detect(1);
12634
        eth_phy.collision(0);
12635
      end
12636
      2'h2: // Interrupt is not generated
12637
      begin
12638
        // set_tx_bd disable the interrupt generation
12639
        // unmask interrupts
12640 274 tadejm
        wait (wbm_working == 0);
12641 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
12642
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12643
        // not detect carrier sense in FD and set collision
12644
        eth_phy.no_carrier_sense_rx_fd_detect(0);
12645
        eth_phy.collision(1);
12646
      end
12647
      default: // 2'h3: // Interrupt is not generated
12648
      begin
12649
        // set_tx_bd disable the interrupt generation
12650
        // mask interrupts
12651 274 tadejm
        wait (wbm_working == 0);
12652 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12653
        // detect carrier sense in FD and set collision
12654
        eth_phy.no_carrier_sense_rx_fd_detect(1);
12655
        eth_phy.collision(1);
12656
      end
12657
      endcase
12658
      // first 8 frames are received with RX BD 0 (wrap bit on RX BD 0)
12659
      // number of all frames is 154 (146 without first 8)
12660
      if (num_of_frames < 8)
12661
      begin
12662
        case (i_length[1:0])
12663
        2'h0: // Interrupt is generated
12664
        begin
12665
          // enable interrupt generation
12666
          set_rx_bd(0, 0, 1'b1, (`MEMORY_BASE + i_length[1:0]));
12667
          // interrupts are unmasked
12668
        end
12669
        2'h1: // Interrupt is not generated
12670
        begin
12671
          // enable interrupt generation
12672
          set_rx_bd(0, 0, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
12673
          // interrupts are masked
12674
        end
12675
        2'h2: // Interrupt is not generated
12676
        begin
12677
          // disable interrupt generation
12678
          set_rx_bd(0, 0, 1'b0, (`MEMORY_BASE + i_length[1:0]));
12679
          // interrupts are unmasked
12680
        end
12681
        default: // 2'h3: // Interrupt is not generated
12682
        begin
12683
          // disable interrupt generation
12684
          set_rx_bd(0, 0, 1'b0, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
12685
          // interrupts are masked
12686
        end
12687
        endcase
12688
        // set wrap bit
12689
        set_rx_bd_wrap(0);
12690
      end
12691
      // after first 8 number of frames, 128 frames form RX BD 0 to 127 will be received
12692
      else if ((num_of_frames - 8) == 0)
12693
      begin
12694
        tmp_len = i_length; // length of frame
12695
        tmp_bd_num = 0; // RX BD number
12696
        while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
12697
        begin
12698
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
12699
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
12700
          if (tmp_len[0] == 0)
12701
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], (`MEMORY_BASE + tmp_len[1:0]));
12702
          else
12703
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
12704
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
12705
          if ((tmp_len + 4) < (min_tmp + 128))
12706
            tmp_len = tmp_len + 1;
12707
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
12708
            tmp_len = 256;
12709
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
12710
            tmp_len = tmp_len + 128;
12711
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
12712
            tmp_len = max_tmp - (4 + 16);
12713
          else if ((tmp_len + 4) >= (max_tmp - 16))
12714
            tmp_len = tmp_len + 1;
12715
          // set RX BD number
12716
          tmp_bd_num = tmp_bd_num + 1;
12717
        end
12718
        // set wrap bit
12719
        set_rx_bd_wrap(127);
12720
      end
12721
      // after 128 + first 8 number of frames, 19 frames form RX BD 0 to 18 will be received
12722
      else if ((num_of_frames - 8) == 20) // 128
12723
      begin
12724
        tmp_len = tmp_len; // length of frame remaines from previous settings
12725
        tmp_bd_num = 0; // TX BD number
12726
        while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
12727
        begin
12728
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
12729
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
12730
          if (tmp_len[0] == 0)
12731
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], (`MEMORY_BASE + tmp_len[1:0]));
12732
          else
12733
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
12734
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
12735
          if ((tmp_len + 4) < (min_tmp + 128))
12736
            tmp_len = tmp_len + 1;
12737
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
12738
            tmp_len = 256;
12739
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
12740
            tmp_len = tmp_len + 128;
12741
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
12742
            tmp_len = max_tmp - (4 + 16);
12743
          else if ((tmp_len + 4) >= (max_tmp - 16))
12744
            tmp_len = tmp_len + 1;
12745
          // set TX BD number
12746
          tmp_bd_num = tmp_bd_num + 1;
12747
        end
12748
      end
12749
      // set empty bit
12750
      if (num_of_frames < 8)
12751
        set_rx_bd_empty(0, 0);
12752
      else if ((num_of_frames - 8) < 128)
12753
        set_rx_bd_empty((num_of_frames - 8), (num_of_frames - 8));
12754
      else if ((num_of_frames - 136) < 19)
12755
        set_rx_bd_empty((num_of_frames - 136), (num_of_frames - 136));
12756
      // CHECK END OF RECEIVE
12757
      fork
12758
        begin
12759
          if (i_length[0] == 1'b0)
12760
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
12761
          else
12762
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
12763
          repeat(10) @(posedge mrx_clk);
12764
        end
12765
        begin
12766
          #1 check_rx_bd(num_of_bd, data);
12767
          if (i_length < min_tmp) // just first four
12768
          begin
12769
            while (data[15] === 1)
12770
            begin
12771
              #1 check_rx_bd(num_of_bd, data);
12772
              @(posedge wb_clk);
12773
            end
12774
            repeat (1) @(posedge wb_clk);
12775
          end
12776
          else
12777
          begin
12778
            wait (MRxDV === 1'b1); // start transmit
12779
            #1 check_rx_bd(num_of_bd, data);
12780
            if (data[15] !== 1)
12781
            begin
12782
              test_fail("Wrong buffer descriptor's ready bit read out from MAC");
12783
              fail = fail + 1;
12784
            end
12785
            wait (MRxDV === 1'b0); // end transmit
12786
            while (data[15] === 1)
12787
            begin
12788
              #1 check_rx_bd(num_of_bd, data);
12789
              @(posedge wb_clk);
12790
            end
12791
            repeat (1) @(posedge wb_clk);
12792
          end
12793
        end
12794
      join
12795
      // check length of a PACKET
12796
      if (data[31:16] != (i_length + 4))
12797
      begin
12798
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
12799
                        data[31:16], (i_length + 4));
12800
        test_fail("Wrong length of the packet out from PHY");
12801
        fail = fail + 1;
12802
      end
12803
      // checking in the following if statement is performed only for first and last 64 lengths
12804
      // check received RX packet data and CRC
12805
      if (i_length[0] == 1'b0)
12806
      begin
12807
        check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
12808
      end
12809
      else
12810
      begin
12811
        check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
12812
      end
12813
      if (tmp > 0)
12814
      begin
12815
        `TIME; $display("*E Wrong data of the received packet");
12816
        test_fail("Wrong data of the received packet");
12817
        fail = fail + 1;
12818
      end
12819
      // check WB INT signal
12820
      if (i_length[1:0] == 2'h0)
12821
      begin
12822
        if (wb_int !== 1'b1)
12823
        begin
12824
          `TIME; $display("*E WB INT signal should be set");
12825
          test_fail("WB INT signal should be set");
12826
          fail = fail + 1;
12827
        end
12828
      end
12829
      else
12830
      begin
12831
        if (wb_int !== 1'b0)
12832
        begin
12833
          `TIME; $display("*E WB INT signal should not be set");
12834
          test_fail("WB INT signal should not be set");
12835
          fail = fail + 1;
12836
        end
12837
      end
12838
      // check RX buffer descriptor of a packet
12839
      check_rx_bd(num_of_bd, data);
12840
      if (i_length[1] == 1'b0) // interrupt enabled
12841
      begin
12842 281 mohor
        if ( ((data[15:0] !== 16'h6080) && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
12843
             ((data[15:0] !== 16'h4080) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
12844 209 tadejm
        begin
12845
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
12846
          test_fail("RX buffer descriptor status is not correct");
12847
          fail = fail + 1;
12848
        end
12849
      end
12850
      else // interrupt not enabled
12851
      begin
12852 281 mohor
        if ( ((data[15:0] !== 16'h2080)  && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
12853
             ((data[15:0] !== 16'h0080) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
12854 209 tadejm
        begin
12855
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
12856
          test_fail("RX buffer descriptor status is not correct");
12857
          fail = fail + 1;
12858
        end
12859
      end
12860
      // clear first half of 8 frames from RX buffer descriptor 0
12861
      if (num_of_frames < 4)
12862
        clear_rx_bd(num_of_bd, num_of_bd);
12863
      // clear BD with wrap bit
12864
      if (num_of_frames == 140)
12865
        clear_rx_bd(127, 127);
12866
      // check interrupts
12867 274 tadejm
      wait (wbm_working == 0);
12868 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12869
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
12870
      begin
12871
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
12872
        begin
12873
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
12874
          test_fail("Interrupt Receive Buffer was not set");
12875
          fail = fail + 1;
12876
        end
12877
        if ((data & (~`ETH_INT_RXB)) !== 0)
12878
        begin
12879
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
12880
          test_fail("Other interrupts (except Receive Buffer) were set");
12881
          fail = fail + 1;
12882
        end
12883
      end
12884
      else
12885
      begin
12886
        if (data !== 0)
12887
        begin
12888
          `TIME; $display("*E Any of interrupts (except Receive Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
12889
          test_fail("Any of interrupts (except Receive Buffer) was set");
12890
          fail = fail + 1;
12891
        end
12892
      end
12893
      // clear interrupts
12894 274 tadejm
      wait (wbm_working == 0);
12895 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12896
      // check WB INT signal
12897
      if (wb_int !== 1'b0)
12898
      begin
12899
        test_fail("WB INT signal should not be set");
12900
        fail = fail + 1;
12901
      end
12902
      // INTERMEDIATE DISPLAYS
12903
      if ((i_length + 4) == (min_tmp + 7))
12904
      begin
12905
        // starting length is min_tmp, ending length is (min_tmp + 128)
12906
        $display("    receive small packets is NOT selected");
12907
        $display("    using only RX BD 0 out of 128 BDs assigned to RX (wrap at first BD - RX BD 0)");
12908
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
12909
                 min_tmp, (min_tmp + 7));
12910
        $display("    ->all packets were received on RX BD 0");
12911
        // reset receive small, remain the rest
12912 274 tadejm
        wait (wbm_working == 0);
12913 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
12914
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12915
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12916
      end
12917
      else if ((i_length + 4) == (min_tmp + 128))
12918
      begin
12919
        // starting length is min_tmp, ending length is (min_tmp + 128)
12920
        $display("    receive small packets is NOT selected");
12921
        $display("    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
12922
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
12923
                 (min_tmp + 8), (min_tmp + 128));
12924
        $display("    ->packets were received on RX BD %0d to RX BD %0d respectively",
12925
                 1'b0, num_of_bd);
12926
        tmp_bd = num_of_bd + 1;
12927
        // set receive small, remain the rest
12928 274 tadejm
        wait (wbm_working == 0);
12929 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
12930
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12931
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12932
      end
12933
      else if ((i_length + 4) == (max_tmp - 16))
12934
      begin
12935
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
12936
        $display("    receive small packets is selected");
12937
        $display("    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
12938
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
12939
                 (min_tmp + 64 + 128), tmp_data);
12940
        if (tmp_bd > num_of_bd)
12941
          $display("    ->packets were received from RX BD %0d to RX BD 127 and from RX BD 0 to RX BD %0d respectively",
12942
                   tmp_bd, num_of_bd);
12943
        else
12944
          $display("    ->packets were received from RX BD %0d to RX BD %0d respectively",
12945
                   tmp_bd, num_of_bd);
12946
        tmp_bd = num_of_bd + 1;
12947
        // reset receive small, remain the rest
12948 274 tadejm
        wait (wbm_working == 0);
12949 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
12950
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12951
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12952
      end
12953
      else if ((i_length + 4) == max_tmp)
12954
      begin
12955
        $display("    receive small packets is NOT selected");
12956
        $display("    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
12957
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
12958
                 (max_tmp - (4 + 16)), max_tmp);
12959
        if (tmp_bd > num_of_bd)
12960
          $display("    ->packets were received from RX BD %0d to RX BD 127 and from RX BD 0 to RX BD %0d respectively",
12961
                   tmp_bd, num_of_bd);
12962
        else
12963
          $display("    ->packets were received from RX BD %0d to RX BD %0d respectively",
12964
                   tmp_bd, num_of_bd);
12965
      end
12966
      // set length (loop variable)
12967
      if ((i_length + 4) < (min_tmp + 128))
12968
        i_length = i_length + 1;
12969
      else if ( ((i_length + 4) == (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
12970
        i_length = 256;
12971
      else if ( ((i_length + 4) > (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
12972
      begin
12973
        i_length = i_length + 128;
12974
        tmp_data = i_length + 4; // last tmp_data is ending length
12975
      end
12976
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
12977
        i_length = max_tmp - (4 + 16);
12978
      else if ((i_length + 4) >= (max_tmp - 16))
12979
        i_length = i_length + 1;
12980
      else
12981
      begin
12982
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
12983
        #10 $stop;
12984
      end
12985
      // the number of frame transmitted
12986
      num_of_frames = num_of_frames + 1;
12987
      if ((num_of_frames <= 8) || ((num_of_frames - 8) == 128))
12988
        num_of_bd = 0;
12989
      else
12990
        num_of_bd = num_of_bd + 1;
12991
    end
12992
    // disable RX
12993 274 tadejm
    wait (wbm_working == 0);
12994 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
12995
              `ETH_MODER_PRO | `ETH_MODER_BRO,
12996
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12997
    @(posedge wb_clk);
12998
    if(fail == 0)
12999
      test_ok;
13000
    else
13001
      fail = 0;
13002
  end
13003
 
13004
 
13005
  ////////////////////////////////////////////////////////////////////
13006
  ////                                                            ////
13007
  ////  Test receive packets form MINFL to MAXFL sizes at         ////
13008
  ////  maximum RX buffer decriptors ( 100Mbps ).                 ////
13009
  ////                                                            ////
13010
  ////////////////////////////////////////////////////////////////////
13011 243 tadejm
  if (test_num == 7) // 
13012 209 tadejm
  begin
13013 243 tadejm
    // TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )
13014
    test_name = "TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )";
13015
    `TIME; $display("  TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )");
13016 209 tadejm
 
13017
    // reset MAC registers
13018
    hard_reset;
13019
    // reset MAC and MII LOGIC with soft reset
13020 274 tadejm
//    reset_mac;
13021
//    reset_mii;
13022 209 tadejm
    // set wb slave response
13023
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
13024
 
13025
    max_tmp = 0;
13026
    min_tmp = 0;
13027
    num_of_frames = 0;
13028
    num_of_bd = 0;
13029
    // set maximum RX buffer descriptors (128) - must be set before RX enable
13030 274 tadejm
    wait (wbm_working == 0);
13031 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13032
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
13033 274 tadejm
    wait (wbm_working == 0);
13034 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
13035
              `ETH_MODER_PRO | `ETH_MODER_BRO,
13036
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13037
    // prepare two packets of MAXFL length
13038 274 tadejm
    wait (wbm_working == 0);
13039 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13040
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
13041
    min_tmp = tmp[31:16];
13042
    st_data = 8'hAC;
13043
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
13044
    st_data = 8'h35;
13045
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
13046
    // check WB INT signal
13047
    if (wb_int !== 1'b0)
13048
    begin
13049
      test_fail("WB INT signal should not be set");
13050
      fail = fail + 1;
13051
    end
13052
 
13053
    // write to phy's control register for 100Mbps
13054
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
13055
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
13056
    speed = 100;
13057
 
13058
    i_length = (min_tmp - 4);
13059
    while (i_length <= (max_tmp - 4))
13060
    begin
13061
      // append CRC to packet
13062
      if (i_length[0] == 1'b0)
13063
        append_rx_crc (0, i_length, 1'b0, 1'b0);
13064
      else
13065
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
13066
      // choose generating carrier sense and collision
13067
      case (i_length[1:0])
13068
      2'h0: // Interrupt is generated
13069
      begin
13070
        // Reset_tx_bd nable interrupt generation
13071
        // unmask interrupts
13072 274 tadejm
        wait (wbm_working == 0);
13073 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
13074
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13075
        // not detect carrier sense in FD and no collision
13076
        eth_phy.no_carrier_sense_rx_fd_detect(0);
13077
        eth_phy.collision(0);
13078
      end
13079
      2'h1: // Interrupt is not generated
13080
      begin
13081
        // set_tx_bd enable interrupt generation
13082
        // mask interrupts
13083 274 tadejm
        wait (wbm_working == 0);
13084 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13085
        // detect carrier sense in FD and no collision
13086
        eth_phy.no_carrier_sense_rx_fd_detect(1);
13087
        eth_phy.collision(0);
13088
      end
13089
      2'h2: // Interrupt is not generated
13090
      begin
13091
        // set_tx_bd disable the interrupt generation
13092
        // unmask interrupts
13093 274 tadejm
        wait (wbm_working == 0);
13094 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
13095
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13096
        // not detect carrier sense in FD and set collision
13097
        eth_phy.no_carrier_sense_rx_fd_detect(0);
13098
        eth_phy.collision(1);
13099
      end
13100
      default: // 2'h3: // Interrupt is not generated
13101
      begin
13102
        // set_tx_bd disable the interrupt generation
13103
        // mask interrupts
13104 274 tadejm
        wait (wbm_working == 0);
13105 209 tadejm
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13106
        // detect carrier sense in FD and set collision
13107
        eth_phy.no_carrier_sense_rx_fd_detect(1);
13108
        eth_phy.collision(1);
13109
      end
13110
      endcase
13111
      // first 8 frames are received with RX BD 0 (wrap bit on RX BD 0)
13112
      // number of all frames is 154 (146 without first 8)
13113
      if (num_of_frames < 8)
13114
      begin
13115
        case (i_length[1:0])
13116
        2'h0: // Interrupt is generated
13117
        begin
13118
          // enable interrupt generation
13119
          set_rx_bd(0, 0, 1'b1, (`MEMORY_BASE + i_length[1:0]));
13120
          // interrupts are unmasked
13121
        end
13122
        2'h1: // Interrupt is not generated
13123
        begin
13124
          // enable interrupt generation
13125
          set_rx_bd(0, 0, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
13126
          // interrupts are masked
13127
        end
13128
        2'h2: // Interrupt is not generated
13129
        begin
13130
          // disable interrupt generation
13131
          set_rx_bd(0, 0, 1'b0, (`MEMORY_BASE + i_length[1:0]));
13132
          // interrupts are unmasked
13133
        end
13134
        default: // 2'h3: // Interrupt is not generated
13135
        begin
13136
          // disable interrupt generation
13137
          set_rx_bd(0, 0, 1'b0, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
13138
          // interrupts are masked
13139
        end
13140
        endcase
13141
        // set wrap bit
13142
        set_rx_bd_wrap(0);
13143
      end
13144
      // after first 8 number of frames, 128 frames form RX BD 0 to 127 will be received
13145
      else if ((num_of_frames - 8) == 0)
13146
      begin
13147
        tmp_len = i_length; // length of frame
13148
        tmp_bd_num = 0; // RX BD number
13149
        while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
13150
        begin
13151
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
13152
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13153
          if (tmp_len[0] == 0)
13154
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], (`MEMORY_BASE + tmp_len[1:0]));
13155
          else
13156
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13157
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13158
          if ((tmp_len + 4) < (min_tmp + 128))
13159
            tmp_len = tmp_len + 1;
13160
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
13161
            tmp_len = 256;
13162
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
13163
            tmp_len = tmp_len + 128;
13164
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
13165
            tmp_len = max_tmp - (4 + 16);
13166
          else if ((tmp_len + 4) >= (max_tmp - 16))
13167
            tmp_len = tmp_len + 1;
13168
          // set RX BD number
13169
          tmp_bd_num = tmp_bd_num + 1;
13170
        end
13171
        // set wrap bit
13172
        set_rx_bd_wrap(127);
13173
      end
13174
      // after 128 + first 8 number of frames, 19 frames form RX BD 0 to 18 will be received
13175
      else if ((num_of_frames - 8) == 20) // 128
13176
      begin
13177
        tmp_len = tmp_len; // length of frame remaines from previous settings
13178
        tmp_bd_num = 0; // TX BD number
13179
        while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
13180
        begin
13181
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
13182
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13183
          if (tmp_len[0] == 0)
13184
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], (`MEMORY_BASE + tmp_len[1:0]));
13185
          else
13186
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13187
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13188
          if ((tmp_len + 4) < (min_tmp + 128))
13189
            tmp_len = tmp_len + 1;
13190
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
13191
            tmp_len = 256;
13192
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
13193
            tmp_len = tmp_len + 128;
13194
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
13195
            tmp_len = max_tmp - (4 + 16);
13196
          else if ((tmp_len + 4) >= (max_tmp - 16))
13197
            tmp_len = tmp_len + 1;
13198
          // set TX BD number
13199
          tmp_bd_num = tmp_bd_num + 1;
13200
        end
13201
      end
13202
      // set empty bit
13203
      if (num_of_frames < 8)
13204
        set_rx_bd_empty(0, 0);
13205
      else if ((num_of_frames - 8) < 128)
13206
        set_rx_bd_empty((num_of_frames - 8), (num_of_frames - 8));
13207
      else if ((num_of_frames - 136) < 19)
13208
        set_rx_bd_empty((num_of_frames - 136), (num_of_frames - 136));
13209
      // CHECK END OF RECEIVE
13210
      fork
13211
        begin
13212
          if (i_length[0] == 1'b0)
13213
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
13214
          else
13215
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
13216
          repeat(10) @(posedge mrx_clk);
13217
        end
13218
        begin
13219
          #1 check_rx_bd(num_of_bd, data);
13220
          if (i_length < min_tmp) // just first four
13221
          begin
13222
            while (data[15] === 1)
13223
            begin
13224
              #1 check_rx_bd(num_of_bd, data);
13225
              @(posedge wb_clk);
13226
            end
13227
            repeat (1) @(posedge wb_clk);
13228
          end
13229
          else
13230
          begin
13231
            wait (MRxDV === 1'b1); // start transmit
13232
            #1 check_rx_bd(num_of_bd, data);
13233
            if (data[15] !== 1)
13234
            begin
13235
              test_fail("Wrong buffer descriptor's ready bit read out from MAC");
13236
              fail = fail + 1;
13237
            end
13238
            wait (MRxDV === 1'b0); // end transmit
13239
            while (data[15] === 1)
13240
            begin
13241
              #1 check_rx_bd(num_of_bd, data);
13242
              @(posedge wb_clk);
13243
            end
13244
            repeat (1) @(posedge wb_clk);
13245
          end
13246
        end
13247
      join
13248
      // check length of a PACKET
13249
      if (data[31:16] != (i_length + 4))
13250
      begin
13251
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
13252
                        data[31:16], (i_length + 4));
13253
        test_fail("Wrong length of the packet out from PHY");
13254
        fail = fail + 1;
13255
      end
13256
      // check received RX packet data and CRC
13257
      if (i_length[0] == 1'b0)
13258
      begin
13259
        check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
13260
      end
13261
      else
13262
      begin
13263
        check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
13264
      end
13265
      if (tmp > 0)
13266
      begin
13267
        `TIME; $display("*E Wrong data of the received packet");
13268
        test_fail("Wrong data of the received packet");
13269
        fail = fail + 1;
13270
      end
13271
      // check WB INT signal
13272
      if (i_length[1:0] == 2'h0)
13273
      begin
13274
        if (wb_int !== 1'b1)
13275
        begin
13276
          `TIME; $display("*E WB INT signal should be set");
13277
          test_fail("WB INT signal should be set");
13278
          fail = fail + 1;
13279
        end
13280
      end
13281
      else
13282
      begin
13283
        if (wb_int !== 1'b0)
13284
        begin
13285
          `TIME; $display("*E WB INT signal should not be set");
13286
          test_fail("WB INT signal should not be set");
13287
          fail = fail + 1;
13288
        end
13289
      end
13290
      // check RX buffer descriptor of a packet
13291
      check_rx_bd(num_of_bd, data);
13292
      if (i_length[1] == 1'b0) // interrupt enabled
13293
      begin
13294 281 mohor
        if ( ((data[15:0] !== 16'h6080) && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
13295
             ((data[15:0] !== 16'h4080) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
13296 209 tadejm
        begin
13297
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
13298
          test_fail("RX buffer descriptor status is not correct");
13299
          fail = fail + 1;
13300
        end
13301
      end
13302
      else // interrupt not enabled
13303
      begin
13304 281 mohor
        if ( ((data[15:0] !== 16'h2080)  && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
13305
             ((data[15:0] !== 16'h0080) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
13306 209 tadejm
        begin
13307
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
13308
          test_fail("RX buffer descriptor status is not correct");
13309
          fail = fail + 1;
13310
        end
13311
      end
13312
      // clear first half of 8 frames from RX buffer descriptor 0
13313
      if (num_of_frames < 4)
13314
        clear_rx_bd(num_of_bd, num_of_bd);
13315
      // clear BD with wrap bit
13316
      if (num_of_frames == 140)
13317
        clear_rx_bd(127, 127);
13318
      // check interrupts
13319 274 tadejm
      wait (wbm_working == 0);
13320 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13321
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
13322
      begin
13323
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
13324
        begin
13325
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
13326
          test_fail("Interrupt Receive Buffer was not set");
13327
          fail = fail + 1;
13328
        end
13329
        if ((data & (~`ETH_INT_RXB)) !== 0)
13330
        begin
13331
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
13332
          test_fail("Other interrupts (except Receive Buffer) were set");
13333
          fail = fail + 1;
13334
        end
13335
      end
13336
      else
13337
      begin
13338
        if (data !== 0)
13339
        begin
13340
          `TIME; $display("*E Any of interrupts (except Receive Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
13341
          test_fail("Any of interrupts (except Receive Buffer) was set");
13342
          fail = fail + 1;
13343
        end
13344
      end
13345
      // clear interrupts
13346 274 tadejm
      wait (wbm_working == 0);
13347 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13348
      // check WB INT signal
13349
      if (wb_int !== 1'b0)
13350
      begin
13351
        test_fail("WB INT signal should not be set");
13352
        fail = fail + 1;
13353
      end
13354
      // INTERMEDIATE DISPLAYS
13355
      if ((i_length + 4) == (min_tmp + 7))
13356
      begin
13357
        // starting length is min_tmp, ending length is (min_tmp + 128)
13358
        $display("    receive small packets is NOT selected");
13359
        $display("    using only RX BD 0 out of 128 BDs assigned to RX (wrap at first BD - RX BD 0)");
13360
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
13361
                 min_tmp, (min_tmp + 7));
13362
        $display("    ->all packets were received on RX BD 0");
13363
        // reset receive small, remain the rest
13364 274 tadejm
        wait (wbm_working == 0);
13365 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
13366
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
13367
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13368
      end
13369
      else if ((i_length + 4) == (min_tmp + 128))
13370
      begin
13371
        // starting length is min_tmp, ending length is (min_tmp + 128)
13372
        $display("    receive small packets is NOT selected");
13373
        $display("    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
13374
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13375
                 (min_tmp + 8), (min_tmp + 128));
13376
        $display("    ->packets were received on RX BD %0d to RX BD %0d respectively",
13377
                 1'b0, num_of_bd);
13378
        tmp_bd = num_of_bd + 1;
13379
        // set receive small, remain the rest
13380 274 tadejm
        wait (wbm_working == 0);
13381 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
13382
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
13383
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13384
      end
13385
      else if ((i_length + 4) == (max_tmp - 16))
13386
      begin
13387
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
13388
        $display("    receive small packets is selected");
13389
        $display("    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
13390
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
13391
                 (min_tmp + 64 + 128), tmp_data);
13392
        if (tmp_bd > num_of_bd)
13393
          $display("    ->packets were received from RX BD %0d to RX BD 127 and from RX BD 0 to RX BD %0d respectively",
13394
                   tmp_bd, num_of_bd);
13395
        else
13396
          $display("    ->packets were received from RX BD %0d to RX BD %0d respectively",
13397
                   tmp_bd, num_of_bd);
13398
        tmp_bd = num_of_bd + 1;
13399
        // reset receive small, remain the rest
13400 274 tadejm
        wait (wbm_working == 0);
13401 209 tadejm
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
13402
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
13403
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13404
      end
13405
      else if ((i_length + 4) == max_tmp)
13406
      begin
13407
        $display("    receive small packets is NOT selected");
13408
        $display("    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
13409
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
13410
                 (max_tmp - (4 + 16)), max_tmp);
13411
        if (tmp_bd > num_of_bd)
13412
          $display("    ->packets were received from RX BD %0d to RX BD 127 and from RX BD 0 to RX BD %0d respectively",
13413
                   tmp_bd, num_of_bd);
13414
        else
13415
          $display("    ->packets were received from RX BD %0d to RX BD %0d respectively",
13416
                   tmp_bd, num_of_bd);
13417
      end
13418
      // set length (loop variable)
13419
      if ((i_length + 4) < (min_tmp + 128))
13420
        i_length = i_length + 1;
13421
      else if ( ((i_length + 4) == (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
13422
        i_length = 256;
13423
      else if ( ((i_length + 4) > (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
13424
      begin
13425
        i_length = i_length + 128;
13426
        tmp_data = i_length + 4; // last tmp_data is ending length
13427
      end
13428
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
13429
        i_length = max_tmp - (4 + 16);
13430
      else if ((i_length + 4) >= (max_tmp - 16))
13431
        i_length = i_length + 1;
13432
      else
13433
      begin
13434
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
13435
        #10 $stop;
13436
      end
13437
      // the number of frame transmitted
13438
      num_of_frames = num_of_frames + 1;
13439
      if ((num_of_frames <= 8) || ((num_of_frames - 8) == 128))
13440
        num_of_bd = 0;
13441
      else
13442
        num_of_bd = num_of_bd + 1;
13443
    end
13444
    // disable RX
13445 274 tadejm
    wait (wbm_working == 0);
13446 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
13447
              `ETH_MODER_PRO | `ETH_MODER_BRO,
13448
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13449
    @(posedge wb_clk);
13450
    if(fail == 0)
13451
      test_ok;
13452
    else
13453
      fail = 0;
13454
  end
13455
 
13456
 
13457
  ////////////////////////////////////////////////////////////////////
13458
  ////                                                            ////
13459 243 tadejm
  ////  Test receive packets form 0 to (MINFL + 12) sizes at       ////
13460 209 tadejm
  ////  8 RX buffer decriptors ( 10Mbps ).                        ////
13461
  ////                                                            ////
13462
  ////////////////////////////////////////////////////////////////////
13463 243 tadejm
  if (test_num == 8) // 
13464 209 tadejm
  begin
13465 243 tadejm
    // TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 10Mbps )
13466
    test_name = "TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 10Mbps )";
13467
    `TIME; $display("  TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 10Mbps )");
13468 209 tadejm
 
13469
    // reset MAC registers
13470
    hard_reset;
13471
    // reset MAC and MII LOGIC with soft reset
13472 274 tadejm
//    reset_mac;
13473
//    reset_mii;
13474 209 tadejm
    // set wb slave response
13475
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
13476
 
13477
    max_tmp = 0;
13478
    min_tmp = 0;
13479
    // set 8 RX buffer descriptors (120 - 127) - must be set before RX enable
13480 274 tadejm
    wait (wbm_working == 0);
13481 209 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h78, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13482
    // enable RX, set full-duplex mode, receive small, NO correct IFG
13483 274 tadejm
    wait (wbm_working == 0);
13484 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
13485
              `ETH_MODER_PRO | `ETH_MODER_BRO,
13486
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13487
    // prepare two packets of MAXFL length
13488 274 tadejm
    wait (wbm_working == 0);
13489 209 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13490
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
13491
    min_tmp = tmp[31:16];
13492
    st_data = 8'hAC;
13493
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
13494
    st_data = 8'h35;
13495
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
13496
    // check WB INT signal
13497
    if (wb_int !== 1'b0)
13498
    begin
13499
      test_fail("WB INT signal should not be set");
13500
      fail = fail + 1;
13501
    end
13502 243 tadejm
    // unmask interrupts
13503 274 tadejm
    wait (wbm_working == 0);
13504 243 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
13505
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13506 209 tadejm
 
13507
    // write to phy's control register for 10Mbps
13508
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
13509
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
13510
    speed = 10;
13511
 
13512 243 tadejm
    frame_ended = 0;
13513
    num_of_frames = 0;// 0; // 10;
13514
    num_of_bd = 120;
13515
    i_length = 0 - 4;// (0 - 4); // 6; // 4 less due to CRC
13516
    while ((i_length + 4) < 78) // (min_tmp - 4))
13517 209 tadejm
    begin
13518 243 tadejm
      // append CRC to packet
13519
      if ((i_length[0] == 1'b0) && (num_of_frames > 4))
13520
        append_rx_crc (0, i_length, 1'b0, 1'b0);
13521
      else if (num_of_frames > 4)
13522
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
13523 209 tadejm
      // choose generating carrier sense and collision
13524
      case (i_length[1:0])
13525 243 tadejm
      2'h0:
13526 209 tadejm
      begin
13527
        // not detect carrier sense in FD and no collision
13528 243 tadejm
        eth_phy.no_carrier_sense_rx_fd_detect(0);
13529 209 tadejm
        eth_phy.collision(0);
13530
      end
13531 243 tadejm
      2'h1:
13532 209 tadejm
      begin
13533
        // detect carrier sense in FD and no collision
13534 243 tadejm
        eth_phy.no_carrier_sense_rx_fd_detect(1);
13535 209 tadejm
        eth_phy.collision(0);
13536
      end
13537 243 tadejm
      2'h2:
13538 209 tadejm
      begin
13539
        // not detect carrier sense in FD and set collision
13540 243 tadejm
        eth_phy.no_carrier_sense_rx_fd_detect(0);
13541 209 tadejm
        eth_phy.collision(1);
13542
      end
13543 243 tadejm
      default: // 2'h3:
13544 209 tadejm
      begin
13545
        // detect carrier sense in FD and set collision
13546 243 tadejm
        eth_phy.no_carrier_sense_rx_fd_detect(1);
13547 209 tadejm
        eth_phy.collision(1);
13548
      end
13549
      endcase
13550
      #1;
13551 243 tadejm
      // first 10 frames are received with RX BD 120 (wrap bit on RX BD 120)
13552 209 tadejm
      if (num_of_frames <= 9)
13553
      begin
13554 243 tadejm
        case (i_length[1:0])
13555
        2'h0: // Interrupt is generated
13556
        begin
13557
          // enable interrupt generation
13558
          set_rx_bd(120, 120, 1'b1, (`MEMORY_BASE + i_length[1:0]));
13559
        end
13560
        2'h1: // Interrupt is generated
13561
        begin
13562
          // enable interrupt generation
13563
          set_rx_bd(120, 120, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
13564
        end
13565
        2'h2: // Interrupt is generated
13566
        begin
13567
          // enable interrupt generation
13568
          set_rx_bd(120, 120, 1'b1, (`MEMORY_BASE + i_length[1:0]));
13569
        end
13570
        default: // 2'h3: // Interrupt is generated
13571
        begin
13572
          // enable interrupt generation
13573
          set_rx_bd(120, 120, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
13574
        end
13575
        endcase
13576 209 tadejm
        // set wrap bit
13577 243 tadejm
        set_rx_bd_wrap(120);
13578 209 tadejm
      end
13579 243 tadejm
      // 10 <= num_of_frames < 18 => wrap set to TX BD 123
13580 209 tadejm
      else if ((num_of_frames == 10) || (num_of_frames == 14))
13581
      begin
13582
        tmp_len = i_length; // length of frame
13583 243 tadejm
        tmp_bd_num = 120; // RX BD number
13584
        while (tmp_bd_num < 124) // 
13585 209 tadejm
        begin
13586
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13587
          if (tmp_len[0] == 0)
13588 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13589 209 tadejm
          else
13590 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13591
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13592 209 tadejm
          tmp_len = tmp_len + 1;
13593 243 tadejm
          // set RX BD number
13594 209 tadejm
          tmp_bd_num = tmp_bd_num + 1;
13595
        end
13596
        // set wrap bit
13597 243 tadejm
        set_rx_bd_wrap(123);
13598 209 tadejm
      end
13599 243 tadejm
      // 18 <= num_of_frames < 28 => wrap set to RX BD 124
13600 209 tadejm
      else if ((num_of_frames == 18) || (num_of_frames == 23))
13601
      begin
13602
        tmp_len = i_length; // length of frame
13603 243 tadejm
        tmp_bd_num = 120; // RX BD number
13604
        while (tmp_bd_num < 125) // 
13605 209 tadejm
        begin
13606
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13607
          if (tmp_len[0] == 0)
13608 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13609 209 tadejm
          else
13610 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13611
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13612 209 tadejm
          tmp_len = tmp_len + 1;
13613 243 tadejm
          // set RX BD number
13614 209 tadejm
          tmp_bd_num = tmp_bd_num + 1;
13615
        end
13616
        // set wrap bit
13617 243 tadejm
        set_rx_bd_wrap(124);
13618 209 tadejm
      end
13619 243 tadejm
      // 28 <= num_of_frames < 40 => wrap set to RX BD 125
13620 209 tadejm
      else if ((num_of_frames == 28) || (num_of_frames == 34))
13621
      begin
13622
        tmp_len = i_length; // length of frame
13623 243 tadejm
        tmp_bd_num = 120; // RX BD number
13624
        while (tmp_bd_num < 126) // 
13625 209 tadejm
        begin
13626
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13627
          if (tmp_len[0] == 0)
13628 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13629 209 tadejm
          else
13630 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13631
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13632 209 tadejm
          tmp_len = tmp_len + 1;
13633 243 tadejm
          // set RX BD number
13634 209 tadejm
          tmp_bd_num = tmp_bd_num + 1;
13635
        end
13636
        // set wrap bit
13637 243 tadejm
        set_rx_bd_wrap(125);
13638 209 tadejm
      end
13639 243 tadejm
      // 40 <= num_of_frames < 54 => wrap set to RX BD 126
13640 209 tadejm
      else if ((num_of_frames == 40) || (num_of_frames == 47))
13641
      begin
13642
        tmp_len = i_length; // length of frame
13643 243 tadejm
        tmp_bd_num = 120; // RX BD number
13644
        while (tmp_bd_num < 127) // 
13645 209 tadejm
        begin
13646
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13647
          if (tmp_len[0] == 0)
13648 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13649 209 tadejm
          else
13650 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13651
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13652 209 tadejm
          tmp_len = tmp_len + 1;
13653 243 tadejm
          // set RX BD number
13654 209 tadejm
          tmp_bd_num = tmp_bd_num + 1;
13655
        end
13656
        // set wrap bit
13657 243 tadejm
        set_rx_bd_wrap(126);
13658 209 tadejm
      end
13659 243 tadejm
      // 54 <= num_of_frames < 70 => wrap set to RX BD 127
13660 209 tadejm
      else if ((num_of_frames == 54) || (num_of_frames == 62))
13661
      begin
13662
        tmp_len = i_length; // length of frame
13663 243 tadejm
        tmp_bd_num = 120; // RX BD number
13664
        while (tmp_bd_num < 128) // 
13665 209 tadejm
        begin
13666
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13667
          if (tmp_len[0] == 0)
13668 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13669 209 tadejm
          else
13670 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13671
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13672 209 tadejm
          tmp_len = tmp_len + 1;
13673 243 tadejm
          // set RX BD number
13674 209 tadejm
          tmp_bd_num = tmp_bd_num + 1;
13675
        end
13676
        // set wrap bit
13677 243 tadejm
        set_rx_bd_wrap(127);
13678 209 tadejm
      end
13679 243 tadejm
      // 70 <= num_of_frames < 78 => wrap set to RX BD 127
13680
      else if (num_of_frames == 70)
13681
      begin
13682
        tmp_len = i_length; // length of frame
13683
        tmp_bd_num = 120; // RX BD number
13684
        while (tmp_bd_num < 128) // 
13685
        begin
13686
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13687
          if (tmp_len[0] == 0)
13688
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13689
          else
13690
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13691
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13692
          tmp_len = tmp_len + 1;
13693
          // set RX BD number
13694
          tmp_bd_num = tmp_bd_num + 1;
13695
        end
13696
        // set wrap bit
13697
        set_rx_bd_wrap(127);
13698
      end
13699 209 tadejm
      #1;
13700 243 tadejm
      // SET empty bit
13701 209 tadejm
      if (num_of_frames < 10)
13702 243 tadejm
        set_rx_bd_empty(120, 120);
13703 209 tadejm
      else if (num_of_frames < 14)
13704 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 10), (120 + num_of_frames - 10));
13705 209 tadejm
      else if (num_of_frames < 18)
13706 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 14), (120 + num_of_frames - 14));
13707 209 tadejm
      else if (num_of_frames < 23)
13708 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 18), (120 + num_of_frames - 18));
13709 209 tadejm
      else if (num_of_frames < 28)
13710 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 23), (120 + num_of_frames - 23));
13711 209 tadejm
      else if (num_of_frames < 34)
13712 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 28), (120 + num_of_frames - 28));
13713 209 tadejm
      else if (num_of_frames < 40)
13714 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 34), (120 + num_of_frames - 34));
13715 209 tadejm
      else if (num_of_frames < 47)
13716 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 40), (120 + num_of_frames - 40));
13717 209 tadejm
      else if (num_of_frames < 54)
13718 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 47), (120 + num_of_frames - 47));
13719 209 tadejm
      else if (num_of_frames < 62)
13720 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 54), (120 + num_of_frames - 54));
13721 209 tadejm
      else if (num_of_frames < 70)
13722 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 62), (120 + num_of_frames - 62));
13723
      else if (num_of_frames < 78)
13724
        set_rx_bd_empty((120 + num_of_frames - 70), (120 + num_of_frames - 70));
13725
      // CHECK END OF RECEIVE
13726 252 tadejm
      // receive just preamble between some packets
13727
      if ((num_of_frames == 0) || (num_of_frames == 4) || (num_of_frames == 9))
13728
      begin
13729
        #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h6, 8'h55, 0, 0, 1'b0);
13730
        @(posedge mrx_clk);
13731
        wait (MRxDV === 1'b0); // end receive
13732
        repeat(10) @(posedge mrx_clk);
13733
        repeat(15) @(posedge wb_clk);
13734
      end
13735
      // receiving frames and checking end of them
13736 243 tadejm
      frame_ended = 0;
13737
      check_frame = 0;
13738 209 tadejm
      fork
13739
        begin
13740 243 tadejm
          if (i_length[0] == 1'b0)
13741
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
13742
          else
13743
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
13744
          repeat(10) @(posedge mrx_clk);
13745
        end
13746
        begin: fr_end1
13747
          wait (MRxDV === 1'b1); // start receive
13748
          #1 check_rx_bd(num_of_bd, data);
13749
          if (data[15] !== 1)
13750 209 tadejm
          begin
13751 243 tadejm
            test_fail("Wrong buffer descriptor's empty bit read out from MAC");
13752
            fail = fail + 1;
13753 209 tadejm
          end
13754 243 tadejm
          wait (MRxDV === 1'b0); // end receive
13755
          while ((data[15] === 1) && (check_frame == 0))
13756
          begin
13757
            #1 check_rx_bd(num_of_bd, data);
13758
            @(posedge wb_clk);
13759
          end
13760
          if (data[15] === 0)
13761
            frame_ended = 1;
13762
          repeat (1) @(posedge wb_clk);
13763 209 tadejm
        end
13764 243 tadejm
        begin
13765
          wait (MRxDV === 1'b1); // start receive
13766
          wait (MRxDV === 1'b0); // end receive
13767
          repeat(10) @(posedge mrx_clk);
13768
          repeat(15) @(posedge wb_clk);
13769
          check_frame = 1;
13770
        end
13771
      join
13772
      // check length of a PACKET
13773
      if ( ((data[31:16] != (i_length + 4)) && (num_of_frames >= 3)) ||
13774
           ((data[31:16] != 0) && (num_of_frames < 3)) )
13775
      begin
13776
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
13777
                        data[31:16], (i_length + 4));
13778
        test_fail("Wrong length of the packet out from PHY");
13779
        fail = fail + 1;
13780
      end
13781
      // check received RX packet data and CRC
13782
      if ((frame_ended == 1) && (num_of_frames >= 5)) // 5 bytes is minimum size without CRC error, since
13783
      begin                                           // CRC has 4 bytes for itself
13784
        if (i_length[0] == 1'b0)
13785
        begin
13786
          check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
13787
        end
13788 209 tadejm
        else
13789
        begin
13790 243 tadejm
          check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
13791 209 tadejm
        end
13792 243 tadejm
        if (tmp > 0)
13793
        begin
13794
          `TIME; $display("*E Wrong data of the received packet");
13795
          test_fail("Wrong data of the received packet");
13796
          fail = fail + 1;
13797
        end
13798 209 tadejm
      end
13799 243 tadejm
      // check WB INT signal
13800
      if (num_of_frames >= 3) // Frames smaller than 3 are not received.
13801
      begin                   // Frames greater then 5 always cause an interrupt (Frame received)
13802
        if (wb_int !== 1'b1)  // Frames with length 3 or 4 always cause an interrupt (CRC error)
13803
        begin
13804
          `TIME; $display("*E WB INT signal should be set");
13805
          test_fail("WB INT signal should be set");
13806
          fail = fail + 1;
13807
        end
13808
      end
13809
      else
13810
      begin
13811
        if (wb_int !== 1'b0)
13812
        begin
13813
          `TIME; $display("*E WB INT signal should not be set");
13814
          test_fail("WB INT signal should not be set");
13815
          fail = fail + 1;
13816
        end
13817
      end
13818
      // check RX buffer descriptor of a packet
13819 254 mohor
      // check RX buffer descriptor of a packet
13820 243 tadejm
      if (num_of_frames >= min_tmp)
13821
      begin
13822 254 mohor
        if ( (data[15:0] !== 16'h6080) && // wrap bit
13823
             (data[15:0] !== 16'h4080) ) // without wrap bit
13824 243 tadejm
        begin
13825
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
13826
          test_fail("RX buffer descriptor status is not correct");
13827
          fail = fail + 1;
13828
        end
13829
      end
13830 254 mohor
      else if (num_of_frames > 6)
13831 243 tadejm
      begin
13832 254 mohor
        if ( (data[15:0] !== 16'h6084) && // wrap bit
13833
             (data[15:0] !== 16'h4084) ) // without wrap bit
13834
        begin
13835
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
13836
          test_fail("RX buffer descriptor status is not correct");
13837
          fail = fail + 1;
13838
        end
13839
      end
13840
      else if (num_of_frames > 4) // MAC does not recognize Dest. ADDR. for lengths 5, 6 => no MISS
13841
      begin
13842 243 tadejm
        if ( (data[15:0] !== 16'h6004) && // wrap bit
13843
             (data[15:0] !== 16'h4004) ) // without wrap bit
13844
        begin
13845
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
13846
          test_fail("RX buffer descriptor status is not correct");
13847
          fail = fail + 1;
13848
        end
13849
      end
13850 254 mohor
      else if (num_of_frames > 2) // MAC does not recognize Dest. ADDR. for length 3, 4 => no MISS, CRC ERROR
13851 243 tadejm
      begin
13852
        if ( (data[15:0] !== 16'h6006) && // wrap bit
13853
             (data[15:0] !== 16'h4006) ) // without wrap bit
13854
        begin
13855
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
13856
          test_fail("RX buffer descriptor status is not correct");
13857
          fail = fail + 1;
13858
        end
13859
      end
13860
      else
13861
      begin
13862
        if (data[15] !== 1'b1)
13863
        begin
13864
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
13865
          test_fail("RX buffer descriptor status is not correct");
13866
          fail = fail + 1;
13867
        end
13868
      end
13869
      // check interrupts
13870 274 tadejm
      wait (wbm_working == 0);
13871 243 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13872 209 tadejm
      if (num_of_frames >= 5)
13873
      begin
13874 243 tadejm
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
13875 209 tadejm
        begin
13876 243 tadejm
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
13877
          test_fail("Interrupt Receive Buffer was not set");
13878
          fail = fail + 1;
13879 209 tadejm
        end
13880 243 tadejm
        if ((data & (~`ETH_INT_RXB)) !== 0)
13881 209 tadejm
        begin
13882 243 tadejm
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
13883
          test_fail("Other interrupts (except Receive Buffer) were set");
13884
          fail = fail + 1;
13885 209 tadejm
        end
13886 243 tadejm
      end
13887
      else if ((num_of_frames < 3)) // Frames smaller than 3 are not received.
13888
      begin
13889
        if (data) // Checking if any interrupt is pending)
13890 209 tadejm
        begin
13891 243 tadejm
          `TIME; $display("*E Interrupt(s) is(are) pending although frame was ignored, interrupt reg: %0h", data);
13892
          test_fail("Interrupts were set");
13893
          fail = fail + 1;
13894
        end
13895
      end
13896
      else
13897
      begin
13898
        if ((data & `ETH_INT_RXE) !== `ETH_INT_RXE)
13899
        begin
13900
          `TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
13901
          test_fail("Interrupt Receive Buffer Error was not set");
13902
          fail = fail + 1;
13903
        end
13904
        if ((data & (~`ETH_INT_RXE)) !== 0)
13905
        begin
13906
          `TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
13907
          test_fail("Other interrupts (except Receive Buffer Error) were set");
13908
          fail = fail + 1;
13909
        end
13910
      end
13911
      // clear interrupts
13912 274 tadejm
      wait (wbm_working == 0);
13913 243 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13914
      // check WB INT signal
13915
      if (wb_int !== 1'b0)
13916
      begin
13917
        test_fail("WB INT signal should not be set");
13918
        fail = fail + 1;
13919
      end
13920
      // INTERMEDIATE DISPLAYS
13921
      if (num_of_frames == 3)
13922
      begin
13923
        $display("    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
13924
        $display("    ->packets with lengths from %0d to %0d are not received (length increasing by 1 byte)",
13925
                 0, 3);
13926
      end
13927
      else if (num_of_frames == 9)
13928
      begin
13929
        $display("    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
13930
        $display("    ->packet with length 4 is not received (length increasing by 1 byte)");
13931
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13932
                 5, 9);
13933
      end
13934
      else if (num_of_frames == 17)
13935
      begin
13936
        $display("    using 4 BDs out of 8 BDs (120..127) assigned to RX (wrap at 4th BD - RX BD 123)");
13937
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13938
                 10, 17);
13939
      end
13940
      else if (num_of_frames == 27)
13941
      begin
13942
        $display("    using 5 BDs out of 8 BDs (120..127) assigned to RX (wrap at 5th BD - RX BD 124)");
13943
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13944
                 18, 27);
13945
      end
13946
      else if (num_of_frames == 40)
13947
      begin
13948
        $display("    using 6 BDs out of 8 BDs (120..127) assigned to RX (wrap at 6th BD - RX BD 125)");
13949
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13950
                 28, 40);
13951
      end
13952
      else if (num_of_frames == 54)
13953
      begin
13954
        $display("    using 7 BDs out of 8 BDs (120..127) assigned to RX (wrap at 7th BD - RX BD 126)");
13955
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13956
                 41, 54);
13957
      end
13958
      else if (num_of_frames == 69)
13959
      begin
13960
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
13961
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13962
                 55, 69);
13963
      end
13964
      else if (num_of_frames == 69)
13965
      begin
13966
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
13967
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13968
                 55, 69);
13969
      end
13970
      else if (num_of_frames == 77)
13971
      begin
13972
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
13973
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13974
                 70, 77);
13975
      end
13976
      // set length (loop variable)
13977
      i_length = i_length + 1;
13978
      // the number of frame transmitted
13979
      num_of_frames = num_of_frames + 1;
13980
      if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
13981
          (num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
13982
          (num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
13983
          (num_of_frames == 54) || (num_of_frames == 62) || (num_of_frames == 70))
13984
        num_of_bd = 120;
13985
      else
13986
        num_of_bd = num_of_bd + 1;
13987
    end
13988
    // disable RX
13989 274 tadejm
    wait (wbm_working == 0);
13990 243 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
13991
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13992
    @(posedge wb_clk);
13993
    if(fail == 0)
13994
      test_ok;
13995
    else
13996
      fail = 0;
13997
  end
13998
 
13999
 
14000
  ////////////////////////////////////////////////////////////////////
14001
  ////                                                            ////
14002
  ////  Test receive packets form 0 to (MINFL + 12) sizes at      ////
14003
  ////  8 RX buffer decriptors ( 100Mbps ).                       ////
14004
  ////                                                            ////
14005
  ////////////////////////////////////////////////////////////////////
14006
  if (test_num == 9) // 
14007
  begin
14008
    // TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 100Mbps )
14009
    test_name = "TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 100Mbps )";
14010
    `TIME; $display("  TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 100Mbps )");
14011
 
14012
    // reset MAC registers
14013
    hard_reset;
14014
    // reset MAC and MII LOGIC with soft reset
14015 274 tadejm
//    reset_mac;
14016
//    reset_mii;
14017 243 tadejm
    // set wb slave response
14018
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
14019
 
14020
    max_tmp = 0;
14021
    min_tmp = 0;
14022
    // set 8 RX buffer descriptors (120 - 127) - must be set before RX enable
14023 274 tadejm
    wait (wbm_working == 0);
14024 243 tadejm
    wbm_write(`ETH_TX_BD_NUM, 32'h78, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14025
    // enable RX, set full-duplex mode, receive small, NO correct IFG
14026 274 tadejm
    wait (wbm_working == 0);
14027 243 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
14028
              `ETH_MODER_PRO | `ETH_MODER_BRO,
14029
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14030
    // prepare two packets of MAXFL length
14031 274 tadejm
    wait (wbm_working == 0);
14032 243 tadejm
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14033
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
14034
    min_tmp = tmp[31:16];
14035
    st_data = 8'hAC;
14036
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
14037
    st_data = 8'h35;
14038
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
14039
    // check WB INT signal
14040
    if (wb_int !== 1'b0)
14041
    begin
14042
      test_fail("WB INT signal should not be set");
14043
      fail = fail + 1;
14044
    end
14045
    // unmask interrupts
14046 274 tadejm
    wait (wbm_working == 0);
14047 243 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
14048
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14049
 
14050
    // write to phy's control register for 100Mbps
14051
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
14052
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
14053
    speed = 100;
14054
 
14055
    frame_ended = 0;
14056 252 tadejm
    num_of_frames = 0;// 0; // 10;
14057 243 tadejm
    num_of_bd = 120;
14058
    i_length = 0 - 4;// (0 - 4); // 6; // 4 less due to CRC
14059
    while ((i_length + 4) < 78) // (min_tmp - 4))
14060
    begin
14061
      // append CRC to packet
14062 252 tadejm
      if ((i_length[0] == 1'b0) && (num_of_frames > 4))
14063 243 tadejm
        append_rx_crc (0, i_length, 1'b0, 1'b0);
14064 252 tadejm
      else if (num_of_frames > 4)
14065 243 tadejm
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
14066
      // choose generating carrier sense and collision
14067
      case (i_length[1:0])
14068
      2'h0:
14069
      begin
14070
        // not detect carrier sense in FD and no collision
14071
        eth_phy.no_carrier_sense_rx_fd_detect(0);
14072
        eth_phy.collision(0);
14073
      end
14074
      2'h1:
14075
      begin
14076
        // detect carrier sense in FD and no collision
14077
        eth_phy.no_carrier_sense_rx_fd_detect(1);
14078
        eth_phy.collision(0);
14079
      end
14080
      2'h2:
14081
      begin
14082
        // not detect carrier sense in FD and set collision
14083
        eth_phy.no_carrier_sense_rx_fd_detect(0);
14084
        eth_phy.collision(1);
14085
      end
14086
      default: // 2'h3:
14087
      begin
14088
        // detect carrier sense in FD and set collision
14089
        eth_phy.no_carrier_sense_rx_fd_detect(1);
14090
        eth_phy.collision(1);
14091
      end
14092
      endcase
14093
      #1;
14094
      // first 10 frames are received with RX BD 120 (wrap bit on RX BD 120)
14095
      if (num_of_frames <= 9)
14096
      begin
14097
        case (i_length[1:0])
14098
        2'h0: // Interrupt is generated
14099
        begin
14100
          // enable interrupt generation
14101
          set_rx_bd(120, 120, 1'b1, (`MEMORY_BASE + i_length[1:0]));
14102
        end
14103
        2'h1: // Interrupt is generated
14104
        begin
14105
          // enable interrupt generation
14106
          set_rx_bd(120, 120, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
14107
        end
14108
        2'h2: // Interrupt is generated
14109
        begin
14110
          // enable interrupt generation
14111
          set_rx_bd(120, 120, 1'b1, (`MEMORY_BASE + i_length[1:0]));
14112
        end
14113
        default: // 2'h3: // Interrupt is generated
14114
        begin
14115
          // enable interrupt generation
14116
          set_rx_bd(120, 120, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
14117
        end
14118
        endcase
14119
        // set wrap bit
14120
        set_rx_bd_wrap(120);
14121
      end
14122
      // 10 <= num_of_frames < 18 => wrap set to TX BD 123
14123
      else if ((num_of_frames == 10) || (num_of_frames == 14))
14124
      begin
14125
        tmp_len = i_length; // length of frame
14126
        tmp_bd_num = 120; // RX BD number
14127
        while (tmp_bd_num < 124) // 
14128
        begin
14129
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
14130
          if (tmp_len[0] == 0)
14131
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
14132
          else
14133
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
14134
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
14135
          tmp_len = tmp_len + 1;
14136
          // set RX BD number
14137
          tmp_bd_num = tmp_bd_num + 1;
14138
        end
14139
        // set wrap bit
14140
        set_rx_bd_wrap(123);
14141
      end
14142
      // 18 <= num_of_frames < 28 => wrap set to RX BD 124
14143
      else if ((num_of_frames == 18) || (num_of_frames == 23))
14144
      begin
14145
        tmp_len = i_length; // length of frame
14146
        tmp_bd_num = 120; // RX BD number
14147
        while (tmp_bd_num < 125) // 
14148
        begin
14149
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
14150
          if (tmp_len[0] == 0)
14151
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
14152
          else
14153
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
14154
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
14155
          tmp_len = tmp_len + 1;
14156
          // set RX BD number
14157
          tmp_bd_num = tmp_bd_num + 1;
14158
        end
14159
        // set wrap bit
14160
        set_rx_bd_wrap(124);
14161
      end
14162
      // 28 <= num_of_frames < 40 => wrap set to RX BD 125
14163
      else if ((num_of_frames == 28) || (num_of_frames == 34))
14164
      begin
14165
        tmp_len = i_length; // length of frame
14166
        tmp_bd_num = 120; // RX BD number
14167
        while (tmp_bd_num < 126) // 
14168
        begin
14169
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
14170
          if (tmp_len[0] == 0)
14171
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
14172
          else
14173
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
14174
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
14175
          tmp_len = tmp_len + 1;
14176
          // set RX BD number
14177
          tmp_bd_num = tmp_bd_num + 1;
14178
        end
14179
        // set wrap bit
14180
        set_rx_bd_wrap(125);
14181
      end
14182
      // 40 <= num_of_frames < 54 => wrap set to RX BD 126
14183
      else if ((num_of_frames == 40) || (num_of_frames == 47))
14184
      begin
14185
        tmp_len = i_length; // length of frame
14186
        tmp_bd_num = 120; // RX BD number
14187
        while (tmp_bd_num < 127) // 
14188
        begin
14189
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
14190
          if (tmp_len[0] == 0)
14191
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
14192
          else
14193
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
14194
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
14195
          tmp_len = tmp_len + 1;
14196
          // set RX BD number
14197
          tmp_bd_num = tmp_bd_num + 1;
14198
        end
14199
        // set wrap bit
14200
        set_rx_bd_wrap(126);
14201
      end
14202
      // 54 <= num_of_frames < 70 => wrap set to RX BD 127
14203
      else if ((num_of_frames == 54) || (num_of_frames == 62))
14204
      begin
14205
        tmp_len = i_length; // length of frame
14206
        tmp_bd_num = 120; // RX BD number
14207
        while (tmp_bd_num < 128) // 
14208
        begin
14209
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
14210
          if (tmp_len[0] == 0)
14211
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
14212
          else
14213
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
14214
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
14215
          tmp_len = tmp_len + 1;
14216
          // set RX BD number
14217
          tmp_bd_num = tmp_bd_num + 1;
14218
        end
14219
        // set wrap bit
14220
        set_rx_bd_wrap(127);
14221
      end
14222
      // 70 <= num_of_frames < 78 => wrap set to RX BD 127
14223
      else if (num_of_frames == 70)
14224
      begin
14225
        tmp_len = i_length; // length of frame
14226
        tmp_bd_num = 120; // RX BD number
14227
        while (tmp_bd_num < 128) // 
14228
        begin
14229
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
14230
          if (tmp_len[0] == 0)
14231
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
14232
          else
14233
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
14234
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
14235
          tmp_len = tmp_len + 1;
14236
          // set RX BD number
14237
          tmp_bd_num = tmp_bd_num + 1;
14238
        end
14239
        // set wrap bit
14240
        set_rx_bd_wrap(127);
14241
      end
14242
      #1;
14243
      // SET empty bit
14244
      if (num_of_frames < 10)
14245
        set_rx_bd_empty(120, 120);
14246
      else if (num_of_frames < 14)
14247
        set_rx_bd_empty((120 + num_of_frames - 10), (120 + num_of_frames - 10));
14248
      else if (num_of_frames < 18)
14249
        set_rx_bd_empty((120 + num_of_frames - 14), (120 + num_of_frames - 14));
14250
      else if (num_of_frames < 23)
14251
        set_rx_bd_empty((120 + num_of_frames - 18), (120 + num_of_frames - 18));
14252
      else if (num_of_frames < 28)
14253
        set_rx_bd_empty((120 + num_of_frames - 23), (120 + num_of_frames - 23));
14254
      else if (num_of_frames < 34)
14255
        set_rx_bd_empty((120 + num_of_frames - 28), (120 + num_of_frames - 28));
14256
      else if (num_of_frames < 40)
14257
        set_rx_bd_empty((120 + num_of_frames - 34), (120 + num_of_frames - 34));
14258
      else if (num_of_frames < 47)
14259
        set_rx_bd_empty((120 + num_of_frames - 40), (120 + num_of_frames - 40));
14260
      else if (num_of_frames < 54)
14261
        set_rx_bd_empty((120 + num_of_frames - 47), (120 + num_of_frames - 47));
14262
      else if (num_of_frames < 62)
14263
        set_rx_bd_empty((120 + num_of_frames - 54), (120 + num_of_frames - 54));
14264
      else if (num_of_frames < 70)
14265
        set_rx_bd_empty((120 + num_of_frames - 62), (120 + num_of_frames - 62));
14266
      else if (num_of_frames < 78)
14267
        set_rx_bd_empty((120 + num_of_frames - 70), (120 + num_of_frames - 70));
14268
      // CHECK END OF RECEIVE
14269 252 tadejm
      // receive just preamble between some packets
14270
      if ((num_of_frames == 0) || (num_of_frames == 4) || (num_of_frames == 9))
14271
      begin
14272
        #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h6, 8'h55, 0, 0, 1'b0);
14273
        @(posedge mrx_clk);
14274
        wait (MRxDV === 1'b0); // end receive
14275
        repeat(10) @(posedge mrx_clk);
14276
        repeat(15) @(posedge wb_clk);
14277
      end
14278
      // receiving frames and checking end of them
14279 243 tadejm
      frame_ended = 0;
14280
      check_frame = 0;
14281
      fork
14282
        begin
14283
          if (i_length[0] == 1'b0)
14284
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
14285
          else
14286
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
14287
          repeat(10) @(posedge mrx_clk);
14288
        end
14289 254 mohor
        begin: fr_end2
14290 243 tadejm
          wait (MRxDV === 1'b1); // start receive
14291
          #1 check_rx_bd(num_of_bd, data);
14292
          if (data[15] !== 1)
14293 209 tadejm
          begin
14294 243 tadejm
            test_fail("Wrong buffer descriptor's empty bit read out from MAC");
14295 209 tadejm
            fail = fail + 1;
14296
          end
14297 243 tadejm
          wait (MRxDV === 1'b0); // end receive
14298
          while ((data[15] === 1) && (check_frame == 0))
14299
          begin
14300
            #1 check_rx_bd(num_of_bd, data);
14301
            @(posedge wb_clk);
14302
          end
14303
          if (data[15] === 0)
14304
            frame_ended = 1;
14305
          repeat (1) @(posedge wb_clk);
14306 209 tadejm
        end
14307
        begin
14308 243 tadejm
          wait (MRxDV === 1'b1); // start receive
14309
          wait (MRxDV === 1'b0); // end receive
14310
          repeat(10) @(posedge mrx_clk);
14311
          repeat(15) @(posedge wb_clk);
14312
          check_frame = 1;
14313 209 tadejm
        end
14314 243 tadejm
      join
14315
      // check length of a PACKET
14316 252 tadejm
      if ( ((data[31:16] != (i_length + 4)) && (num_of_frames >= 3)) ||
14317
           ((data[31:16] != 0) && (num_of_frames < 3)) )
14318 243 tadejm
      begin
14319
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
14320
                        data[31:16], (i_length + 4));
14321
        test_fail("Wrong length of the packet out from PHY");
14322
        fail = fail + 1;
14323
      end
14324
      // check received RX packet data and CRC
14325 252 tadejm
      if ((frame_ended == 1) && (num_of_frames >= 5)) // 5 bytes is minimum size without CRC error, since
14326
      begin                                           // CRC has 4 bytes for itself
14327 243 tadejm
        if (i_length[0] == 1'b0)
14328 209 tadejm
        begin
14329 243 tadejm
          check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
14330 209 tadejm
        end
14331 243 tadejm
        else
14332 209 tadejm
        begin
14333 243 tadejm
          check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
14334 209 tadejm
        end
14335
        if (tmp > 0)
14336
        begin
14337 243 tadejm
          `TIME; $display("*E Wrong data of the received packet");
14338
          test_fail("Wrong data of the received packet");
14339 209 tadejm
          fail = fail + 1;
14340
        end
14341
      end
14342
      // check WB INT signal
14343 252 tadejm
      if (num_of_frames >= 3) // Frames smaller than 3 are not received.
14344
      begin                   // Frames greater then 5 always cause an interrupt (Frame received)
14345
        if (wb_int !== 1'b1)  // Frames with length 3 or 4 always cause an interrupt (CRC error)
14346 209 tadejm
        begin
14347
          `TIME; $display("*E WB INT signal should be set");
14348
          test_fail("WB INT signal should be set");
14349
          fail = fail + 1;
14350
        end
14351
      end
14352 252 tadejm
      else
14353 209 tadejm
      begin
14354
        if (wb_int !== 1'b0)
14355
        begin
14356
          `TIME; $display("*E WB INT signal should not be set");
14357
          test_fail("WB INT signal should not be set");
14358
          fail = fail + 1;
14359
        end
14360
      end
14361 243 tadejm
      // check RX buffer descriptor of a packet
14362
      if (num_of_frames >= min_tmp)
14363
      begin
14364 254 mohor
        if ( (data[15:0] !== 16'h6080) && // wrap bit
14365
             (data[15:0] !== 16'h4080) ) // without wrap bit
14366 209 tadejm
        begin
14367 243 tadejm
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
14368
          test_fail("RX buffer descriptor status is not correct");
14369
          fail = fail + 1;
14370 209 tadejm
        end
14371 243 tadejm
      end
14372 254 mohor
      else if (num_of_frames > 6)
14373 243 tadejm
      begin
14374 254 mohor
        if ( (data[15:0] !== 16'h6084) && // wrap bit
14375
             (data[15:0] !== 16'h4084) ) // without wrap bit
14376
        begin
14377
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
14378
          test_fail("RX buffer descriptor status is not correct");
14379
          fail = fail + 1;
14380
        end
14381
      end
14382
      else if (num_of_frames > 4) // MAC does not recognize Dest. ADDR. for lengths 5, 6 => no MISS
14383
      begin
14384 243 tadejm
        if ( (data[15:0] !== 16'h6004) && // wrap bit
14385
             (data[15:0] !== 16'h4004) ) // without wrap bit
14386 209 tadejm
        begin
14387 243 tadejm
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
14388
          test_fail("RX buffer descriptor status is not correct");
14389
          fail = fail + 1;
14390 209 tadejm
        end
14391
      end
14392 254 mohor
      else if (num_of_frames > 2) // MAC does not recognize Dest. ADDR. for length 3, 4 => no MISS, CRC ERROR
14393 243 tadejm
      begin
14394
        if ( (data[15:0] !== 16'h6006) && // wrap bit
14395
             (data[15:0] !== 16'h4006) ) // without wrap bit
14396
        begin
14397
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
14398
          test_fail("RX buffer descriptor status is not correct");
14399
          fail = fail + 1;
14400
        end
14401
      end
14402 209 tadejm
      else
14403
      begin
14404
        if (data[15] !== 1'b1)
14405
        begin
14406 243 tadejm
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
14407
          test_fail("RX buffer descriptor status is not correct");
14408 209 tadejm
          fail = fail + 1;
14409
        end
14410
      end
14411
      // check interrupts
14412 274 tadejm
      wait (wbm_working == 0);
14413 209 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14414 252 tadejm
      if (num_of_frames >= 5)
14415 209 tadejm
      begin
14416 252 tadejm
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
14417 209 tadejm
        begin
14418 243 tadejm
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
14419
          test_fail("Interrupt Receive Buffer was not set");
14420 209 tadejm
          fail = fail + 1;
14421
        end
14422 243 tadejm
        if ((data & (~`ETH_INT_RXB)) !== 0)
14423 209 tadejm
        begin
14424 243 tadejm
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
14425
          test_fail("Other interrupts (except Receive Buffer) were set");
14426 209 tadejm
          fail = fail + 1;
14427
        end
14428
      end
14429 252 tadejm
      else if ((num_of_frames < 3)) // Frames smaller than 3 are not received.
14430
      begin
14431
        if (data) // Checking if any interrupt is pending)
14432
        begin
14433
          `TIME; $display("*E Interrupt(s) is(are) pending although frame was ignored, interrupt reg: %0h", data);
14434
          test_fail("Interrupts were set");
14435
          fail = fail + 1;
14436
        end
14437
      end
14438 209 tadejm
      else
14439
      begin
14440 252 tadejm
        if ((data & `ETH_INT_RXE) !== `ETH_INT_RXE)
14441 209 tadejm
        begin
14442 243 tadejm
          `TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
14443
          test_fail("Interrupt Receive Buffer Error was not set");
14444 209 tadejm
          fail = fail + 1;
14445
        end
14446 243 tadejm
        if ((data & (~`ETH_INT_RXE)) !== 0)
14447
        begin
14448
          `TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
14449
          test_fail("Other interrupts (except Receive Buffer Error) were set");
14450
          fail = fail + 1;
14451
        end
14452 209 tadejm
      end
14453
      // clear interrupts
14454 274 tadejm
      wait (wbm_working == 0);
14455 209 tadejm
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14456
      // check WB INT signal
14457
      if (wb_int !== 1'b0)
14458
      begin
14459
        test_fail("WB INT signal should not be set");
14460
        fail = fail + 1;
14461
      end
14462
      // INTERMEDIATE DISPLAYS
14463 243 tadejm
      if (num_of_frames == 3)
14464 209 tadejm
      begin
14465 243 tadejm
        $display("    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
14466
        $display("    ->packets with lengths from %0d to %0d are not received (length increasing by 1 byte)",
14467 209 tadejm
                 0, 3);
14468
      end
14469 243 tadejm
      else if (num_of_frames == 9)
14470 209 tadejm
      begin
14471 243 tadejm
        $display("    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
14472
        $display("    ->packet with length 4 is not received (length increasing by 1 byte)");
14473 209 tadejm
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
14474
                 5, 9);
14475
      end
14476 243 tadejm
      else if (num_of_frames == 17)
14477 209 tadejm
      begin
14478 243 tadejm
        $display("    using 4 BDs out of 8 BDs (120..127) assigned to RX (wrap at 4th BD - RX BD 123)");
14479 209 tadejm
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
14480
                 10, 17);
14481
      end
14482 243 tadejm
      else if (num_of_frames == 27)
14483 209 tadejm
      begin
14484 243 tadejm
        $display("    using 5 BDs out of 8 BDs (120..127) assigned to RX (wrap at 5th BD - RX BD 124)");
14485 209 tadejm
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
14486
                 18, 27);
14487
      end
14488 243 tadejm
      else if (num_of_frames == 40)
14489 209 tadejm
      begin
14490 243 tadejm
        $display("    using 6 BDs out of 8 BDs (120..127) assigned to RX (wrap at 6th BD - RX BD 125)");
14491 209 tadejm
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
14492
                 28, 40);
14493
      end
14494 243 tadejm
      else if (num_of_frames == 54)
14495 209 tadejm
      begin
14496 243 tadejm
        $display("    using 7 BDs out of 8 BDs (120..127) assigned to RX (wrap at 7th BD - RX BD 126)");
14497 209 tadejm
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
14498
                 41, 54);
14499
      end
14500 243 tadejm
      else if (num_of_frames == 69)
14501 209 tadejm
      begin
14502 243 tadejm
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
14503 209 tadejm
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
14504
                 55, 69);
14505
      end
14506 243 tadejm
      else if (num_of_frames == 69)
14507
      begin
14508
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
14509
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
14510
                 55, 69);
14511
      end
14512
      else if (num_of_frames == 77)
14513
      begin
14514
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
14515
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
14516
                 70, 77);
14517
      end
14518 209 tadejm
      // set length (loop variable)
14519
      i_length = i_length + 1;
14520
      // the number of frame transmitted
14521
      num_of_frames = num_of_frames + 1;
14522
      if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
14523
          (num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
14524
          (num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
14525 243 tadejm
          (num_of_frames == 54) || (num_of_frames == 62) || (num_of_frames == 70))
14526
        num_of_bd = 120;
14527 209 tadejm
      else
14528
        num_of_bd = num_of_bd + 1;
14529
    end
14530 243 tadejm
    // disable RX
14531 274 tadejm
    wait (wbm_working == 0);
14532 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
14533
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14534
    @(posedge wb_clk);
14535
    if(fail == 0)
14536
      test_ok;
14537
    else
14538
      fail = 0;
14539
  end
14540
 
14541
 
14542 243 tadejm
  ////////////////////////////////////////////////////////////////////
14543
  ////                                                            ////
14544
  ////  Test receive packet synchronization with receive          ////
14545
  ////  disable/enable ( 10Mbps ).                                ////
14546
  ////                                                            ////
14547
  ////////////////////////////////////////////////////////////////////
14548
  if (test_num == 10) // Test no receive when all buffers are TX ( 10Mbps ).
14549
  begin
14550
    // TEST 10: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
14551
    test_name   = "TEST 10: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
14552
    `TIME; $display("  TEST 10: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
14553 209 tadejm
 
14554 243 tadejm
 
14555
 
14556
 
14557
 
14558
 
14559
  end
14560
 
14561
 
14562
  ////////////////////////////////////////////////////////////////////
14563
  ////                                                            ////
14564
  ////  Test receive packet synchronization with receive          ////
14565
  ////  disable/enable ( 10Mbps ).                                ////
14566
  ////                                                            ////
14567
  ////////////////////////////////////////////////////////////////////
14568
  if (test_num == 12) // Test no receive when all buffers are TX ( 10Mbps ).
14569
  begin
14570
    // TEST 12: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
14571
    test_name   = "TEST 12: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
14572
    `TIME; $display("  TEST 12: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
14573
 
14574
 
14575
 
14576
 
14577
 
14578
 
14579
  end
14580
 
14581
 
14582
  ////////////////////////////////////////////////////////////////////
14583
  ////                                                            ////
14584
  ////  Test receive packet synchronization with receive          ////
14585
  ////  disable/enable ( 10Mbps ).                                ////
14586
  ////                                                            ////
14587
  ////////////////////////////////////////////////////////////////////
14588
  if (test_num == 14) // Test no receive when all buffers are TX ( 10Mbps ).
14589
  begin
14590
    // TEST 14: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
14591
    test_name   = "TEST 14: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
14592
    `TIME; $display("  TEST 14: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
14593
 
14594
 
14595
 
14596
 
14597
 
14598
 
14599
  end
14600
 
14601
 
14602
  ////////////////////////////////////////////////////////////////////
14603
  ////                                                            ////
14604
  ////  Test receive packet synchronization with receive          ////
14605
  ////  disable/enable ( 10Mbps ).                                ////
14606
  ////                                                            ////
14607
  ////////////////////////////////////////////////////////////////////
14608
  if (test_num == 16) // Test no receive when all buffers are TX ( 10Mbps ).
14609
  begin
14610
    // TEST 16: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
14611
    test_name   = "TEST 16: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
14612
    `TIME; $display("  TEST 16: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
14613
 
14614
 
14615
 
14616
 
14617
 
14618
 
14619
  end
14620
 
14621
 
14622
 
14623 209 tadejm
end   //  for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
14624
 
14625
end
14626
endtask // test_mac_full_duplex_receive
14627
 
14628
 
14629 263 mohor
task test_mac_full_duplex_flow_control;
14630 209 tadejm
  input  [31:0]  start_task;
14631
  input  [31:0]  end_task;
14632
  integer        bit_start_1;
14633
  integer        bit_end_1;
14634
  integer        bit_start_2;
14635
  integer        bit_end_2;
14636
  integer        num_of_reg;
14637
  integer        num_of_frames;
14638 274 tadejm
  integer        num_of_rx_frames;
14639 209 tadejm
  integer        num_of_bd;
14640
  integer        i_addr;
14641
  integer        i_data;
14642
  integer        i_length;
14643
  integer        tmp_len;
14644
  integer        tmp_bd;
14645
  integer        tmp_bd_num;
14646
  integer        tmp_data;
14647
  integer        tmp_ipgt;
14648
  integer        test_num;
14649 274 tadejm
  integer        rx_len;
14650
  integer        tx_len;
14651 209 tadejm
  reg    [31:0]  tx_bd_num;
14652 274 tadejm
  reg    [31:0]  rx_bd_num;
14653 209 tadejm
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
14654
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
14655
  integer        i;
14656
  integer        i1;
14657
  integer        i2;
14658
  integer        i3;
14659
  integer        fail;
14660
  integer        speed;
14661 260 mohor
  integer        mac_hi_addr;
14662
  integer        mac_lo_addr;
14663 209 tadejm
  reg            frame_started;
14664
  reg            frame_ended;
14665
  reg            wait_for_frame;
14666
  reg    [31:0]  addr;
14667
  reg    [31:0]  data;
14668
  reg    [31:0]  tmp;
14669
  reg    [ 7:0]  st_data;
14670
  reg    [15:0]  max_tmp;
14671
  reg    [15:0]  min_tmp;
14672 263 mohor
  reg            PassAll;
14673
  reg            RxFlow;
14674 266 mohor
  reg            enable_irq_in_rxbd;
14675 267 mohor
  reg    [15:0]  pause_value;
14676 274 tadejm
 
14677 209 tadejm
begin
14678 263 mohor
// MAC FULL DUPLEX FLOW CONTROL TEST
14679
test_heading("MAC FULL DUPLEX FLOW CONTROL TEST");
14680 209 tadejm
$display(" ");
14681 263 mohor
$display("MAC FULL DUPLEX FLOW CONTROL TEST");
14682 209 tadejm
fail = 0;
14683
 
14684
// reset MAC registers
14685
hard_reset;
14686
// reset MAC and MII LOGIC with soft reset
14687 274 tadejm
//reset_mac;
14688
//reset_mii;
14689 209 tadejm
// set wb slave response
14690
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
14691
 
14692
  /*
14693
  TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
14694
  -------------------------------------------------------------------------------------
14695
  set_tx_bd
14696
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0], len[15:0], irq, pad, crc, txpnt[31:0]);
14697
  set_tx_bd_wrap
14698
    (tx_bd_num_end[6:0]);
14699
  set_tx_bd_ready
14700
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
14701
  check_tx_bd
14702
    (tx_bd_num_start[6:0], tx_bd_status[31:0]);
14703
  clear_tx_bd
14704
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
14705
 
14706
  TASKS for set and control RX buffer descriptors:
14707
  ------------------------------------------------
14708
  set_rx_bd
14709
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0], irq, rxpnt[31:0]);
14710
  set_rx_bd_wrap
14711
    (rx_bd_num_end[6:0]);
14712
  set_rx_bd_empty
14713
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
14714
  check_rx_bd
14715
    (rx_bd_num_end[6:0], rx_bd_status);
14716
  clear_rx_bd
14717
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
14718
 
14719
  TASKS for set and check TX packets:
14720
  -----------------------------------
14721
  set_tx_packet
14722
    (txpnt[31:0], len[15:0], eth_start_data[7:0]);
14723
  check_tx_packet
14724
    (txpnt_wb[31:0], txpnt_phy[31:0], len[15:0], failure[31:0]);
14725
 
14726
  TASKS for set and check RX packets:
14727
  -----------------------------------
14728
  set_rx_packet
14729
    (rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
14730
  check_rx_packet
14731
    (rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
14732
 
14733
  TASKS for append and check CRC to/of TX packet:
14734
  -----------------------------------------------
14735
  append_tx_crc
14736
    (txpnt_wb[31:0], len[15:0], negated_crc);
14737
  check_tx_crc
14738
    (txpnt_phy[31:0], len[15:0], negated_crc, failure[31:0]);
14739
 
14740
  TASK for append CRC to RX packet (CRC is checked together with check_rx_packet):
14741
  --------------------------------------------------------------------------------
14742
  append_rx_crc
14743
    (rxpnt_phy[31:0], len[15:0], plus_nibble, negated_crc);
14744
  */
14745
 
14746
//////////////////////////////////////////////////////////////////////
14747
////                                                              ////
14748 263 mohor
////  test_mac_full_duplex_flow_control:                          ////
14749 209 tadejm
////                                                              ////
14750
////  0: Test                                                     ////
14751
////                                                              ////
14752
//////////////////////////////////////////////////////////////////////
14753 260 mohor
 
14754 209 tadejm
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
14755
begin
14756
 
14757
  ////////////////////////////////////////////////////////////////////
14758
  ////                                                            ////
14759 254 mohor
  ////  Test inserts control frames while transmitting normal     ////
14760
  ////  frames. Using 4 TX buffer decriptors ( 10Mbps ).          ////
14761 209 tadejm
  ////                                                            ////
14762
  ////////////////////////////////////////////////////////////////////
14763 254 mohor
  if (test_num == 0) // 
14764 209 tadejm
  begin
14765 254 mohor
    // TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps )
14766
    test_name = "TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps )";
14767
    `TIME; $display("  TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps )");
14768 260 mohor
 
14769 254 mohor
    // reset MAC completely
14770
    hard_reset;
14771
    // set wb slave response
14772
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
14773
    max_tmp = 0;
14774
    min_tmp = 0;
14775
    // set 4 TX buffer descriptors - must be set before TX enable
14776
    wbm_write(`ETH_TX_BD_NUM, 32'h4, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14777
    // enable TX, set full-duplex mode, padding and CRC appending
14778
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
14779
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14780
    // enable TX flow control
14781
    wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_TXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14782 260 mohor
    // Set MAC address
14783
    mac_hi_addr = 32'h00000001;
14784
    mac_lo_addr = 32'h02030405;
14785
    wbm_write(`ETH_MAC_ADDR1, mac_hi_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14786
    wbm_write(`ETH_MAC_ADDR0, mac_lo_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14787 254 mohor
    // prepare two packets of MAXFL length
14788
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14789
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
14790
    min_tmp = tmp[31:16];
14791 260 mohor
    st_data = 8'h34;
14792 254 mohor
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC. Writing data to the memory
14793 260 mohor
    st_data = 8'h56;
14794 254 mohor
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp - 4), st_data); // length without CRC. Writing data to the memory
14795
    // check WB INT signal
14796
    if (wb_int !== 1'b0)
14797
    begin
14798
      test_fail("WB INT signal should not be set");
14799
      fail = fail + 1;
14800
    end
14801
 
14802
    // write to phy's control register for 10Mbps
14803
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
14804
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
14805
    speed = 10;
14806
 
14807
    frame_started = 0;
14808
    num_of_frames = 0;
14809
    num_of_bd = 0;
14810
    i_length = 0; // 0;
14811 260 mohor
    // Initialize one part of memory with data of control packet
14812
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h0), 32'h0180c200, 4'hF);
14813
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h4), {16'h0001, mac_hi_addr[15:0]}, 4'hF);
14814
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h8), mac_lo_addr, 4'hF);
14815
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'hc), 32'h88080001, 4'hF);
14816
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), 32'h11110000, 4'hF);
14817
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h14), 32'h00000000, 4'hF);
14818
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h18), 32'h00000000, 4'hF);
14819
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h1c), 32'h00000000, 4'hF);
14820
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h20), 32'h00000000, 4'hF);
14821
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h24), 32'h00000000, 4'hF);
14822
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h28), 32'h00000000, 4'hF);
14823
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h2c), 32'h00000000, 4'hF);
14824
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h30), 32'h00000000, 4'hF);
14825
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h34), 32'h00000000, 4'hF);
14826
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h38), 32'h00000000, 4'hF);
14827
//    append_tx_crc(`MEMORY_BASE + 2 * max_tmp, 60, 0);       // CRC is appended after the data
14828 254 mohor
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14829
    // In the following section, control frame will be sent while no other transmission is in progress.//
14830
    // TXC interrupt won't be unmasked.                                                                //
14831
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14832 274 tadejm
    // check interrupts
14833 254 mohor
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14834
    if(data)
14835
      begin
14836
        test_fail("IRQ already pending!");
14837
        fail = fail + 1;
14838
        `TIME; $display("*E IRQ already pending!");
14839
      end
14840
    if (wb_int)
14841
    begin
14842
      test_fail("WB INT signal should not be set!");
14843
      fail = fail + 1;
14844
      `TIME; $display("*E WB INT signal should not be set!");
14845
    end
14846 260 mohor
    // first destination address on ethernet PHY
14847
    eth_phy.set_tx_mem_addr(0);
14848
    // Request sending the control frame with pause value = 0x1111
14849
    wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | 32'h1111, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14850 274 tadejm
    // wait for transmission to come over
14851 254 mohor
    wait (MTxEn === 1'b1); // start transmit
14852
    wait (MTxEn === 1'b0); // end transmit
14853
    repeat(10) @ (posedge wb_clk);  // wait some time
14854
    repeat(10) @ (posedge mtx_clk); // wait some time
14855 274 tadejm
    // check interrupt
14856 254 mohor
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14857
    if(data !== `ETH_INT_TXC)
14858
      begin
14859
        test_fail("TXC IRQ should be set!");
14860
        fail = fail + 1;
14861
        `TIME; $display("*E TXC IRQ should be set!");
14862
      end
14863
    if (wb_int)
14864
    begin
14865
      test_fail("WB INT signal should not be set because TXC irq is masked!");
14866
      fail = fail + 1;
14867
      `TIME; $display("*E WB INT signal should not be set because TXC irq is masked!");
14868
    end
14869
    // Clear TXC interrupt
14870
    wbm_write(`ETH_INT, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14871
    if (wb_int)
14872
    begin
14873
      test_fail("WB INT signal should not be set!");
14874
      fail = fail + 1;
14875
      `TIME; $display("*E WB INT signal should not be set!");
14876
    end
14877 274 tadejm
    // check transmited TX packet
14878 260 mohor
    check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
14879
    if (tmp > 0)
14880
    begin
14881
      $display("Wrong data of the transmitted packet");
14882
      test_fail("Wrong data of the transmitted packet");
14883
      fail = fail + 1;
14884
    end
14885
    // check transmited TX packet CRC
14886
    #1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
14887
    if (tmp > 0)
14888
    begin
14889
      $display("Wrong CRC of the transmitted packet");
14890
      test_fail("Wrong CRC of the transmitted packet");
14891
      fail = fail + 1;
14892
    end
14893 254 mohor
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14894
    // In the following section, control frame will be sent while no other transmission is in progress.//
14895
    // TXC interrupt is unmasked.                                                                      //
14896
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14897
    // unmask all interrupts
14898
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
14899
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14900 274 tadejm
    // check interrupts
14901 254 mohor
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14902
    if(data)
14903
      begin
14904
        test_fail("IRQ already pending!");
14905
        fail = fail + 1;
14906
        `TIME; $display("*E IRQ already pending!");
14907
      end
14908
    if (wb_int)
14909
    begin
14910
      test_fail("WB INT signal should not be set!");
14911
      fail = fail + 1;
14912
      `TIME; $display("*E WB INT signal should not be set!");
14913
    end
14914
    // unmask only TXC interrupts
14915
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14916 260 mohor
    // first destination address on ethernet PHY
14917
    eth_phy.set_tx_mem_addr(0);
14918
    // Request sending the control frame with pause value = 0x2222
14919
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), 32'h22220000, 4'hF);  // Just for data test
14920
    wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | 32'h2222, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14921 274 tadejm
    // wait for transmit to come over
14922 254 mohor
    wait (MTxEn === 1'b1); // start transmit
14923
    wait (MTxEn === 1'b0); // end transmit
14924
    repeat(10) @ (posedge wb_clk);  // wait some time
14925
    repeat(10) @ (posedge mtx_clk); // wait some time
14926 274 tadejm
    // check INT
14927 254 mohor
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14928
    if(data !== `ETH_INT_TXC)
14929
      begin
14930
        test_fail("TXC IRQ should be set!");
14931
        fail = fail + 1;
14932
        `TIME; $display("*E TXC IRQ should be set!");
14933
      end
14934
    if (!wb_int)
14935
    begin
14936
      test_fail("WB INT signal should be set!");
14937
      fail = fail + 1;
14938
      `TIME; $display("*E WB INT signal should be set!");
14939
    end
14940
    // Clear TXC interrupt
14941
    wbm_write(`ETH_INT, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14942
    if (wb_int)
14943
    begin
14944
      test_fail("WB INT signal should not be set!");
14945
      fail = fail + 1;
14946
      `TIME; $display("*E WB INT signal should not be set!");
14947
    end
14948 274 tadejm
    // check transmited TX packet
14949 260 mohor
    check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
14950
    if (tmp > 0)
14951
    begin
14952
      $display("Wrong data of the transmitted packet");
14953
      test_fail("Wrong data of the transmitted packet");
14954
      fail = fail + 1;
14955
    end
14956
    // check transmited TX packet CRC
14957
    #1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
14958
    if (tmp > 0)
14959
    begin
14960
      $display("Wrong CRC of the transmitted packet");
14961
      test_fail("Wrong CRC of the transmitted packet");
14962
      fail = fail + 1;
14963
    end
14964 254 mohor
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14965 260 mohor
    // In the following section, control frame sending is requested while no other transmission        //
14966
    // is in progress. TXC interrupt is unmasked.                                                      //
14967 254 mohor
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14968
    // unmask all interrupts
14969
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
14970
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14971
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14972
    if(data)
14973
      begin
14974
        test_fail("IRQ already pending!");
14975
        fail = fail + 1;
14976
        `TIME; $display("*E IRQ already pending!");
14977
      end
14978
    if (wb_int)
14979
    begin
14980
      test_fail("WB INT signal should not be set!");
14981
      fail = fail + 1;
14982
      `TIME; $display("*E WB INT signal should not be set!");
14983
    end
14984 260 mohor
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14985
    // In the following section, control frame request and data send request are both set. At the      //
14986
    // beginning control frame request will be faster than data send request, later the opposite.      //
14987
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14988
    for (i=0; i<32; i=i+1)
14989
    begin
14990
      // Request sending the control frame with pause value = 0x5678
14991
      set_tx_bd(0, 0, 16'h100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE)); // irq, pad, crc
14992
      set_tx_bd_wrap(0);
14993
      // first destination address on ethernet PHY
14994
      eth_phy.set_tx_mem_addr(0);
14995
      set_tx_bd_ready(0, 0);
14996 274 tadejm
      // wait for transmission to start  
14997 260 mohor
      wait (MTxEn === 1'b1); // start transmit
14998
      repeat(i) @ (posedge mtx_clk);  // We need to wait some time until TX module starts using the data (preamble stage is over)
14999
      // Send control frame request
15000
      wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), {i[3:0], i[3:0], i[3:0], i[3:0], 16'h0}, 4'hF);  // Just for data test
15001
      wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | {16'h0, i[3:0], i[3:0], i[3:0], i[3:0]}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15002 274 tadejm
      // wait until transmission is over  
15003 260 mohor
      wait (MTxEn === 1'b0); // Wait until data frame transmission is over
15004
      repeat(10) @ (posedge mtx_clk); // wait some time so status is written
15005
      tmp_len = eth_phy.tx_len; // the length of a packet which was sent out first!!!
15006
      repeat(10) @ (posedge wb_clk);  // wait some time so status is written
15007
      // first destination address on ethernet PHY
15008
      eth_phy.set_tx_mem_addr(0);
15009 274 tadejm
      // check interrupt depending on which packet was sent
15010 260 mohor
      if(tmp_len == 64)  // Control frame
15011 254 mohor
      begin
15012 260 mohor
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15013
        if(data !== `ETH_INT_TXC)
15014
        begin
15015
          test_fail("TXC IRQ should be set!");
15016
          fail = fail + 1;
15017
          `TIME; $display("*E TXC IRQ should be set!");
15018
          `TIME; $display("ETH_INT = 0x%0x", data);
15019
        end
15020
      end
15021
      else
15022
      begin
15023
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15024
        if(data !== `ETH_INT_TXB)
15025
        begin
15026
          test_fail("TXB IRQ should be set!");
15027
          fail = fail + 1;
15028
          `TIME; $display("*E TXB IRQ should be set!");
15029
          `TIME; $display("ETH_INT = 0x%0x", data);
15030
        end
15031
      end
15032 274 tadejm
      // check transmited TX packet
15033 260 mohor
      if(tmp_len == 64)  // Control frame
15034
        check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
15035
      else
15036
        check_tx_packet((`MEMORY_BASE), 0, 32'h100, tmp);
15037
      if (tmp > 0)
15038
      begin
15039
        $display("Wrong data of the transmitted packet");
15040
        test_fail("Wrong data of the transmitted packet");
15041 254 mohor
        fail = fail + 1;
15042
      end
15043 260 mohor
      // check transmited TX packet CRC
15044
      if(tmp_len == 64)  // Control frame
15045
        #1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
15046
      else
15047
        #1 check_tx_crc(0, 32'h100, 1'b0, tmp); // length without CRC
15048
 
15049
      if (tmp > 0)
15050 254 mohor
      begin
15051 260 mohor
        $display("Wrong CRC of the transmitted packet");
15052
        test_fail("Wrong CRC of the transmitted packet");
15053
        fail = fail + 1;
15054
      end
15055 274 tadejm
      // wait for control frame to transmit
15056 260 mohor
      wait (MTxEn === 1'b1); // start transmit of the control frame
15057
      wait (MTxEn === 1'b0); // end transmit of the control frame
15058
      repeat(10) @ (posedge wb_clk);  // wait some time
15059
      repeat(10) @ (posedge mtx_clk); // wait some time so status is written
15060 274 tadejm
      // check interrupts  
15061 260 mohor
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15062
      if(data !== (`ETH_INT_TXC | `ETH_INT_TXB))
15063
      begin
15064 254 mohor
        test_fail("TXC and TXB IRQ should be set!");
15065
        fail = fail + 1;
15066 260 mohor
        `TIME; $display("*E TXC and TXB IRQ should be set! (ETH_INT=0x%0x)", data);
15067 254 mohor
      end
15068 260 mohor
      if (!wb_int)
15069
      begin
15070
        test_fail("WB INT signal should be set!");
15071
        fail = fail + 1;
15072
        `TIME; $display("*E WB INT signal should be set!");
15073
      end
15074
      // Clear TXC and TXB interrupt
15075
      wbm_write(`ETH_INT, `ETH_INT_TXC | `ETH_INT_TXB, 4'hF, 1, 4'h0, 4'h0);
15076
      if (wb_int)
15077
      begin
15078
        test_fail("WB INT signal should not be set!");
15079
        fail = fail + 1;
15080
        `TIME; $display("*E WB INT signal should not be set!");
15081
      end
15082
      if(tmp_len == 64)  // Control frame
15083
        check_tx_packet((`MEMORY_BASE), 0, 32'h100, tmp);
15084
      else
15085
        check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
15086
      if (tmp > 0)
15087
      begin
15088
        $display("Wrong data of the transmitted packet");
15089
        test_fail("Wrong data of the transmitted packet");
15090
        fail = fail + 1;
15091
      end
15092
      // check transmited TX packet CRC
15093
      if(tmp_len == 64)  // Control frame
15094
        #1 check_tx_crc(0, 32'h100, 1'b0, tmp); // length without CRC
15095
      else
15096
        #1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
15097
      if (tmp > 0)
15098
      begin
15099
        $display("Wrong CRC of the transmitted packet");
15100
        test_fail("Wrong CRC of the transmitted packet");
15101
        fail = fail + 1;
15102
      end
15103
    end // for loop
15104
    if(fail == 0)
15105
      test_ok;
15106
    else
15107
      fail = 0;
15108
  end
15109 254 mohor
 
15110
 
15111 274 tadejm
  ////////////////////////////////////////////////////////////////////
15112
  ////                                                            ////
15113
  ////  Test inserts control frames while transmitting normal     ////
15114
  ////  frames. Using 4 TX buffer decriptors ( 100Mbps ).         ////
15115
  ////                                                            ////
15116
  ////////////////////////////////////////////////////////////////////
15117 263 mohor
  if (test_num == 1) // 
15118
  begin
15119
    // TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps )
15120
    test_name = "TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps )";
15121
    `TIME; $display("  TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps )");
15122 274 tadejm
 
15123
    // reset MAC completely
15124
    hard_reset;
15125
    // set wb slave response
15126
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
15127
    max_tmp = 0;
15128
    min_tmp = 0;
15129
    // set 4 TX buffer descriptors - must be set before TX enable
15130
    wbm_write(`ETH_TX_BD_NUM, 32'h4, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15131
    // enable TX, set full-duplex mode, padding and CRC appending
15132
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
15133
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15134
    // enable TX flow control
15135
    wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_TXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15136
    // Set MAC address
15137
    mac_hi_addr = 32'h00000001;
15138
    mac_lo_addr = 32'h02030405;
15139
    wbm_write(`ETH_MAC_ADDR1, mac_hi_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15140
    wbm_write(`ETH_MAC_ADDR0, mac_lo_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15141
    // prepare two packets of MAXFL length
15142
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15143
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
15144
    min_tmp = tmp[31:16];
15145
    st_data = 8'h34;
15146
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC. Writing data to the memory
15147
    st_data = 8'h56;
15148
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp - 4), st_data); // length without CRC. Writing data to the memory
15149
    // check WB INT signal
15150
    if (wb_int !== 1'b0)
15151
    begin
15152
      test_fail("WB INT signal should not be set");
15153
      fail = fail + 1;
15154
    end
15155
 
15156
    // write to phy's control register for 100Mbps
15157
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
15158
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
15159
    speed = 100;
15160
 
15161
    frame_started = 0;
15162
    num_of_frames = 0;
15163
    num_of_bd = 0;
15164
    i_length = 0; // 0;
15165
    // Initialize one part of memory with data of control packet
15166
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h0), 32'h0180c200, 4'hF);
15167
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h4), {16'h0001, mac_hi_addr[15:0]}, 4'hF);
15168
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h8), mac_lo_addr, 4'hF);
15169
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'hc), 32'h88080001, 4'hF);
15170
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), 32'h11110000, 4'hF);
15171
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h14), 32'h00000000, 4'hF);
15172
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h18), 32'h00000000, 4'hF);
15173
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h1c), 32'h00000000, 4'hF);
15174
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h20), 32'h00000000, 4'hF);
15175
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h24), 32'h00000000, 4'hF);
15176
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h28), 32'h00000000, 4'hF);
15177
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h2c), 32'h00000000, 4'hF);
15178
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h30), 32'h00000000, 4'hF);
15179
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h34), 32'h00000000, 4'hF);
15180
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h38), 32'h00000000, 4'hF);
15181
//    append_tx_crc(`MEMORY_BASE + 2 * max_tmp, 60, 0);       // CRC is appended after the data
15182
    /////////////////////////////////////////////////////////////////////////////////////////////////////
15183
    // In the following section, control frame will be sent while no other transmission is in progress.//
15184
    // TXC interrupt won't be unmasked.                                                                //
15185
    /////////////////////////////////////////////////////////////////////////////////////////////////////
15186
    // check interrupts
15187
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15188
    if(data)
15189
      begin
15190
        test_fail("IRQ already pending!");
15191
        fail = fail + 1;
15192
        `TIME; $display("*E IRQ already pending!");
15193
      end
15194
    if (wb_int)
15195
    begin
15196
      test_fail("WB INT signal should not be set!");
15197
      fail = fail + 1;
15198
      `TIME; $display("*E WB INT signal should not be set!");
15199
    end
15200
    // first destination address on ethernet PHY
15201
    eth_phy.set_tx_mem_addr(0);
15202
    // Request sending the control frame with pause value = 0x1111
15203
    wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | 32'h1111, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15204
    // wait for transmission to come over
15205
    wait (MTxEn === 1'b1); // start transmit
15206
    wait (MTxEn === 1'b0); // end transmit
15207
    repeat(10) @ (posedge wb_clk);  // wait some time
15208
    repeat(10) @ (posedge mtx_clk); // wait some time
15209
    // check interrupt
15210
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15211
    if(data !== `ETH_INT_TXC)
15212
      begin
15213
        test_fail("TXC IRQ should be set!");
15214
        fail = fail + 1;
15215
        `TIME; $display("*E TXC IRQ should be set!");
15216
      end
15217
    if (wb_int)
15218
    begin
15219
      test_fail("WB INT signal should not be set because TXC irq is masked!");
15220
      fail = fail + 1;
15221
      `TIME; $display("*E WB INT signal should not be set because TXC irq is masked!");
15222
    end
15223
    // Clear TXC interrupt
15224
    wbm_write(`ETH_INT, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15225
    if (wb_int)
15226
    begin
15227
      test_fail("WB INT signal should not be set!");
15228
      fail = fail + 1;
15229
      `TIME; $display("*E WB INT signal should not be set!");
15230
    end
15231
    // check transmited TX packet
15232
    check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
15233
    if (tmp > 0)
15234
    begin
15235
      $display("Wrong data of the transmitted packet");
15236
      test_fail("Wrong data of the transmitted packet");
15237
      fail = fail + 1;
15238
    end
15239
    // check transmited TX packet CRC
15240
    #1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
15241
    if (tmp > 0)
15242
    begin
15243
      $display("Wrong CRC of the transmitted packet");
15244
      test_fail("Wrong CRC of the transmitted packet");
15245
      fail = fail + 1;
15246
    end
15247
    /////////////////////////////////////////////////////////////////////////////////////////////////////
15248
    // In the following section, control frame will be sent while no other transmission is in progress.//
15249
    // TXC interrupt is unmasked.                                                                      //
15250
    /////////////////////////////////////////////////////////////////////////////////////////////////////
15251
    // unmask all interrupts
15252
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
15253
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15254
    // check interrupts
15255
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15256
    if(data)
15257
      begin
15258
        test_fail("IRQ already pending!");
15259
        fail = fail + 1;
15260
        `TIME; $display("*E IRQ already pending!");
15261
      end
15262
    if (wb_int)
15263
    begin
15264
      test_fail("WB INT signal should not be set!");
15265
      fail = fail + 1;
15266
      `TIME; $display("*E WB INT signal should not be set!");
15267
    end
15268
    // unmask only TXC interrupts
15269
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15270
    // first destination address on ethernet PHY
15271
    eth_phy.set_tx_mem_addr(0);
15272
    // Request sending the control frame with pause value = 0x2222
15273
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), 32'h22220000, 4'hF);  // Just for data test
15274
    wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | 32'h2222, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15275
    // wait for transmit to come over
15276
    wait (MTxEn === 1'b1); // start transmit
15277
    wait (MTxEn === 1'b0); // end transmit
15278
    repeat(10) @ (posedge wb_clk);  // wait some time
15279
    repeat(10) @ (posedge mtx_clk); // wait some time
15280
    // check INT
15281
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15282
    if(data !== `ETH_INT_TXC)
15283
      begin
15284
        test_fail("TXC IRQ should be set!");
15285
        fail = fail + 1;
15286
        `TIME; $display("*E TXC IRQ should be set!");
15287
      end
15288
    if (!wb_int)
15289
    begin
15290
      test_fail("WB INT signal should be set!");
15291
      fail = fail + 1;
15292
      `TIME; $display("*E WB INT signal should be set!");
15293
    end
15294
    // Clear TXC interrupt
15295
    wbm_write(`ETH_INT, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15296
    if (wb_int)
15297
    begin
15298
      test_fail("WB INT signal should not be set!");
15299
      fail = fail + 1;
15300
      `TIME; $display("*E WB INT signal should not be set!");
15301
    end
15302
    // check transmited TX packet
15303
    check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
15304
    if (tmp > 0)
15305
    begin
15306
      $display("Wrong data of the transmitted packet");
15307
      test_fail("Wrong data of the transmitted packet");
15308
      fail = fail + 1;
15309
    end
15310
    // check transmited TX packet CRC
15311
    #1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
15312
    if (tmp > 0)
15313
    begin
15314
      $display("Wrong CRC of the transmitted packet");
15315
      test_fail("Wrong CRC of the transmitted packet");
15316
      fail = fail + 1;
15317
    end
15318
    /////////////////////////////////////////////////////////////////////////////////////////////////////
15319
    // In the following section, control frame sending is requested while no other transmission        //
15320
    // is in progress. TXC interrupt is unmasked.                                                      //
15321
    /////////////////////////////////////////////////////////////////////////////////////////////////////
15322
    // unmask all interrupts
15323
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
15324
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15325
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15326
    if(data)
15327
      begin
15328
        test_fail("IRQ already pending!");
15329
        fail = fail + 1;
15330
        `TIME; $display("*E IRQ already pending!");
15331
      end
15332
    if (wb_int)
15333
    begin
15334
      test_fail("WB INT signal should not be set!");
15335
      fail = fail + 1;
15336
      `TIME; $display("*E WB INT signal should not be set!");
15337
    end
15338
 
15339
    /////////////////////////////////////////////////////////////////////////////////////////////////////
15340
    // In the following section, control frame request and data send request are both set. At the      //
15341
    // beginning control frame request will be faster than data send request, later the opposite.      //
15342
    /////////////////////////////////////////////////////////////////////////////////////////////////////
15343
    for (i=0; i<32; i=i+1)
15344
    begin
15345
      // Request sending the control frame with pause value = 0x5678
15346
      set_tx_bd(0, 0, 16'h100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE)); // irq, pad, crc
15347
      set_tx_bd_wrap(0);
15348
      // first destination address on ethernet PHY
15349
      eth_phy.set_tx_mem_addr(0);
15350
      set_tx_bd_ready(0, 0);
15351
      // wait for transmission to start  
15352
      wait (MTxEn === 1'b1); // start transmit
15353
      repeat(i) @ (posedge mtx_clk);  // We need to wait some time until TX module starts using the data (preamble stage is over)
15354
      // Send control frame request
15355
      wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), {i[3:0], i[3:0], i[3:0], i[3:0], 16'h0}, 4'hF);  // Just for data test
15356
      wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | {16'h0, i[3:0], i[3:0], i[3:0], i[3:0]}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15357
      // wait until transmission is over  
15358
      wait (MTxEn === 1'b0); // Wait until data frame transmission is over
15359
      repeat(10) @ (posedge mtx_clk); // wait some time so status is written
15360
      tmp_len = eth_phy.tx_len; // the length of a packet which was sent out first!!!
15361
      repeat(10) @ (posedge wb_clk);  // wait some time so status is written
15362
      // first destination address on ethernet PHY
15363
      eth_phy.set_tx_mem_addr(0);
15364
      // check interrupt depending on which packet was sent
15365
 
15366
      if(tmp_len == 64)  // Control frame
15367
      begin
15368
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15369
        if(data !== `ETH_INT_TXC)
15370
        begin
15371
          test_fail("TXC IRQ should be set!");
15372
          fail = fail + 1;
15373
          `TIME; $display("*E TXC IRQ should be set!");
15374
          `TIME; $display("ETH_INT = 0x%0x", data);
15375
        end
15376
      end
15377
      else
15378
      begin
15379
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15380
        if(data !== `ETH_INT_TXB)
15381
        begin
15382
          test_fail("TXB IRQ should be set!");
15383
          fail = fail + 1;
15384
          `TIME; $display("*E TXB IRQ should be set!");
15385
          `TIME; $display("ETH_INT = 0x%0x", data);
15386
        end
15387
      end
15388
      // check transmited TX packet
15389
      if(tmp_len == 64)  // Control frame
15390
        check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
15391
      else
15392
        check_tx_packet((`MEMORY_BASE), 0, 32'h100, tmp);
15393
      if (tmp > 0)
15394
      begin
15395
        $display("Wrong data of the transmitted packet");
15396
        test_fail("Wrong data of the transmitted packet");
15397
        fail = fail + 1;
15398
      end
15399
      // check transmited TX packet CRC
15400
      if(tmp_len == 64)  // Control frame
15401
        #1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
15402
      else
15403
        #1 check_tx_crc(0, 32'h100, 1'b0, tmp); // length without CRC
15404
 
15405
      if (tmp > 0)
15406
      begin
15407
        $display("Wrong CRC of the transmitted packet");
15408
        test_fail("Wrong CRC of the transmitted packet");
15409
        fail = fail + 1;
15410
      end
15411
      // wait for control frame to transmit
15412
      wait (MTxEn === 1'b1); // start transmit of the control frame
15413
      wait (MTxEn === 1'b0); // end transmit of the control frame
15414
      repeat(10) @ (posedge wb_clk);  // wait some time
15415
      repeat(10) @ (posedge mtx_clk); // wait some time so status is written
15416
      // check interrupts  
15417
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15418
      if(data !== (`ETH_INT_TXC | `ETH_INT_TXB))
15419
      begin
15420
        test_fail("TXC and TXB IRQ should be set!");
15421
        fail = fail + 1;
15422
        `TIME; $display("*E TXC and TXB IRQ should be set! (ETH_INT=0x%0x)", data);
15423
      end
15424
      if (!wb_int)
15425
      begin
15426
        test_fail("WB INT signal should be set!");
15427
        fail = fail + 1;
15428
        `TIME; $display("*E WB INT signal should be set!");
15429
      end
15430
      // Clear TXC and TXB interrupt
15431
      wbm_write(`ETH_INT, `ETH_INT_TXC | `ETH_INT_TXB, 4'hF, 1, 4'h0, 4'h0);
15432
      if (wb_int)
15433
      begin
15434
        test_fail("WB INT signal should not be set!");
15435
        fail = fail + 1;
15436
        `TIME; $display("*E WB INT signal should not be set!");
15437
      end
15438
      if(tmp_len == 64)  // Control frame
15439
        check_tx_packet((`MEMORY_BASE), 0, 32'h100, tmp);
15440
      else
15441
        check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
15442
      if (tmp > 0)
15443
      begin
15444
        $display("Wrong data of the transmitted packet");
15445
        test_fail("Wrong data of the transmitted packet");
15446
        fail = fail + 1;
15447
      end
15448
      // check transmited TX packet CRC
15449
      if(tmp_len == 64)  // Control frame
15450
        #1 check_tx_crc(0, 32'h100, 1'b0, tmp); // length without CRC
15451
      else
15452
        #1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
15453
      if (tmp > 0)
15454
      begin
15455
        $display("Wrong CRC of the transmitted packet");
15456
        test_fail("Wrong CRC of the transmitted packet");
15457
        fail = fail + 1;
15458
      end
15459
    end // for loop
15460
    if(fail == 0)
15461
      test_ok;
15462
    else
15463
      fail = 0;
15464 263 mohor
  end
15465 254 mohor
 
15466 274 tadejm
 
15467 260 mohor
  ////////////////////////////////////////////////////////////////////
15468
  ////                                                            ////
15469 267 mohor
  ////  Receive control frames with PASSALL option turned on and  ////
15470
  ////  off. Using only one RX buffer decriptor ( 10Mbps ).       ////
15471 260 mohor
  ////                                                            ////
15472
  ////////////////////////////////////////////////////////////////////
15473 263 mohor
  if (test_num == 2) // 
15474 260 mohor
  begin
15475 267 mohor
    // TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 10Mbps )
15476
    test_name   = "TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 10Mbps )";
15477
    `TIME; $display("  TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 10Mbps )");
15478 254 mohor
 
15479 260 mohor
    // unmask interrupts
15480
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
15481
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15482
    // set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
15483
    wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15484
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
15485 267 mohor
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
15486 260 mohor
              `ETH_MODER_PRO | `ETH_MODER_BRO,
15487
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15488 263 mohor
    // enable RX_FLOW control
15489
    wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15490 260 mohor
    // prepare one packet of 100 bytes long
15491 267 mohor
//    st_data = 8'h1A;
15492
//    set_rx_packet(64, 100, 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data); 
15493
//    append_rx_crc (64, 100, 1'b0, 1'b0); // CRC for data packet
15494
    st_data = 8'h01;
15495
    set_tx_packet(`MEMORY_BASE + 64, 100, 8'h01); // length without CRC
15496
    set_tx_bd(0, 0, 100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + 64));
15497
    set_tx_bd_wrap(0);
15498 260 mohor
    // check WB INT signal
15499
    if (wb_int !== 1'b0)
15500
    begin
15501
      test_fail("WB INT signal should not be set");
15502
      fail = fail + 1;
15503
    end
15504 274 tadejm
 
15505 260 mohor
    // write to phy's control register for 10Mbps
15506
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
15507
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
15508
    speed = 10;
15509 254 mohor
 
15510 266 mohor
    // RXB and RXC interrupts masked
15511
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXE | `ETH_INT_BUSY |
15512
                             `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15513
    // Test irq logic while RXB and RXC interrupts are masked. IRQ in RxBD is cleared
15514
    for (i=0; i<3; i=i+1)
15515
    begin
15516 274 tadejm
      pause_value = i+2;
15517 267 mohor
      set_rx_control_packet(0, pause_value);  // CRC already appended
15518 266 mohor
      // choose generating carrier sense and collision for first and last 64 lengths of frames
15519
      case (i)
15520
      0: // PASSALL = 0, RXFLOW = 1, IRQ in RxBD = 1
15521
      begin
15522
        PassAll=0; RxFlow=1; enable_irq_in_rxbd=1;
15523
        // enable interrupt generation
15524
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
15525
        // Set PASSALL = 0 and RXFLOW = 0
15526
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15527
      end
15528
      1: // PASSALL = 1, RXFLOW = 0, IRQ in RxBD = 1
15529
      begin
15530
        PassAll=1; RxFlow=0; enable_irq_in_rxbd=1;
15531
        // enable interrupt generation
15532
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
15533
        // Set PASSALL = 0 and RXFLOW = 0
15534
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15535
      end
15536
      2: // PASSALL = 1, RXFLOW = 0, IRQ in RxBD = 0
15537
      begin
15538
        PassAll=1; RxFlow=0; enable_irq_in_rxbd=0;
15539
        // enable interrupt generation
15540
        set_rx_bd(127, 127, 1'b0, `MEMORY_BASE);
15541
        // Set PASSALL = 0 and RXFLOW = 0
15542
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15543
      end
15544
      default:
15545
      begin
15546
        $display("*E We should never get here !!!");
15547
        test_fail("We should never get here !!!");
15548
        fail = fail + 1;
15549
      end
15550
      endcase
15551
      // not detect carrier sense in FD and no collision
15552
      eth_phy.no_carrier_sense_rx_fd_detect(0);
15553
      eth_phy.collision(0);
15554
      // set wrap bit and empty bit
15555
      set_rx_bd_wrap(127);
15556
      set_rx_bd_empty(127, 127);
15557 274 tadejm
      // transmit
15558 266 mohor
      fork
15559
        begin
15560
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, 64, 1'b0);
15561
          repeat(10) @(posedge mrx_clk);
15562
        end
15563
        begin
15564
          wait (MRxDV === 1'b1); // start transmit
15565
          #1 check_rx_bd(127, data);
15566
          if (data[15] !== 1)
15567
          begin
15568
            $display("*E Wrong buffer descriptor's ready bit read out from MAC");
15569
            test_fail("Wrong buffer descriptor's ready bit read out from MAC");
15570
            fail = fail + 1;
15571
          end
15572 267 mohor
          wait (MRxDV === 1'b0); // received pause frame
15573
          repeat(5) @(posedge mrx_clk);  // Wait some time so pause is activated.
15574
          repeat(5) @(posedge mtx_clk);  // Wait some time so pause is activated.
15575
          set_tx_bd_ready(0, 0); // Request sending the data. Data should not be sent when pause frame was received
15576
                                 // and RxFlow enabled.
15577
          // When we exit the while loop, status frame is received
15578
          repeat(`ETH_TX_FIFO_DEPTH) @(eth_ma_wb_ack_i);  // Waiting until TX fifo is filled.
15579
          repeat(10) @(posedge mtx_clk);  // Wait some time for tx start.
15580 266 mohor
        end
15581
      join
15582
      #1 check_rx_bd(127, data);
15583
      // Checking buffer descriptor
15584
      if(PassAll)
15585
      begin
15586
        if(enable_irq_in_rxbd)
15587
        begin
15588
          if(data !== 32'h406100)    // Rx BD must not be marked as EMPTY (control frame is received)
15589
          begin
15590
            $display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
15591
            $display("RxBD = 0x%0x", data);
15592
            test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
15593
            fail = fail + 1;
15594
          end
15595
        end
15596
        else
15597
        begin
15598
          if(data !== 32'h402100)    // Rx BD must not be marked as EMPTY (control frame is received)
15599
          begin
15600
            $display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
15601
            $display("RxBD = 0x%0x", data);
15602
            test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
15603
            fail = fail + 1;
15604
          end
15605
        end
15606
      end
15607
      else
15608
      begin
15609
        if(data !== 32'he000)    // Rx BD must be marked as EMPTY (no packet received)
15610
        begin
15611
          $display("*E Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
15612
          $display("RxBD = 0x%0x", data);
15613
          test_fail("Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
15614
          fail = fail + 1;
15615
        end
15616
      end
15617
      // Checking if interrupt was generated
15618
      if (wb_int)
15619
      begin
15620
        `TIME; $display("*E WB INT signal should not be set because both RXB and RXC interrupts are masked");
15621
        test_fail("WB INT signal should not be set because both RXB and RXC interrupts are masked");
15622
        fail = fail + 1;
15623
      end
15624
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15625
      if(RxFlow)
15626
      begin
15627
        if(data !== (`ETH_INT_RXC))
15628
        begin
15629
          test_fail("RXC is not set or multiple IRQs active!");
15630
          fail = fail + 1;
15631
          `TIME; $display("*E RXC is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
15632
        end
15633
        // Clear RXC interrupt
15634
        wbm_write(`ETH_INT, `ETH_INT_RXC, 4'hF, 1, 4'h0, 4'h0);
15635
      end
15636
      else if(enable_irq_in_rxbd)
15637
      begin
15638
        if(data !== (`ETH_INT_RXB))
15639
        begin
15640
          test_fail("RXB is not set or multiple IRQs active!");
15641
          fail = fail + 1;
15642
          `TIME; $display("*E RXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
15643
        end
15644
        // Clear RXC interrupt
15645
        wbm_write(`ETH_INT, `ETH_INT_RXB, 4'hF, 1, 4'h0, 4'h0);
15646
      end
15647
      else
15648
      begin
15649
        if(data !== 0)
15650
        begin
15651
          test_fail("Some IRQs is active!");
15652
          fail = fail + 1;
15653
          `TIME; $display("*E Some IRQs is active! (ETH_INT=0x%0x)", data);
15654
        end
15655
      end
15656 267 mohor
      if(RxFlow)
15657
        begin
15658
          if(MTxEn)   // If pause frame was received OK, transmission of the data packet should not start
15659
            begin
15660
              `TIME; $display("*E Transmission should not be started because pause frame was received.");
15661
              test_fail("Transmission should not be started because pause frame was received.");
15662
              fail = fail + 1;
15663
            end
15664
          while(pause_value)
15665
            begin
15666
              pause_value=pause_value-1;
15667
              repeat(2*64) @(posedge mtx_clk);  // Wait for the time needed for the pause (1 slot).
15668
              if((!pause_value) && (!MTxEn))        // Transmission should be enabled now.
15669
                begin
15670
                  `TIME; $display("*E Transmission should be started because pause passed.");
15671
                  test_fail("Transmission should be started because pause passed.");
15672
                  fail = fail + 1;
15673
                end
15674
              else if((pause_value) && (MTxEn))     // Transmission should not be enabled now.
15675
                begin
15676
                  `TIME; $display("*E Transmission should still be paused.");
15677
                  test_fail("Transmission should still be paused.");
15678
                  fail = fail + 1;
15679
                end
15680
            end
15681
        end
15682
      else
15683
        begin
15684
          if(!MTxEn)   // Pause frame was not received because RxFlow is turned off.
15685
            begin
15686
              `TIME; $display("*E Transmission should be started because pause frame was not received (RxFlow=0).");
15687
              test_fail("Transmission should be started because pause frame was not received (RxFlow=0).");
15688
              fail = fail + 1;
15689
            end
15690
        end
15691
      wait(wb_int);   // Wait antil frame transmission is over and irq generated
15692
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15693
      if(data !== (`ETH_INT_TXB))
15694
        begin
15695
          test_fail("TXB is not set or multiple IRQs active!");
15696
          fail = fail + 1;
15697
          `TIME; $display("*E TXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
15698
        end
15699
        // Clear TXB interrupt
15700
        wbm_write(`ETH_INT, `ETH_INT_TXB, 4'hF, 1, 4'h0, 4'h0);
15701 266 mohor
    end
15702
    // End: Test is irq is set while RXB and RXC interrupts are masked.
15703
 
15704
    // Now all interrupts are unmasked. Performing tests again.
15705 263 mohor
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
15706
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15707 260 mohor
    for (i=0; i<4; i=i+1)
15708 254 mohor
    begin
15709 267 mohor
      pause_value = i+1;
15710
      set_rx_control_packet(0, pause_value);  // CRC already appended
15711 260 mohor
      // choose generating carrier sense and collision for first and last 64 lengths of frames
15712
      case (i)
15713 263 mohor
      0: // PASSALL = 0, RXFLOW = 0
15714 254 mohor
      begin
15715 263 mohor
        PassAll=0; RxFlow=0;
15716 260 mohor
        // enable interrupt generation
15717 263 mohor
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
15718
        // Set PASSALL = 0 and RXFLOW = 0
15719
        wbm_write(`ETH_CTRLMODER, 0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15720 254 mohor
      end
15721 263 mohor
      1: // PASSALL = 0, RXFLOW = 1
15722 254 mohor
      begin
15723 263 mohor
        PassAll=0; RxFlow=1;
15724 260 mohor
        // enable interrupt generation
15725 263 mohor
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
15726
        // Set PASSALL = 0 and RXFLOW = 0
15727
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15728 254 mohor
      end
15729 263 mohor
      2: // PASSALL = 1, RXFLOW = 0
15730 254 mohor
      begin
15731 263 mohor
        PassAll=1; RxFlow=0;
15732
        // enable interrupt generation
15733
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
15734
        // Set PASSALL = 0 and RXFLOW = 0
15735
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15736 254 mohor
      end
15737 263 mohor
      default: // 3: PASSALL = 1, RXFLOW = 1
15738 254 mohor
      begin
15739 263 mohor
        PassAll=1; RxFlow=1;
15740
        // enable interrupt generation
15741
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
15742
        // Set PASSALL = 1 and RXFLOW = 1
15743
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL | `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15744 254 mohor
      end
15745
      endcase
15746 263 mohor
      // not detect carrier sense in FD and no collision
15747
      eth_phy.no_carrier_sense_rx_fd_detect(0);
15748
      eth_phy.collision(0);
15749
      // set wrap bit and empty bit
15750 260 mohor
      set_rx_bd_wrap(127);
15751
      set_rx_bd_empty(127, 127);
15752 274 tadejm
      // transmit
15753 260 mohor
      fork
15754 254 mohor
        begin
15755 260 mohor
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, 64, 1'b0);
15756
          repeat(10) @(posedge mrx_clk);
15757 254 mohor
        end
15758
        begin
15759 260 mohor
          #1 check_rx_bd(127, data);
15760
          wait (MRxDV === 1'b1); // start transmit
15761 263 mohor
          #1 check_rx_bd(127, data);
15762 260 mohor
          if (data[15] !== 1)
15763
          begin
15764 263 mohor
            $display("*E Wrong buffer descriptor's ready bit read out from MAC");
15765 260 mohor
            test_fail("Wrong buffer descriptor's ready bit read out from MAC");
15766
            fail = fail + 1;
15767
          end
15768
          wait (MRxDV === 1'b0); // end transmit
15769 263 mohor
          repeat(50) @(posedge mrx_clk);  // Wait some time so frame is received and
15770
          repeat (100) @(posedge wb_clk); // status/irq is written.
15771 267 mohor
 
15772
          if(RxFlow)    // Waiting x slot times before continuing so pause is deactivated.
15773
            repeat(64 * 2 * pause_value) @(posedge mrx_clk);
15774 254 mohor
        end
15775 260 mohor
      join
15776 263 mohor
      #1 check_rx_bd(127, data);
15777
      // Checking buffer descriptor
15778
      if(PassAll)
15779 254 mohor
      begin
15780 263 mohor
        if(data !== 32'h406100)    // Rx BD must not be marked as EMPTY (control frame is received)
15781
        begin
15782
          $display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
15783
          $display("RxBD = 0x%0x", data);
15784
          test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
15785
          fail = fail + 1;
15786
        end
15787 254 mohor
      end
15788 260 mohor
      else
15789 254 mohor
      begin
15790 263 mohor
        if(data !== 32'he000)    // Rx BD must be marked as EMPTY (no packet received)
15791
        begin
15792
          $display("*E Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
15793
          $display("RxBD = 0x%0x", data);
15794
          test_fail("Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
15795
          fail = fail + 1;
15796
        end
15797 254 mohor
      end
15798 263 mohor
      // Checking if interrupt was generated
15799
      if(RxFlow || PassAll)
15800 254 mohor
      begin
15801 263 mohor
        if (!wb_int)
15802 254 mohor
        begin
15803
          `TIME; $display("*E WB INT signal should be set");
15804
          test_fail("WB INT signal should be set");
15805
          fail = fail + 1;
15806
        end
15807
      end
15808
      else
15809
      begin
15810 263 mohor
        if (wb_int)
15811 254 mohor
        begin
15812
          `TIME; $display("*E WB INT signal should not be set");
15813
          test_fail("WB INT signal should not be set");
15814
          fail = fail + 1;
15815
        end
15816
      end
15817 274 tadejm
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15818
      if(RxFlow)
15819
      begin
15820
        if(data !== (`ETH_INT_RXC))
15821
        begin
15822
          test_fail("RXC is not set or multiple IRQs active!");
15823
          fail = fail + 1;
15824
          `TIME; $display("*E RXC is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
15825
        end
15826
        // Clear RXC interrupt
15827
        wbm_write(`ETH_INT, `ETH_INT_RXC, 4'hF, 1, 4'h0, 4'h0);
15828
      end
15829
      else if(PassAll)
15830
      begin
15831
        if(data !== (`ETH_INT_RXB))
15832
        begin
15833
          test_fail("RXB is not set or multiple IRQs active!");
15834
          fail = fail + 1;
15835
          `TIME; $display("*E RXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
15836
        end
15837
        // Clear RXB interrupt
15838
        wbm_write(`ETH_INT, `ETH_INT_RXB, 4'hF, 1, 4'h0, 4'h0);
15839
      end
15840
      else
15841
      begin
15842
        if(data !== 0)
15843
        begin
15844
          test_fail("No interrupt should be set!");
15845
          fail = fail + 1;
15846
          `TIME; $display("*E No interrupt should be set! (ETH_INT=0x%0x)", data);
15847
        end
15848
      end
15849
    end
15850
    // disable RX
15851
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
15852
              `ETH_MODER_PRO | `ETH_MODER_BRO,
15853
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15854
    if(fail == 0)
15855
      test_ok;
15856
    else
15857
      fail = 0;
15858
  end
15859 263 mohor
 
15860 274 tadejm
 
15861
  ////////////////////////////////////////////////////////////////////
15862
  ////                                                            ////
15863
  ////  Receive control frames with PASSALL option turned on and  ////
15864
  ////  off. Using only one RX buffer decriptor ( 100Mbps ).      ////
15865
  ////                                                            ////
15866
  ////////////////////////////////////////////////////////////////////
15867
  if (test_num == 3) // 
15868
  begin
15869
    // TEST 3: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 100Mbps )
15870
    test_name   = "TEST 3: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 100Mbps )";
15871
    `TIME; $display("  TEST 3: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 100Mbps )");
15872
 
15873
    // unmask interrupts
15874
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
15875
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15876
    // set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
15877
    wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15878
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
15879
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
15880
              `ETH_MODER_PRO | `ETH_MODER_BRO,
15881
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15882
    // enable RX_FLOW control
15883
    wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15884
    // prepare one packet of 100 bytes long
15885
//    st_data = 8'h1A;
15886
//    set_rx_packet(64, 100, 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data); 
15887
//    append_rx_crc (64, 100, 1'b0, 1'b0); // CRC for data packet
15888
    st_data = 8'h01;
15889
    set_tx_packet(`MEMORY_BASE + 64, 100, 8'h01); // length without CRC
15890
    set_tx_bd(0, 0, 100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + 64));
15891
    set_tx_bd_wrap(0);
15892
    // check WB INT signal
15893
    if (wb_int !== 1'b0)
15894
    begin
15895
      test_fail("WB INT signal should not be set");
15896
      fail = fail + 1;
15897
    end
15898
 
15899
    // write to phy's control register for 100Mbps
15900
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
15901
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
15902
    speed = 100;
15903
 
15904
    // RXB and RXC interrupts masked
15905
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXE | `ETH_INT_BUSY |
15906
                             `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15907
    // Test irq logic while RXB and RXC interrupts are masked. IRQ in RxBD is cleared
15908
    for (i=0; i<3; i=i+1)
15909
    begin
15910
      pause_value = i+2;
15911
      set_rx_control_packet(0, pause_value);  // CRC already appended
15912
      // choose generating carrier sense and collision for first and last 64 lengths of frames
15913
      case (i)
15914
      0: // PASSALL = 0, RXFLOW = 1, IRQ in RxBD = 1
15915
      begin
15916
        PassAll=0; RxFlow=1; enable_irq_in_rxbd=1;
15917
        // enable interrupt generation
15918
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
15919
        // Set PASSALL = 0 and RXFLOW = 0
15920
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15921
      end
15922
      1: // PASSALL = 1, RXFLOW = 0, IRQ in RxBD = 1
15923
      begin
15924
        PassAll=1; RxFlow=0; enable_irq_in_rxbd=1;
15925
        // enable interrupt generation
15926
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
15927
        // Set PASSALL = 0 and RXFLOW = 0
15928
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15929
      end
15930
      2: // PASSALL = 1, RXFLOW = 0, IRQ in RxBD = 0
15931
      begin
15932
        PassAll=1; RxFlow=0; enable_irq_in_rxbd=0;
15933
        // enable interrupt generation
15934
        set_rx_bd(127, 127, 1'b0, `MEMORY_BASE);
15935
        // Set PASSALL = 0 and RXFLOW = 0
15936
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15937
      end
15938
      default:
15939
      begin
15940
        `TIME; $display("*E We should never get here !!!");
15941
        test_fail("We should never get here !!!");
15942
        fail = fail + 1;
15943
      end
15944
      endcase
15945
      // not detect carrier sense in FD and no collision
15946
      eth_phy.no_carrier_sense_rx_fd_detect(0);
15947
      eth_phy.collision(0);
15948
      // set wrap bit and empty bit
15949
      set_rx_bd_wrap(127);
15950
      set_rx_bd_empty(127, 127);
15951
      // transmit
15952
      fork
15953
        begin
15954
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, 64, 1'b0);
15955
          repeat(10) @(posedge mrx_clk);
15956
        end
15957
        begin
15958
          wait (MRxDV === 1'b1); // start transmit
15959
          #1 check_rx_bd(127, data);
15960
          if (data[15] !== 1)
15961
          begin
15962
            `TIME; $display("*E Wrong buffer descriptor's ready bit read out from MAC");
15963
            test_fail("Wrong buffer descriptor's ready bit read out from MAC");
15964
            fail = fail + 1;
15965
          end
15966
          wait (MRxDV === 1'b0); // received pause frame
15967
          repeat(5) @(posedge mrx_clk);  // Wait some time so pause is activated.
15968
          repeat(5) @(posedge mtx_clk);  // Wait some time so pause is activated.
15969
          set_tx_bd_ready(0, 0); // Request sending the data. Data should not be sent when pause frame was received
15970
                                 // and RxFlow enabled.
15971
          // When we exit the while loop, status frame is received
15972
          repeat(`ETH_TX_FIFO_DEPTH) @(eth_ma_wb_ack_i);  // Waiting until TX fifo is filled.
15973
          repeat(10) @(posedge mtx_clk);  // Wait some time for tx start.
15974
        end
15975
      join
15976
      #1 check_rx_bd(127, data);
15977
      // Checking buffer descriptor
15978
      if(PassAll)
15979
      begin
15980
        if(enable_irq_in_rxbd)
15981
        begin
15982
          if(data !== 32'h406100)    // Rx BD must not be marked as EMPTY (control frame is received)
15983
          begin
15984
            `TIME; $display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
15985
            $display("RxBD = 0x%0x", data);
15986
            test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
15987
            fail = fail + 1;
15988
          end
15989
        end
15990
        else
15991
        begin
15992
          if(data !== 32'h402100)    // Rx BD must not be marked as EMPTY (control frame is received)
15993
          begin
15994
            `TIME; $display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
15995
            $display("RxBD = 0x%0x", data);
15996
            test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
15997
            fail = fail + 1;
15998
          end
15999
        end
16000
      end
16001
      else
16002
      begin
16003
        if(data !== 32'he000)    // Rx BD must be marked as EMPTY (no packet received)
16004
        begin
16005
          `TIME; $display("*E Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
16006
          $display("RxBD = 0x%0x", data);
16007
          test_fail("Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
16008
          fail = fail + 1;
16009
        end
16010
      end
16011
      // Checking if interrupt was generated
16012
      if (wb_int)
16013
      begin
16014
        `TIME; $display("*E WB INT signal should not be set because both RXB and RXC interrupts are masked");
16015
        test_fail("WB INT signal should not be set because both RXB and RXC interrupts are masked");
16016
        fail = fail + 1;
16017
      end
16018 263 mohor
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16019
      if(RxFlow)
16020 254 mohor
      begin
16021 263 mohor
        if(data !== (`ETH_INT_RXC))
16022 254 mohor
        begin
16023 263 mohor
          test_fail("RXC is not set or multiple IRQs active!");
16024 260 mohor
          fail = fail + 1;
16025 263 mohor
          `TIME; $display("*E RXC is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
16026 254 mohor
        end
16027 263 mohor
        // Clear RXC interrupt
16028
        wbm_write(`ETH_INT, `ETH_INT_RXC, 4'hF, 1, 4'h0, 4'h0);
16029 254 mohor
      end
16030 274 tadejm
      else if(enable_irq_in_rxbd)
16031
      begin
16032
        if(data !== (`ETH_INT_RXB))
16033
        begin
16034
          test_fail("RXB is not set or multiple IRQs active!");
16035
          fail = fail + 1;
16036
          `TIME; $display("*E RXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
16037
        end
16038
        // Clear RXC interrupt
16039
        wbm_write(`ETH_INT, `ETH_INT_RXB, 4'hF, 1, 4'h0, 4'h0);
16040
      end
16041
      else
16042
      begin
16043
        if(data !== 0)
16044
        begin
16045
          test_fail("Some IRQs is active!");
16046
          fail = fail + 1;
16047
          `TIME; $display("*E Some IRQs is active! (ETH_INT=0x%0x)", data);
16048
        end
16049
      end
16050
      if(RxFlow)
16051
        begin
16052
          if(MTxEn)   // If pause frame was received OK, transmission of the data packet should not start
16053
            begin
16054
              `TIME; $display("*E Transmission should not be started because pause frame was received.");
16055
              test_fail("Transmission should not be started because pause frame was received.");
16056
              fail = fail + 1;
16057
            end
16058
          while(pause_value)
16059
            begin
16060
              pause_value=pause_value-1;
16061
              repeat(2*64) @(posedge mtx_clk);  // Wait for the time needed for the pause (1 slot).
16062
              if((!pause_value) && (!MTxEn))        // Transmission should be enabled now.
16063
                begin
16064
                  `TIME; $display("*E Transmission should be started because pause passed.");
16065
                  test_fail("Transmission should be started because pause passed.");
16066
                  fail = fail + 1;
16067
                end
16068
              else if((pause_value) && (MTxEn))     // Transmission should not be enabled now.
16069
                begin
16070
                  `TIME; $display("*E Transmission should still be paused.");
16071
                  test_fail("Transmission should still be paused.");
16072
                  fail = fail + 1;
16073
                end
16074
            end
16075
        end
16076
      else
16077
        begin
16078
          if(!MTxEn)   // Pause frame was not received because RxFlow is turned off.
16079
            begin
16080
              `TIME; $display("*E Transmission should be started because pause frame was not received (RxFlow=0).");
16081
              test_fail("Transmission should be started because pause frame was not received (RxFlow=0).");
16082
              fail = fail + 1;
16083
            end
16084
        end
16085
      wait(wb_int);   // Wait antil frame transmission is over and irq generated
16086
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16087
      if(data !== (`ETH_INT_TXB))
16088
        begin
16089
          test_fail("TXB is not set or multiple IRQs active!");
16090
          fail = fail + 1;
16091
          `TIME; $display("*E TXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
16092
        end
16093
        // Clear TXB interrupt
16094
        wbm_write(`ETH_INT, `ETH_INT_TXB, 4'hF, 1, 4'h0, 4'h0);
16095
    end
16096
    // End: Test is irq is set while RXB and RXC interrupts are masked.
16097
 
16098
    // Now all interrupts are unmasked. Performing tests again.
16099
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
16100
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16101
    for (i=0; i<4; i=i+1)
16102
    begin
16103
      pause_value = i+1;
16104
      set_rx_control_packet(0, pause_value);  // CRC already appended
16105
      // choose generating carrier sense and collision for first and last 64 lengths of frames
16106
      case (i)
16107
      0: // PASSALL = 0, RXFLOW = 0
16108
      begin
16109
        PassAll=0; RxFlow=0;
16110
        // enable interrupt generation
16111
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
16112
        // Set PASSALL = 0 and RXFLOW = 0
16113
        wbm_write(`ETH_CTRLMODER, 0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16114
      end
16115
      1: // PASSALL = 0, RXFLOW = 1
16116
      begin
16117
        PassAll=0; RxFlow=1;
16118
        // enable interrupt generation
16119
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
16120
        // Set PASSALL = 0 and RXFLOW = 0
16121
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16122
      end
16123
      2: // PASSALL = 1, RXFLOW = 0
16124
      begin
16125
        PassAll=1; RxFlow=0;
16126
        // enable interrupt generation
16127
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
16128
        // Set PASSALL = 0 and RXFLOW = 0
16129
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16130
      end
16131
      default: // 3: PASSALL = 1, RXFLOW = 1
16132
      begin
16133
        PassAll=1; RxFlow=1;
16134
        // enable interrupt generation
16135
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
16136
        // Set PASSALL = 1 and RXFLOW = 1
16137
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL | `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16138
      end
16139
      endcase
16140
      // not detect carrier sense in FD and no collision
16141
      eth_phy.no_carrier_sense_rx_fd_detect(0);
16142
      eth_phy.collision(0);
16143
      // set wrap bit and empty bit
16144
      set_rx_bd_wrap(127);
16145
      set_rx_bd_empty(127, 127);
16146
      // transmit
16147
      fork
16148
        begin
16149
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, 64, 1'b0);
16150
          repeat(10) @(posedge mrx_clk);
16151
        end
16152
        begin
16153
          #1 check_rx_bd(127, data);
16154
          wait (MRxDV === 1'b1); // start transmit
16155
          #1 check_rx_bd(127, data);
16156
          if (data[15] !== 1)
16157
          begin
16158
            $display("*E Wrong buffer descriptor's ready bit read out from MAC");
16159
            test_fail("Wrong buffer descriptor's ready bit read out from MAC");
16160
            fail = fail + 1;
16161
          end
16162
          wait (MRxDV === 1'b0); // end transmit
16163
          repeat(50) @(posedge mrx_clk);  // Wait some time so frame is received and
16164
          repeat (100) @(posedge wb_clk); // status/irq is written.
16165
 
16166
          if(RxFlow)    // Waiting x slot times before continuing so pause is deactivated.
16167
            repeat(64 * 2 * pause_value) @(posedge mrx_clk);
16168
        end
16169
      join
16170
      #1 check_rx_bd(127, data);
16171
      // Checking buffer descriptor
16172
      if(PassAll)
16173
      begin
16174
        if(data !== 32'h406100)    // Rx BD must not be marked as EMPTY (control frame is received)
16175
        begin
16176
          `TIME; $display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
16177
          $display("RxBD = 0x%0x", data);
16178
          test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
16179
          fail = fail + 1;
16180
        end
16181
      end
16182
      else
16183
      begin
16184
        if(data !== 32'he000)    // Rx BD must be marked as EMPTY (no packet received)
16185
        begin
16186
          `TIME; $display("*E Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
16187
          $display("RxBD = 0x%0x", data);
16188
          test_fail("Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
16189
          fail = fail + 1;
16190
        end
16191
      end
16192
      // Checking if interrupt was generated
16193
 
16194
      if(RxFlow | PassAll)
16195
      begin
16196
        if (!wb_int)
16197
        begin
16198
          `TIME; $display("*E WB INT signal should be set");
16199
          test_fail("WB INT signal should be set");
16200
          fail = fail + 1;
16201
        end
16202
      end
16203
      else
16204
      begin
16205
        if (wb_int)
16206
        begin
16207
          `TIME; $display("*E WB INT signal should not be set");
16208
          test_fail("WB INT signal should not be set");
16209
          fail = fail + 1;
16210
        end
16211
      end
16212
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16213
      if(RxFlow)
16214
      begin
16215
        if(data !== (`ETH_INT_RXC))
16216
        begin
16217
          test_fail("RXC is not set or multiple IRQs active!");
16218
          fail = fail + 1;
16219
          `TIME; $display("*E RXC is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
16220
        end
16221
        // Clear RXC interrupt
16222
        wbm_write(`ETH_INT, `ETH_INT_RXC, 4'hF, 1, 4'h0, 4'h0);
16223
      end
16224 263 mohor
      else if(PassAll)
16225 254 mohor
      begin
16226 263 mohor
        if(data !== (`ETH_INT_RXB))
16227 254 mohor
        begin
16228 263 mohor
          test_fail("RXB is not set or multiple IRQs active!");
16229 254 mohor
          fail = fail + 1;
16230 263 mohor
          `TIME; $display("*E RXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
16231 254 mohor
        end
16232 263 mohor
        // Clear RXB interrupt
16233
        wbm_write(`ETH_INT, `ETH_INT_RXB, 4'hF, 1, 4'h0, 4'h0);
16234 254 mohor
      end
16235
      else
16236
      begin
16237 263 mohor
        if(data !== 0)
16238 254 mohor
        begin
16239 263 mohor
          test_fail("No interrupt should be set!");
16240 254 mohor
          fail = fail + 1;
16241 263 mohor
          `TIME; $display("*E No interrupt should be set! (ETH_INT=0x%0x)", data);
16242 254 mohor
        end
16243
      end
16244
    end
16245 274 tadejm
    // disable RX
16246
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
16247
              `ETH_MODER_PRO | `ETH_MODER_BRO,
16248
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16249
    if(fail == 0)
16250
      test_ok;
16251
    else
16252
      fail = 0;
16253
  end
16254 266 mohor
 
16255 274 tadejm
 
16256
  ////////////////////////////////////////////////////////////////////
16257
  ////                                                            ////
16258
  ////  Receive control frames with PASSALL option turned on and  ////
16259
  ////  off. Using only one RX buffer decriptor ( 10Mbps ).       ////
16260
  ////                                                            ////
16261
  ////////////////////////////////////////////////////////////////////
16262
  if (test_num == 4) // 
16263
  begin
16264
    // TEST 4: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 10Mbps )
16265
    test_name   = "TEST 4: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 10Mbps )";
16266
    `TIME; $display("  TEST 4: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 10Mbps )");
16267
 
16268
    // unmask interrupts
16269
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
16270
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16271
    // set 1 TX and 1 RX buffer descriptor (8'h01) - must be set before RX enable
16272
    wbm_write(`ETH_TX_BD_NUM, 32'h01, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16273
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
16274
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
16275
              `ETH_MODER_PRO | `ETH_MODER_BRO,
16276
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16277
    // enable flow control
16278
 
16279
    wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL | `ETH_CTRLMODER_RXFLOW | `ETH_CTRLMODER_TXFLOW,
16280
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16281
    // prepare one RX and one TX packet of 100 bytes long
16282
    rx_len = 100; // length of frame without CRC
16283
    st_data = 8'h1A;
16284
    set_rx_packet(200, rx_len, 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
16285
    append_rx_crc (200, rx_len, 1'b0, 1'b0); // CRC for data packet
16286
    tx_len = 64; // length of frame without CRC
16287
    st_data = 8'h01;
16288
    set_tx_packet(`MEMORY_BASE + 64, tx_len, st_data); // length without CRC
16289
    // set TX and RX Buffer Descriptors 
16290
    tx_bd_num = 0; // tx BDs go from 0 to 0
16291
    rx_bd_num = 1; // rx BDs go from 1 to 1
16292
    // check WB INT signal
16293
    if (wb_int !== 1'b0)
16294
    begin
16295
      test_fail("WB INT signal should not be set");
16296
      fail = fail + 1;
16297
    end
16298
 
16299
    // set EQUAL mrx_clk to mtx_clk!
16300
//    eth_phy.set_mrx_equal_mtx = 1'b1;
16301 263 mohor
 
16302 274 tadejm
    // write to phy's control register for 10Mbps
16303
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
16304
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
16305
    speed = 10;
16306
 
16307
    // TXB and RXB interrupts masked
16308
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXE | `ETH_INT_RXE | `ETH_INT_BUSY | `ETH_INT_TXC | `ETH_INT_RXC,
16309
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16310
 
16311
    tmp_len = 0;
16312
    num_of_frames = 0;
16313
    num_of_rx_frames = 0;
16314
//    num_of_iter = 0;
16315
    // TX frame loop & RX frame loop work independently
16316
 
16317
 
16318
    fork
16319
      // TX frame loop
16320
      while (num_of_frames < 400)
16321
      begin
16322
        eth_phy.set_tx_mem_addr(64 + num_of_frames);
16323
        // set tx bd
16324
          // wait for WB master if it is working
16325
          @(posedge wb_clk);
16326
          while (wbm_working)
16327
          begin
16328
            @(posedge wb_clk);
16329
          end
16330
        set_tx_bd(0, 0, tx_len, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + 64));
16331
        set_tx_bd_wrap(0);
16332
        set_tx_bd_ready(0, 0);
16333
        check_tx_bd(0, data);
16334
        // check frame
16335
        i = 0;
16336
        while((i < 100) && (MTxEn === 1'b0)) // wait for start of TX frame!
16337
        begin
16338
          @(posedge mtx_clk);
16339
          i = i + 1;
16340
        end
16341
        if (MTxEn != 1'b1)
16342
        begin
16343
          `TIME; $display("*E Tx Frame %0d: MAC TX didn't start transmitting the packet", num_of_frames);
16344
          test_fail("MAC TX didn't start transmitting the packet");
16345
          fail = fail + 1;
16346
          #10000 $stop;
16347
        end
16348
 
16349
        repeat (30) @(posedge mtx_clk); // waiting some time so PHY clears the tx_len
16350
 
16351
        wait ((MTxEn === 1'b0) || (eth_phy.tx_len > (tx_len + 4))) // wait for end of TX frame
16352
        if (MTxEn != 1'b0)
16353
        begin
16354
          `TIME; $display("*E Tx Frame %0d: MAC TX didn't stop transmitting the packet", num_of_frames);
16355
          test_fail("MAC TX didn't stop transmitting the packet");
16356
          fail = fail + 1;
16357
          #10000 $stop;
16358
        end
16359
        tmp_len = eth_phy.tx_len;
16360
          // wait for WB master if it is working
16361
          @(posedge wb_clk);
16362
          while (wbm_working)
16363
          begin
16364
            @(posedge wb_clk);
16365
          end
16366
        check_tx_bd(0, data);
16367
        while (data[15] === 1)
16368
        begin
16369
            // wait for WB master if it is working
16370
            @(posedge wb_clk);
16371
            while (wbm_working)
16372
            begin
16373
              @(posedge wb_clk);
16374
            end
16375
          check_tx_bd(0, data);
16376
        end
16377
        repeat (1) @(posedge wb_clk);
16378
        // check length of a PACKET
16379
        if (tmp_len != (tx_len + 4))
16380
        begin
16381
          `TIME; $display("*E Tx Frame %0d: Wrong length of the packet out from MAC (%0d instead of %0d)", num_of_frames,
16382
                          tmp_len, (tx_len + 4));
16383
          test_fail("Wrong length of the packet out from MAC");
16384
          fail = fail + 1;
16385
        end
16386
        // check transmitted TX packet data
16387
        check_tx_packet((`MEMORY_BASE + 64), (64 + num_of_frames), (tx_len), tmp);
16388
        if (tmp > 0)
16389
        begin
16390
          `TIME; $display("*E Tx Frame %0d: Wrong data of the transmitted packet", num_of_frames);
16391
          test_fail("Wrong data of the transmitted packet");
16392
          fail = fail + 1;
16393
        end
16394
        // check transmited TX packet CRC
16395
        check_tx_crc((64 + num_of_frames), (tx_len), 1'b0, tmp); // length without CRC
16396
        if (tmp > 0)
16397
        begin
16398
          `TIME; $display("*E Tx Frame %0d: Wrong CRC of the transmitted packet", num_of_frames);
16399
          test_fail("Wrong CRC of the transmitted packet");
16400
          fail = fail + 1;
16401
        end
16402
        // check WB INT signal
16403
        if (wb_int !== 1'b0)
16404
        begin
16405
          `TIME; $display("*E Tx Frame %0d: WB INT signal should not be set", num_of_frames);
16406
          test_fail("WB INT signal should not be set");
16407
          fail = fail + 1;
16408
        end
16409
        // check TX buffer descriptor of a packet
16410
          // wait for WB master if it is working
16411
          @(posedge wb_clk);
16412
          while (wbm_working)
16413
          begin
16414
            @(posedge wb_clk);
16415
          end
16416
        check_tx_bd(0, data);
16417
        if (data[15:0] !== 16'h7800)
16418
        begin
16419
          `TIME; $display("*E Tx Frame %0d: TX buffer descriptor status is not correct: %0h", num_of_frames, data[15:0]);
16420
          test_fail("TX buffer descriptor status is not correct");
16421
          fail = fail + 1;
16422
        end
16423
        // check interrupts
16424
          // wait for WB master if it is working
16425
          @(posedge wb_clk);
16426
          while (wbm_working)
16427
          begin
16428
            @(posedge wb_clk);
16429
          end
16430
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16431
        if ((data & `ETH_INT_TXB) !== `ETH_INT_TXB)
16432
        begin
16433
          `TIME; $display("*E Tx Frame %0d: Interrupt Transmit Buffer was not set, interrupt reg: %0h", num_of_frames, data);
16434
          test_fail("Interrupt Transmit Buffer was not set");
16435
          fail = fail + 1;
16436
        end
16437
        if ((data & (~(`ETH_INT_TXB | `ETH_INT_RXB))) !== 0) // RXB might occur at the same time - not error
16438
        begin
16439
          `TIME; $display("*E Tx Frame %0d: Other interrupts (except Tx and Rx Buffer) were set, interrupt reg: %0h",
16440
                          num_of_frames, data);
16441
          test_fail("Other interrupts (except Transmit Buffer) were set");
16442
          fail = fail + 1;
16443
        end
16444
        // clear interrupts (except RXB)
16445
          // wait for WB master if it is working
16446
          @(posedge wb_clk);
16447
          while (wbm_working)
16448
          begin
16449
            @(posedge wb_clk);
16450
          end
16451
        wbm_write(`ETH_INT, (data & (~`ETH_INT_RXB)), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16452
        // check WB INT signal
16453
        if (wb_int !== 1'b0)
16454
        begin
16455
          `TIME; $display("*E Tx Frame %0d: WB INT signal should not be set", num_of_frames);
16456
          test_fail("WB INT signal should not be set");
16457
          fail = fail + 1;
16458
        end
16459
        // Displays
16460
        if (num_of_frames[2:0] == 3'b111)
16461
        begin
16462
          `TIME; $display("   ->8 frames transmitted");
16463
        end
16464
        // set length (loop variable)
16465
        num_of_frames = num_of_frames + 1;
16466
      end // TX frame loop
16467
      // RX frame loop
16468
      while (num_of_rx_frames < 400)
16469
      begin
16470
        // set rx bd
16471
          // wait for WB master if it is working
16472
          @(posedge wb_clk);
16473
          #1;
16474
          while (wbm_working)
16475
          begin
16476
            @(posedge wb_clk);
16477
            #1;
16478
          end
16479
        set_rx_bd(1, 1, 1'b1, (`MEMORY_BASE + 200 + num_of_rx_frames));
16480
        set_rx_bd_wrap(1);
16481
        set_rx_bd_empty(1, 1);
16482
        // check frame
16483
        fork
16484
          begin
16485
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 200, (rx_len + 4), 1'b0);
16486
            repeat(10) @(posedge mrx_clk);
16487
          end
16488
          begin
16489
            wait (MRxDV === 1'b1); // start receive
16490
              // wait for WB master if it is working
16491
              @(posedge wb_clk);
16492
              #1;
16493
              while (wbm_working)
16494
              begin
16495
                @(posedge wb_clk);
16496
                #1;
16497
              end
16498
            check_rx_bd(1, data);
16499
            if (data[15] !== 1)
16500
            begin
16501
              `TIME; $display("*E Rx Frame %0d: Wrong buffer descriptor's ready bit read out from MAC", num_of_rx_frames);
16502
              test_fail("Wrong buffer descriptor's ready bit read out from MAC");
16503
              fail = fail + 1;
16504
            end
16505
            wait (MRxDV === 1'b0); // end receive
16506
 
16507
            while (data[15] === 1)
16508
            begin
16509
                // wait for WB master if it is working
16510
                @(posedge wb_clk);
16511
                #1;
16512
                while (wbm_working)
16513
                begin
16514
                  @(posedge wb_clk);
16515
                  #1;
16516
                end
16517
              check_rx_bd(1, data);
16518
            end
16519
            repeat (1) @(posedge wb_clk);
16520
          end
16521
        join
16522
        // check length of a PACKET
16523
 
16524
        // Additional read because simulator was not working OK.
16525
        // wait for WB master if it is working
16526
        @(posedge wb_clk);
16527
        #1;
16528
        while (wbm_working)
16529
        begin
16530
          @(posedge wb_clk);
16531
          #1;
16532
        end
16533
        check_rx_bd(1, data);
16534
 
16535
        if (data[31:16] != (rx_len + 4))
16536
        begin
16537
          `TIME; $display("*E Rx Frame %0d: Wrong length of the packet written to MAC's register (%0d instead of %0d)",
16538
                          num_of_rx_frames, data[31:16], (rx_len + 4));
16539
          test_fail("Wrong length of the packet out from PHY");
16540
          fail = fail + 1;
16541
        end
16542
        // check received RX packet data and CRC
16543
        check_rx_packet(200, (`MEMORY_BASE + 200 + num_of_rx_frames), (rx_len + 4), 1'b0, 1'b0, tmp);
16544
        if (tmp > 0)
16545
        begin
16546
          `TIME; $display("*E Rx Frame %0d: Wrong data of the received packet", num_of_rx_frames);
16547
          test_fail("Wrong data of the received packet");
16548
          fail = fail + 1;
16549
        end
16550
        // check WB INT signal
16551
        if (wb_int !== 1'b0)
16552
        begin
16553
          `TIME; $display("*E Rx Frame %0d: WB INT signal should not be set", num_of_rx_frames);
16554
          test_fail("WB INT signal should not be set");
16555
          fail = fail + 1;
16556
        end
16557
        // check RX buffer descriptor of a packet
16558
          // wait for WB master if it is working
16559
          @(posedge wb_clk);
16560
          #1;
16561
          while (wbm_working)
16562
          begin
16563
            @(posedge wb_clk);
16564
            #1;
16565
          end
16566
        check_rx_bd(1, data);
16567
        if (data[15:0] !== 16'h6080)
16568
        begin
16569
          `TIME; $display("*E Rx Frame %0d: RX buffer descriptor status is not correct: %0h", num_of_rx_frames, data[15:0]);
16570
          test_fail("RX buffer descriptor status is not correct");
16571
          fail = fail + 1;
16572
        end
16573
        // check interrupts
16574
          // wait for WB master if it is working
16575
          @(posedge wb_clk);
16576
          #1;
16577
          while (wbm_working)
16578
          begin
16579
            @(posedge wb_clk);
16580
            #1;
16581
          end
16582
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16583
 
16584
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
16585
        begin
16586
          `TIME; $display("*E Rx Frame %0d: Interrupt Receive Buffer was not set, interrupt reg: %0h",
16587
                          num_of_rx_frames, data);
16588
          test_fail("Interrupt Receive Buffer was not set");
16589
          fail = fail + 1;
16590
        end
16591
        if ((data & (~(`ETH_INT_RXB | `ETH_INT_TXB))) !== 0) // TXB might occur at the same time - not error
16592
        begin
16593
          `TIME; $display("*E Rx Frame %0d: Other interrupts (except Rx and Tx Buffer) were set, interrupt reg: %0h",
16594
                          num_of_rx_frames, data);
16595
          test_fail("Other interrupts (except Receive Buffer) were set");
16596
          fail = fail + 1;
16597
        end
16598
        // clear interrupts (except TXB)
16599
          // wait for WB master if it is working
16600
          @(posedge wb_clk);
16601
          #1;
16602
          while (wbm_working)
16603
          begin
16604
            @(posedge wb_clk);
16605
            #1;
16606
          end
16607
        wbm_write(`ETH_INT, (data & (~`ETH_INT_TXB)), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16608
        // check WB INT signal
16609
        if (wb_int !== 1'b0)
16610
        begin
16611
          `TIME; $display("*E Rx Frame %0d: WB INT signal should not be set", num_of_rx_frames);
16612
          test_fail("WB INT signal should not be set");
16613
          fail = fail + 1;
16614
        end
16615
        // Displays
16616
        if (num_of_rx_frames[2:0] == 3'b111)
16617
        begin
16618
          `TIME; $display("   ->8 frames received");
16619
        end
16620
        // set length (loop variable)
16621
        num_of_rx_frames = num_of_rx_frames + 1;
16622
      end // RX frame loop
16623
    join
16624
    // disable TX & RX
16625
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_PAD | `ETH_MODER_CRCEN |
16626
              `ETH_MODER_IFG | `ETH_MODER_PRO | `ETH_MODER_BRO,
16627
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16628
    // set DIFFERENT mrx_clk to mtx_clk!
16629
//    eth_phy.set_mrx_equal_mtx = 1'b0;
16630
    if(fail == 0)
16631
      test_ok;
16632
    else
16633
      fail = 0;
16634
  end
16635
 
16636
end   //  for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
16637
 
16638
end
16639
endtask // test_mac_full_duplex_flow_control
16640
 
16641
 
16642
task test_mac_half_duplex_flow;
16643
  input  [31:0]  start_task;
16644
  input  [31:0]  end_task;
16645
  integer        bit_start_1;
16646
  integer        bit_end_1;
16647
  integer        bit_start_2;
16648
  integer        bit_end_2;
16649
  integer        num_of_reg;
16650
  integer        num_of_frames;
16651
  integer        num_of_bd;
16652
  integer        num_of_iter;
16653
  integer        i_addr;
16654
  integer        i_data;
16655
  integer        i_length;
16656
  integer        tmp_len;
16657
  integer        tmp_bd;
16658
  integer        tmp_bd_num;
16659
  integer        tmp_data;
16660
  integer        tmp_ipgt;
16661
  integer        test_num;
16662
  reg    [31:0]  tx_bd_num;
16663
  reg    [31:0]  rx_bd_num;
16664
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
16665
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
16666
  integer        i;
16667
  integer        i1;
16668
  integer        i2;
16669
  integer        i3;
16670
  integer        fail;
16671
  integer        speed;
16672
  integer        mac_hi_addr;
16673
  integer        mac_lo_addr;
16674
  reg            frame_started;
16675
  reg            frame_ended;
16676
  reg            check_rx_frame;
16677
  reg            wait_for_tx_frame;
16678
  reg    [31:0]  addr;
16679
  reg    [31:0]  data;
16680
  reg    [31:0]  tmp;
16681
  reg    [ 7:0]  st_data;
16682
  reg    [15:0]  max_tmp;
16683
  reg    [15:0]  min_tmp;
16684
begin
16685
// MAC HALF DUPLEX FLOW TEST
16686
test_heading("MAC HALF DUPLEX FLOW TEST");
16687
$display(" ");
16688
$display("MAC HALF DUPLEX FLOW TEST");
16689
fail = 0;
16690
 
16691
// reset MAC registers
16692
hard_reset;
16693
// reset MAC and MII LOGIC with soft reset
16694
//reset_mac;
16695
//reset_mii;
16696
// set wb slave response
16697
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
16698
 
16699
  /*
16700
  TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
16701
  -------------------------------------------------------------------------------------
16702
  set_tx_bd
16703
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0], len[15:0], irq, pad, crc, txpnt[31:0]);
16704
  set_tx_bd_wrap
16705
    (tx_bd_num_end[6:0]);
16706
  set_tx_bd_ready
16707
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
16708
  check_tx_bd
16709
    (tx_bd_num_start[6:0], tx_bd_status[31:0]);
16710
  clear_tx_bd
16711
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
16712
 
16713
  TASKS for set and control RX buffer descriptors:
16714
  ------------------------------------------------
16715
  set_rx_bd
16716
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0], irq, rxpnt[31:0]);
16717
  set_rx_bd_wrap
16718
    (rx_bd_num_end[6:0]);
16719
  set_rx_bd_empty
16720
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
16721
  check_rx_bd
16722
    (rx_bd_num_end[6:0], rx_bd_status);
16723
  clear_rx_bd
16724
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
16725
 
16726
  TASKS for set and check TX packets:
16727
  -----------------------------------
16728
  set_tx_packet
16729
    (txpnt[31:0], len[15:0], eth_start_data[7:0]);
16730
  check_tx_packet
16731
    (txpnt_wb[31:0], txpnt_phy[31:0], len[15:0], failure[31:0]);
16732
 
16733
  TASKS for set and check RX packets:
16734
  -----------------------------------
16735
  set_rx_packet
16736
    (rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
16737
  check_rx_packet
16738
    (rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
16739
 
16740
  TASKS for append and check CRC to/of TX packet:
16741
  -----------------------------------------------
16742
  append_tx_crc
16743
    (txpnt_wb[31:0], len[15:0], negated_crc);
16744
  check_tx_crc
16745
    (txpnt_phy[31:0], len[15:0], negated_crc, failure[31:0]);
16746
 
16747
  TASK for append CRC to RX packet (CRC is checked together with check_rx_packet):
16748
  --------------------------------------------------------------------------------
16749
  append_rx_crc
16750
    (rxpnt_phy[31:0], len[15:0], plus_nibble, negated_crc);
16751
  */
16752
 
16753
//////////////////////////////////////////////////////////////////////
16754
////                                                              ////
16755
////  test_mac_half_duplex_flow:                                  ////
16756
////                                                              ////
16757
////  0: Test                                                     ////
16758
////                                                              ////
16759
//////////////////////////////////////////////////////////////////////
16760
 
16761
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
16762
begin
16763
 
16764
  ////////////////////////////////////////////////////////////////////
16765
  ////                                                            ////
16766
  ////  Test collision and late collision while transmitting and  ////
16767
  ////  receiving normal frames. Using 4 TX and RX buffer         ////
16768
  ////  decriptors ( 10Mbps ).                                    ////
16769
  ////                                                            ////
16770
  ////////////////////////////////////////////////////////////////////
16771
  if (test_num == 0) // 
16772
  begin
16773
    // TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )
16774
    //         
16775
    test_name = "TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )";
16776
    `TIME; $display("  TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )");
16777
 
16778
    // reset MAC completely
16779
    hard_reset;
16780
    // set wb slave response
16781
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
16782
 
16783
    max_tmp = 0;
16784
    min_tmp = 0;
16785
    // set 4 TX buffer descriptors (4 TX and 4 RX BDs will be used) - must be set before TX/RX enable
16786
    wait (wbm_working == 0);
16787
    wbm_write(`ETH_TX_BD_NUM, 32'h4, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16788
    // enable TX and RX, set half-duplex mode, receive small, NO correct IFG
16789
    wait (wbm_working == 0);
16790
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_RXEN | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
16791
              `ETH_MODER_PRO | `ETH_MODER_BRO,
16792
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16793
    // prepare two packets of MAXFL length for TX and RX
16794
    wait (wbm_working == 0);
16795
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16796
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
16797
    min_tmp = tmp[31:16];
16798
    st_data = 8'h17;
16799
    set_rx_packet(0, (min_tmp), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
16800
    append_rx_crc (0, (min_tmp), 1'b0, 1'b0);
16801
    st_data = 8'h92;
16802
    set_tx_packet(`MEMORY_BASE, (min_tmp), st_data); // length without CRC
16803
    append_tx_crc (`MEMORY_BASE, (min_tmp), 1'b0);
16804
 
16805
    // check WB INT signal
16806
    if (wb_int !== 1'b0)
16807
    begin
16808
      test_fail("WB INT signal should not be set");
16809
      fail = fail + 1;
16810
    end
16811
    // unmask interrupts
16812
    wait (wbm_working == 0);
16813
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
16814
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16815
 
16816
    // write to phy's control register for 10Mbps
16817
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
16818
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
16819
    speed = 10;
16820
 
16821
    // set TX and RX Buffer Descriptors 
16822
    tx_bd_num = 0; // tx BDs go from 0 to 3
16823
    rx_bd_num = 4; // rx BDs go from 4 to 7
16824
    set_tx_bd(0, 3, i_length[15:0], 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
16825
    set_tx_bd_wrap(3);
16826
    set_rx_bd(4, 7, 1'b1, `MEMORY_BASE);
16827
    set_rx_bd_wrap(7);
16828
    set_rx_bd_empty(4, 7);
16829
 
16830
//    frame_ended = 0;
16831
    tmp_len = 0;
16832
    num_of_frames = 0;// 0; // 10;
16833
    num_of_iter = 0;
16834
//    num_of_bd = 0;
16835
//    i_length = 0;// (0 - 4); // 6; // 4 less due to CRC
16836
    while (num_of_frames < 80)
16837
    begin
16838
      // change COLLVALID bits in COLLCONF register
16839
      if ((num_of_frames == 0) && (num_of_iter == 0))
16840
      begin
16841
        wait (wbm_working == 0);
16842
        wbm_read(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16843
        tmp[5:0] = 6'h00; // 6'b00_0000 ->  0 + 1 =  1 byte from preamble
16844
        wait (wbm_working == 0);
16845
        wbm_write(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16846
        $display("    Collision window is set to 1 byte after preamble and SFD");
16847
      end
16848
      else if ((num_of_frames == 0) && (num_of_iter == 1))
16849
      begin
16850
        wait (wbm_working == 0);
16851
        wbm_read(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16852
        tmp[5:0] = 6'h15; // 6'b01_0101 -> 21 + 1 = 22 bytes from preamble
16853
        wait (wbm_working == 0);
16854
        wbm_write(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16855
        $display("    Collision window is set to 22 bytes after preamble and SFD");
16856
      end
16857
      else if ((num_of_frames == 0) && (num_of_iter == 2))
16858
      begin
16859
        wait (wbm_working == 0);
16860
        wbm_read(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16861
        tmp[5:0] = 6'h2A; // 6'b10_1010 -> 42 + 1 = 43 bytes from preamble
16862
        wait (wbm_working == 0);
16863
        wbm_write(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16864
        $display("    Collision window is set to 43 bytes after preamble and SFD");
16865
      end
16866
      else if ((num_of_frames == 0) && (num_of_iter == 3))
16867
      begin
16868
        wait (wbm_working == 0);
16869
        wbm_read(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16870
        tmp[5:0] = 6'h3F; // 6'b11_1111 -> 63 + 1 = 64 bytes from preamble
16871
        wait (wbm_working == 0);
16872
        wbm_write(`ETH_COLLCONF, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16873
        $display("    Collision window is set to 64 bytes after preamble and SFD");
16874
      end
16875
 
16876
 
16877
//wire          MRxDV;    // This goes to PHY
16878
//wire          MRxErr;   // This goes to PHY
16879
//wire          MColl;    // This goes to PHY
16880
//wire          MCrs;     // This goes to PHY
16881
//wire          MTxEn;
16882
//wire          MTxErr;
16883
      // CHECK END OF RECEIVE WHILE TRANSMITTING
16884
      frame_ended = 0;
16885
      check_rx_frame = 0;
16886
      fork
16887
        // send frames
16888
        begin // start with RX frame
16889
          repeat(num_of_frames) @(posedge mrx_clk);
16890
          #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (min_tmp + 4), 1'b0);
16891
          repeat(10) @(posedge mrx_clk);
16892
        end
16893
        begin // start with TX frame 
16894
          repeat(2) @(posedge mrx_clk);
16895
          repeat(2) @(posedge wb_clk);
16896
          #1 set_tx_bd_ready(tx_bd_num, tx_bd_num);
16897
        end
16898
        // observe TX Enable, Carrier Sense and Collision - TX frame is not repeated after Late Collision
16899
        begin
16900
          wait (MCrs || MTxEn);
16901
          #1;
16902
          if ((MCrs == 1'b1) && (MTxEn == 1'b0)) // defer TX due to Carrier Sense
16903
            wait_for_tx_frame = 1'b1; // wait for retransmission of TX frame
16904
          else
16905
          begin
16906
            i = 0;
16907
            while (MColl == 1'b0) // wait for Collision to occure
16908
            begin
16909
              repeat(2) @(posedge mtx_clk); // counting bytes
16910
              #1 i = i + 1'b1;
16911
            end
16912
            i = i - 8; // subtract preamble and SFD (bytes) - Late Collision is measured from SFD!
16913
            tmp_len = eth_phy.tx_len; // without preamble and SFD (bytes)
16914
            //wait (MTxEn == 1'b0); // wait for TX frame to end
16915
            repeat(10) @(posedge mrx_clk);
16916
            repeat(8) @(posedge wb_clk);
16917
            #1 check_tx_bd(tx_bd_num, data);
16918
            if (data[15] === 0) // if transmit is aborted, then it was Late Collision
16919
            begin
16920
              wait_for_tx_frame = 1'b0; // don't wait for retransmission of TX frame
16921
              $display("    ->Late Collision occured on %0d. byte after frame and SFD", i);
16922
            end
16923
            else
16924
              wait_for_tx_frame = 1'b1; // wait for retransmission of TX frame
16925
          end
16926
        end
16927
        // check if RX frame is accepted
16928
        begin
16929
          wait (MRxDV === 1'b1); // start receive
16930
          wait (MRxDV === 1'b0); // end receive
16931
          repeat(10) @(posedge mrx_clk);
16932
          repeat(8) @(posedge wb_clk);
16933
          #1 check_rx_bd(rx_bd_num, data);
16934
          if (data[15] === 0)
16935
          begin
16936
            check_rx_frame = 1'b1; // RX frame accepted and must be checked
16937
            if ((i + 8) == 0) // add preamble and SFD length (bytes)
16938
              $display("    ->RX frame, which started before or at beginning of TX frame, was accepted");
16939
            else
16940
              $display("    ->RX frame, which started %0d byte(s) after beginning of TX frame, was accepted", (i + 8));
16941
          end
16942
          else
16943
            check_rx_frame = 1'b0; // RX frame rejected
16944
          repeat(1) @(posedge wb_clk);
16945
        end
16946
      join
16947
 
16948
 
16949
 
16950
      // check length of a PACKET
16951
      if ( ((data[31:16] != (i_length + 4)) && (num_of_frames >= 3)) ||
16952
           ((data[31:16] != 0) && (num_of_frames < 3)) )
16953
      begin
16954
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
16955
                        data[31:16], (i_length + 4));
16956
        test_fail("Wrong length of the packet out from PHY");
16957
        fail = fail + 1;
16958
      end
16959
      // check received RX packet data and CRC
16960
//if ((num_of_frames == 5))
16961
//begin                                           // CRC has 4 bytes for itself
16962
//  if (i_length[0] == 1'b1)
16963
//  begin
16964
//    check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
16965
//  end
16966
//  else
16967
//  begin
16968
//    check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
16969
//  end
16970
//  if (tmp > 0)
16971
//  begin
16972
//    `TIME; $display("*E Wrong data of the received packet");
16973
//    test_fail("Wrong data of the received packet");
16974
//    fail = fail + 1;
16975
//  end
16976
//end
16977
//else
16978
//if ((num_of_frames == 10))
16979
//begin                                           // CRC has 4 bytes for itself
16980
//  if (i_length[0] == 1'b1)
16981
//  begin
16982
//    check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
16983
//  end
16984
//  else
16985
//  begin
16986
//    check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
16987
//  end
16988
//  if (tmp > 0)
16989
//  begin
16990
//    `TIME; $display("*E Wrong data of the received packet");
16991
//    test_fail("Wrong data of the received packet");
16992
//    fail = fail + 1;
16993
//  end
16994
//end
16995
//else
16996
      if ((frame_ended == 1) && (num_of_frames >= 5)) // 5 bytes is minimum size without CRC error, since
16997
      begin                                           // CRC has 4 bytes for itself
16998
        if (i_length[0] == 1'b0)
16999
        begin
17000
          check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
17001
        end
17002
        else
17003
        begin
17004
          check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
17005
        end
17006
        if (tmp > 0)
17007
        begin
17008
          `TIME; $display("*E Wrong data of the received packet");
17009
          test_fail("Wrong data of the received packet");
17010
          fail = fail + 1;
17011
        end
17012
      end
17013
 
17014
      // check WB INT signal
17015
      if (num_of_frames >= 3) // Frames smaller than 3 are not received.
17016
      begin                   // Frames greater then 5 always cause an interrupt (Frame received)
17017
        if (wb_int !== 1'b1)  // Frames with length 3 or 4 always cause an interrupt (CRC error)
17018
        begin
17019
          `TIME; $display("*E WB INT signal should be set");
17020
          test_fail("WB INT signal should be set");
17021
          fail = fail + 1;
17022
        end
17023
      end
17024
      else
17025
      begin
17026
        if (wb_int !== 1'b0)
17027
        begin
17028
          `TIME; $display("*E WB INT signal should not be set");
17029
          test_fail("WB INT signal should not be set");
17030
          fail = fail + 1;
17031
        end
17032
      end
17033
 
17034
      // check RX buffer descriptor of a packet
17035
      if (num_of_frames >= min_tmp)
17036
      begin
17037
        if ( (data[15:0] !== 16'h6000) && // wrap bit
17038
             (data[15:0] !== 16'h4000) ) // without wrap bit
17039
        begin
17040
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
17041
          test_fail("RX buffer descriptor status is not correct");
17042
          fail = fail + 1;
17043
        end
17044
      end
17045
      else if (num_of_frames > 4)
17046
      begin
17047
        if ( (data[15:0] !== 16'h6004) && // wrap bit
17048
             (data[15:0] !== 16'h4004) ) // without wrap bit
17049
        begin
17050
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
17051
          test_fail("RX buffer descriptor status is not correct");
17052
          fail = fail + 1;
17053
        end
17054
      end
17055
      else if (num_of_frames > 2)
17056
      begin
17057
        if ( (data[15:0] !== 16'h6006) && // wrap bit
17058
             (data[15:0] !== 16'h4006) ) // without wrap bit
17059
        begin
17060
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
17061
          test_fail("RX buffer descriptor status is not correct");
17062
          fail = fail + 1;
17063
        end
17064
      end
17065
      else
17066
      begin
17067
        if (data[15] !== 1'b1)
17068
        begin
17069
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
17070
          test_fail("RX buffer descriptor status is not correct");
17071
          fail = fail + 1;
17072
        end
17073
      end
17074
      // check interrupts
17075
      wait (wbm_working == 0);
17076
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17077
      if (num_of_frames >= 5)
17078
      begin
17079
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
17080
        begin
17081
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
17082
          test_fail("Interrupt Receive Buffer was not set");
17083
          fail = fail + 1;
17084
        end
17085
        if ((data & (~`ETH_INT_RXB)) !== 0)
17086
        begin
17087
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
17088
          test_fail("Other interrupts (except Receive Buffer) were set");
17089
          fail = fail + 1;
17090
        end
17091
      end
17092
      else if ((num_of_frames < 3)) // Frames smaller than 3 are not received.
17093
      begin
17094
        if (data) // Checking if any interrupt is pending)
17095
        begin
17096
          `TIME; $display("*E Interrupt(s) is(are) pending although frame was ignored, interrupt reg: %0h", data);
17097
          test_fail("Interrupts were set");
17098
          fail = fail + 1;
17099
        end
17100
      end
17101
      else
17102
      begin
17103
        if ((data & `ETH_INT_RXE) !== `ETH_INT_RXE)
17104
        begin
17105
          `TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
17106
          test_fail("Interrupt Receive Buffer Error was not set");
17107
          fail = fail + 1;
17108
        end
17109
        if ((data & (~`ETH_INT_RXE)) !== 0)
17110
        begin
17111
          `TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
17112
          test_fail("Other interrupts (except Receive Buffer Error) were set");
17113
          fail = fail + 1;
17114
        end
17115
      end
17116
      // clear interrupts
17117
      wait (wbm_working == 0);
17118
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17119
      // check WB INT signal
17120
      if (wb_int !== 1'b0)
17121
      begin
17122
        test_fail("WB INT signal should not be set");
17123
        fail = fail + 1;
17124
      end
17125
      // INTERMEDIATE DISPLAYS
17126
      if (num_of_frames == 3)
17127
      begin
17128
        $display("    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
17129
        $display("    ->packets with lengths from %0d to %0d are not received (length increasing by 1 byte)",
17130
                 0, 3);
17131
      end
17132
      else if (num_of_frames == 9)
17133
      begin
17134
        $display("    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
17135
        $display("    ->packet with length 4 is not received (length increasing by 1 byte)");
17136
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
17137
                 5, 9);
17138
      end
17139
      else if (num_of_frames == 17)
17140
      begin
17141
        $display("    using 4 BDs out of 8 BDs (120..127) assigned to RX (wrap at 4th BD - RX BD 123)");
17142
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
17143
                 10, 17);
17144
      end
17145
      else if (num_of_frames == 27)
17146
      begin
17147
        $display("    using 5 BDs out of 8 BDs (120..127) assigned to RX (wrap at 5th BD - RX BD 124)");
17148
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
17149
                 18, 27);
17150
      end
17151
      else if (num_of_frames == 40)
17152
      begin
17153
        $display("    using 6 BDs out of 8 BDs (120..127) assigned to RX (wrap at 6th BD - RX BD 125)");
17154
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
17155
                 28, 40);
17156
      end
17157
      else if (num_of_frames == 54)
17158
      begin
17159
        $display("    using 7 BDs out of 8 BDs (120..127) assigned to RX (wrap at 7th BD - RX BD 126)");
17160
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
17161
                 41, 54);
17162
      end
17163
      else if (num_of_frames == 69)
17164
      begin
17165
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
17166
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
17167
                 55, 69);
17168
      end
17169
      else if (num_of_frames == 69)
17170
      begin
17171
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
17172
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
17173
                 55, 69);
17174
      end
17175
      else if (num_of_frames == 77)
17176
      begin
17177
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
17178
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
17179
                 70, 77);
17180
      end
17181
      // set length (loop variable)
17182
      i_length = i_length + 1;
17183
      // the number of frame transmitted
17184
      num_of_frames = num_of_frames + 1;
17185
      if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
17186
          (num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
17187
          (num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
17188
          (num_of_frames == 54) || (num_of_frames == 62) || (num_of_frames == 70))
17189
        num_of_bd = 120;
17190
      else
17191
        num_of_bd = num_of_bd + 1;
17192
    end
17193 260 mohor
    // disable RX
17194 274 tadejm
    wait (wbm_working == 0);
17195
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
17196
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17197
    @(posedge wb_clk);
17198
    if(fail == 0)
17199
      test_ok;
17200
    else
17201
      fail = 0;
17202
  end
17203
 
17204
 
17205
  ////////////////////////////////////////////////////////////////////
17206
  ////                                                            ////
17207
  ////  Receive control frames with PASSALL option turned off     ////
17208
  ////  Using only one RX buffer decriptor ( 10Mbps ).            ////
17209
  ////                                                            ////
17210
  ////////////////////////////////////////////////////////////////////
17211
  if (test_num == 1) // 
17212
  begin
17213
    // TEST 1: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps )
17214
    test_name   = "TEST 1: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps )";
17215
    `TIME; $display("  TEST 1: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps )");
17216
 
17217
    // unmask interrupts
17218
    wait (wbm_working == 0);
17219
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
17220
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17221
    // set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
17222
    wait (wbm_working == 0);
17223
    wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17224
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
17225
    wait (wbm_working == 0);
17226
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
17227
              `ETH_MODER_PRO | `ETH_MODER_BRO,
17228
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17229
    // prepare one control (PAUSE)packet
17230
    st_data = 8'h00;
17231
    set_rx_packet(0, 60, 1'b0, 48'h0180_c200_0001, 48'h0708_090A_0B0C, 16'h8808, st_data); // length without CRC
17232
    // prepare one packet of 100 bytes long
17233
    st_data = 8'h1A;
17234
    set_rx_packet(64, 100, 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
17235
    // check WB INT signal
17236
    if (wb_int !== 1'b0)
17237
    begin
17238
      test_fail("WB INT signal should not be set");
17239
      fail = fail + 1;
17240
    end
17241
 
17242
    // write to phy's control register for 10Mbps
17243
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
17244
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
17245
    speed = 10;
17246
 
17247
    for (i=0; i<4; i=i+1)
17248
    begin
17249
      // choose generating carrier sense and collision for first and last 64 lengths of frames
17250
      case (i)
17251
      0: // Interrupt is generated
17252
      begin
17253
        // enable interrupt generation
17254
        set_rx_bd(127, 127, 1'b1, (`MEMORY_BASE + i));
17255
        // unmask interrupts
17256
        wait (wbm_working == 0);
17257
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
17258
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17259
        // not detect carrier sense in FD and no collision
17260
        eth_phy.no_carrier_sense_rx_fd_detect(0);
17261
        eth_phy.collision(0);
17262
      end
17263
      1: // Interrupt is not generated
17264
      begin
17265
        // enable interrupt generation
17266
        set_rx_bd(127, 127, 1'b1, ((`MEMORY_BASE + i) + 64));
17267
        // mask interrupts
17268
        wait (wbm_working == 0);
17269
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17270
        // detect carrier sense in FD and no collision
17271
        eth_phy.no_carrier_sense_rx_fd_detect(1);
17272
        eth_phy.collision(0);
17273
      end
17274
      2: // Interrupt is not generated
17275
      begin
17276
        // disable interrupt generation
17277
        set_rx_bd(127, 127, 1'b0, (`MEMORY_BASE + i));
17278
        // unmask interrupts
17279
        wait (wbm_working == 0);
17280
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
17281
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17282
        // not detect carrier sense in FD and set collision
17283
        eth_phy.no_carrier_sense_rx_fd_detect(0);
17284
        eth_phy.collision(1);
17285
      end
17286
      default: // 3: // Interrupt is not generated
17287
      begin
17288
        // disable interrupt generation
17289
        set_rx_bd(127, 127, 1'b0, ((`MEMORY_BASE + i) + 64));
17290
        // mask interrupts
17291
        wait (wbm_working == 0);
17292
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17293
        // detect carrier sense in FD and set collision
17294
        eth_phy.no_carrier_sense_rx_fd_detect(1);
17295
        eth_phy.collision(1);
17296
      end
17297
      endcase
17298
 
17299
      append_rx_crc (64, 100, 1'b0, 1'b0); // To the second (data) packet
17300
      // set wrap bit
17301
      set_rx_bd_wrap(127);
17302
      set_rx_bd_empty(127, 127);
17303
      fork
17304
        begin
17305
          if (i[0] == 1'b0)
17306
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, 64, 1'b0);
17307
          else
17308
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 64, 104, 1'b0);
17309
          repeat(10) @(posedge mrx_clk);
17310
$display("1111");
17311
        end
17312
        begin
17313
          #1 check_rx_bd(127, data);
17314
$display("aaaa");
17315
          wait (MRxDV === 1'b1); // start transmit
17316
$display("bbbb");
17317
          #1 check_rx_bd(127, data);
17318
          if (data[15] !== 1)
17319
          begin
17320
            test_fail("Wrong buffer descriptor's ready bit read out from MAC");
17321
            fail = fail + 1;
17322
          end
17323
          wait (MRxDV === 1'b0); // end transmit
17324
$display("cccc");
17325
          while (data[15] === 1)
17326
          begin
17327
            #1 check_rx_bd(127, data);
17328
            @(posedge wb_clk);
17329
          end
17330
          repeat (1) @(posedge wb_clk);
17331
$display("2222");
17332
        end
17333
      join
17334
$display("dddd");
17335
      // check length of a PACKET
17336
      if (data[31:16] != (i_length + 4))
17337
      begin
17338
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
17339
                        data[31:16], (i_length + 4));
17340
        test_fail("Wrong length of the packet out from PHY");
17341
        fail = fail + 1;
17342
      end
17343
      // checking in the following if statement is performed only for first and last 64 lengths
17344
      // check received RX packet data and CRC
17345
      if (i_length[0] == 1'b0)
17346
      begin
17347
        check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
17348
      end
17349
      else
17350
      begin
17351
        check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
17352
      end
17353
      if (tmp > 0)
17354
      begin
17355
        `TIME; $display("*E Wrong data of the received packet");
17356
        test_fail("Wrong data of the received packet");
17357
        fail = fail + 1;
17358
      end
17359
      // check WB INT signal
17360
      if (i_length[1:0] == 2'h0)
17361
      begin
17362
        if (wb_int !== 1'b1)
17363
        begin
17364
          `TIME; $display("*E WB INT signal should be set");
17365
          test_fail("WB INT signal should be set");
17366
          fail = fail + 1;
17367
        end
17368
      end
17369
      else
17370
      begin
17371
        if (wb_int !== 1'b0)
17372
        begin
17373
          `TIME; $display("*E WB INT signal should not be set");
17374
          test_fail("WB INT signal should not be set");
17375
          fail = fail + 1;
17376
        end
17377
      end
17378
      // check RX buffer descriptor of a packet
17379
      check_rx_bd(127, data);
17380
      if (i_length[1] == 1'b0) // interrupt enabled no_carrier_sense_rx_fd_detect
17381
      begin
17382
        if ( ((data[15:0] !== 16'h6000) && (i_length[0] == 1'b0)) ||
17383
             ((data[15:0] !== 16'h6000) && (i_length[0] == 1'b1)) )
17384
        begin
17385
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
17386
          test_fail("RX buffer descriptor status is not correct");
17387
          fail = fail + 1;
17388
        end
17389
      end
17390
      else // interrupt not enabled
17391
      begin
17392
        if ( ((data[15:0] !== 16'h2000) && (i_length[0] == 1'b0)) ||
17393
             ((data[15:0] !== 16'h2000) && (i_length[0] == 1'b1)) )
17394
        begin
17395
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
17396
          test_fail("RX buffer descriptor status is not correct");
17397
          fail = fail + 1;
17398
        end
17399
      end
17400
      // clear RX buffer descriptor for first 4 frames
17401
      if (i_length < min_tmp)
17402
        clear_rx_bd(127, 127);
17403
      // check interrupts
17404
      wait (wbm_working == 0);
17405
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17406
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
17407
      begin
17408
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
17409
        begin
17410
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
17411
          test_fail("Interrupt Receive Buffer was not set");
17412
          fail = fail + 1;
17413
        end
17414
        if ((data & (~`ETH_INT_RXB)) !== 0)
17415
        begin
17416
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
17417
          test_fail("Other interrupts (except Receive Buffer) were set");
17418
          fail = fail + 1;
17419
        end
17420
      end
17421
      else
17422
      begin
17423
        if (data !== 0)
17424
        begin
17425
          `TIME; $display("*E Any of interrupts (except Receive Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
17426
          test_fail("Any of interrupts (except Receive Buffer) was set");
17427
          fail = fail + 1;
17428
        end
17429
      end
17430
      // clear interrupts
17431
      wait (wbm_working == 0);
17432
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17433
      // check WB INT signal
17434
      if (wb_int !== 1'b0)
17435
      begin
17436
        test_fail("WB INT signal should not be set");
17437
        fail = fail + 1;
17438
      end
17439
      // INTERMEDIATE DISPLAYS
17440
      if ((i_length + 4) == (min_tmp + 64))
17441
      begin
17442
        // starting length is min_tmp, ending length is (min_tmp + 64)
17443
        $display("    receive small packets is NOT selected");
17444
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
17445
                 min_tmp, (min_tmp + 64));
17446
        // set receive small, remain the rest
17447
        wait (wbm_working == 0);
17448
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
17449
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
17450
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17451
      end
17452
      else if ((i_length + 4) == (max_tmp - 16))
17453
      begin
17454
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
17455
        $display("    receive small packets is selected");
17456
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
17457
                 (min_tmp + 64 + 128), tmp_data);
17458
        // reset receive small, remain the rest
17459
        wait (wbm_working == 0);
17460
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
17461
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
17462
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17463
      end
17464
      else if ((i_length + 4) == max_tmp)
17465
      begin
17466
        $display("    receive small packets is NOT selected");
17467
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
17468
                 (max_tmp - (4 + 16)), max_tmp);
17469
      end
17470
      // set length (loop variable)
17471
      if ((i_length + 4) < (min_tmp + 64))
17472
        i_length = i_length + 1;
17473
      else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
17474
      begin
17475
        i_length = i_length + 128;
17476
        tmp_data = i_length + 4; // last tmp_data is ending length
17477
      end
17478
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
17479
        i_length = max_tmp - (4 + 16);
17480
      else if ((i_length + 4) >= (max_tmp - 16))
17481
        i_length = i_length + 1;
17482
      else
17483
      begin
17484
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
17485
        #10 $stop;
17486
      end
17487
    end
17488
    // disable RX
17489
    wait (wbm_working == 0);
17490 260 mohor
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
17491
              `ETH_MODER_PRO | `ETH_MODER_BRO,
17492 254 mohor
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17493
    if(fail == 0)
17494
      test_ok;
17495
    else
17496
      fail = 0;
17497 209 tadejm
  end
17498
 
17499
 
17500
end   //  for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
17501
 
17502 260 mohor
 
17503 209 tadejm
end
17504 274 tadejm
endtask // test_mac_half_duplex_flow
17505 209 tadejm
 
17506
 
17507 169 mohor
//////////////////////////////////////////////////////////////
17508
// WB Behavioral Models Basic tasks
17509
//////////////////////////////////////////////////////////////
17510
 
17511
task wbm_write;
17512
  input  [31:0] address_i;
17513
  input  [((`MAX_BLK_SIZE * 32) - 1):0] data_i;
17514
  input  [3:0]  sel_i;
17515
  input  [31:0] size_i;
17516
  input  [3:0]  init_waits_i;
17517
  input  [3:0]  subseq_waits_i;
17518
 
17519
  reg `WRITE_STIM_TYPE write_data;
17520
  reg `WB_TRANSFER_FLAGS flags;
17521
  reg `WRITE_RETURN_TYPE write_status;
17522
  integer i;
17523
begin
17524 274 tadejm
  wbm_working = 1;
17525
 
17526 169 mohor
  write_status = 0;
17527
 
17528
  flags                    = 0;
17529
  flags`WB_TRANSFER_SIZE   = size_i;
17530
  flags`INIT_WAITS         = init_waits_i;
17531
  flags`SUBSEQ_WAITS       = subseq_waits_i;
17532
 
17533
  write_data               = 0;
17534
  write_data`WRITE_DATA    = data_i[31:0];
17535
  write_data`WRITE_ADDRESS = address_i;
17536
  write_data`WRITE_SEL     = sel_i;
17537
 
17538
  for (i = 0; i < size_i; i = i + 1)
17539
  begin
17540
    wb_master.blk_write_data[i] = write_data;
17541
    data_i                      = data_i >> 32;
17542
    write_data`WRITE_DATA       = data_i[31:0];
17543
    write_data`WRITE_ADDRESS    = write_data`WRITE_ADDRESS + 4;
17544 116 mohor
  end
17545
 
17546 169 mohor
  wb_master.wb_block_write(flags, write_status);
17547 116 mohor
 
17548 169 mohor
  if (write_status`CYC_ACTUAL_TRANSFER !== size_i)
17549
  begin
17550
    `TIME;
17551
    $display("*E WISHBONE Master was unable to complete the requested write operation to MAC!");
17552
  end
17553 274 tadejm
 
17554
  @(posedge wb_clk);
17555
  #3;
17556
  wbm_working = 0;
17557
  #1;
17558 169 mohor
end
17559
endtask // wbm_write
17560 116 mohor
 
17561 169 mohor
task wbm_read;
17562
  input  [31:0] address_i;
17563
  output [((`MAX_BLK_SIZE * 32) - 1):0] data_o;
17564
  input  [3:0]  sel_i;
17565
  input  [31:0] size_i;
17566
  input  [3:0]  init_waits_i;
17567
  input  [3:0]  subseq_waits_i;
17568
 
17569
  reg `READ_RETURN_TYPE read_data;
17570
  reg `WB_TRANSFER_FLAGS flags;
17571
  reg `READ_RETURN_TYPE read_status;
17572
  integer i;
17573
begin
17574 274 tadejm
  wbm_working = 1;
17575
 
17576 169 mohor
  read_status = 0;
17577
  data_o      = 0;
17578
 
17579
  flags                  = 0;
17580
  flags`WB_TRANSFER_SIZE = size_i;
17581
  flags`INIT_WAITS       = init_waits_i;
17582
  flags`SUBSEQ_WAITS     = subseq_waits_i;
17583
 
17584
  read_data              = 0;
17585
  read_data`READ_ADDRESS = address_i;
17586
  read_data`READ_SEL     = sel_i;
17587
 
17588
  for (i = 0; i < size_i; i = i + 1)
17589 116 mohor
  begin
17590 169 mohor
    wb_master.blk_read_data_in[i] = read_data;
17591
    read_data`READ_ADDRESS        = read_data`READ_ADDRESS + 4;
17592
  end
17593
 
17594
  wb_master.wb_block_read(flags, read_status);
17595
 
17596
  if (read_status`CYC_ACTUAL_TRANSFER !== size_i)
17597
  begin
17598
    `TIME;
17599
    $display("*E WISHBONE Master was unable to complete the requested read operation from MAC!");
17600
  end
17601
 
17602
  for (i = 0; i < size_i; i = i + 1)
17603
  begin
17604
    data_o       = data_o << 32;
17605
    read_data    = wb_master.blk_read_data_out[(size_i - 1) - i]; // [31 - i];
17606
    data_o[31:0] = read_data`READ_DATA;
17607
  end
17608 274 tadejm
 
17609
  @(posedge wb_clk);
17610
  #3;
17611
  wbm_working = 0;
17612
  #1;
17613 169 mohor
end
17614
endtask // wbm_read
17615
 
17616
 
17617
//////////////////////////////////////////////////////////////
17618
// Ethernet Basic tasks
17619
//////////////////////////////////////////////////////////////
17620
 
17621
task hard_reset; //  MAC registers
17622
begin
17623
  // reset MAC registers
17624
  @(posedge wb_clk);
17625
  #2 wb_rst = 1'b1;
17626
  repeat(2) @(posedge wb_clk);
17627
  #2 wb_rst = 1'b0;
17628
end
17629
endtask // hard_reset
17630
 
17631
task reset_mac; //  MAC module
17632
  reg [31:0] tmp;
17633
  reg [31:0] tmp_no_rst;
17634
begin
17635
  // read MODER register first
17636
  wbm_read(`ETH_MODER, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17637
  // set reset bit - write back to MODER register with RESET bit
17638
  wbm_write(`ETH_MODER, (`ETH_MODER_RST | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17639
  // clear reset bit - write back to MODER register without RESET bit
17640
  tmp_no_rst = `ETH_MODER_RST;
17641
  tmp_no_rst = ~tmp_no_rst;
17642
  wbm_write(`ETH_MODER, (tmp_no_rst & tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17643
end
17644
endtask // reset_mac
17645
 
17646
task set_tx_bd;
17647
  input  [6:0]  tx_bd_num_start;
17648
  input  [6:0]  tx_bd_num_end;
17649
  input  [15:0] len;
17650
  input         irq;
17651
  input         pad;
17652
  input         crc;
17653
  input  [31:0] txpnt;
17654
 
17655
  integer       i;
17656
  integer       bd_status_addr, bd_ptr_addr;
17657
//  integer       buf_addr;
17658
begin
17659
  for(i = tx_bd_num_start; i <= tx_bd_num_end; i = i + 1)
17660
  begin
17661
//    buf_addr = `TX_BUF_BASE + i * 32'h600;
17662
    bd_status_addr = `TX_BD_BASE + i * 8;
17663
    bd_ptr_addr = bd_status_addr + 4;
17664
    // initialize BD - status
17665
    wbm_write(bd_status_addr, {len, 1'b0, irq, 1'b0, pad, crc, 11'h0},
17666
              4'hF, 1, wbm_init_waits, wbm_subseq_waits); // IRQ + PAD + CRC
17667
    // initialize BD - pointer
17668
    wbm_write(bd_ptr_addr, txpnt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Initializing BD-pointer
17669
  end
17670
end
17671
endtask // set_tx_bd
17672
 
17673
task set_tx_bd_wrap;
17674
  input  [6:0]  tx_bd_num_end;
17675
  integer       bd_status_addr, tmp;
17676
begin
17677
  bd_status_addr = `TX_BD_BASE + tx_bd_num_end * 8;
17678
  wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17679
  // set wrap bit to this BD - this BD should be last-one
17680
  wbm_write(bd_status_addr, (`ETH_TX_BD_WRAP | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17681
end
17682
endtask // set_tx_bd_wrap
17683
 
17684
task set_tx_bd_ready;
17685
  input  [6:0]  tx_nd_num_strat;
17686
  input  [6:0]  tx_bd_num_end;
17687
  integer       i;
17688
  integer       bd_status_addr, tmp;
17689
begin
17690
  for(i = tx_nd_num_strat; i <= tx_bd_num_end; i = i + 1)
17691
  begin
17692
    bd_status_addr = `TX_BD_BASE + i * 8;
17693
    wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17694
    // set empty bit to this BD - this BD should be ready
17695
    wbm_write(bd_status_addr, (`ETH_TX_BD_READY | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17696
  end
17697
end
17698
endtask // set_tx_bd_ready
17699
 
17700
task check_tx_bd;
17701
  input  [6:0]  tx_bd_num_end;
17702
  output [31:0] tx_bd_status;
17703
  integer       bd_status_addr, tmp;
17704
begin
17705
  bd_status_addr = `TX_BD_BASE + tx_bd_num_end * 8;
17706
  wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17707 274 tadejm
  tx_bd_status = tmp;
17708 169 mohor
end
17709
endtask // check_tx_bd
17710
 
17711
task clear_tx_bd;
17712
  input  [6:0]  tx_nd_num_strat;
17713
  input  [6:0]  tx_bd_num_end;
17714
  integer       i;
17715
  integer       bd_status_addr, bd_ptr_addr;
17716
begin
17717
  for(i = tx_nd_num_strat; i <= tx_bd_num_end; i = i + 1)
17718
  begin
17719
    bd_status_addr = `TX_BD_BASE + i * 8;
17720
    bd_ptr_addr = bd_status_addr + 4;
17721
    // clear BD - status
17722
    wbm_write(bd_status_addr, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17723
    // clear BD - pointer
17724
    wbm_write(bd_ptr_addr, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17725
  end
17726
end
17727
endtask // clear_tx_bd
17728
 
17729
task set_rx_bd;
17730
  input  [6:0]  rx_bd_num_strat;
17731
  input  [6:0]  rx_bd_num_end;
17732
  input         irq;
17733
  input  [31:0] rxpnt;
17734
//  input  [6:0]  rxbd_num;
17735
  integer       i;
17736
  integer       bd_status_addr, bd_ptr_addr;
17737
//  integer       buf_addr;
17738
begin
17739
  for(i = rx_bd_num_strat; i <= rx_bd_num_end; i = i + 1)
17740
  begin
17741
//    buf_addr = `RX_BUF_BASE + i * 32'h600;
17742 209 tadejm
//    bd_status_addr = `RX_BD_BASE + i * 8;
17743
//    bd_ptr_addr = bd_status_addr + 4; 
17744
    bd_status_addr = `TX_BD_BASE + i * 8;
17745
    bd_ptr_addr = bd_status_addr + 4;
17746 116 mohor
 
17747 169 mohor
    // initialize BD - status
17748
//    wbm_write(bd_status_addr, 32'h0000c000, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // IRQ + PAD + CRC
17749
    wbm_write(bd_status_addr, {17'h0, irq, 14'h0},
17750
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17751
    // initialize BD - pointer
17752
//    wbm_write(bd_ptr_addr, buf_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Initializing BD-pointer
17753
    wbm_write(bd_ptr_addr, rxpnt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Initializing BD-pointer
17754
  end
17755
end
17756
endtask // set_rx_bd
17757 116 mohor
 
17758 169 mohor
task set_rx_bd_wrap;
17759
  input  [6:0]  rx_bd_num_end;
17760
  integer       bd_status_addr, tmp;
17761
begin
17762 209 tadejm
//  bd_status_addr = `RX_BD_BASE + rx_bd_num_end * 8;
17763
  bd_status_addr = `TX_BD_BASE + rx_bd_num_end * 8;
17764 169 mohor
  wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17765
  // set wrap bit to this BD - this BD should be last-one
17766
  wbm_write(bd_status_addr, (`ETH_RX_BD_WRAP | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17767
end
17768
endtask // set_rx_bd_wrap
17769 116 mohor
 
17770 169 mohor
task set_rx_bd_empty;
17771
  input  [6:0]  rx_bd_num_strat;
17772
  input  [6:0]  rx_bd_num_end;
17773
  integer       i;
17774
  integer       bd_status_addr, tmp;
17775
begin
17776
  for(i = rx_bd_num_strat; i <= rx_bd_num_end; i = i + 1)
17777
  begin
17778 209 tadejm
//    bd_status_addr = `RX_BD_BASE + i * 8;
17779
    bd_status_addr = `TX_BD_BASE + i * 8;
17780 169 mohor
    wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17781
    // set empty bit to this BD - this BD should be ready
17782
    wbm_write(bd_status_addr, (`ETH_RX_BD_EMPTY | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17783 116 mohor
  end
17784 169 mohor
end
17785
endtask // set_rx_bd_empty
17786 116 mohor
 
17787 169 mohor
task check_rx_bd;
17788
  input  [6:0]  rx_bd_num_end;
17789
  output [31:0] rx_bd_status;
17790
  integer       bd_status_addr, tmp;
17791
begin
17792 209 tadejm
//  bd_status_addr = `RX_BD_BASE + rx_bd_num_end * 8;
17793
  bd_status_addr = `TX_BD_BASE + rx_bd_num_end * 8;
17794 169 mohor
  wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17795 274 tadejm
  rx_bd_status = tmp;
17796 169 mohor
end
17797
endtask // check_rx_bd
17798 116 mohor
 
17799 169 mohor
task clear_rx_bd;
17800
  input  [6:0]  rx_bd_num_strat;
17801
  input  [6:0]  rx_bd_num_end;
17802
  integer       i;
17803
  integer       bd_status_addr, bd_ptr_addr;
17804
begin
17805
  for(i = rx_bd_num_strat; i <= rx_bd_num_end; i = i + 1)
17806
  begin
17807 209 tadejm
//    bd_status_addr = `RX_BD_BASE + i * 8;
17808
    bd_status_addr = `TX_BD_BASE + i * 8;
17809 169 mohor
    bd_ptr_addr = bd_status_addr + 4;
17810
    // clear BD - status
17811
    wbm_write(bd_status_addr, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17812
    // clear BD - pointer
17813
    wbm_write(bd_ptr_addr, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
17814
  end
17815
end
17816
endtask // clear_rx_bd
17817 116 mohor
 
17818 169 mohor
task set_tx_packet;
17819
  input  [31:0] txpnt;
17820
  input  [15:0] len;
17821
  input  [7:0]  eth_start_data;
17822
  integer       i, sd;
17823
  integer       buffer;
17824
  reg           delta_t;
17825
begin
17826
  buffer = txpnt;
17827
  sd = eth_start_data;
17828
  delta_t = 0;
17829 116 mohor
 
17830 169 mohor
  // First write might not be word allign.
17831
  if(buffer[1:0] == 1)
17832
  begin
17833
    wb_slave.wr_mem(buffer - 1, {8'h0, sd[7:0], sd[7:0] + 3'h1, sd[7:0] + 3'h2}, 4'h7);
17834
    sd = sd + 3;
17835
    i = 3;
17836
  end
17837
  else if(buffer[1:0] == 2)
17838
  begin
17839
    wb_slave.wr_mem(buffer - 2, {16'h0, sd[7:0], sd[7:0] + 3'h1}, 4'h3);
17840
    sd = sd + 2;
17841
    i = 2;
17842
  end
17843
  else if(buffer[1:0] == 3)
17844
  begin
17845
    wb_slave.wr_mem(buffer - 3, {24'h0, sd[7:0]}, 4'h1);
17846
    sd = sd + 1;
17847
    i = 1;
17848
  end
17849
  else
17850
    i = 0;
17851
  delta_t = !delta_t;
17852 116 mohor
 
17853 169 mohor
  for(i = i; i < (len - 4); i = i + 4) // Last 0-3 bytes are not written
17854
  begin
17855
    wb_slave.wr_mem(buffer + i, {sd[7:0], sd[7:0] + 3'h1, sd[7:0] + 3'h2, sd[7:0] + 3'h3}, 4'hF);
17856
    sd = sd + 4;
17857
  end
17858
  delta_t = !delta_t;
17859
 
17860
  // Last word
17861
  if((len - i) == 3)
17862 116 mohor
  begin
17863 169 mohor
    wb_slave.wr_mem(buffer + i, {sd[7:0], sd[7:0] + 3'h1, sd[7:0] + 3'h2, 8'h0}, 4'hE);
17864
  end
17865
  else if((len - i) == 2)
17866
  begin
17867
    wb_slave.wr_mem(buffer + i, {sd[7:0], sd[7:0] + 3'h1, 16'h0}, 4'hC);
17868
  end
17869
  else if((len - i) == 1)
17870
  begin
17871
    wb_slave.wr_mem(buffer + i, {sd[7:0], 24'h0}, 4'h8);
17872
  end
17873
  else if((len - i) == 4)
17874
  begin
17875
    wb_slave.wr_mem(buffer + i, {sd[7:0], sd[7:0] + 3'h1, sd[7:0] + 3'h2, sd[7:0] + 3'h3}, 4'hF);
17876
  end
17877
  else
17878
    $display("(%0t)(%m) ERROR", $time);
17879
  delta_t = !delta_t;
17880
end
17881
endtask // set_tx_packet
17882
 
17883
task check_tx_packet;
17884
  input  [31:0] txpnt_wb;  // source
17885
  input  [31:0] txpnt_phy; // destination
17886
  input  [15:0] len;
17887
  output [31:0] failure;
17888
  integer       i, data_wb, data_phy;
17889
  reg    [31:0] addr_wb, addr_phy;
17890
  reg    [31:0] failure;
17891
  reg           delta_t;
17892
begin
17893
  addr_wb = txpnt_wb;
17894
  addr_phy = txpnt_phy;
17895
  delta_t = 0;
17896
  failure = 0;
17897 209 tadejm
  #1;
17898 169 mohor
  // First write might not be word allign.
17899
  if(addr_wb[1:0] == 1)
17900
  begin
17901
    wb_slave.rd_mem(addr_wb - 1, data_wb, 4'h7);
17902
    data_phy[31:24] = 0;
17903
    data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0]];
17904
    data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + 1];
17905
    data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + 2];
17906
    i = 3;
17907
    if (data_phy[23:0] !== data_wb[23:0])
17908
    begin
17909
      `TIME;
17910 209 tadejm
      $display("*E Wrong 1. word (3 bytes) of TX packet! phy: %0h, wb: %0h", data_phy[23:0], data_wb[23:0]);
17911
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
17912 169 mohor
      failure = 1;
17913
    end
17914
  end
17915
  else if (addr_wb[1:0] == 2)
17916
  begin
17917
    wb_slave.rd_mem(addr_wb - 2, data_wb, 4'h3);
17918
    data_phy[31:16] = 0;
17919
    data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0]];
17920
    data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + 1];
17921
    i = 2;
17922
    if (data_phy[15:0] !== data_wb[15:0])
17923
    begin
17924
      `TIME;
17925 209 tadejm
      $display("*E Wrong 1. word (2 bytes) of TX packet! phy: %0h, wb: %0h", data_phy[15:0], data_wb[15:0]);
17926
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
17927 169 mohor
      failure = 1;
17928
    end
17929
  end
17930
  else if (addr_wb[1:0] == 3)
17931
  begin
17932
    wb_slave.rd_mem(addr_wb - 3, data_wb, 4'h1);
17933
    data_phy[31: 8] = 0;
17934
    data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0]];
17935
    i = 1;
17936
    if (data_phy[7:0] !== data_wb[7:0])
17937
    begin
17938
      `TIME;
17939 209 tadejm
      $display("*E Wrong 1. word (1 byte) of TX packet! phy: %0h, wb: %0h", data_phy[7:0], data_wb[7:0]);
17940
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
17941 169 mohor
      failure = 1;
17942
    end
17943
  end
17944
  else
17945
    i = 0;
17946
  delta_t = !delta_t;
17947 209 tadejm
  #1;
17948 169 mohor
  for(i = i; i < (len - 4); i = i + 4) // Last 0-3 bytes are not checked
17949
  begin
17950
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hF);
17951
    data_phy[31:24] = eth_phy.tx_mem[addr_phy[21:0] + i];
17952
    data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0] + i + 1];
17953
    data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + i + 2];
17954
    data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + i + 3];
17955 279 mohor
 
17956 169 mohor
    if (data_phy[31:0] !== data_wb[31:0])
17957
    begin
17958
      `TIME;
17959 209 tadejm
      $display("*E Wrong %d. word (4 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
17960
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
17961 169 mohor
      failure = failure + 1;
17962
    end
17963
  end
17964
  delta_t = !delta_t;
17965 209 tadejm
  #1;
17966 169 mohor
  // Last word
17967
  if((len - i) == 3)
17968
  begin
17969
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hE);
17970
    data_phy[31:24] = eth_phy.tx_mem[addr_phy[21:0] + i];
17971
    data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0] + i + 1];
17972
    data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + i + 2];
17973
    data_phy[ 7: 0] = 0;
17974
    if (data_phy[31:8] !== data_wb[31:8])
17975
    begin
17976
      `TIME;
17977 209 tadejm
      $display("*E Wrong %d. word (3 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:8], data_wb[31:8]);
17978
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
17979 169 mohor
      failure = failure + 1;
17980
    end
17981
  end
17982
  else if((len - i) == 2)
17983
  begin
17984
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hC);
17985
    data_phy[31:24] = eth_phy.tx_mem[addr_phy[21:0] + i];
17986
    data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0] + i + 1];
17987
    data_phy[15: 8] = 0;
17988
    data_phy[ 7: 0] = 0;
17989
    if (data_phy[31:16] !== data_wb[31:16])
17990
    begin
17991
      `TIME;
17992 209 tadejm
      $display("*E Wrong %d. word (2 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:16], data_wb[31:16]);
17993
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
17994 169 mohor
      failure = failure + 1;
17995
    end
17996
  end
17997
  else if((len - i) == 1)
17998
  begin
17999
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'h8);
18000
    data_phy[31:24] = eth_phy.tx_mem[addr_phy[21:0] + i];
18001
    data_phy[23:16] = 0;
18002
    data_phy[15: 8] = 0;
18003
    data_phy[ 7: 0] = 0;
18004
    if (data_phy[31:24] !== data_wb[31:24])
18005
    begin
18006
      `TIME;
18007 209 tadejm
      $display("*E Wrong %d. word (1 byte) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:24], data_wb[31:24]);
18008
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
18009 169 mohor
      failure = failure + 1;
18010
    end
18011
  end
18012
  else if((len - i) == 4)
18013
  begin
18014
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hF);
18015
    data_phy[31:24] = eth_phy.tx_mem[addr_phy[21:0] + i];
18016
    data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0] + i + 1];
18017
    data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + i + 2];
18018
    data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + i + 3];
18019
    if (data_phy[31:0] !== data_wb[31:0])
18020
    begin
18021
      `TIME;
18022 209 tadejm
      $display("*E Wrong %d. word (4 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
18023
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
18024 169 mohor
      failure = failure + 1;
18025
    end
18026
  end
18027
  else
18028
    $display("(%0t)(%m) ERROR", $time);
18029
  delta_t = !delta_t;
18030
end
18031
endtask // check_tx_packet
18032
 
18033
task set_rx_packet;
18034
  input  [31:0] rxpnt;
18035
  input  [15:0] len;
18036
  input         plus_dribble_nibble; // if length is longer for one nibble
18037
  input  [47:0] eth_dest_addr;
18038
  input  [47:0] eth_source_addr;
18039
  input  [15:0] eth_type_len;
18040
  input  [7:0]  eth_start_data;
18041
  integer       i, sd;
18042
  reg    [47:0] dest_addr;
18043
  reg    [47:0] source_addr;
18044
  reg    [15:0] type_len;
18045
  reg    [21:0] buffer;
18046
  reg           delta_t;
18047
begin
18048
  buffer = rxpnt[21:0];
18049
  dest_addr = eth_dest_addr;
18050
  source_addr = eth_source_addr;
18051
  type_len = eth_type_len;
18052
  sd = eth_start_data;
18053
  delta_t = 0;
18054
  for(i = 0; i < len; i = i + 1)
18055
  begin
18056
    if (i < 6)
18057
    begin
18058
      eth_phy.rx_mem[buffer] = dest_addr[47:40];
18059
      dest_addr = dest_addr << 8;
18060
    end
18061
    else if (i < 12)
18062
    begin
18063
      eth_phy.rx_mem[buffer] = source_addr[47:40];
18064
      source_addr = source_addr << 8;
18065
    end
18066
    else if (i < 14)
18067
    begin
18068
      eth_phy.rx_mem[buffer] = type_len[15:8];
18069
      type_len = type_len << 8;
18070
    end
18071
    else
18072
    begin
18073
      eth_phy.rx_mem[buffer] = sd[7:0];
18074
      sd = sd + 1;
18075
    end
18076
    buffer = buffer + 1;
18077
  end
18078
  delta_t = !delta_t;
18079
  if (plus_dribble_nibble)
18080
    eth_phy.rx_mem[buffer] = {4'h0, 4'hD /*sd[3:0]*/};
18081
  delta_t = !delta_t;
18082
end
18083
endtask // set_rx_packet
18084
 
18085 267 mohor
task set_rx_control_packet;
18086
  input  [31:0] rxpnt;
18087
  input  [15:0] PauseTV;
18088
  integer       i;
18089
  reg    [47:0] dest_addr;
18090
  reg    [47:0] source_addr;
18091
  reg    [15:0] type_len;
18092
  reg    [21:0] buffer;
18093
  reg           delta_t;
18094
  reg    [15:0] PTV;
18095
  reg    [15:0] opcode;
18096
begin
18097
  buffer = rxpnt[21:0];
18098
  dest_addr = 48'h0180_c200_0001;
18099
  source_addr = 48'h0708_090A_0B0C;
18100
  type_len = 16'h8808;
18101
  opcode = 16'h0001;
18102
  PTV = PauseTV;
18103
  delta_t = 0;
18104
  for(i = 0; i < 60; i = i + 1)
18105
  begin
18106
    if (i < 6)
18107
    begin
18108
      eth_phy.rx_mem[buffer] = dest_addr[47:40];
18109
      dest_addr = dest_addr << 8;
18110
    end
18111
    else if (i < 12)
18112
    begin
18113
      eth_phy.rx_mem[buffer] = source_addr[47:40];
18114
      source_addr = source_addr << 8;
18115
    end
18116
    else if (i < 14)
18117
    begin
18118
      eth_phy.rx_mem[buffer] = type_len[15:8];
18119
      type_len = type_len << 8;
18120
    end
18121
    else if (i < 16)
18122
    begin
18123
      eth_phy.rx_mem[buffer] = opcode[15:8];
18124
      opcode = opcode << 8;
18125
    end
18126
    else if (i < 18)
18127
    begin
18128
      eth_phy.rx_mem[buffer] = PTV[15:8];
18129
      PTV = PTV << 8;
18130
    end
18131
    else
18132
    begin
18133
      eth_phy.rx_mem[buffer] = 0;
18134
    end
18135
    buffer = buffer + 1;
18136
  end
18137
  delta_t = !delta_t;
18138
  append_rx_crc (rxpnt, 60, 1'b0, 1'b0); // CRC for control packet
18139
end
18140
endtask // set_rx_control_packet
18141
 
18142 243 tadejm
task set_rx_addr_type;
18143
  input  [31:0] rxpnt;
18144
  input  [47:0] eth_dest_addr;
18145
  input  [47:0] eth_source_addr;
18146
  input  [15:0] eth_type_len;
18147
  integer       i;
18148
  reg    [47:0] dest_addr;
18149
  reg    [47:0] source_addr;
18150
  reg    [15:0] type_len;
18151
  reg    [21:0] buffer;
18152
  reg           delta_t;
18153
begin
18154
  buffer = rxpnt[21:0];
18155
  dest_addr = eth_dest_addr;
18156
  source_addr = eth_source_addr;
18157
  type_len = eth_type_len;
18158
  delta_t = 0;
18159
  for(i = 0; i < 14; i = i + 1)
18160
  begin
18161
    if (i < 6)
18162
    begin
18163
      eth_phy.rx_mem[buffer] = dest_addr[47:40];
18164
      dest_addr = dest_addr << 8;
18165
    end
18166
    else if (i < 12)
18167
    begin
18168
      eth_phy.rx_mem[buffer] = source_addr[47:40];
18169
      source_addr = source_addr << 8;
18170
    end
18171
    else // if (i < 14)
18172
    begin
18173
      eth_phy.rx_mem[buffer] = type_len[15:8];
18174
      type_len = type_len << 8;
18175
    end
18176
    buffer = buffer + 1;
18177
  end
18178
  delta_t = !delta_t;
18179
end
18180
endtask // set_rx_addr_type
18181
 
18182 169 mohor
task check_rx_packet;
18183
  input  [31:0] rxpnt_phy; // source
18184
  input  [31:0] rxpnt_wb;  // destination
18185
  input  [15:0] len;
18186
  input         plus_dribble_nibble; // if length is longer for one nibble
18187
  input         successful_dribble_nibble; // if additional nibble is stored into memory
18188
  output [31:0] failure;
18189
  integer       i, data_wb, data_phy;
18190
  reg    [31:0] addr_wb, addr_phy;
18191
  reg    [31:0] failure;
18192
  reg    [21:0] buffer;
18193
  reg           delta_t;
18194
begin
18195
  addr_phy = rxpnt_phy;
18196
  addr_wb = rxpnt_wb;
18197
  delta_t = 0;
18198
  failure = 0;
18199
 
18200
  // First write might not be word allign.
18201
  if(addr_wb[1:0] == 1)
18202
  begin
18203
    wb_slave.rd_mem(addr_wb - 1, data_wb, 4'h7);
18204
    data_phy[31:24] = 0;
18205
    data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0]];
18206
    data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + 1];
18207
    data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + 2];
18208
    i = 3;
18209
    if (data_phy[23:0] !== data_wb[23:0])
18210
    begin
18211
      `TIME;
18212 243 tadejm
      $display("   addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
18213
      $display("*E Wrong 1. word (3 bytes) of RX packet! phy = %h, wb = %h", data_phy[23:0], data_wb[23:0]);
18214 169 mohor
      failure = 1;
18215
    end
18216
  end
18217
  else if (addr_wb[1:0] == 2)
18218
  begin
18219
    wb_slave.rd_mem(addr_wb - 2, data_wb, 4'h3);
18220
    data_phy[31:16] = 0;
18221
    data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0]];
18222
    data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + 1];
18223
    i = 2;
18224
    if (data_phy[15:0] !== data_wb[15:0])
18225
    begin
18226
      `TIME;
18227 243 tadejm
      $display("   addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
18228
      $display("*E Wrong 1. word (2 bytes) of RX packet! phy = %h, wb = %h", data_phy[15:0], data_wb[15:0]);
18229 169 mohor
      failure = 1;
18230
    end
18231
  end
18232
  else if (addr_wb[1:0] == 3)
18233
  begin
18234
    wb_slave.rd_mem(addr_wb - 3, data_wb, 4'h1);
18235
    data_phy[31: 8] = 0;
18236
    data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0]];
18237
    i = 1;
18238
    if (data_phy[7:0] !== data_wb[7:0])
18239
    begin
18240
      `TIME;
18241 243 tadejm
      $display("   addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
18242
      $display("*E Wrong 1. word (1 byte) of RX packet! phy = %h, wb = %h", data_phy[7:0], data_wb[7:0]);
18243 169 mohor
      failure = 1;
18244
    end
18245
  end
18246
  else
18247
    i = 0;
18248
  delta_t = !delta_t;
18249
 
18250
  for(i = i; i < (len - 4); i = i + 4) // Last 0-3 bytes are not checked
18251
  begin
18252
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hF);
18253
    data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
18254
    data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
18255
    data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + i + 2];
18256
    data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + i + 3];
18257
    if (data_phy[31:0] !== data_wb[31:0])
18258
    begin
18259
      `TIME;
18260 243 tadejm
      if (i == 0)
18261
        $display("   addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
18262
      $display("*E Wrong %0d. word (4 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
18263 169 mohor
      failure = failure + 1;
18264
    end
18265
  end
18266
  delta_t = !delta_t;
18267
 
18268
  // Last word
18269
  if((len - i) == 3)
18270
  begin
18271
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hF);
18272
    data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
18273
    data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
18274
    data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + i + 2];
18275
    if (plus_dribble_nibble)
18276
      data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + i + 3];
18277
    else
18278
      data_phy[ 7: 0] = 0;
18279
    if (data_phy[31:8] !== data_wb[31:8])
18280
    begin
18281
      `TIME;
18282 243 tadejm
      $display("*E Wrong %0d. word (3 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:8], data_wb[31:8]);
18283 169 mohor
      failure = failure + 1;
18284
    end
18285
    if (plus_dribble_nibble && successful_dribble_nibble)
18286
    begin
18287
      if (data_phy[3:0] !== data_wb[3:0])
18288 116 mohor
      begin
18289 169 mohor
        `TIME;
18290 243 tadejm
        $display("*E Wrong dribble nibble in %0d. word (3 bytes) of RX packet!", ((i/4)+1));
18291 169 mohor
        failure = failure + 1;
18292 116 mohor
      end
18293 169 mohor
    end
18294
    else if (plus_dribble_nibble && !successful_dribble_nibble)
18295
    begin
18296
      if (data_phy[3:0] === data_wb[3:0])
18297 116 mohor
      begin
18298 169 mohor
        `TIME;
18299 243 tadejm
        $display("*E Wrong dribble nibble in %0d. word (3 bytes) of RX packet!", ((i/4)+1));
18300 169 mohor
        failure = failure + 1;
18301 116 mohor
      end
18302 169 mohor
    end
18303
  end
18304
  else if((len - i) == 2)
18305
  begin
18306
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hE);
18307
    data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
18308
    data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
18309
    if (plus_dribble_nibble)
18310
      data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + i + 2];
18311
    else
18312
      data_phy[15: 8] = 0;
18313
    data_phy[ 7: 0] = 0;
18314
    if (data_phy[31:16] !== data_wb[31:16])
18315
    begin
18316
      `TIME;
18317 243 tadejm
      $display("*E Wrong %0d. word (2 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:16], data_wb[31:16]);
18318 169 mohor
      failure = failure + 1;
18319
    end
18320
    if (plus_dribble_nibble && successful_dribble_nibble)
18321
    begin
18322
      if (data_phy[11:8] !== data_wb[11:8])
18323
      begin
18324
        `TIME;
18325 243 tadejm
        $display("*E Wrong dribble nibble in %0d. word (2 bytes) of RX packet!", ((i/4)+1));
18326 169 mohor
        failure = failure + 1;
18327
      end
18328
    end
18329
    else if (plus_dribble_nibble && !successful_dribble_nibble)
18330
    begin
18331
      if (data_phy[11:8] === data_wb[11:8])
18332
      begin
18333
        `TIME;
18334 243 tadejm
        $display("*E Wrong dribble nibble in %0d. word (2 bytes) of RX packet!", ((i/4)+1));
18335 169 mohor
        failure = failure + 1;
18336
      end
18337
    end
18338
  end
18339
  else if((len - i) == 1)
18340
  begin
18341
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hC);
18342
    data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
18343
    if (plus_dribble_nibble)
18344
      data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
18345
    else
18346
      data_phy[23:16] = 0;
18347
    data_phy[15: 8] = 0;
18348
    data_phy[ 7: 0] = 0;
18349
    if (data_phy[31:24] !== data_wb[31:24])
18350
    begin
18351
      `TIME;
18352 243 tadejm
      $display("*E Wrong %0d. word (1 byte) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:24], data_wb[31:24]);
18353 169 mohor
      failure = failure + 1;
18354
    end
18355
    if (plus_dribble_nibble && successful_dribble_nibble)
18356
    begin
18357
      if (data_phy[19:16] !== data_wb[19:16])
18358
      begin
18359
        `TIME;
18360 243 tadejm
        $display("*E Wrong dribble nibble in %0d. word (1 byte) of RX packet!", ((i/4)+1));
18361 169 mohor
        failure = failure + 1;
18362
      end
18363
    end
18364
    else if (plus_dribble_nibble && !successful_dribble_nibble)
18365
    begin
18366
      if (data_phy[19:16] === data_wb[19:16])
18367
      begin
18368
        `TIME;
18369 243 tadejm
        $display("*E Wrong dribble nibble in %0d. word (1 byte) of RX packet!", ((i/4)+1));
18370 169 mohor
        failure = failure + 1;
18371
      end
18372
    end
18373
  end
18374
  else if((len - i) == 4)
18375
  begin
18376
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hF);
18377
    data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
18378
    data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
18379
    data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + i + 2];
18380
    data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + i + 3];
18381
    if (data_phy[31:0] !== data_wb[31:0])
18382
    begin
18383
      `TIME;
18384 243 tadejm
      $display("*E Wrong %0d. word (4 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
18385 169 mohor
      failure = failure + 1;
18386
    end
18387
    if (plus_dribble_nibble)
18388
    begin
18389
      wb_slave.rd_mem(addr_wb + i + 4, data_wb, 4'h8);
18390
      data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i + 4];
18391
      if (successful_dribble_nibble)
18392
      begin
18393
        if (data_phy[27:24] !== data_wb[27:24])
18394
        begin
18395
          `TIME;
18396 243 tadejm
          $display("*E Wrong dribble nibble in %0d. word (0 bytes) of RX packet!", ((i/4)+2));
18397 169 mohor
          failure = failure + 1;
18398
        end
18399
      end
18400
      else
18401
      begin
18402
        if (data_phy[27:24] === data_wb[27:24])
18403
        begin
18404
          `TIME;
18405 243 tadejm
          $display("*E Wrong dribble nibble in %0d. word (0 bytes) of RX packet!", ((i/4)+2));
18406 169 mohor
          failure = failure + 1;
18407
        end
18408
      end
18409
    end
18410
  end
18411
  else
18412
    $display("(%0t)(%m) ERROR", $time);
18413
  delta_t = !delta_t;
18414
end
18415
endtask // check_rx_packet
18416 116 mohor
 
18417 169 mohor
//////////////////////////////////////////////////////////////
18418
// Ethernet CRC Basic tasks
18419
//////////////////////////////////////////////////////////////
18420
 
18421
task append_tx_crc;
18422
  input  [31:0] txpnt_wb;  // source
18423
  input  [15:0] len; // length in bytes without CRC
18424
  input         negated_crc; // if appended CRC is correct or not
18425
  reg    [31:0] crc;
18426
  reg    [31:0] addr_wb;
18427
  reg           delta_t;
18428
begin
18429 243 tadejm
  addr_wb = txpnt_wb + {16'h0, len};
18430 169 mohor
  delta_t = 0;
18431
  // calculate CRC from prepared packet
18432
  paralel_crc_mac(txpnt_wb, {16'h0, len}, 1'b0, crc);
18433
  if (negated_crc)
18434
    crc = ~crc;
18435
  delta_t = !delta_t;
18436
 
18437
  // Write might not be word allign.
18438
  if (addr_wb[1:0] == 1)
18439
  begin
18440
    wb_slave.wr_mem(addr_wb - 1, {8'h0, crc[7:0], crc[15:8], crc[23:16]}, 4'h7);
18441
    wb_slave.wr_mem(addr_wb + 3, {crc[31:24], 24'h0}, 4'h8);
18442 116 mohor
  end
18443 169 mohor
  else if (addr_wb[1:0] == 2)
18444
  begin
18445
    wb_slave.wr_mem(addr_wb - 2, {16'h0, crc[7:0], crc[15:8]}, 4'h3);
18446
    wb_slave.wr_mem(addr_wb + 2, {crc[23:16], crc[31:24], 16'h0}, 4'hC);
18447
  end
18448
  else if (addr_wb[1:0] == 3)
18449
  begin
18450
    wb_slave.wr_mem(addr_wb - 3, {24'h0, crc[7:0]}, 4'h1);
18451
    wb_slave.wr_mem(addr_wb + 1, {crc[15:8], crc[23:16], crc[31:24], 8'h0}, 4'hE);
18452
  end
18453
  else
18454
  begin
18455
    wb_slave.wr_mem(addr_wb, {crc[7:0], crc[15:8], crc[23:16], crc[31:24]}, 4'hF);
18456
  end
18457
  delta_t = !delta_t;
18458
end
18459
endtask // append_tx_crc
18460 116 mohor
 
18461 169 mohor
task check_tx_crc; // used to check crc added to TX packets by MAC
18462
  input  [31:0] txpnt_phy; // destination
18463
  input  [15:0] len; // length in bytes without CRC
18464
  input         negated_crc; // if appended CRC is correct or not
18465
  output [31:0] failure;
18466
  reg    [31:0] failure;
18467
  reg    [31:0] crc_calc;
18468
  reg    [31:0] crc;
18469
  reg    [31:0] addr_phy;
18470
  reg           delta_t;
18471
begin
18472
  addr_phy = txpnt_phy;
18473
  failure = 0;
18474
  // calculate CRC from sent packet
18475
//  serial_crc_phy_tx(addr_phy, {16'h0, len}, 1'b0, crc_calc);
18476
//#10;
18477
  paralel_crc_phy_tx(addr_phy, {16'h0, len}, 1'b0, crc_calc);
18478 209 tadejm
  #1;
18479 169 mohor
  addr_phy = addr_phy + len;
18480
  // Read CRC - BIG endian
18481
  crc[31:24] = eth_phy.tx_mem[addr_phy[21:0]];
18482
  crc[23:16] = eth_phy.tx_mem[addr_phy[21:0] + 1];
18483
  crc[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + 2];
18484
  crc[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + 3];
18485
 
18486
  delta_t = !delta_t;
18487
  if (negated_crc)
18488
  begin
18489
    if ((~crc_calc) !== crc)
18490
    begin
18491
      `TIME;
18492
      $display("*E Negated CRC was not successfuly transmitted!");
18493
      failure = failure + 1;
18494
    end
18495
  end
18496
  else
18497
  begin
18498
    if (crc_calc !== crc)
18499
    begin
18500
      `TIME;
18501 209 tadejm
      $display("*E Transmitted CRC was not correct; crc_calc: %0h, crc_mem: %0h", crc_calc, crc);
18502 169 mohor
      failure = failure + 1;
18503
    end
18504
  end
18505
  delta_t = !delta_t;
18506
end
18507
endtask // check_tx_crc
18508
 
18509
task append_rx_crc;
18510
  input  [31:0] rxpnt_phy; // source
18511
  input  [15:0] len; // length in bytes without CRC
18512
  input         plus_dribble_nibble; // if length is longer for one nibble
18513
  input         negated_crc; // if appended CRC is correct or not
18514
  reg    [31:0] crc;
18515
  reg    [7:0]  tmp;
18516
  reg    [31:0] addr_phy;
18517
  reg           delta_t;
18518
begin
18519
  addr_phy = rxpnt_phy + len;
18520
  delta_t = 0;
18521
  // calculate CRC from prepared packet
18522
  paralel_crc_phy_rx(rxpnt_phy, {16'h0, len}, plus_dribble_nibble, crc);
18523
  if (negated_crc)
18524
    crc = ~crc;
18525
  delta_t = !delta_t;
18526
 
18527
  if (plus_dribble_nibble)
18528
  begin
18529
    tmp = eth_phy.rx_mem[addr_phy];
18530 209 tadejm
    eth_phy.rx_mem[addr_phy]     = {crc[27:24], tmp[3:0]};
18531
    eth_phy.rx_mem[addr_phy + 1] = {crc[19:16], crc[31:28]};
18532
    eth_phy.rx_mem[addr_phy + 2] = {crc[11:8], crc[23:20]};
18533
    eth_phy.rx_mem[addr_phy + 3] = {crc[3:0], crc[15:12]};
18534
    eth_phy.rx_mem[addr_phy + 4] = {4'h0, crc[7:4]};
18535 169 mohor
  end
18536
  else
18537
  begin
18538 209 tadejm
    eth_phy.rx_mem[addr_phy]     = crc[31:24];
18539
    eth_phy.rx_mem[addr_phy + 1] = crc[23:16];
18540
    eth_phy.rx_mem[addr_phy + 2] = crc[15:8];
18541
    eth_phy.rx_mem[addr_phy + 3] = crc[7:0];
18542 169 mohor
  end
18543
end
18544
endtask // append_rx_crc
18545
 
18546
// paralel CRC checking for PHY TX
18547
task paralel_crc_phy_tx;
18548
  input  [31:0] start_addr; // start address
18549
  input  [31:0] len; // length of frame in Bytes without CRC length
18550
  input         plus_dribble_nibble; // if length is longer for one nibble
18551
  output [31:0] crc_out;
18552
  reg    [21:0] addr_cnt; // only 22 address lines
18553
  integer       word_cnt;
18554
  integer       nibble_cnt;
18555
  reg    [31:0] load_reg;
18556
  reg           delta_t;
18557
  reg    [31:0] crc_next;
18558
  reg    [31:0] crc;
18559
  reg           crc_error;
18560
  reg     [3:0] data_in;
18561
  integer       i;
18562
begin
18563
  #1 addr_cnt = start_addr[21:0];
18564
  word_cnt = 24; // 27; // start of the frame - nibble granularity (MSbit first)
18565
  crc = 32'hFFFF_FFFF; // INITIAL value
18566
  delta_t = 0;
18567
  // length must include 4 bytes of ZEROs, to generate CRC
18568
  // get number of nibbles from Byte length (2^1 = 2)
18569
  if (plus_dribble_nibble)
18570
    nibble_cnt = ((len + 4) << 1) + 1'b1; // one nibble longer
18571
  else
18572
    nibble_cnt = ((len + 4) << 1);
18573
  // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
18574
  load_reg[31:24] = eth_phy.tx_mem[addr_cnt];
18575
  addr_cnt = addr_cnt + 1;
18576
  load_reg[23:16] = eth_phy.tx_mem[addr_cnt];
18577
  addr_cnt = addr_cnt + 1;
18578
  load_reg[15: 8] = eth_phy.tx_mem[addr_cnt];
18579
  addr_cnt = addr_cnt + 1;
18580
  load_reg[ 7: 0] = eth_phy.tx_mem[addr_cnt];
18581
  addr_cnt = addr_cnt + 1;
18582
  while (nibble_cnt > 0)
18583
  begin
18584
    // wait for delta time
18585
    delta_t = !delta_t;
18586
    // shift data in
18587
 
18588
    if(nibble_cnt <= 8) // for additional 8 nibbles shift ZEROs in!
18589
      data_in[3:0] = 4'h0;
18590
    else
18591
 
18592
      data_in[3:0] = {load_reg[word_cnt], load_reg[word_cnt+1], load_reg[word_cnt+2], load_reg[word_cnt+3]};
18593
    crc_next[0]  = (data_in[0] ^ crc[28]);
18594
    crc_next[1]  = (data_in[1] ^ data_in[0] ^ crc[28]    ^ crc[29]);
18595
    crc_next[2]  = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]);
18596
    crc_next[3]  = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]);
18597
    crc_next[4]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[0];
18598
    crc_next[5]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[1];
18599
    crc_next[6]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[ 2];
18600
    crc_next[7]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[3];
18601
    crc_next[8]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[4];
18602
    crc_next[9]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[5];
18603
    crc_next[10] = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[6];
18604
    crc_next[11] = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[7];
18605
    crc_next[12] = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]) ^ crc[8];
18606
    crc_next[13] = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]) ^ crc[9];
18607
    crc_next[14] = (data_in[3] ^ data_in[2] ^ crc[30]    ^ crc[31]) ^ crc[10];
18608
    crc_next[15] = (data_in[3] ^ crc[31])   ^ crc[11];
18609
    crc_next[16] = (data_in[0] ^ crc[28])   ^ crc[12];
18610
    crc_next[17] = (data_in[1] ^ crc[29])   ^ crc[13];
18611
    crc_next[18] = (data_in[2] ^ crc[30])   ^ crc[14];
18612
    crc_next[19] = (data_in[3] ^ crc[31])   ^ crc[15];
18613
    crc_next[20] =  crc[16];
18614
    crc_next[21] =  crc[17];
18615
    crc_next[22] = (data_in[0] ^ crc[28])   ^ crc[18];
18616
    crc_next[23] = (data_in[1] ^ data_in[0] ^ crc[29]    ^ crc[28]) ^ crc[19];
18617
    crc_next[24] = (data_in[2] ^ data_in[1] ^ crc[30]    ^ crc[29]) ^ crc[20];
18618
    crc_next[25] = (data_in[3] ^ data_in[2] ^ crc[31]    ^ crc[30]) ^ crc[21];
18619
    crc_next[26] = (data_in[3] ^ data_in[0] ^ crc[31]    ^ crc[28]) ^ crc[22];
18620
    crc_next[27] = (data_in[1] ^ crc[29])   ^ crc[23];
18621
    crc_next[28] = (data_in[2] ^ crc[30])   ^ crc[24];
18622
    crc_next[29] = (data_in[3] ^ crc[31])   ^ crc[25];
18623
    crc_next[30] =  crc[26];
18624
    crc_next[31] =  crc[27];
18625
 
18626
    crc = crc_next;
18627
    crc_error = crc[31:0] != 32'hc704dd7b;  // CRC not equal to magic number
18628
    case (nibble_cnt)
18629
    9: crc_out = {!crc[24], !crc[25], !crc[26], !crc[27], !crc[28], !crc[29], !crc[30], !crc[31],
18630
                  !crc[16], !crc[17], !crc[18], !crc[19], !crc[20], !crc[21], !crc[22], !crc[23],
18631
                  !crc[ 8], !crc[ 9], !crc[10], !crc[11], !crc[12], !crc[13], !crc[14], !crc[15],
18632
                  !crc[ 0], !crc[ 1], !crc[ 2], !crc[ 3], !crc[ 4], !crc[ 5], !crc[ 6], !crc[ 7]};
18633
    default: crc_out = crc_out;
18634
    endcase
18635
    // wait for delta time
18636
    delta_t = !delta_t;
18637
    // increment address and load new data
18638
    if ((word_cnt+3) == 7)//4)
18639
    begin
18640
      // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
18641
      load_reg[31:24] = eth_phy.tx_mem[addr_cnt];
18642
      addr_cnt = addr_cnt + 1;
18643
      load_reg[23:16] = eth_phy.tx_mem[addr_cnt];
18644
      addr_cnt = addr_cnt + 1;
18645
      load_reg[15: 8] = eth_phy.tx_mem[addr_cnt];
18646
      addr_cnt = addr_cnt + 1;
18647
      load_reg[ 7: 0] = eth_phy.tx_mem[addr_cnt];
18648
      addr_cnt = addr_cnt + 1;
18649
    end
18650
    // set new load bit position
18651
    if((word_cnt+3) == 31)
18652
      word_cnt = 16;
18653
    else if ((word_cnt+3) == 23)
18654
      word_cnt = 8;
18655
    else if ((word_cnt+3) == 15)
18656
      word_cnt = 0;
18657
    else if ((word_cnt+3) == 7)
18658
      word_cnt = 24;
18659
    else
18660
      word_cnt = word_cnt + 4;// - 4;
18661
    // decrement nibble counter
18662
    nibble_cnt = nibble_cnt - 1;
18663
    // wait for delta time
18664
    delta_t = !delta_t;
18665
  end // while
18666
  #1;
18667
end
18668
endtask // paralel_crc_phy_tx
18669
 
18670
// paralel CRC calculating for PHY RX
18671
task paralel_crc_phy_rx;
18672
  input  [31:0] start_addr; // start address
18673
  input  [31:0] len; // length of frame in Bytes without CRC length
18674
  input         plus_dribble_nibble; // if length is longer for one nibble
18675 209 tadejm
  output [31:0] crc_out;
18676 169 mohor
  reg    [21:0] addr_cnt; // only 22 address lines
18677
  integer       word_cnt;
18678 209 tadejm
  integer       nibble_cnt;
18679 169 mohor
  reg    [31:0] load_reg;
18680
  reg           delta_t;
18681 209 tadejm
  reg    [31:0] crc_next;
18682
  reg    [31:0] crc;
18683
  reg           crc_error;
18684
  reg     [3:0] data_in;
18685
  integer       i;
18686 169 mohor
begin
18687
  #1 addr_cnt = start_addr[21:0];
18688 209 tadejm
  word_cnt = 24; // 27; // start of the frame - nibble granularity (MSbit first)
18689
  crc = 32'hFFFF_FFFF; // INITIAL value
18690 169 mohor
  delta_t = 0;
18691
  // length must include 4 bytes of ZEROs, to generate CRC
18692 209 tadejm
  // get number of nibbles from Byte length (2^1 = 2)
18693 169 mohor
  if (plus_dribble_nibble)
18694 209 tadejm
    nibble_cnt = ((len + 4) << 1) + 1'b1; // one nibble longer
18695 169 mohor
  else
18696 209 tadejm
    nibble_cnt = ((len + 4) << 1);
18697
  // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
18698 169 mohor
  load_reg[31:24] = eth_phy.rx_mem[addr_cnt];
18699
  addr_cnt = addr_cnt + 1;
18700
  load_reg[23:16] = eth_phy.rx_mem[addr_cnt];
18701
  addr_cnt = addr_cnt + 1;
18702 209 tadejm
  load_reg[15: 8] = eth_phy.rx_mem[addr_cnt];
18703 169 mohor
  addr_cnt = addr_cnt + 1;
18704 209 tadejm
  load_reg[ 7: 0] = eth_phy.rx_mem[addr_cnt];
18705
  addr_cnt = addr_cnt + 1;
18706
  while (nibble_cnt > 0)
18707 169 mohor
  begin
18708
    // wait for delta time
18709
    delta_t = !delta_t;
18710
    // shift data in
18711 209 tadejm
 
18712
    if(nibble_cnt <= 8) // for additional 8 nibbles shift ZEROs in!
18713
      data_in[3:0] = 4'h0;
18714 169 mohor
    else
18715 209 tadejm
 
18716
      data_in[3:0] = {load_reg[word_cnt], load_reg[word_cnt+1], load_reg[word_cnt+2], load_reg[word_cnt+3]};
18717
    crc_next[0]  = (data_in[0] ^ crc[28]);
18718
    crc_next[1]  = (data_in[1] ^ data_in[0] ^ crc[28]    ^ crc[29]);
18719
    crc_next[2]  = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]);
18720
    crc_next[3]  = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]);
18721
    crc_next[4]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[0];
18722
    crc_next[5]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[1];
18723
    crc_next[6]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[ 2];
18724
    crc_next[7]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[3];
18725
    crc_next[8]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[4];
18726
    crc_next[9]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[5];
18727
    crc_next[10] = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[6];
18728
    crc_next[11] = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[7];
18729
    crc_next[12] = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]) ^ crc[8];
18730
    crc_next[13] = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]) ^ crc[9];
18731
    crc_next[14] = (data_in[3] ^ data_in[2] ^ crc[30]    ^ crc[31]) ^ crc[10];
18732
    crc_next[15] = (data_in[3] ^ crc[31])   ^ crc[11];
18733
    crc_next[16] = (data_in[0] ^ crc[28])   ^ crc[12];
18734
    crc_next[17] = (data_in[1] ^ crc[29])   ^ crc[13];
18735
    crc_next[18] = (data_in[2] ^ crc[30])   ^ crc[14];
18736
    crc_next[19] = (data_in[3] ^ crc[31])   ^ crc[15];
18737
    crc_next[20] =  crc[16];
18738
    crc_next[21] =  crc[17];
18739
    crc_next[22] = (data_in[0] ^ crc[28])   ^ crc[18];
18740
    crc_next[23] = (data_in[1] ^ data_in[0] ^ crc[29]    ^ crc[28]) ^ crc[19];
18741
    crc_next[24] = (data_in[2] ^ data_in[1] ^ crc[30]    ^ crc[29]) ^ crc[20];
18742
    crc_next[25] = (data_in[3] ^ data_in[2] ^ crc[31]    ^ crc[30]) ^ crc[21];
18743
    crc_next[26] = (data_in[3] ^ data_in[0] ^ crc[31]    ^ crc[28]) ^ crc[22];
18744
    crc_next[27] = (data_in[1] ^ crc[29])   ^ crc[23];
18745
    crc_next[28] = (data_in[2] ^ crc[30])   ^ crc[24];
18746
    crc_next[29] = (data_in[3] ^ crc[31])   ^ crc[25];
18747
    crc_next[30] =  crc[26];
18748
    crc_next[31] =  crc[27];
18749
 
18750
    crc = crc_next;
18751
    crc_error = crc[31:0] != 32'hc704dd7b;  // CRC not equal to magic number
18752
    case (nibble_cnt)
18753
    9: crc_out = {!crc[24], !crc[25], !crc[26], !crc[27], !crc[28], !crc[29], !crc[30], !crc[31],
18754
                  !crc[16], !crc[17], !crc[18], !crc[19], !crc[20], !crc[21], !crc[22], !crc[23],
18755
                  !crc[ 8], !crc[ 9], !crc[10], !crc[11], !crc[12], !crc[13], !crc[14], !crc[15],
18756
                  !crc[ 0], !crc[ 1], !crc[ 2], !crc[ 3], !crc[ 4], !crc[ 5], !crc[ 6], !crc[ 7]};
18757
    default: crc_out = crc_out;
18758
    endcase
18759 169 mohor
    // wait for delta time
18760
    delta_t = !delta_t;
18761
    // increment address and load new data
18762 209 tadejm
    if ((word_cnt+3) == 7)//4)
18763 169 mohor
    begin
18764 209 tadejm
      // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
18765 169 mohor
      load_reg[31:24] = eth_phy.rx_mem[addr_cnt];
18766
      addr_cnt = addr_cnt + 1;
18767
      load_reg[23:16] = eth_phy.rx_mem[addr_cnt];
18768
      addr_cnt = addr_cnt + 1;
18769 209 tadejm
      load_reg[15: 8] = eth_phy.rx_mem[addr_cnt];
18770 169 mohor
      addr_cnt = addr_cnt + 1;
18771 209 tadejm
      load_reg[ 7: 0] = eth_phy.rx_mem[addr_cnt];
18772
      addr_cnt = addr_cnt + 1;
18773 169 mohor
    end
18774
    // set new load bit position
18775 209 tadejm
    if((word_cnt+3) == 31)
18776 169 mohor
      word_cnt = 16;
18777 209 tadejm
    else if ((word_cnt+3) == 23)
18778 169 mohor
      word_cnt = 8;
18779 209 tadejm
    else if ((word_cnt+3) == 15)
18780 169 mohor
      word_cnt = 0;
18781 209 tadejm
    else if ((word_cnt+3) == 7)
18782 169 mohor
      word_cnt = 24;
18783
    else
18784 209 tadejm
      word_cnt = word_cnt + 4;// - 4;
18785
    // decrement nibble counter
18786
    nibble_cnt = nibble_cnt - 1;
18787 169 mohor
    // wait for delta time
18788
    delta_t = !delta_t;
18789
  end // while
18790
  #1;
18791
end
18792
endtask // paralel_crc_phy_rx
18793
 
18794
// paralel CRC checking for MAC
18795
task paralel_crc_mac;
18796
  input  [31:0] start_addr; // start address
18797
  input  [31:0] len; // length of frame in Bytes without CRC length
18798
  input         plus_dribble_nibble; // if length is longer for one nibble
18799 209 tadejm
  output [31:0] crc_out;
18800
 
18801
  reg    [21:0] addr_cnt; // only 22 address lines
18802 169 mohor
  integer       word_cnt;
18803 209 tadejm
  integer       nibble_cnt;
18804 169 mohor
  reg    [31:0] load_reg;
18805
  reg           delta_t;
18806 209 tadejm
  reg    [31:0] crc_next;
18807
  reg    [31:0] crc;
18808
  reg           crc_error;
18809
  reg     [3:0] data_in;
18810
  integer       i;
18811 169 mohor
begin
18812
  #1 addr_cnt = start_addr[19:0];
18813
  // set starting point depending with which byte frame starts (e.g. if addr_cnt[1:0] == 0, then
18814
  //   MSB of the packet must be written to the LSB of Big ENDIAN Word [31:24])
18815
  if (addr_cnt[1:0] == 2'h1)
18816
    word_cnt = 16; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
18817
  else if (addr_cnt[1:0] == 2'h2)
18818
    word_cnt = 8; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
18819
  else if (addr_cnt[1:0] == 2'h3)
18820
    word_cnt = 0; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
18821
  else
18822
    word_cnt = 24; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
18823 209 tadejm
  crc = 32'hFFFF_FFFF; // INITIAL value
18824 169 mohor
  delta_t = 0;
18825
  // length must include 4 bytes of ZEROs, to generate CRC
18826 209 tadejm
  // get number of nibbles from Byte length (2^1 = 2)
18827 169 mohor
  if (plus_dribble_nibble)
18828 209 tadejm
    nibble_cnt = ((len + 4) << 1) + 1'b1; // one nibble longer
18829 169 mohor
  else
18830 209 tadejm
    nibble_cnt = ((len + 4) << 1);
18831 169 mohor
  load_reg = wb_slave.wb_memory[{12'h0, addr_cnt}];
18832 209 tadejm
  addr_cnt = addr_cnt + 4;
18833
  while (nibble_cnt > 0)
18834 169 mohor
  begin
18835
    // wait for delta time
18836
    delta_t = !delta_t;
18837
    // shift data in
18838 209 tadejm
 
18839
    if(nibble_cnt <= 8) // for additional 8 nibbles shift ZEROs in!
18840
      data_in[3:0] = 4'h0;
18841 169 mohor
    else
18842 209 tadejm
 
18843
      data_in[3:0] = {load_reg[word_cnt], load_reg[word_cnt+1], load_reg[word_cnt+2], load_reg[word_cnt+3]};
18844
    crc_next[0]  = (data_in[0] ^ crc[28]);
18845
    crc_next[1]  = (data_in[1] ^ data_in[0] ^ crc[28]    ^ crc[29]);
18846
    crc_next[2]  = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]);
18847
    crc_next[3]  = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]);
18848
    crc_next[4]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[0];
18849
    crc_next[5]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[1];
18850
    crc_next[6]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[ 2];
18851
    crc_next[7]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[3];
18852
    crc_next[8]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[4];
18853
    crc_next[9]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[5];
18854
    crc_next[10] = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[6];
18855
    crc_next[11] = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[7];
18856
    crc_next[12] = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]) ^ crc[8];
18857
    crc_next[13] = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]) ^ crc[9];
18858
    crc_next[14] = (data_in[3] ^ data_in[2] ^ crc[30]    ^ crc[31]) ^ crc[10];
18859
    crc_next[15] = (data_in[3] ^ crc[31])   ^ crc[11];
18860
    crc_next[16] = (data_in[0] ^ crc[28])   ^ crc[12];
18861
    crc_next[17] = (data_in[1] ^ crc[29])   ^ crc[13];
18862
    crc_next[18] = (data_in[2] ^ crc[30])   ^ crc[14];
18863
    crc_next[19] = (data_in[3] ^ crc[31])   ^ crc[15];
18864
    crc_next[20] =  crc[16];
18865
    crc_next[21] =  crc[17];
18866
    crc_next[22] = (data_in[0] ^ crc[28])   ^ crc[18];
18867
    crc_next[23] = (data_in[1] ^ data_in[0] ^ crc[29]    ^ crc[28]) ^ crc[19];
18868
    crc_next[24] = (data_in[2] ^ data_in[1] ^ crc[30]    ^ crc[29]) ^ crc[20];
18869
    crc_next[25] = (data_in[3] ^ data_in[2] ^ crc[31]    ^ crc[30]) ^ crc[21];
18870
    crc_next[26] = (data_in[3] ^ data_in[0] ^ crc[31]    ^ crc[28]) ^ crc[22];
18871
    crc_next[27] = (data_in[1] ^ crc[29])   ^ crc[23];
18872
    crc_next[28] = (data_in[2] ^ crc[30])   ^ crc[24];
18873
    crc_next[29] = (data_in[3] ^ crc[31])   ^ crc[25];
18874
    crc_next[30] =  crc[26];
18875
    crc_next[31] =  crc[27];
18876
 
18877
    crc = crc_next;
18878
    crc_error = crc[31:0] != 32'hc704dd7b;  // CRC not equal to magic number
18879
    case (nibble_cnt)
18880
    9: crc_out = {!crc[24], !crc[25], !crc[26], !crc[27], !crc[28], !crc[29], !crc[30], !crc[31],
18881
                  !crc[16], !crc[17], !crc[18], !crc[19], !crc[20], !crc[21], !crc[22], !crc[23],
18882
                  !crc[ 8], !crc[ 9], !crc[10], !crc[11], !crc[12], !crc[13], !crc[14], !crc[15],
18883
                  !crc[ 0], !crc[ 1], !crc[ 2], !crc[ 3], !crc[ 4], !crc[ 5], !crc[ 6], !crc[ 7]};
18884
    default: crc_out = crc_out;
18885
    endcase
18886 169 mohor
    // wait for delta time
18887
    delta_t = !delta_t;
18888 209 tadejm
    // increment address and load new data
18889
    if ((word_cnt+3) == 7)//4)
18890 169 mohor
    begin
18891 209 tadejm
      // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
18892
      load_reg = wb_slave.wb_memory[{12'h0, addr_cnt}];
18893 169 mohor
      addr_cnt = addr_cnt + 4;
18894
    end
18895 209 tadejm
    // set new load bit position
18896
    if((word_cnt+3) == 31)
18897 169 mohor
      word_cnt = 16;
18898 209 tadejm
    else if ((word_cnt+3) == 23)
18899 169 mohor
      word_cnt = 8;
18900 209 tadejm
    else if ((word_cnt+3) == 15)
18901 169 mohor
      word_cnt = 0;
18902 209 tadejm
    else if ((word_cnt+3) == 7)
18903 169 mohor
      word_cnt = 24;
18904
    else
18905 209 tadejm
      word_cnt = word_cnt + 4;// - 4;
18906
    // decrement nibble counter
18907
    nibble_cnt = nibble_cnt - 1;
18908 169 mohor
    // wait for delta time
18909
    delta_t = !delta_t;
18910
  end // while
18911
  #1;
18912
end
18913
endtask // paralel_crc_mac
18914
 
18915
// serial CRC checking for PHY TX
18916
task serial_crc_phy_tx;
18917
  input  [31:0] start_addr; // start address
18918
  input  [31:0] len; // length of frame in Bytes without CRC length
18919
  input         plus_dribble_nibble; // if length is longer for one nibble
18920
  output [31:0] crc;
18921
  reg    [21:0] addr_cnt; // only 22 address lines
18922
  integer       word_cnt;
18923
  integer       bit_cnt;
18924
  reg    [31:0] load_reg;
18925
  reg    [31:0] crc_shift_reg;
18926
  reg    [31:0] crc_store_reg;
18927
  reg           delta_t;
18928
begin
18929
  #1 addr_cnt = start_addr[21:0];
18930
  word_cnt = 24; // 27; // start of the frame - nibble granularity (MSbit first)
18931
  crc_store_reg = 32'hFFFF_FFFF; // INITIAL value
18932
  delta_t = 0;
18933
  // length must include 4 bytes of ZEROs, to generate CRC
18934
  // get number of bits from Byte length (2^3 = 8)
18935
  if (plus_dribble_nibble)
18936
    bit_cnt = ((len + 4) << 3) + 3'h4; // one nibble longer
18937
  else
18938
    bit_cnt = ((len + 4) << 3);
18939
  // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
18940
  load_reg[31:24] = eth_phy.tx_mem[addr_cnt];
18941
  addr_cnt = addr_cnt + 1;
18942
  load_reg[23:16] = eth_phy.tx_mem[addr_cnt];
18943
  addr_cnt = addr_cnt + 1;
18944
  load_reg[15: 8] = eth_phy.tx_mem[addr_cnt];
18945
  addr_cnt = addr_cnt + 1;
18946
  load_reg[ 7: 0] = eth_phy.tx_mem[addr_cnt];
18947
  addr_cnt = addr_cnt + 1;
18948
#1;
18949
  while (bit_cnt > 0)
18950
  begin
18951
    // wait for delta time
18952
    delta_t = !delta_t;
18953
#1;
18954
    // shift data in
18955
 
18956
    if(bit_cnt <= 32) // for additional 32 bits shift ZEROs in!
18957
     crc_shift_reg[0] = 1'b0               ^ crc_store_reg[31];
18958
    else
18959
 
18960
     crc_shift_reg[0] = load_reg[word_cnt] ^ crc_store_reg[31];
18961
    crc_shift_reg[1]  = crc_store_reg[0]   ^ crc_store_reg[31];
18962
    crc_shift_reg[2]  = crc_store_reg[1]   ^ crc_store_reg[31];
18963
    crc_shift_reg[3]  = crc_store_reg[2];
18964
    crc_shift_reg[4]  = crc_store_reg[3]   ^ crc_store_reg[31];
18965
    crc_shift_reg[5]  = crc_store_reg[4]   ^ crc_store_reg[31];
18966
    crc_shift_reg[6]  = crc_store_reg[5];
18967
    crc_shift_reg[7]  = crc_store_reg[6]   ^ crc_store_reg[31];
18968
    crc_shift_reg[8]  = crc_store_reg[7]   ^ crc_store_reg[31];
18969
    crc_shift_reg[9]  = crc_store_reg[8];
18970
    crc_shift_reg[10] = crc_store_reg[9]   ^ crc_store_reg[31];
18971
    crc_shift_reg[11] = crc_store_reg[10]  ^ crc_store_reg[31];
18972
    crc_shift_reg[12] = crc_store_reg[11]  ^ crc_store_reg[31];
18973
    crc_shift_reg[13] = crc_store_reg[12];
18974
    crc_shift_reg[14] = crc_store_reg[13];
18975
    crc_shift_reg[15] = crc_store_reg[14];
18976
    crc_shift_reg[16] = crc_store_reg[15]  ^ crc_store_reg[31];
18977
    crc_shift_reg[17] = crc_store_reg[16];
18978
    crc_shift_reg[18] = crc_store_reg[17];
18979
    crc_shift_reg[19] = crc_store_reg[18];
18980
    crc_shift_reg[20] = crc_store_reg[19];
18981
    crc_shift_reg[21] = crc_store_reg[20];
18982
    crc_shift_reg[22] = crc_store_reg[21]  ^ crc_store_reg[31];
18983
    crc_shift_reg[23] = crc_store_reg[22]  ^ crc_store_reg[31];
18984
    crc_shift_reg[24] = crc_store_reg[23];
18985
    crc_shift_reg[25] = crc_store_reg[24];
18986
    crc_shift_reg[26] = crc_store_reg[25]  ^ crc_store_reg[31];
18987
    crc_shift_reg[27] = crc_store_reg[26];
18988
    crc_shift_reg[28] = crc_store_reg[27];
18989
    crc_shift_reg[29] = crc_store_reg[28];
18990
    crc_shift_reg[30] = crc_store_reg[29];
18991
    crc_shift_reg[31] = crc_store_reg[30];
18992
    // wait for delta time
18993
    delta_t = !delta_t;
18994
 
18995
    // store previous data
18996
    crc_store_reg = crc_shift_reg;
18997
 
18998
    // put CRC out
18999
    case (bit_cnt)
19000
    33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 1:
19001
    begin
19002
      crc = crc_store_reg;
19003
      crc = {!crc[24], !crc[25], !crc[26], !crc[27], !crc[28], !crc[29], !crc[30], !crc[31],
19004
             !crc[16], !crc[17], !crc[18], !crc[19], !crc[20], !crc[21], !crc[22], !crc[23],
19005
             !crc[ 8], !crc[ 9], !crc[10], !crc[11], !crc[12], !crc[13], !crc[14], !crc[15],
19006
             !crc[ 0], !crc[ 1], !crc[ 2], !crc[ 3], !crc[ 4], !crc[ 5], !crc[ 6], !crc[ 7]};
19007
    end
19008
    default: crc = crc;
19009
    endcase
19010
 
19011
    // increment address and load new data
19012
#1;
19013
    if (word_cnt == 7)//4)
19014
    begin
19015
      // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
19016
      load_reg[31:24] = eth_phy.tx_mem[addr_cnt];
19017
//      load_reg[31:24] = {load_reg[28], load_reg[29], load_reg[30], load_reg[31], 
19018
//                         load_reg[24], load_reg[25], load_reg[26], load_reg[27]};
19019
      addr_cnt = addr_cnt + 1;
19020
      load_reg[23:16] = eth_phy.tx_mem[addr_cnt];
19021
//      load_reg[23:16] = {load_reg[20], load_reg[21], load_reg[22], load_reg[23], 
19022
//                         load_reg[16], load_reg[17], load_reg[18], load_reg[19]};
19023
      addr_cnt = addr_cnt + 1;
19024
      load_reg[15: 8] = eth_phy.tx_mem[addr_cnt];
19025
//      load_reg[15: 8] = {load_reg[12], load_reg[13], load_reg[14], load_reg[15], 
19026
//                         load_reg[ 8], load_reg[ 9], load_reg[10], load_reg[11]};
19027
      addr_cnt = addr_cnt + 1;
19028
      load_reg[ 7: 0] = eth_phy.tx_mem[addr_cnt];
19029
//      load_reg[ 7: 0] = {load_reg[ 4], load_reg[ 5], load_reg[ 6], load_reg[ 7], 
19030
//                         load_reg[ 0], load_reg[ 1], load_reg[ 2], load_reg[ 3]};
19031
      addr_cnt = addr_cnt + 1;
19032
    end
19033
#1;
19034
    // set new load bit position
19035
    if(word_cnt == 31)
19036
      word_cnt = 16;
19037
    else if (word_cnt == 23)
19038
      word_cnt = 8;
19039
    else if (word_cnt == 15)
19040
      word_cnt = 0;
19041
    else if (word_cnt == 7)
19042
      word_cnt = 24;
19043
 
19044
//   if(word_cnt == 24)
19045
//     word_cnt = 31;
19046
//   else if (word_cnt == 28)
19047
//     word_cnt = 19;
19048
//   else if (word_cnt == 16)
19049
//     word_cnt = 23;
19050
//   else if (word_cnt == 20)
19051
//     word_cnt = 11;
19052
//   else if(word_cnt == 8)
19053
//     word_cnt = 15;
19054
//   else if (word_cnt == 12)
19055
//     word_cnt = 3;
19056
//   else if (word_cnt == 0)
19057
//     word_cnt = 7;
19058
//   else if (word_cnt == 4)
19059
//     word_cnt = 27;
19060
    else
19061
      word_cnt = word_cnt + 1;// - 1;
19062
#1;
19063
    // decrement bit counter
19064
    bit_cnt = bit_cnt - 1;
19065
#1;
19066
    // wait for delta time
19067
    delta_t = !delta_t;
19068
  end // while
19069
 
19070
  #1;
19071
end
19072
endtask // serial_crc_phy_tx
19073
 
19074
// serial CRC calculating for PHY RX
19075
task serial_crc_phy_rx;
19076
  input  [31:0] start_addr; // start address
19077
  input  [31:0] len; // length of frame in Bytes without CRC length
19078
  input         plus_dribble_nibble; // if length is longer for one nibble
19079
  output [31:0] crc;
19080
  reg    [21:0] addr_cnt; // only 22 address lines
19081
  integer       word_cnt;
19082
  integer       bit_cnt;
19083
  reg    [31:0] load_reg;
19084
  reg    [31:0] crc_shift_reg;
19085
  reg    [31:0] crc_store_reg;
19086
  reg           delta_t;
19087
begin
19088
  #1 addr_cnt = start_addr[21:0];
19089
  word_cnt = 24; // start of the frame
19090
  crc_shift_reg = 0;
19091
  delta_t = 0;
19092
  // length must include 4 bytes of ZEROs, to generate CRC
19093
  // get number of bits from Byte length (2^3 = 8)
19094
  if (plus_dribble_nibble)
19095
    bit_cnt = ((len + 4) << 3) + 3'h4; // one nibble longer
19096
  else
19097
    bit_cnt = ((len + 4) << 3);
19098
  load_reg[31:24] = eth_phy.rx_mem[addr_cnt];
19099
  addr_cnt = addr_cnt + 1;
19100
  load_reg[23:16] = eth_phy.rx_mem[addr_cnt];
19101
  addr_cnt = addr_cnt + 1;
19102
  load_reg[15:8]  = eth_phy.rx_mem[addr_cnt];
19103
  addr_cnt = addr_cnt + 1;
19104
  load_reg[7:0]   = eth_phy.rx_mem[addr_cnt];
19105
 
19106
  while (bit_cnt > 0)
19107
  begin
19108
    // wait for delta time
19109
    delta_t = !delta_t;
19110
    // store previous data
19111
    crc_store_reg = crc_shift_reg;
19112
    // shift data in
19113
    if(bit_cnt <= 32) // for additional 32 bits shift ZEROs in!
19114
     crc_shift_reg[0] = 1'b0               ^ crc_store_reg[31];
19115
    else
19116
     crc_shift_reg[0] = load_reg[word_cnt] ^ crc_store_reg[31];
19117
    crc_shift_reg[1]  = crc_store_reg[0]   ^ crc_store_reg[31];
19118
    crc_shift_reg[2]  = crc_store_reg[1]   ^ crc_store_reg[31];
19119
    crc_shift_reg[3]  = crc_store_reg[2];
19120
    crc_shift_reg[4]  = crc_store_reg[3]   ^ crc_store_reg[31];
19121
    crc_shift_reg[5]  = crc_store_reg[4]   ^ crc_store_reg[31];
19122
    crc_shift_reg[6]  = crc_store_reg[5];
19123
    crc_shift_reg[7]  = crc_store_reg[6]   ^ crc_store_reg[31];
19124
    crc_shift_reg[8]  = crc_store_reg[7]   ^ crc_store_reg[31];
19125
    crc_shift_reg[9]  = crc_store_reg[8];
19126
    crc_shift_reg[10] = crc_store_reg[9]   ^ crc_store_reg[31];
19127
    crc_shift_reg[11] = crc_store_reg[10]  ^ crc_store_reg[31];
19128
    crc_shift_reg[12] = crc_store_reg[11]  ^ crc_store_reg[31];
19129
    crc_shift_reg[13] = crc_store_reg[12];
19130
    crc_shift_reg[14] = crc_store_reg[13];
19131
    crc_shift_reg[15] = crc_store_reg[14];
19132
    crc_shift_reg[16] = crc_store_reg[15]  ^ crc_store_reg[31];
19133
    crc_shift_reg[17] = crc_store_reg[16];
19134
    crc_shift_reg[18] = crc_store_reg[17];
19135
    crc_shift_reg[19] = crc_store_reg[18];
19136
    crc_shift_reg[20] = crc_store_reg[19];
19137
    crc_shift_reg[21] = crc_store_reg[20];
19138
    crc_shift_reg[22] = crc_store_reg[21]  ^ crc_store_reg[31];
19139
    crc_shift_reg[23] = crc_store_reg[22]  ^ crc_store_reg[31];
19140
    crc_shift_reg[24] = crc_store_reg[23];
19141
    crc_shift_reg[25] = crc_store_reg[24];
19142
    crc_shift_reg[26] = crc_store_reg[25]  ^ crc_store_reg[31];
19143
    crc_shift_reg[27] = crc_store_reg[26];
19144
    crc_shift_reg[28] = crc_store_reg[27];
19145
    crc_shift_reg[29] = crc_store_reg[28];
19146
    crc_shift_reg[30] = crc_store_reg[29];
19147
    crc_shift_reg[31] = crc_store_reg[30];
19148
    // wait for delta time
19149
    delta_t = !delta_t;
19150
    // increment address and load new data
19151
    if (word_cnt == 7)
19152
    begin
19153
      addr_cnt = addr_cnt + 1;
19154
      load_reg[31:24] = eth_phy.rx_mem[addr_cnt];
19155
      addr_cnt = addr_cnt + 1;
19156
      load_reg[23:16] = eth_phy.rx_mem[addr_cnt];
19157
      addr_cnt = addr_cnt + 1;
19158
      load_reg[15:8]  = eth_phy.rx_mem[addr_cnt];
19159
      addr_cnt = addr_cnt + 1;
19160
      load_reg[7:0]   = eth_phy.rx_mem[addr_cnt];
19161
    end
19162
    // set new load bit position
19163
    if(word_cnt == 31)
19164
      word_cnt = 16;
19165
    else if (word_cnt == 23)
19166
      word_cnt = 8;
19167
    else if (word_cnt == 15)
19168
      word_cnt = 0;
19169
    else if (word_cnt == 7)
19170
      word_cnt = 24;
19171
    else
19172
      word_cnt = word_cnt + 1;
19173
    // decrement bit counter
19174
    bit_cnt = bit_cnt - 1;
19175
    // wait for delta time
19176
    delta_t = !delta_t;
19177
  end // while
19178
 
19179
  // put CRC out
19180
  crc = crc_shift_reg;
19181
  #1;
19182
end
19183
endtask // serial_crc_phy_rx
19184
 
19185
// serial CRC checking for MAC
19186
task serial_crc_mac;
19187
  input  [31:0] start_addr; // start address
19188
  input  [31:0] len; // length of frame in Bytes without CRC length
19189
  input         plus_dribble_nibble; // if length is longer for one nibble
19190
  output [31:0] crc;
19191
  reg    [19:0] addr_cnt; // only 20 address lines
19192
  integer       word_cnt;
19193
  integer       bit_cnt;
19194
  reg    [31:0] load_reg;
19195
  reg    [31:0] crc_shift_reg;
19196
  reg    [31:0] crc_store_reg;
19197
  reg           delta_t;
19198
begin
19199
  #1 addr_cnt = start_addr[19:0];
19200
  // set starting point depending with which byte frame starts (e.g. if addr_cnt[1:0] == 0, then
19201
  //   MSB of the packet must be written to the LSB of Big ENDIAN Word [31:24])
19202
  if (addr_cnt[1:0] == 2'h1)
19203
    word_cnt = 16; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
19204
  else if (addr_cnt[1:0] == 2'h2)
19205
    word_cnt = 8; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
19206
  else if (addr_cnt[1:0] == 2'h3)
19207
    word_cnt = 0; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
19208
  else
19209
    word_cnt = 24; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
19210
 
19211
  crc_shift_reg = 0;
19212
  delta_t = 0;
19213
  // length must include 4 bytes of ZEROs, to generate CRC
19214
  // get number of bits from Byte length (2^3 = 8)
19215
  if (plus_dribble_nibble)
19216
    bit_cnt = ((len + 4) << 3) + 3'h4; // one nibble longer
19217
  else
19218
    bit_cnt = ((len + 4) << 3);
19219
  load_reg = wb_slave.wb_memory[{12'h0, addr_cnt}];
19220
 
19221
  while (bit_cnt > 0)
19222
  begin
19223
    // wait for delta time
19224
    delta_t = !delta_t;
19225
    // store previous data
19226
    crc_store_reg = crc_shift_reg;
19227
    // shift data in
19228
    if(bit_cnt <= 32) // for additional 32 bits shift ZEROs in!
19229
     crc_shift_reg[0] = 1'b0               ^ crc_store_reg[31];
19230
    else
19231
     crc_shift_reg[0] = load_reg[word_cnt] ^ crc_store_reg[31];
19232
    crc_shift_reg[1]  = crc_store_reg[0]   ^ crc_store_reg[31];
19233
    crc_shift_reg[2]  = crc_store_reg[1]   ^ crc_store_reg[31];
19234
    crc_shift_reg[3]  = crc_store_reg[2];
19235
    crc_shift_reg[4]  = crc_store_reg[3]   ^ crc_store_reg[31];
19236
    crc_shift_reg[5]  = crc_store_reg[4]   ^ crc_store_reg[31];
19237
    crc_shift_reg[6]  = crc_store_reg[5];
19238
    crc_shift_reg[7]  = crc_store_reg[6]   ^ crc_store_reg[31];
19239
    crc_shift_reg[8]  = crc_store_reg[7]   ^ crc_store_reg[31];
19240
    crc_shift_reg[9]  = crc_store_reg[8];
19241
    crc_shift_reg[10] = crc_store_reg[9]   ^ crc_store_reg[31];
19242
    crc_shift_reg[11] = crc_store_reg[10]  ^ crc_store_reg[31];
19243
    crc_shift_reg[12] = crc_store_reg[11]  ^ crc_store_reg[31];
19244
    crc_shift_reg[13] = crc_store_reg[12];
19245
    crc_shift_reg[14] = crc_store_reg[13];
19246
    crc_shift_reg[15] = crc_store_reg[14];
19247
    crc_shift_reg[16] = crc_store_reg[15]  ^ crc_store_reg[31];
19248
    crc_shift_reg[17] = crc_store_reg[16];
19249
    crc_shift_reg[18] = crc_store_reg[17];
19250
    crc_shift_reg[19] = crc_store_reg[18];
19251
    crc_shift_reg[20] = crc_store_reg[19];
19252
    crc_shift_reg[21] = crc_store_reg[20];
19253
    crc_shift_reg[22] = crc_store_reg[21]  ^ crc_store_reg[31];
19254
    crc_shift_reg[23] = crc_store_reg[22]  ^ crc_store_reg[31];
19255
    crc_shift_reg[24] = crc_store_reg[23];
19256
    crc_shift_reg[25] = crc_store_reg[24];
19257
    crc_shift_reg[26] = crc_store_reg[25]  ^ crc_store_reg[31];
19258
    crc_shift_reg[27] = crc_store_reg[26];
19259
    crc_shift_reg[28] = crc_store_reg[27];
19260
    crc_shift_reg[29] = crc_store_reg[28];
19261
    crc_shift_reg[30] = crc_store_reg[29];
19262
    crc_shift_reg[31] = crc_store_reg[30];
19263
    // wait for delta time
19264
    delta_t = !delta_t;
19265
    // increment address and load new data for Big ENDIAN Bytes (Litle ENDIAN bits)
19266
    if (word_cnt == 7)
19267
    begin
19268
      addr_cnt = addr_cnt + 4;
19269
      load_reg = wb_slave.wb_memory[{12'h0, addr_cnt}];
19270
    end
19271
    // set new load bit position for Big ENDIAN Bytes (Litle ENDIAN bits)
19272
    if(word_cnt == 31)
19273
      word_cnt = 16;
19274
    else if (word_cnt == 23)
19275
      word_cnt = 8;
19276
    else if (word_cnt == 15)
19277
      word_cnt = 0;
19278
    else if (word_cnt == 7)
19279
      word_cnt = 24;
19280
    else
19281
      word_cnt = word_cnt + 1;
19282
    // decrement bit counter
19283
    bit_cnt = bit_cnt - 1;
19284
    // wait for delta time
19285
    delta_t = !delta_t;
19286
  end // while
19287
 
19288
  // put CRC out
19289
  crc = crc_shift_reg;
19290
  #1;
19291
end
19292
endtask // serial_crc_mac
19293
 
19294
//////////////////////////////////////////////////////////////
19295
// MIIM Basic tasks
19296
//////////////////////////////////////////////////////////////
19297
 
19298
task reset_mii; //  MII module
19299
  reg [31:0] tmp;
19300
  reg [31:0] tmp_no_rst;
19301
begin
19302
  // read MII mode register first
19303
  wbm_read(`ETH_MIIMODER, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19304
  // set reset bit - write back to MII mode register with RESET bit
19305
  wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_RST | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19306
  // clear reset bit - write back to MII mode register without RESET bit
19307
  tmp_no_rst = `ETH_MIIMODER_RST;
19308
  tmp_no_rst = ~tmp_no_rst;
19309
  wbm_write(`ETH_MIIMODER, (tmp_no_rst & tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19310
end
19311
endtask // reset_mii
19312
 
19313
task mii_set_clk_div; // set clock divider for MII clock
19314
  input [7:0]  clk_div;
19315
begin
19316
  // MII mode register
19317
  wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_CLKDIV & clk_div), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19318
end
19319
endtask // mii_set_clk_div
19320
 
19321
 
19322
task check_mii_busy; // MII - check if BUSY
19323
  reg [31:0] tmp;
19324
begin
19325
  @(posedge wb_clk);
19326
  // MII read status register
19327
  wbm_read(`ETH_MIISTATUS, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19328
  while(tmp[`ETH_MIISTATUS_BUSY] !== 1'b0) //`ETH_MIISTATUS_BUSY
19329
  begin
19330
    @(posedge wb_clk);
19331
    wbm_read(`ETH_MIISTATUS, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19332
  end
19333
end
19334
endtask // check_mii_busy
19335
 
19336
 
19337
task check_mii_scan_valid; // MII - check if SCAN data are valid
19338
  reg [31:0] tmp;
19339
begin
19340
  @(posedge wb_clk);
19341
  // MII read status register
19342
  wbm_read(`ETH_MIISTATUS, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19343
  while(tmp[`ETH_MIISTATUS_NVALID] !== 1'b0) //`ETH_MIISTATUS_NVALID
19344
  begin
19345
    @(posedge wb_clk);
19346
    wbm_read(`ETH_MIISTATUS, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19347
  end
19348
end
19349
endtask // check_mii_scan_valid
19350
 
19351
 
19352
task mii_write_req; // requests write to MII
19353
  input [4:0]  phy_addr;
19354
  input [4:0]  reg_addr;
19355
  input [15:0] data_in;
19356
begin
19357
  // MII address, PHY address = 1, command register address = 0
19358
  wbm_write(`ETH_MIIADDRESS, (`ETH_MIIADDRESS_FIAD & phy_addr) | (`ETH_MIIADDRESS_RGAD & (reg_addr << 8)),
19359
            4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19360
  // MII TX data
19361
  wbm_write(`ETH_MIITX_DATA, {16'h0000, data_in}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19362
  // MII command
19363
  wbm_write(`ETH_MIICOMMAND, `ETH_MIICOMMAND_WCTRLDATA, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19364
  @(posedge wb_clk);
19365
end
19366
endtask // mii_write_req
19367
 
19368
 
19369
task mii_read_req; // requests read from MII
19370
  input [4:0]  phy_addr;
19371
  input [4:0]  reg_addr;
19372
begin
19373
  // MII address, PHY address = 1, command register address = 0
19374
  wbm_write(`ETH_MIIADDRESS, (`ETH_MIIADDRESS_FIAD & phy_addr) | (`ETH_MIIADDRESS_RGAD & (reg_addr << 8)),
19375
            4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19376
  // MII command
19377
  wbm_write(`ETH_MIICOMMAND, `ETH_MIICOMMAND_RSTAT, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19378
  @(posedge wb_clk);
19379
end
19380
endtask // mii_read_req
19381
 
19382
 
19383
task mii_scan_req; // requests scan from MII
19384
  input [4:0]  phy_addr;
19385
  input [4:0]  reg_addr;
19386
begin
19387
  // MII address, PHY address = 1, command register address = 0
19388
  wbm_write(`ETH_MIIADDRESS, (`ETH_MIIADDRESS_FIAD & phy_addr) | (`ETH_MIIADDRESS_RGAD & (reg_addr << 8)),
19389
            4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19390
  // MII command
19391
  wbm_write(`ETH_MIICOMMAND, `ETH_MIICOMMAND_SCANSTAT, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19392
  @(posedge wb_clk);
19393
end
19394
endtask // mii_scan_req
19395
 
19396
 
19397
task mii_scan_finish; // finish scan from MII
19398
begin
19399
  // MII command
19400
  wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
19401
  @(posedge wb_clk);
19402
end
19403
endtask // mii_scan_finish
19404
 
19405
//////////////////////////////////////////////////////////////
19406
// Log files and memory tasks
19407
//////////////////////////////////////////////////////////////
19408
 
19409
task clear_memories;
19410
  reg    [22:0]  adr_i;
19411
  reg            delta_t;
19412
begin
19413
  for (adr_i = 0; adr_i < 4194304; adr_i = adr_i + 1)
19414
  begin
19415
    eth_phy.rx_mem[adr_i[21:0]] = 0;
19416
    eth_phy.tx_mem[adr_i[21:0]] = 0;
19417
    wb_slave.wb_memory[adr_i[21:2]] = 0;
19418
  end
19419
end
19420
endtask // clear_memories
19421
 
19422 243 tadejm
task clear_buffer_descriptors;
19423
  reg    [8:0]  adr_i;
19424
  reg            delta_t;
19425
begin
19426
  delta_t = 0;
19427
  for (adr_i = 0; adr_i < 256; adr_i = adr_i + 1)
19428
  begin
19429
    wbm_write((`TX_BD_BASE + {adr_i[7:0], 2'b0}), 32'h0, 4'hF, 1, 4'h1, 4'h1);
19430
    delta_t = !delta_t;
19431
  end
19432
end
19433
endtask // clear_buffer_descriptors
19434
 
19435 169 mohor
task test_note;
19436
  input [799:0] test_note ;
19437
  reg   [799:0] display_note ;
19438
begin
19439
  display_note = test_note;
19440
  while ( display_note[799:792] == 0 )
19441
    display_note = display_note << 8 ;
19442
  $fdisplay( tb_log_file, " " ) ;
19443
  $fdisplay( tb_log_file, "NOTE: %s", display_note ) ;
19444
  $fdisplay( tb_log_file, " " ) ;
19445
end
19446
endtask // test_note
19447
 
19448
task test_heading;
19449
  input [799:0] test_heading ;
19450
  reg   [799:0] display_test ;
19451
begin
19452
  display_test = test_heading;
19453
  while ( display_test[799:792] == 0 )
19454
    display_test = display_test << 8 ;
19455
  $fdisplay( tb_log_file, "  ***************************************************************************************" ) ;
19456
  $fdisplay( tb_log_file, "  ***************************************************************************************" ) ;
19457
  $fdisplay( tb_log_file, "  Heading: %s", display_test ) ;
19458
  $fdisplay( tb_log_file, "  ***************************************************************************************" ) ;
19459
  $fdisplay( tb_log_file, "  ***************************************************************************************" ) ;
19460
  $fdisplay( tb_log_file, " " ) ;
19461
end
19462
endtask // test_heading
19463
 
19464
 
19465
task test_fail ;
19466
  input [7999:0] failure_reason ;
19467
//  reg   [8007:0] display_failure ;
19468
  reg   [7999:0] display_failure ;
19469
  reg   [799:0] display_test ;
19470
begin
19471
  tests_failed = tests_failed + 1 ;
19472
 
19473
  display_failure = failure_reason; // {failure_reason, "!"} ;
19474
  while ( display_failure[7999:7992] == 0 )
19475
    display_failure = display_failure << 8 ;
19476
 
19477
  display_test = test_name ;
19478
  while ( display_test[799:792] == 0 )
19479
    display_test = display_test << 8 ;
19480
 
19481
  $fdisplay( tb_log_file, "    *************************************************************************************" ) ;
19482
  $fdisplay( tb_log_file, "    At time: %t ", $time ) ;
19483
  $fdisplay( tb_log_file, "    Test: %s", display_test ) ;
19484
  $fdisplay( tb_log_file, "    *FAILED* because") ;
19485
  $fdisplay( tb_log_file, "    %s", display_failure ) ;
19486
  $fdisplay( tb_log_file, "    *************************************************************************************" ) ;
19487
  $fdisplay( tb_log_file, " " ) ;
19488
 
19489
 `ifdef STOP_ON_FAILURE
19490
    #20 $stop ;
19491
 `endif
19492
end
19493
endtask // test_fail
19494
 
19495
 
19496
task test_ok ;
19497
  reg [799:0] display_test ;
19498
begin
19499
  tests_successfull = tests_successfull + 1 ;
19500
 
19501
  display_test = test_name ;
19502
  while ( display_test[799:792] == 0 )
19503
    display_test = display_test << 8 ;
19504
 
19505
  $fdisplay( tb_log_file, "    *************************************************************************************" ) ;
19506
  $fdisplay( tb_log_file, "    At time: %t ", $time ) ;
19507
  $fdisplay( tb_log_file, "    Test: %s", display_test ) ;
19508
  $fdisplay( tb_log_file, "    reported *SUCCESSFULL*! ") ;
19509
  $fdisplay( tb_log_file, "    *************************************************************************************" ) ;
19510
  $fdisplay( tb_log_file, " " ) ;
19511
end
19512
endtask // test_ok
19513
 
19514
 
19515
task test_summary;
19516
begin
19517
  $fdisplay(tb_log_file, "**************************** Ethernet MAC test summary **********************************") ;
19518
  $fdisplay(tb_log_file, "Tests performed:   %d", tests_successfull + tests_failed) ;
19519
  $fdisplay(tb_log_file, "Failed tests   :   %d", tests_failed) ;
19520
  $fdisplay(tb_log_file, "Successfull tests: %d", tests_successfull) ;
19521
  $fdisplay(tb_log_file, "**************************** Ethernet MAC test summary **********************************") ;
19522
  $fclose(tb_log_file) ;
19523
end
19524
endtask // test_summary
19525
 
19526
 
19527 116 mohor
endmodule

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