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[/] [ethmac/] [trunk/] [bench/] [verilog/] [wb_bus_mon.v] - Blame information for rev 170

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1 169 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  File name "wb_bus_mon.v"                                    ////
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////                                                              ////
5 170 mohor
////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/projects/ethmac/                   ////
7 169 mohor
////                                                              ////
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////  Author(s):                                                  ////
9 170 mohor
////      - Miha Dolenc (mihad@opencores.org)                     ////
10 169 mohor
////                                                              ////
11 170 mohor
////  All additional information is available in the README.pdf   ////
12 169 mohor
////  file.                                                       ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
17 170 mohor
//// Copyright (C) 2002 Authors                                   ////
18 169 mohor
////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
42
// CVS Revision History
43
//
44
// $Log: not supported by cvs2svn $
45 170 mohor
// Revision 1.1  2002/09/13 11:57:20  mohor
46
// New testbench. Thanks to Tadej M - "The Spammer".
47
//
48 169 mohor
// Revision 1.1  2002/02/01 13:39:43  mihad
49
// Initial testbench import. Still under development
50
//
51
// Revision 1.1  2001/08/06 18:12:58  mihad
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// Pocasi delamo kompletno zadevo
53
//
54
//
55
 
56
`include "wb_model_defines.v"
57
// WISHBONE bus monitor module - it connects to WISHBONE master signals and
58
// monitors for any illegal combinations appearing on the bus.
59
module WB_BUS_MON(
60
                    CLK_I,
61
                    RST_I,
62
                    ACK_I,
63
                    ADDR_O,
64
                    CYC_O,
65
                    DAT_I,
66
                    DAT_O,
67
                    ERR_I,
68
                    RTY_I,
69
                    SEL_O,
70
                    STB_O,
71
                    WE_O,
72
                    TAG_I,
73
                    TAG_O,
74
                    CAB_O,
75
                    log_file_desc
76
                  ) ;
77
 
78
input                           CLK_I  ;
79
input                           RST_I  ;
80
input                           ACK_I  ;
81
input   [(`WB_ADDR_WIDTH-1):0]  ADDR_O ;
82
input                           CYC_O  ;
83
input   [(`WB_DATA_WIDTH-1):0]  DAT_I  ;
84
input   [(`WB_DATA_WIDTH-1):0]  DAT_O  ;
85
input                           ERR_I  ;
86
input                           RTY_I  ;
87
input   [(`WB_SEL_WIDTH-1):0]   SEL_O  ;
88
input                           STB_O  ;
89
input                           WE_O   ;
90
input   [(`WB_TAG_WIDTH-1):0] TAG_I  ;
91
input   [(`WB_TAG_WIDTH-1):0] TAG_O  ;
92
input                           CAB_O  ;
93
input [31:0] log_file_desc ;
94
 
95
always@(posedge CLK_I or posedge RST_I)
96
begin
97
    if (RST_I)
98
    begin
99
        // when reset is applied, all control signals must be low
100
        if (CYC_O)
101
        begin
102
            $display("*E (%0t) CYC_O active under reset", $time) ;
103
            $fdisplay(log_file_desc, "*E (%0t)(%m)CYC_O active under reset", $time) ;
104
        end
105
        if (STB_O)
106
        begin
107
            $display("*E (%0t) STB_O active under reset", $time) ;
108
            $fdisplay(log_file_desc, "*E (%0t)(%m)STB_O active under reset", $time) ;
109
        end
110
        /*if (ACK_I)
111
            $display("ACK_I active under reset") ;*/
112
        if (ERR_I)
113
        begin
114
            $display("*E (%0t) ERR_I active under reset", $time) ;
115
            $fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I active under reset", $time) ;
116
        end
117
        if (RTY_I)
118
        begin
119
            $display("*E (%0t) RTY_I active under reset", $time) ;
120
            $fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I active under reset", $time) ;
121
        end
122
        if (CAB_O)
123
        begin
124
            $display("*E (%0t) CAB_O active under reset", $time) ;
125
            $fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O active under reset", $time) ;
126
        end
127
    end // reset
128
    else
129
    if (~CYC_O)
130
    begin
131
        // when cycle indicator is low, all control signals must be low
132
        if (STB_O)
133
        begin
134
            $display("*E (%0t) STB_O active without CYC_O being active", $time) ;
135
            $fdisplay(log_file_desc, "*E (%0t)(%m)STB_O active without CYC_O being active", $time) ;
136
        end
137
        if (ACK_I)
138
        begin
139
            $display("*E (%0t) ACK_I active without CYC_O being active", $time) ;
140
            $fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I active without CYC_O being active", $time) ;
141
        end
142
        if (ERR_I)
143
        begin
144
            $display("*E (%0t) ERR_I active without CYC_O being active", $time) ;
145
            $fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I active without CYC_O being active", $time) ;
146
        end
147
        if (RTY_I)
148
        begin
149
            $display("*E (%0t) RTY_I active without CYC_O being active", $time) ;
150
            $fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I active without CYC_O being active", $time) ;
151
        end
152
        if (CAB_O)
153
        begin
154
            $display("*E (%0t) CAB_O active without CYC_O being active", $time) ;
155
            $fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O active without CYC_O being active", $time) ;
156
        end
157
    end // ~CYC_O
158
end
159
 
160
reg [`WB_DATA_WIDTH-1:0] previous_data ;
161
reg [`WB_ADDR_WIDTH-1:0] previous_address ;
162
reg [`WB_SEL_WIDTH-1:0] previous_sel ;
163
reg                     previous_stb ;
164
reg                     previous_ack ;
165
reg                     previous_err ;
166
reg                     previous_rty ;
167
reg                     previous_cyc ;
168
reg can_change ;
169
 
170
always@(posedge CLK_I or posedge RST_I)
171
begin
172
    if (RST_I)
173
    begin
174
        previous_stb <= 1'b0 ;
175
        previous_ack <= 1'b0 ;
176
        previous_err <= 1'b0 ;
177
        previous_rty <= 1'b0 ;
178
        previous_cyc <= 1'b0 ;
179
    end
180
    else
181
    begin
182
        previous_stb <= STB_O ;
183
        previous_ack <= ACK_I ;
184
        previous_err <= ERR_I ;
185
        previous_rty <= RTY_I ;
186
        previous_cyc <= CYC_O ;
187
    end
188
end
189
 
190
// cycle monitor
191
always@(posedge CLK_I)
192
begin
193
    if (CYC_O && ~RST_I) // cycle in progress
194
    begin
195
        if (STB_O)
196
        begin
197
            // check for two control signals active at same edge
198
            if ( ACK_I && RTY_I )
199
            begin
200
                $display("*E (%0t) ACK_I and RTY_I asserted at the same time during cycle", $time) ;
201
                $fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I and RTY_I asserted at the same time during cycle", $time) ;
202
            end
203
            if ( ACK_I && ERR_I )
204
            begin
205
                $display("*E (%0t) ACK_I and ERR_I asserted at the same time during cycle", $time) ;
206
                $fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I and ERR_I asserted at the same time during cycle", $time) ;
207
            end
208
            if ( RTY_I && ERR_I )
209
            begin
210
                $display("*E (%0t) RTY_I and ERR_I asserted at the same time during cycle", $time) ;
211
                $fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I and ERR_I asserted at the same time during cycle", $time) ;
212
            end
213
 
214
            if ( can_change !== 1 )
215
            begin
216
                if ( ADDR_O !== previous_address )
217
                begin
218
                    $display("*E (%0t) WB bus monitor detected address change in the middle of the cycle!", $time) ;
219
                    $fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected address change in the middle of the cycle!", $time) ;
220
                end
221
 
222
                if ( SEL_O !== previous_sel )
223
                begin
224
                    $display("*E (%0t) WB bus monitor detected select lines changed in the middle of the cycle!", $time) ;
225
                    $fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected select lines changed in the middle of the cycle!", $time) ;
226
                end
227
 
228
                if ( (WE_O !== 0) && ( DAT_O !== previous_data ) )
229
                begin
230
                    $display("*E (%0t) WB bus monitor detected data lines changed in the middle of the cycle!", $time) ;
231
                    $fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected data lines changed in the middle of the cycle!", $time) ;
232
                end
233
            end
234
 
235
            if ( ACK_I || RTY_I || ERR_I )
236
                can_change       = 1 ;
237
            else
238
            begin
239
                previous_data    = DAT_O ;
240
                previous_address = ADDR_O ;
241
                previous_sel     = SEL_O ;
242
                can_change = 0 ;
243
            end
244
 
245
        end // STB_O
246
        else
247
        begin //~STB_O
248
            // while STB_O is inactive, only ACK_I is allowed to be active
249
            if ( ERR_I )
250
            begin
251
                $display("*E (%0t) ERR_I asserted during cycle without STB_O", $time) ;
252
                $fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I asserted during cycle without STB_O", $time) ;
253
            end
254
            if ( RTY_I )
255
            begin
256
                $display("*E (%0t) RTY_I asserted during cycle without STB_O", $time) ;
257
                $fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I asserted during cycle without STB_O", $time) ;
258
            end
259
 
260
            if ((previous_ack !== 1) && (previous_err !== 1) && (previous_rty !== 1) && (previous_stb !== 0))
261
            begin
262
                $display("STB_O de-asserted without reception of slave response") ;
263
                $fdisplay(log_file_desc, "STB_O de-asserted without reception of slave response") ;
264
            end
265
 
266
            can_change = 1 ;
267
        end   // ~STB_O
268
    end // cycle in progress
269
    else if (!RST_I)
270
    begin
271
        // cycle not in progress anymore
272
        can_change = 1 ;
273
        if ((previous_ack !== 1) && (previous_err !== 1) && (previous_rty !== 1) && (previous_stb !== 0))
274
        begin
275
            $display("STB_O de-asserted without reception of slave response") ;
276
            $fdisplay(log_file_desc, "STB_O de-asserted without reception of slave response") ;
277
        end
278
    end
279
end // cycle monitor
280
 
281
// CAB_O monitor - CAB_O musn't change during one cycle
282
reg [1:0] first_cab_val ;
283
always@(posedge CLK_I or RST_I)
284
begin
285
    if ((CYC_O === 0) || RST_I)
286
        first_cab_val <= 2'b00 ;
287
    else
288
    begin
289
        // cycle in progress - is this first clock edge in a cycle ?
290
        if (first_cab_val[1] === 1'b0)
291
            first_cab_val <= {1'b1, CAB_O} ;
292
        else if ( first_cab_val[0] !== CAB_O )
293
        begin
294
            $display("*E (%0t) CAB_O value changed during cycle", $time) ;
295
            $fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O value changed during cycle", $time) ;
296
        end
297
    end
298
end // CAB_O monitor
299
 
300
// WE_O monitor for consecutive address bursts
301
reg [1:0] first_we_val ;
302
always@(posedge CLK_I or posedge RST_I)
303
begin
304
    if (~CYC_O || ~CAB_O || RST_I)
305
        first_we_val <= 2'b00 ;
306
    else
307
    if (STB_O)
308
    begin
309
        // cycle in progress - is this first clock edge in a cycle ?
310
        if (first_we_val[1] == 1'b0)
311
            first_we_val <= {1'b1, WE_O} ;
312
        else if ( first_we_val[0] != WE_O )
313
        begin
314
            $display("*E (%0t) WE_O value changed during CAB cycle", $time) ;
315
            $fdisplay(log_file_desc, "*E (%0t)(%m)WE_O value changed during CAB cycle", $time) ;
316
        end
317
    end
318
end // CAB_O monitor
319
 
320
// address monitor for consecutive address bursts
321
reg [`WB_ADDR_WIDTH:0] address ;
322
always@(posedge CLK_I or posedge RST_I)
323
begin
324
    if (~CYC_O || ~CAB_O || RST_I)
325
        address <= {(`WB_ADDR_WIDTH + 1){1'b0}} ;
326
    else
327
    begin
328
        if (STB_O && ACK_I)
329
        begin
330
            if (address[`WB_ADDR_WIDTH] == 1'b0)
331
                address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
332
            else
333
            begin
334
                if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
335
                begin
336
                    $display("*E (%0t) Consecutive address burst address incrementing incorrect", $time) ;
337
                    $fdisplay(log_file_desc, "*E (%0t)(%m)Consecutive address burst address incrementing incorrect", $time) ;
338
                end
339
                else
340
                    address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
341
            end
342
        end
343
    end
344
end // address monitor
345
 
346
// data monitor
347
always@(posedge CLK_I or posedge RST_I)
348
begin
349
    if (CYC_O && STB_O && ~RST_I)
350
    begin
351
        if ( ((^ADDR_O) !== 1'b1) && ((^ADDR_O) !== 1'b0) )
352
        begin
353
            $display("*E (%0t) Master provided invalid address and qualified it with STB_O", $time) ;
354
            $fdisplay(log_file_desc, "*E (%0t)(%m)Master provided invalid address and qualified it with STB_O", $time) ;
355
        end
356
        if ( WE_O )
357
        begin
358
            if (
359
                (SEL_O[0] && (((^DAT_O[7:0])   !== 1'b0) && ((^DAT_O[7:0])   !== 1'b1))) ||
360
                (SEL_O[1] && (((^DAT_O[15:8])  !== 1'b0) && ((^DAT_O[15:8])  !== 1'b1))) ||
361
                (SEL_O[2] && (((^DAT_O[23:16]) !== 1'b0) && ((^DAT_O[23:16]) !== 1'b1))) ||
362
                (SEL_O[3] && (((^DAT_O[31:24]) !== 1'b0) && ((^DAT_O[31:24]) !== 1'b1)))
363
               )
364
            begin
365
                $display("*E (%0t) Master provided invalid data during write and qualified it with STB_O", $time) ;
366
                $fdisplay(log_file_desc, "*E (%0t)(%m)Master provided invalid data during write and qualified it with STB_O", $time) ;
367
                $display("*E (%0t) Byte select value: SEL_O = %b, Data bus value: DAT_O =  %h ", $time, SEL_O, DAT_O) ;
368
                $fdisplay(log_file_desc, "*E (%0t)(%m)Byte select value: SEL_O = %b, Data bus value: DAT_O =  %h ", $time, SEL_O, DAT_O) ;
369
            end
370
 
371
        end
372
        else
373
        if (~WE_O && ACK_I)
374
        begin
375
            if (
376
                (SEL_O[0] && (((^DAT_I[7:0])   !== 1'b0) && ((^DAT_I[7:0])   !== 1'b1))) ||
377
                (SEL_O[1] && (((^DAT_I[15:8])  !== 1'b0) && ((^DAT_I[15:8])  !== 1'b1))) ||
378
                (SEL_O[2] && (((^DAT_I[23:16]) !== 1'b0) && ((^DAT_I[23:16]) !== 1'b1))) ||
379
                (SEL_O[3] && (((^DAT_I[31:24]) !== 1'b0) && ((^DAT_I[31:24]) !== 1'b1)))
380
               )
381
            begin
382
                $display("*E (%0t) Slave provided invalid data during read and qualified it with ACK_I", $time) ;
383
                $fdisplay(log_file_desc, "*E (%0t)(%m)Slave provided invalid data during read and qualified it with ACK_I", $time) ;
384
                $display("*E (%0t) Byte select value: SEL_O = %b, Data bus value: DAT_I =  %h ", $time, SEL_O, DAT_I) ;
385
                $fdisplay(log_file_desc, "*E (%0t)(%m)Byte select value: SEL_O = %b, Data bus value: DAT_I =  %h ", $time, SEL_O, DAT_I) ;
386
            end
387
        end
388
    end
389
end
390
 
391
initial
392
begin
393
    previous_data = 0 ;
394
    previous_address = 0 ;
395
    can_change = 1 ;
396
end
397
endmodule // BUS_MON

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