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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "wb_bus_mon.v"                                    ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////  All additional information is available in the README.pdf   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/09/13 12:29:14  mohor
// Headers changed.
//
// Revision 1.1  2002/09/13 11:57:20  mohor
// New testbench. Thanks to Tadej M - "The Spammer".
//
// Revision 1.1  2002/02/01 13:39:43  mihad
// Initial testbench import. Still under development
//
// Revision 1.1  2001/08/06 18:12:58  mihad
// Pocasi delamo kompletno zadevo
//
//
 
`include "timescale.v"
`include "wb_model_defines.v"
// WISHBONE bus monitor module - it connects to WISHBONE master signals and
// monitors for any illegal combinations appearing on the bus.
module WB_BUS_MON(
                    CLK_I,
                    RST_I,
                    ACK_I,
                    ADDR_O,
                    CYC_O,
                    DAT_I,
                    DAT_O,
                    ERR_I,
                    RTY_I,
                    SEL_O,
                    STB_O,
                    WE_O,
                    TAG_I,
                    TAG_O,
                    CAB_O,
                    log_file_desc
                  ) ;
 
input                           CLK_I  ;
input                           RST_I  ;
input                           ACK_I  ;
input   [(`WB_ADDR_WIDTH-1):0]  ADDR_O ;
input                           CYC_O  ;
input   [(`WB_DATA_WIDTH-1):0]  DAT_I  ;
input   [(`WB_DATA_WIDTH-1):0]  DAT_O  ;
input                           ERR_I  ;
input                           RTY_I  ;
input   [(`WB_SEL_WIDTH-1):0]   SEL_O  ;
input                           STB_O  ;
input                           WE_O   ;
input   [(`WB_TAG_WIDTH-1):0] TAG_I  ;
input   [(`WB_TAG_WIDTH-1):0] TAG_O  ;
input                           CAB_O  ;
input [31:0] log_file_desc ;
 
always@(posedge CLK_I or posedge RST_I)
begin
    if (RST_I)
    begin
        // when reset is applied, all control signals must be low
        if (CYC_O)
        begin
            $display("*E (%0t) CYC_O active under reset", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)CYC_O active under reset", $time) ;
        end
        if (STB_O)
        begin
            $display("*E (%0t) STB_O active under reset", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)STB_O active under reset", $time) ;
        end
        /*if (ACK_I)
            $display("ACK_I active under reset") ;*/
        if (ERR_I)
        begin
            $display("*E (%0t) ERR_I active under reset", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I active under reset", $time) ;
        end
        if (RTY_I)
        begin
            $display("*E (%0t) RTY_I active under reset", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I active under reset", $time) ;
        end
        if (CAB_O)
        begin
            $display("*E (%0t) CAB_O active under reset", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O active under reset", $time) ;
        end
    end // reset
    else
    if (~CYC_O)
    begin
        // when cycle indicator is low, all control signals must be low
        if (STB_O)
        begin
            $display("*E (%0t) STB_O active without CYC_O being active", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)STB_O active without CYC_O being active", $time) ;
        end
        if (ACK_I)
        begin
            $display("*E (%0t) ACK_I active without CYC_O being active", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I active without CYC_O being active", $time) ;
        end
        if (ERR_I)
        begin
            $display("*E (%0t) ERR_I active without CYC_O being active", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I active without CYC_O being active", $time) ;
        end
        if (RTY_I)
        begin
            $display("*E (%0t) RTY_I active without CYC_O being active", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I active without CYC_O being active", $time) ;
        end
        if (CAB_O)
        begin
            $display("*E (%0t) CAB_O active without CYC_O being active", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O active without CYC_O being active", $time) ;
        end
    end // ~CYC_O
end
 
reg [`WB_DATA_WIDTH-1:0] previous_data ;
reg [`WB_ADDR_WIDTH-1:0] previous_address ;
reg [`WB_SEL_WIDTH-1:0] previous_sel ;
reg                     previous_stb ;
reg                     previous_ack ;
reg                     previous_err ;
reg                     previous_rty ;
reg                     previous_cyc ;
reg can_change ;
 
always@(posedge CLK_I or posedge RST_I)
begin
    if (RST_I)
    begin
        previous_stb <= 1'b0 ;
        previous_ack <= 1'b0 ;
        previous_err <= 1'b0 ;
        previous_rty <= 1'b0 ;
        previous_cyc <= 1'b0 ;
    end
    else
    begin
        previous_stb <= STB_O ;
        previous_ack <= ACK_I ;
        previous_err <= ERR_I ;
        previous_rty <= RTY_I ;
        previous_cyc <= CYC_O ;
    end
end
 
// cycle monitor
always@(posedge CLK_I)
begin
    if (CYC_O && ~RST_I) // cycle in progress
    begin
        if (STB_O)
        begin
            // check for two control signals active at same edge
            if ( ACK_I && RTY_I )
            begin
                $display("*E (%0t) ACK_I and RTY_I asserted at the same time during cycle", $time) ;
                $fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I and RTY_I asserted at the same time during cycle", $time) ;
            end
            if ( ACK_I && ERR_I )
            begin
                $display("*E (%0t) ACK_I and ERR_I asserted at the same time during cycle", $time) ;
                $fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I and ERR_I asserted at the same time during cycle", $time) ;
            end
            if ( RTY_I && ERR_I )
            begin
                $display("*E (%0t) RTY_I and ERR_I asserted at the same time during cycle", $time) ;
                $fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I and ERR_I asserted at the same time during cycle", $time) ;
            end
 
            if ( can_change !== 1 )
            begin
                if ( ADDR_O !== previous_address )
                begin
                    $display("*E (%0t) WB bus monitor detected address change in the middle of the cycle!", $time) ;
                    $fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected address change in the middle of the cycle!", $time) ;
                end
 
                if ( SEL_O !== previous_sel )
                begin
                    $display("*E (%0t) WB bus monitor detected select lines changed in the middle of the cycle!", $time) ;
                    $fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected select lines changed in the middle of the cycle!", $time) ;
                end
 
                if ( (WE_O !== 0) && ( DAT_O !== previous_data ) )
                begin
                    $display("*E (%0t) WB bus monitor detected data lines changed in the middle of the cycle!", $time) ;
                    $fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected data lines changed in the middle of the cycle!", $time) ;
                end
            end
 
            if ( ACK_I || RTY_I || ERR_I )
                can_change       = 1 ;
            else
            begin
                previous_data    = DAT_O ;
                previous_address = ADDR_O ;
                previous_sel     = SEL_O ;
                can_change = 0 ;
            end
 
        end // STB_O
        else
        begin //~STB_O
            // while STB_O is inactive, only ACK_I is allowed to be active
            if ( ERR_I )
            begin
                $display("*E (%0t) ERR_I asserted during cycle without STB_O", $time) ;
                $fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I asserted during cycle without STB_O", $time) ;
            end
            if ( RTY_I )
            begin
                $display("*E (%0t) RTY_I asserted during cycle without STB_O", $time) ;
                $fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I asserted during cycle without STB_O", $time) ;
            end
 
            if ((previous_ack !== 1) && (previous_err !== 1) && (previous_rty !== 1) && (previous_stb !== 0))
            begin
                $display("STB_O de-asserted without reception of slave response") ;
                $fdisplay(log_file_desc, "STB_O de-asserted without reception of slave response") ;
            end
 
            can_change = 1 ;
        end   // ~STB_O
    end // cycle in progress
    else if (!RST_I)
    begin
        // cycle not in progress anymore
        can_change = 1 ;
        if ((previous_ack !== 1) && (previous_err !== 1) && (previous_rty !== 1) && (previous_stb !== 0))
        begin
            $display("STB_O de-asserted without reception of slave response") ;
            $fdisplay(log_file_desc, "STB_O de-asserted without reception of slave response") ;
        end
    end
end // cycle monitor
 
// CAB_O monitor - CAB_O musn't change during one cycle
reg [1:0] first_cab_val ;
always@(posedge CLK_I or RST_I)
begin
    if ((CYC_O === 0) || RST_I)
        first_cab_val <= 2'b00 ;
    else
    begin
        // cycle in progress - is this first clock edge in a cycle ?
        if (first_cab_val[1] === 1'b0)
            first_cab_val <= {1'b1, CAB_O} ;
        else if ( first_cab_val[0] !== CAB_O )
        begin
            $display("*E (%0t) CAB_O value changed during cycle", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O value changed during cycle", $time) ;
        end
    end
end // CAB_O monitor
 
// WE_O monitor for consecutive address bursts
reg [1:0] first_we_val ;
always@(posedge CLK_I or posedge RST_I)
begin
    if (~CYC_O || ~CAB_O || RST_I)
        first_we_val <= 2'b00 ;
    else
    if (STB_O)
    begin
        // cycle in progress - is this first clock edge in a cycle ?
        if (first_we_val[1] == 1'b0)
            first_we_val <= {1'b1, WE_O} ;
        else if ( first_we_val[0] != WE_O )
        begin
            $display("*E (%0t) WE_O value changed during CAB cycle", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)WE_O value changed during CAB cycle", $time) ;
        end
    end
end // CAB_O monitor
 
// address monitor for consecutive address bursts
reg [`WB_ADDR_WIDTH:0] address ;
always@(posedge CLK_I or posedge RST_I)
begin
    if (~CYC_O || ~CAB_O || RST_I)
        address <= {(`WB_ADDR_WIDTH + 1){1'b0}} ;
    else
    begin
        if (STB_O && ACK_I)
        begin
            if (address[`WB_ADDR_WIDTH] == 1'b0)
                address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
            else
            begin
                if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
                begin
                    $display("*E (%0t) Consecutive address burst address incrementing incorrect", $time) ;
                    $fdisplay(log_file_desc, "*E (%0t)(%m)Consecutive address burst address incrementing incorrect", $time) ;
                end
                else
                    address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
            end
        end
    end
end // address monitor
 
// data monitor
always@(posedge CLK_I or posedge RST_I)
begin
    if (CYC_O && STB_O && ~RST_I)
    begin
        if ( ((^ADDR_O) !== 1'b1) && ((^ADDR_O) !== 1'b0) )
        begin
            $display("*E (%0t) Master provided invalid address and qualified it with STB_O", $time) ;
            $fdisplay(log_file_desc, "*E (%0t)(%m)Master provided invalid address and qualified it with STB_O", $time) ;
        end
        if ( WE_O )
        begin
            if (
                (SEL_O[0] && (((^DAT_O[7:0])   !== 1'b0) && ((^DAT_O[7:0])   !== 1'b1))) ||
                (SEL_O[1] && (((^DAT_O[15:8])  !== 1'b0) && ((^DAT_O[15:8])  !== 1'b1))) ||
                (SEL_O[2] && (((^DAT_O[23:16]) !== 1'b0) && ((^DAT_O[23:16]) !== 1'b1))) ||
                (SEL_O[3] && (((^DAT_O[31:24]) !== 1'b0) && ((^DAT_O[31:24]) !== 1'b1)))
               )
            begin
                $display("*E (%0t) Master provided invalid data during write and qualified it with STB_O", $time) ;
                $fdisplay(log_file_desc, "*E (%0t)(%m)Master provided invalid data during write and qualified it with STB_O", $time) ;
                $display("*E (%0t) Byte select value: SEL_O = %b, Data bus value: DAT_O =  %h ", $time, SEL_O, DAT_O) ;
                $fdisplay(log_file_desc, "*E (%0t)(%m)Byte select value: SEL_O = %b, Data bus value: DAT_O =  %h ", $time, SEL_O, DAT_O) ;
            end
 
        end
        else
        if (~WE_O && ACK_I)
        begin
            if (
                (SEL_O[0] && (((^DAT_I[7:0])   !== 1'b0) && ((^DAT_I[7:0])   !== 1'b1))) ||
                (SEL_O[1] && (((^DAT_I[15:8])  !== 1'b0) && ((^DAT_I[15:8])  !== 1'b1))) ||
                (SEL_O[2] && (((^DAT_I[23:16]) !== 1'b0) && ((^DAT_I[23:16]) !== 1'b1))) ||
                (SEL_O[3] && (((^DAT_I[31:24]) !== 1'b0) && ((^DAT_I[31:24]) !== 1'b1)))
               )
            begin
                $display("*E (%0t) Slave provided invalid data during read and qualified it with ACK_I", $time) ;
                $fdisplay(log_file_desc, "*E (%0t)(%m)Slave provided invalid data during read and qualified it with ACK_I", $time) ;
                $display("*E (%0t) Byte select value: SEL_O = %b, Data bus value: DAT_I =  %h ", $time, SEL_O, DAT_I) ;
                $fdisplay(log_file_desc, "*E (%0t)(%m)Byte select value: SEL_O = %b, Data bus value: DAT_I =  %h ", $time, SEL_O, DAT_I) ;
            end
        end
    end
end
 
initial
begin
    previous_data = 0 ;
    previous_address = 0 ;
    can_change = 1 ;
end
endmodule // BUS_MON

Line No.	Rev	Author	Line
1	169	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "wb_bus_mon.v" ////`
4			`//// ////`
5	170	mohor	`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects/ethmac/ ////`
7	169	mohor	`//// ////`
8			`//// Author(s): ////`
9	170	mohor	`//// - Miha Dolenc (mihad@opencores.org) ////`
10	169	mohor	`//// ////`
11	170	mohor	`//// All additional information is available in the README.pdf ////`
12	169	mohor	`//// file. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17	170	mohor	`//// Copyright (C) 2002 Authors ////`
18	169	mohor	`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45	209	tadejm	`// Revision 1.2 2002/09/13 12:29:14 mohor`
46			`// Headers changed.`
47			`//`
48	170	mohor	`// Revision 1.1 2002/09/13 11:57:20 mohor`
49			`// New testbench. Thanks to Tadej M - "The Spammer".`
50			`//`
51	169	mohor	`// Revision 1.1 2002/02/01 13:39:43 mihad`
52			`// Initial testbench import. Still under development`
53			`//`
54			`// Revision 1.1 2001/08/06 18:12:58 mihad`
55			`// Pocasi delamo kompletno zadevo`
56			`//`
57			`//`
58
59	209	tadejm	`include "timescale.v"
60	169	mohor	`include "wb_model_defines.v"
61			`// WISHBONE bus monitor module - it connects to WISHBONE master signals and`
62			`// monitors for any illegal combinations appearing on the bus.`
63			`module WB_BUS_MON(`
64			`CLK_I,`
65			`RST_I,`
66			`ACK_I,`
67			`ADDR_O,`
68			`CYC_O,`
69			`DAT_I,`
70			`DAT_O,`
71			`ERR_I,`
72			`RTY_I,`
73			`SEL_O,`
74			`STB_O,`
75			`WE_O,`
76			`TAG_I,`
77			`TAG_O,`
78			`CAB_O,`
79			`log_file_desc`
80			`) ;`
81
82			`input CLK_I ;`
83			`input RST_I ;`
84			`input ACK_I ;`
85			input [(`WB_ADDR_WIDTH-1):0] ADDR_O ;
86			`input CYC_O ;`
87			input [(`WB_DATA_WIDTH-1):0] DAT_I ;
88			input [(`WB_DATA_WIDTH-1):0] DAT_O ;
89			`input ERR_I ;`
90			`input RTY_I ;`
91			input [(`WB_SEL_WIDTH-1):0] SEL_O ;
92			`input STB_O ;`
93			`input WE_O ;`
94			input [(`WB_TAG_WIDTH-1):0] TAG_I ;
95			input [(`WB_TAG_WIDTH-1):0] TAG_O ;
96			`input CAB_O ;`
97			`input [31:0] log_file_desc ;`
98
99			`always@(posedge CLK_I or posedge RST_I)`
100			`begin`
101			`if (RST_I)`
102			`begin`
103			`// when reset is applied, all control signals must be low`
104			`if (CYC_O)`
105			`begin`
106			`$display("*E (%0t) CYC_O active under reset", $time) ;`
107			`$fdisplay(log_file_desc, "*E (%0t)(%m)CYC_O active under reset", $time) ;`
108			`end`
109			`if (STB_O)`
110			`begin`
111			`$display("*E (%0t) STB_O active under reset", $time) ;`
112			`$fdisplay(log_file_desc, "*E (%0t)(%m)STB_O active under reset", $time) ;`
113			`end`
114			`/*if (ACK_I)`
115			`$display("ACK_I active under reset") ;*/`
116			`if (ERR_I)`
117			`begin`
118			`$display("*E (%0t) ERR_I active under reset", $time) ;`
119			`$fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I active under reset", $time) ;`
120			`end`
121			`if (RTY_I)`
122			`begin`
123			`$display("*E (%0t) RTY_I active under reset", $time) ;`
124			`$fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I active under reset", $time) ;`
125			`end`
126			`if (CAB_O)`
127			`begin`
128			`$display("*E (%0t) CAB_O active under reset", $time) ;`
129			`$fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O active under reset", $time) ;`
130			`end`
131			`end // reset`
132			`else`
133			`if (~CYC_O)`
134			`begin`
135			`// when cycle indicator is low, all control signals must be low`
136			`if (STB_O)`
137			`begin`
138			`$display("*E (%0t) STB_O active without CYC_O being active", $time) ;`
139			`$fdisplay(log_file_desc, "*E (%0t)(%m)STB_O active without CYC_O being active", $time) ;`
140			`end`
141			`if (ACK_I)`
142			`begin`
143			`$display("*E (%0t) ACK_I active without CYC_O being active", $time) ;`
144			`$fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I active without CYC_O being active", $time) ;`
145			`end`
146			`if (ERR_I)`
147			`begin`
148			`$display("*E (%0t) ERR_I active without CYC_O being active", $time) ;`
149			`$fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I active without CYC_O being active", $time) ;`
150			`end`
151			`if (RTY_I)`
152			`begin`
153			`$display("*E (%0t) RTY_I active without CYC_O being active", $time) ;`
154			`$fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I active without CYC_O being active", $time) ;`
155			`end`
156			`if (CAB_O)`
157			`begin`
158			`$display("*E (%0t) CAB_O active without CYC_O being active", $time) ;`
159			`$fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O active without CYC_O being active", $time) ;`
160			`end`
161			`end // ~CYC_O`
162			`end`
163
164			reg [`WB_DATA_WIDTH-1:0] previous_data ;
165			reg [`WB_ADDR_WIDTH-1:0] previous_address ;
166			reg [`WB_SEL_WIDTH-1:0] previous_sel ;
167			`reg previous_stb ;`
168			`reg previous_ack ;`
169			`reg previous_err ;`
170			`reg previous_rty ;`
171			`reg previous_cyc ;`
172			`reg can_change ;`
173
174			`always@(posedge CLK_I or posedge RST_I)`
175			`begin`
176			`if (RST_I)`
177			`begin`
178			`previous_stb <= 1'b0 ;`
179			`previous_ack <= 1'b0 ;`
180			`previous_err <= 1'b0 ;`
181			`previous_rty <= 1'b0 ;`
182			`previous_cyc <= 1'b0 ;`
183			`end`
184			`else`
185			`begin`
186			`previous_stb <= STB_O ;`
187			`previous_ack <= ACK_I ;`
188			`previous_err <= ERR_I ;`
189			`previous_rty <= RTY_I ;`
190			`previous_cyc <= CYC_O ;`
191			`end`
192			`end`
193
194			`// cycle monitor`
195			`always@(posedge CLK_I)`
196			`begin`
197			`if (CYC_O && ~RST_I) // cycle in progress`
198			`begin`
199			`if (STB_O)`
200			`begin`
201			`// check for two control signals active at same edge`
202			`if ( ACK_I && RTY_I )`
203			`begin`
204			`$display("*E (%0t) ACK_I and RTY_I asserted at the same time during cycle", $time) ;`
205			`$fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I and RTY_I asserted at the same time during cycle", $time) ;`
206			`end`
207			`if ( ACK_I && ERR_I )`
208			`begin`
209			`$display("*E (%0t) ACK_I and ERR_I asserted at the same time during cycle", $time) ;`
210			`$fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I and ERR_I asserted at the same time during cycle", $time) ;`
211			`end`
212			`if ( RTY_I && ERR_I )`
213			`begin`
214			`$display("*E (%0t) RTY_I and ERR_I asserted at the same time during cycle", $time) ;`
215			`$fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I and ERR_I asserted at the same time during cycle", $time) ;`
216			`end`
217
218			`if ( can_change !== 1 )`
219			`begin`
220			`if ( ADDR_O !== previous_address )`
221			`begin`
222			`$display("*E (%0t) WB bus monitor detected address change in the middle of the cycle!", $time) ;`
223			`$fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected address change in the middle of the cycle!", $time) ;`
224			`end`
225
226			`if ( SEL_O !== previous_sel )`
227			`begin`
228			`$display("*E (%0t) WB bus monitor detected select lines changed in the middle of the cycle!", $time) ;`
229			`$fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected select lines changed in the middle of the cycle!", $time) ;`
230			`end`
231
232			`if ( (WE_O !== 0) && ( DAT_O !== previous_data ) )`
233			`begin`
234			`$display("*E (%0t) WB bus monitor detected data lines changed in the middle of the cycle!", $time) ;`
235			`$fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected data lines changed in the middle of the cycle!", $time) ;`
236			`end`
237			`end`
238
239			`if ( ACK_I \|\| RTY_I \|\| ERR_I )`
240			`can_change = 1 ;`
241			`else`
242			`begin`
243			`previous_data = DAT_O ;`
244			`previous_address = ADDR_O ;`
245			`previous_sel = SEL_O ;`
246			`can_change = 0 ;`
247			`end`
248
249			`end // STB_O`
250			`else`
251			`begin //~STB_O`
252			`// while STB_O is inactive, only ACK_I is allowed to be active`
253			`if ( ERR_I )`
254			`begin`
255			`$display("*E (%0t) ERR_I asserted during cycle without STB_O", $time) ;`
256			`$fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I asserted during cycle without STB_O", $time) ;`
257			`end`
258			`if ( RTY_I )`
259			`begin`
260			`$display("*E (%0t) RTY_I asserted during cycle without STB_O", $time) ;`
261			`$fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I asserted during cycle without STB_O", $time) ;`
262			`end`
263
264			`if ((previous_ack !== 1) && (previous_err !== 1) && (previous_rty !== 1) && (previous_stb !== 0))`
265			`begin`
266			`$display("STB_O de-asserted without reception of slave response") ;`
267			`$fdisplay(log_file_desc, "STB_O de-asserted without reception of slave response") ;`
268			`end`
269
270			`can_change = 1 ;`
271			`end // ~STB_O`
272			`end // cycle in progress`
273			`else if (!RST_I)`
274			`begin`
275			`// cycle not in progress anymore`
276			`can_change = 1 ;`
277			`if ((previous_ack !== 1) && (previous_err !== 1) && (previous_rty !== 1) && (previous_stb !== 0))`
278			`begin`
279			`$display("STB_O de-asserted without reception of slave response") ;`
280			`$fdisplay(log_file_desc, "STB_O de-asserted without reception of slave response") ;`
281			`end`
282			`end`
283			`end // cycle monitor`
284
285			`// CAB_O monitor - CAB_O musn't change during one cycle`
286			`reg [1:0] first_cab_val ;`
287			`always@(posedge CLK_I or RST_I)`
288			`begin`
289			`if ((CYC_O === 0) \|\| RST_I)`
290			`first_cab_val <= 2'b00 ;`
291			`else`
292			`begin`
293			`// cycle in progress - is this first clock edge in a cycle ?`
294			`if (first_cab_val[1] === 1'b0)`
295			`first_cab_val <= {1'b1, CAB_O} ;`
296			`else if ( first_cab_val[0] !== CAB_O )`
297			`begin`
298			`$display("*E (%0t) CAB_O value changed during cycle", $time) ;`
299			`$fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O value changed during cycle", $time) ;`
300			`end`
301			`end`
302			`end // CAB_O monitor`
303
304			`// WE_O monitor for consecutive address bursts`
305			`reg [1:0] first_we_val ;`
306			`always@(posedge CLK_I or posedge RST_I)`
307			`begin`
308			`if (~CYC_O \|\| ~CAB_O \|\| RST_I)`
309			`first_we_val <= 2'b00 ;`
310			`else`
311			`if (STB_O)`
312			`begin`
313			`// cycle in progress - is this first clock edge in a cycle ?`
314			`if (first_we_val[1] == 1'b0)`
315			`first_we_val <= {1'b1, WE_O} ;`
316			`else if ( first_we_val[0] != WE_O )`
317			`begin`
318			`$display("*E (%0t) WE_O value changed during CAB cycle", $time) ;`
319			`$fdisplay(log_file_desc, "*E (%0t)(%m)WE_O value changed during CAB cycle", $time) ;`
320			`end`
321			`end`
322			`end // CAB_O monitor`
323
324			`// address monitor for consecutive address bursts`
325			reg [`WB_ADDR_WIDTH:0] address ;
326			`always@(posedge CLK_I or posedge RST_I)`
327			`begin`
328			`if (~CYC_O \|\| ~CAB_O \|\| RST_I)`
329			address <= {(`WB_ADDR_WIDTH + 1){1'b0}} ;
330			`else`
331			`begin`
332			`if (STB_O && ACK_I)`
333			`begin`
334			if (address[`WB_ADDR_WIDTH] == 1'b0)
335			address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
336			`else`
337			`begin`
338			if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
339			`begin`
340			`$display("*E (%0t) Consecutive address burst address incrementing incorrect", $time) ;`
341			`$fdisplay(log_file_desc, "*E (%0t)(%m)Consecutive address burst address incrementing incorrect", $time) ;`
342			`end`
343			`else`
344			address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
345			`end`
346			`end`
347			`end`
348			`end // address monitor`
349
350			`// data monitor`
351			`always@(posedge CLK_I or posedge RST_I)`
352			`begin`
353			`if (CYC_O && STB_O && ~RST_I)`
354			`begin`
355			`if ( ((^ADDR_O) !== 1'b1) && ((^ADDR_O) !== 1'b0) )`
356			`begin`
357			`$display("*E (%0t) Master provided invalid address and qualified it with STB_O", $time) ;`
358			`$fdisplay(log_file_desc, "*E (%0t)(%m)Master provided invalid address and qualified it with STB_O", $time) ;`
359			`end`
360			`if ( WE_O )`
361			`begin`
362			`if (`
363			`(SEL_O[0] && (((^DAT_O[7:0]) !== 1'b0) && ((^DAT_O[7:0]) !== 1'b1))) \|\|`
364			`(SEL_O[1] && (((^DAT_O[15:8]) !== 1'b0) && ((^DAT_O[15:8]) !== 1'b1))) \|\|`
365			`(SEL_O[2] && (((^DAT_O[23:16]) !== 1'b0) && ((^DAT_O[23:16]) !== 1'b1))) \|\|`
366			`(SEL_O[3] && (((^DAT_O[31:24]) !== 1'b0) && ((^DAT_O[31:24]) !== 1'b1)))`
367			`)`
368			`begin`
369			`$display("*E (%0t) Master provided invalid data during write and qualified it with STB_O", $time) ;`
370			`$fdisplay(log_file_desc, "*E (%0t)(%m)Master provided invalid data during write and qualified it with STB_O", $time) ;`
371			`$display("*E (%0t) Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", $time, SEL_O, DAT_O) ;`
372			`$fdisplay(log_file_desc, "*E (%0t)(%m)Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", $time, SEL_O, DAT_O) ;`
373			`end`
374
375			`end`
376			`else`
377			`if (~WE_O && ACK_I)`
378			`begin`
379			`if (`
380			`(SEL_O[0] && (((^DAT_I[7:0]) !== 1'b0) && ((^DAT_I[7:0]) !== 1'b1))) \|\|`
381			`(SEL_O[1] && (((^DAT_I[15:8]) !== 1'b0) && ((^DAT_I[15:8]) !== 1'b1))) \|\|`
382			`(SEL_O[2] && (((^DAT_I[23:16]) !== 1'b0) && ((^DAT_I[23:16]) !== 1'b1))) \|\|`
383			`(SEL_O[3] && (((^DAT_I[31:24]) !== 1'b0) && ((^DAT_I[31:24]) !== 1'b1)))`
384			`)`
385			`begin`
386			`$display("*E (%0t) Slave provided invalid data during read and qualified it with ACK_I", $time) ;`
387			`$fdisplay(log_file_desc, "*E (%0t)(%m)Slave provided invalid data during read and qualified it with ACK_I", $time) ;`
388			`$display("*E (%0t) Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", $time, SEL_O, DAT_I) ;`
389			`$fdisplay(log_file_desc, "*E (%0t)(%m)Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", $time, SEL_O, DAT_I) ;`
390			`end`
391			`end`
392			`end`
393			`end`
394
395			`initial`
396			`begin`
397			`previous_data = 0 ;`
398			`previous_address = 0 ;`
399			`can_change = 1 ;`
400			`end`
401			`endmodule // BUS_MON`

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