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mohor |
// WISHBONE frequency in GHz
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`define WB_FREQ 0.100
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// memory frequency in GHz
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`define MEM_FREQ 0.100
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// setup and hold time definitions for WISHBONE - used in BFMs for signal generation
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`define Tsetup 4
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`define Thold 1
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// how many clock cycles should model wait for design's response - integer 32 bit value
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`define WAIT_FOR_RESPONSE 1023
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// maximum number of transactions allowed in single call to block or cab transfer routines
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`define MAX_BLK_SIZE 1024
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// maximum retry terminations allowed for WISHBONE master to repeat an access
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`define WB_TB_MAX_RTY 0
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// some common types and defines
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`define WB_ADDR_WIDTH 32
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`define WB_DATA_WIDTH 32
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`define WB_SEL_WIDTH `WB_DATA_WIDTH/8
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`define WB_TAG_WIDTH 1
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`define WB_ADDR_TYPE [(`WB_ADDR_WIDTH - 1):0]
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`define WB_DATA_TYPE [(`WB_DATA_WIDTH - 1):0]
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`define WB_SEL_TYPE [(`WB_SEL_WIDTH - 1):0]
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`define WB_TAG_TYPE [(`WB_TAG_WIDTH - 1):0]
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// read cycle stimulus - consists of:
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// - address field - which address read will be performed from
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// - sel field - what byte select value should be
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// - tag field - what tag values should be put on the bus
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`define READ_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
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`define READ_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
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`define READ_ADDRESS [(`WB_ADDR_WIDTH - 1):0]
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`define READ_SEL [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH - 1):`WB_ADDR_WIDTH]
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`define READ_TAG_STIM [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_SEL_WIDTH)]
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// read cycle return type consists of:
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// - read data field
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// - tag field received from WISHBONE
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// - wishbone slave response fields - ACK, ERR and RTY
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// - test bench error indicator (when testcase has not used wb master model properly)
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// - how much data was actually transfered
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`define READ_RETURN_TYPE [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):0]
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`define READ_DATA [(32 + `WB_DATA_WIDTH + 4 - 1):32 + 4]
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`define READ_TAG_RET [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):(`WB_DATA_WIDTH + 32 + 4)]
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`define READ_RETURN_LENGTH (32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1)
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// write cycle stimulus type consists of
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// - address field
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// - data field
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// - sel field
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// - tag field
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`define WRITE_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
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`define WRITE_ADDRESS [(`WB_ADDR_WIDTH - 1):0]
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`define WRITE_DATA [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH - 1):`WB_ADDR_WIDTH]
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`define WRITE_SEL [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH)]
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`define WRITE_TAG_STIM [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH)]
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// length of WRITE_STIMULUS
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`define WRITE_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
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// write cycle return type consists of:
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// - test bench error indicator (when testcase has not used wb master model properly)
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// - wishbone slave response fields - ACK, ERR and RTY
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// - tag field received from WISHBONE
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// - how much data was actually transfered
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`define WRITE_RETURN_TYPE [(32 + 4 + `WB_TAG_WIDTH - 1):0]
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`define WRITE_TAG_RET [(32 + 4 + `WB_TAG_WIDTH - 1):32 + 4]
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// this four fields are common to both read and write routines return values
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`define TB_ERROR_BIT [0]
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`define CYC_ACK [1]
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`define CYC_RTY [2]
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`define CYC_ERR [3]
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`define CYC_RESPONSE [3:1]
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`define CYC_ACTUAL_TRANSFER [35:4]
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// block transfer flags
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`define WB_TRANSFER_FLAGS [41:0]
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// consists of:
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// - number of transfer cycles to perform
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// - flag that enables retry termination handling - if disabled, block transfer routines will return on any termination other than acknowledge
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// - flag indicating CAB transfer is to be performed - ignored by all single transfer routines
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// - number of initial wait states to insert
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// - number of subsequent wait states to insert
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`define WB_TRANSFER_SIZE [41:10]
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`define WB_TRANSFER_AUTO_RTY [8]
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`define WB_TRANSFER_CAB [9]
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`define INIT_WAITS [3:0]
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`define SUBSEQ_WAITS [7:4]
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// wb slave response
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`define ACK_RESPONSE 3'b100
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`define ERR_RESPONSE 3'b010
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`define RTY_RESPONSE 3'b001
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`define NO_RESPONSE 3'b000
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