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1 129 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_cop.v                                                   ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 129 mohor
////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001, 2002 Authors                             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 286 mohor
// Revision 1.3  2002/10/10 16:43:59  mohor
45
// Minor $display change.
46
//
47 212 mohor
// Revision 1.2  2002/09/09 12:54:13  mohor
48
// error acknowledge cycle termination added to display.
49
//
50 160 mohor
// Revision 1.1  2002/08/14 17:16:07  mohor
51
// Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
52
// interfaces:
53
// - Host connects to the master interface
54
// - Ethernet master (DMA) connects to the second master interface
55
// - Memory interface connects to the slave interface
56
// - Ethernet slave interface (access to registers and BDs) connects to second
57
//   slave interface
58 129 mohor
//
59
//
60
//
61
//
62 160 mohor
//
63 129 mohor
 
64 286 mohor
`include "eth_defines.v"
65 129 mohor
`include "timescale.v"
66
 
67
module eth_cop
68
(
69
  // WISHBONE common
70
  wb_clk_i, wb_rst_i,
71
 
72
  // WISHBONE MASTER 1
73
  m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i,  m1_wb_dat_o,
74
  m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o,
75
  m1_wb_err_o,
76
 
77
  // WISHBONE MASTER 2
78
  m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i,  m2_wb_dat_o,
79
  m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o,
80
  m2_wb_err_o,
81
 
82
  // WISHBONE slave 1
83
        s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o,  s1_wb_cyc_o,
84
        s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i,
85
        s1_wb_dat_o,
86
 
87
  // WISHBONE slave 2
88
        s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o,  s2_wb_cyc_o,
89
        s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
90
        s2_wb_dat_o
91
);
92
 
93
parameter Tp=1;
94
 
95
// WISHBONE common
96
input wb_clk_i, wb_rst_i;
97
 
98
// WISHBONE MASTER 1
99
input  [31:0] m1_wb_adr_i, m1_wb_dat_i;
100
input   [3:0] m1_wb_sel_i;
101
input         m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i;
102
output [31:0] m1_wb_dat_o;
103
output        m1_wb_ack_o, m1_wb_err_o;
104
 
105
// WISHBONE MASTER 2
106
input  [31:0] m2_wb_adr_i, m2_wb_dat_i;
107
input   [3:0] m2_wb_sel_i;
108
input         m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i;
109
output [31:0] m2_wb_dat_o;
110
output        m2_wb_ack_o, m2_wb_err_o;
111
 
112
// WISHBONE slave 1
113
input  [31:0] s1_wb_dat_i;
114
input         s1_wb_ack_i, s1_wb_err_i;
115
output [31:0] s1_wb_adr_o, s1_wb_dat_o;
116
output  [3:0] s1_wb_sel_o;
117
output        s1_wb_we_o,  s1_wb_cyc_o, s1_wb_stb_o;
118
 
119
// WISHBONE slave 2
120
input  [31:0] s2_wb_dat_i;
121
input         s2_wb_ack_i, s2_wb_err_i;
122
output [31:0] s2_wb_adr_o, s2_wb_dat_o;
123
output  [3:0] s2_wb_sel_o;
124
output        s2_wb_we_o,  s2_wb_cyc_o, s2_wb_stb_o;
125
 
126
reg           m1_in_progress;
127
reg           m2_in_progress;
128
reg    [31:0] s1_wb_adr_o;
129
reg     [3:0] s1_wb_sel_o;
130
reg           s1_wb_we_o;
131
reg    [31:0] s1_wb_dat_o;
132
reg           s1_wb_cyc_o;
133
reg           s1_wb_stb_o;
134
reg    [31:0] s2_wb_adr_o;
135
reg     [3:0] s2_wb_sel_o;
136
reg           s2_wb_we_o;
137
reg    [31:0] s2_wb_dat_o;
138
reg           s2_wb_cyc_o;
139
reg           s2_wb_stb_o;
140
 
141
reg           m1_wb_ack_o;
142
reg    [31:0] m1_wb_dat_o;
143
reg           m2_wb_ack_o;
144
reg    [31:0] m2_wb_dat_o;
145
 
146
reg           m1_wb_err_o;
147
reg           m2_wb_err_o;
148
 
149
wire m_wb_access_finished;
150
wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (`M1_ADDRESSED_S1 | `M1_ADDRESSED_S2);
151
wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (`M2_ADDRESSED_S1 | `M2_ADDRESSED_S2);
152
 
153
always @ (posedge wb_clk_i or posedge wb_rst_i)
154
begin
155
  if(wb_rst_i)
156
    begin
157
      m1_in_progress <=#Tp 0;
158
      m2_in_progress <=#Tp 0;
159
      s1_wb_adr_o    <=#Tp 0;
160
      s1_wb_sel_o    <=#Tp 0;
161
      s1_wb_we_o     <=#Tp 0;
162
      s1_wb_dat_o    <=#Tp 0;
163
      s1_wb_cyc_o    <=#Tp 0;
164
      s1_wb_stb_o    <=#Tp 0;
165
      s2_wb_adr_o    <=#Tp 0;
166
      s2_wb_sel_o    <=#Tp 0;
167
      s2_wb_we_o     <=#Tp 0;
168
      s2_wb_dat_o    <=#Tp 0;
169
      s2_wb_cyc_o    <=#Tp 0;
170
      s2_wb_stb_o    <=#Tp 0;
171
    end
172
  else
173
    begin
174
      case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished})  // synopsys_full_case synopsys_paralel_case
175
        5'b00_10_0, 5'b00_11_0 :
176
          begin
177
            m1_in_progress <=#Tp 1'b1;  // idle: m1 or (m1 & m2) want access: m1 -> m
178
            if(`M1_ADDRESSED_S1)
179
              begin
180
                s1_wb_adr_o <=#Tp m1_wb_adr_i;
181
                s1_wb_sel_o <=#Tp m1_wb_sel_i;
182
                s1_wb_we_o  <=#Tp m1_wb_we_i;
183
                s1_wb_dat_o <=#Tp m1_wb_dat_i;
184
                s1_wb_cyc_o <=#Tp 1'b1;
185
                s1_wb_stb_o <=#Tp 1'b1;
186
              end
187
            else if(`M1_ADDRESSED_S2)
188
              begin
189
                s2_wb_adr_o <=#Tp m1_wb_adr_i;
190
                s2_wb_sel_o <=#Tp m1_wb_sel_i;
191
                s2_wb_we_o  <=#Tp m1_wb_we_i;
192
                s2_wb_dat_o <=#Tp m1_wb_dat_i;
193
                s2_wb_cyc_o <=#Tp 1'b1;
194
                s2_wb_stb_o <=#Tp 1'b1;
195
              end
196
            else
197
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
198
          end
199
        5'b00_01_0 :
200
          begin
201
            m2_in_progress <=#Tp 1'b1;  // idle: m2 wants access: m2 -> m
202
            if(`M2_ADDRESSED_S1)
203
              begin
204
                s1_wb_adr_o <=#Tp m2_wb_adr_i;
205
                s1_wb_sel_o <=#Tp m2_wb_sel_i;
206
                s1_wb_we_o  <=#Tp m2_wb_we_i;
207
                s1_wb_dat_o <=#Tp m2_wb_dat_i;
208
                s1_wb_cyc_o <=#Tp 1'b1;
209
                s1_wb_stb_o <=#Tp 1'b1;
210
              end
211
            else if(`M2_ADDRESSED_S2)
212
              begin
213
                s2_wb_adr_o <=#Tp m2_wb_adr_i;
214
                s2_wb_sel_o <=#Tp m2_wb_sel_i;
215
                s2_wb_we_o  <=#Tp m2_wb_we_i;
216
                s2_wb_dat_o <=#Tp m2_wb_dat_i;
217
                s2_wb_cyc_o <=#Tp 1'b1;
218
                s2_wb_stb_o <=#Tp 1'b1;
219
              end
220
            else
221
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
222
          end
223
        5'b10_10_1, 5'b10_11_1 :
224
          begin
225
            m1_in_progress <=#Tp 1'b0;  // m1 in progress. Cycle is finished. Send ack or err to m1.
226
            if(`M1_ADDRESSED_S1)
227
              begin
228
                s1_wb_cyc_o <=#Tp 1'b0;
229
                s1_wb_stb_o <=#Tp 1'b0;
230
              end
231
            else if(`M1_ADDRESSED_S2)
232
              begin
233
                s2_wb_cyc_o <=#Tp 1'b0;
234
                s2_wb_stb_o <=#Tp 1'b0;
235
              end
236
          end
237
        5'b01_01_1, 5'b01_11_1 :
238
          begin
239
            m2_in_progress <=#Tp 1'b0;  // m2 in progress. Cycle is finished. Send ack or err to m2.
240
            if(`M2_ADDRESSED_S1)
241
              begin
242
                s1_wb_cyc_o <=#Tp 1'b0;
243
                s1_wb_stb_o <=#Tp 1'b0;
244
              end
245
            else if(`M2_ADDRESSED_S2)
246
              begin
247
                s2_wb_cyc_o <=#Tp 1'b0;
248
                s2_wb_stb_o <=#Tp 1'b0;
249
              end
250
          end
251
      endcase
252
    end
253
end
254
 
255
// Generating Ack for master 1
256
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M1_ADDRESSED_S1 or `M1_ADDRESSED_S2)
257
begin
258
  if(m1_in_progress)
259
    begin
260
      if(`M1_ADDRESSED_S1) begin
261
        m1_wb_ack_o <= s1_wb_ack_i;
262
        m1_wb_dat_o <= s1_wb_dat_i;
263
      end
264
      else if(`M1_ADDRESSED_S2) begin
265
        m1_wb_ack_o <= s2_wb_ack_i;
266
        m1_wb_dat_o <= s2_wb_dat_i;
267
      end
268
    end
269
  else
270
    m1_wb_ack_o <= 0;
271
end
272
 
273
 
274
// Generating Ack for master 2
275
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2)
276
begin
277
  if(m2_in_progress)
278
    begin
279
      if(`M2_ADDRESSED_S1) begin
280
        m2_wb_ack_o <= s1_wb_ack_i;
281
        m2_wb_dat_o <= s1_wb_dat_i;
282
      end
283
      else if(`M2_ADDRESSED_S2) begin
284
        m2_wb_ack_o <= s2_wb_ack_i;
285
        m2_wb_dat_o <= s2_wb_dat_i;
286
      end
287
    end
288
  else
289
    m2_wb_ack_o <= 0;
290
end
291
 
292
 
293
// Generating Err for master 1
294
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
295
          m1_wb_cyc_i or m1_wb_stb_i)
296
begin
297
  if(m1_in_progress)  begin
298
    if(`M1_ADDRESSED_S1)
299
      m1_wb_err_o <= s1_wb_err_i;
300
    else if(`M1_ADDRESSED_S2)
301
      m1_wb_err_o <= s2_wb_err_i;
302
  end
303
  else if(m1_wb_cyc_i & m1_wb_stb_i & ~`M1_ADDRESSED_S1 & ~`M1_ADDRESSED_S2)
304
    m1_wb_err_o <= 1'b1;
305
  else
306
    m1_wb_err_o <= 1'b0;
307
end
308
 
309
 
310
// Generating Err for master 2
311
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
312
          m2_wb_cyc_i or m2_wb_stb_i)
313
begin
314
  if(m2_in_progress)  begin
315
    if(`M2_ADDRESSED_S1)
316
      m2_wb_err_o <= s1_wb_err_i;
317
    else if(`M2_ADDRESSED_S2)
318
      m2_wb_err_o <= s2_wb_err_i;
319
  end
320
  else if(m2_wb_cyc_i & m2_wb_stb_i & ~`M2_ADDRESSED_S1 & ~`M2_ADDRESSED_S2)
321
    m2_wb_err_o <= 1'b1;
322
  else
323
    m2_wb_err_o <= 1'b0;
324
end
325
 
326
 
327
assign m_wb_access_finished = m1_wb_ack_o | m1_wb_err_o | m2_wb_ack_o | m2_wb_err_o;
328
 
329
 
330
// Activity monitor
331
integer cnt;
332
always @ (posedge wb_clk_i or posedge wb_rst_i)
333
begin
334
  if(wb_rst_i)
335
    cnt <=#Tp 0;
336
  else
337
  if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i)
338
    cnt <=#Tp 0;
339
  else
340
  if(s1_wb_cyc_o | s2_wb_cyc_o)
341
    cnt <=#Tp cnt+1;
342
end
343
 
344
always @ (posedge wb_clk_i)
345
begin
346
  if(cnt==1000) begin
347 212 mohor
    $display("(%0t)(%m) ERROR: WB activity ??? ", $time);
348 129 mohor
    if(s1_wb_cyc_o) begin
349
      $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
350
      $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
351
      $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
352
      $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
353
    end
354 160 mohor
    else if(s2_wb_cyc_o) begin
355 129 mohor
      $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
356
      $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
357
      $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
358
      $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
359
    end
360
 
361
    $stop;
362
  end
363
end
364
 
365
 
366 160 mohor
always @ (posedge wb_clk_i)
367
begin
368
  if(s1_wb_err_i & s1_wb_cyc_o) begin
369
    $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
370
    $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
371
    $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
372
    $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
373
    $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
374
    $stop;
375
  end
376
  if(s2_wb_err_i & s2_wb_cyc_o) begin
377
    $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
378
    $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
379
    $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
380
    $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
381
    $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
382
    $stop;
383
  end
384
end
385 129 mohor
 
386 160 mohor
 
387
 
388 286 mohor
endmodule

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