OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_cop.v] - Blame information for rev 350

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 129 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_cop.v                                                   ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 129 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001, 2002 Authors                             ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 286 mohor
// Revision 1.3  2002/10/10 16:43:59  mohor
45
// Minor $display change.
46
//
47 212 mohor
// Revision 1.2  2002/09/09 12:54:13  mohor
48
// error acknowledge cycle termination added to display.
49
//
50 160 mohor
// Revision 1.1  2002/08/14 17:16:07  mohor
51
// Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
52
// interfaces:
53
// - Host connects to the master interface
54
// - Ethernet master (DMA) connects to the second master interface
55
// - Memory interface connects to the slave interface
56
// - Ethernet slave interface (access to registers and BDs) connects to second
57
//   slave interface
58 129 mohor
//
59
//
60
//
61
//
62 160 mohor
//
63 129 mohor
 
64 286 mohor
`include "eth_defines.v"
65 129 mohor
`include "timescale.v"
66
 
67
module eth_cop
68
(
69
  // WISHBONE common
70
  wb_clk_i, wb_rst_i,
71
 
72
  // WISHBONE MASTER 1
73
  m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i,  m1_wb_dat_o,
74
  m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o,
75
  m1_wb_err_o,
76
 
77
  // WISHBONE MASTER 2
78
  m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i,  m2_wb_dat_o,
79
  m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o,
80
  m2_wb_err_o,
81
 
82
  // WISHBONE slave 1
83
        s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o,  s1_wb_cyc_o,
84
        s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i,
85
        s1_wb_dat_o,
86
 
87
  // WISHBONE slave 2
88
        s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o,  s2_wb_cyc_o,
89
        s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
90
        s2_wb_dat_o
91
);
92
 
93
parameter Tp=1;
94
 
95
// WISHBONE common
96
input wb_clk_i, wb_rst_i;
97
 
98
// WISHBONE MASTER 1
99
input  [31:0] m1_wb_adr_i, m1_wb_dat_i;
100
input   [3:0] m1_wb_sel_i;
101
input         m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i;
102
output [31:0] m1_wb_dat_o;
103
output        m1_wb_ack_o, m1_wb_err_o;
104
 
105
// WISHBONE MASTER 2
106
input  [31:0] m2_wb_adr_i, m2_wb_dat_i;
107
input   [3:0] m2_wb_sel_i;
108
input         m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i;
109
output [31:0] m2_wb_dat_o;
110
output        m2_wb_ack_o, m2_wb_err_o;
111
 
112
// WISHBONE slave 1
113
input  [31:0] s1_wb_dat_i;
114
input         s1_wb_ack_i, s1_wb_err_i;
115
output [31:0] s1_wb_adr_o, s1_wb_dat_o;
116
output  [3:0] s1_wb_sel_o;
117
output        s1_wb_we_o,  s1_wb_cyc_o, s1_wb_stb_o;
118
 
119
// WISHBONE slave 2
120
input  [31:0] s2_wb_dat_i;
121
input         s2_wb_ack_i, s2_wb_err_i;
122
output [31:0] s2_wb_adr_o, s2_wb_dat_o;
123
output  [3:0] s2_wb_sel_o;
124
output        s2_wb_we_o,  s2_wb_cyc_o, s2_wb_stb_o;
125
 
126
reg           m1_in_progress;
127
reg           m2_in_progress;
128
reg    [31:0] s1_wb_adr_o;
129
reg     [3:0] s1_wb_sel_o;
130
reg           s1_wb_we_o;
131
reg    [31:0] s1_wb_dat_o;
132
reg           s1_wb_cyc_o;
133
reg           s1_wb_stb_o;
134
reg    [31:0] s2_wb_adr_o;
135
reg     [3:0] s2_wb_sel_o;
136
reg           s2_wb_we_o;
137
reg    [31:0] s2_wb_dat_o;
138
reg           s2_wb_cyc_o;
139
reg           s2_wb_stb_o;
140
 
141
reg           m1_wb_ack_o;
142
reg    [31:0] m1_wb_dat_o;
143
reg           m2_wb_ack_o;
144
reg    [31:0] m2_wb_dat_o;
145
 
146
reg           m1_wb_err_o;
147
reg           m2_wb_err_o;
148
 
149
wire m_wb_access_finished;
150 350 olof
wire m1_addressed_s1 = (m1_wb_adr_i >= `ETH_BASE) &
151
                       (m1_wb_adr_i < (`ETH_BASE + `ETH_WIDTH));
152
wire m1_addressed_s2 = (m1_wb_adr_i >= `MEMORY_BASE) &
153
                       (m1_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH));
154
wire m2_addressed_s1 = (m2_wb_adr_i >= `ETH_BASE) &
155
                       (m2_wb_adr_i < (`ETH_BASE + `ETH_WIDTH));
156
wire m2_addressed_s2 = (m2_wb_adr_i >= `MEMORY_BASE) &
157
                       (m2_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH));
158
 
159
wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (m1_addressed_s1 | m1_addressed_s2);
160
wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (m2_addressed_s1 | m2_addressed_s2);
161 129 mohor
 
162
always @ (posedge wb_clk_i or posedge wb_rst_i)
163
begin
164
  if(wb_rst_i)
165
    begin
166
      m1_in_progress <=#Tp 0;
167
      m2_in_progress <=#Tp 0;
168
      s1_wb_adr_o    <=#Tp 0;
169
      s1_wb_sel_o    <=#Tp 0;
170
      s1_wb_we_o     <=#Tp 0;
171
      s1_wb_dat_o    <=#Tp 0;
172
      s1_wb_cyc_o    <=#Tp 0;
173
      s1_wb_stb_o    <=#Tp 0;
174
      s2_wb_adr_o    <=#Tp 0;
175
      s2_wb_sel_o    <=#Tp 0;
176
      s2_wb_we_o     <=#Tp 0;
177
      s2_wb_dat_o    <=#Tp 0;
178
      s2_wb_cyc_o    <=#Tp 0;
179
      s2_wb_stb_o    <=#Tp 0;
180
    end
181
  else
182
    begin
183
      case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished})  // synopsys_full_case synopsys_paralel_case
184
        5'b00_10_0, 5'b00_11_0 :
185
          begin
186
            m1_in_progress <=#Tp 1'b1;  // idle: m1 or (m1 & m2) want access: m1 -> m
187 350 olof
            if(m1_addressed_s1)
188 129 mohor
              begin
189
                s1_wb_adr_o <=#Tp m1_wb_adr_i;
190
                s1_wb_sel_o <=#Tp m1_wb_sel_i;
191
                s1_wb_we_o  <=#Tp m1_wb_we_i;
192
                s1_wb_dat_o <=#Tp m1_wb_dat_i;
193
                s1_wb_cyc_o <=#Tp 1'b1;
194
                s1_wb_stb_o <=#Tp 1'b1;
195
              end
196 350 olof
            else if(m1_addressed_s2)
197 129 mohor
              begin
198
                s2_wb_adr_o <=#Tp m1_wb_adr_i;
199
                s2_wb_sel_o <=#Tp m1_wb_sel_i;
200
                s2_wb_we_o  <=#Tp m1_wb_we_i;
201
                s2_wb_dat_o <=#Tp m1_wb_dat_i;
202
                s2_wb_cyc_o <=#Tp 1'b1;
203
                s2_wb_stb_o <=#Tp 1'b1;
204
              end
205
            else
206
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
207
          end
208
        5'b00_01_0 :
209
          begin
210
            m2_in_progress <=#Tp 1'b1;  // idle: m2 wants access: m2 -> m
211 350 olof
            if(m2_addressed_s1)
212 129 mohor
              begin
213
                s1_wb_adr_o <=#Tp m2_wb_adr_i;
214
                s1_wb_sel_o <=#Tp m2_wb_sel_i;
215
                s1_wb_we_o  <=#Tp m2_wb_we_i;
216
                s1_wb_dat_o <=#Tp m2_wb_dat_i;
217
                s1_wb_cyc_o <=#Tp 1'b1;
218
                s1_wb_stb_o <=#Tp 1'b1;
219
              end
220 350 olof
            else if(m2_addressed_s2)
221 129 mohor
              begin
222
                s2_wb_adr_o <=#Tp m2_wb_adr_i;
223
                s2_wb_sel_o <=#Tp m2_wb_sel_i;
224
                s2_wb_we_o  <=#Tp m2_wb_we_i;
225
                s2_wb_dat_o <=#Tp m2_wb_dat_i;
226
                s2_wb_cyc_o <=#Tp 1'b1;
227
                s2_wb_stb_o <=#Tp 1'b1;
228
              end
229
            else
230
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
231
          end
232
        5'b10_10_1, 5'b10_11_1 :
233
          begin
234
            m1_in_progress <=#Tp 1'b0;  // m1 in progress. Cycle is finished. Send ack or err to m1.
235 350 olof
            if(m1_addressed_s1)
236 129 mohor
              begin
237
                s1_wb_cyc_o <=#Tp 1'b0;
238
                s1_wb_stb_o <=#Tp 1'b0;
239
              end
240 350 olof
            else if(m1_addressed_s2)
241 129 mohor
              begin
242
                s2_wb_cyc_o <=#Tp 1'b0;
243
                s2_wb_stb_o <=#Tp 1'b0;
244
              end
245
          end
246
        5'b01_01_1, 5'b01_11_1 :
247
          begin
248
            m2_in_progress <=#Tp 1'b0;  // m2 in progress. Cycle is finished. Send ack or err to m2.
249 350 olof
            if(m2_addressed_s1)
250 129 mohor
              begin
251
                s1_wb_cyc_o <=#Tp 1'b0;
252
                s1_wb_stb_o <=#Tp 1'b0;
253
              end
254 350 olof
            else if(m2_addressed_s2)
255 129 mohor
              begin
256
                s2_wb_cyc_o <=#Tp 1'b0;
257
                s2_wb_stb_o <=#Tp 1'b0;
258
              end
259
          end
260
      endcase
261
    end
262
end
263
 
264
// Generating Ack for master 1
265 350 olof
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or m1_addressed_s1 or m1_addressed_s2)
266 129 mohor
begin
267
  if(m1_in_progress)
268
    begin
269 350 olof
      if(m1_addressed_s1) begin
270 129 mohor
        m1_wb_ack_o <= s1_wb_ack_i;
271
        m1_wb_dat_o <= s1_wb_dat_i;
272
      end
273 350 olof
      else if(m1_addressed_s2) begin
274 129 mohor
        m1_wb_ack_o <= s2_wb_ack_i;
275
        m1_wb_dat_o <= s2_wb_dat_i;
276
      end
277
    end
278
  else
279
    m1_wb_ack_o <= 0;
280
end
281
 
282
 
283
// Generating Ack for master 2
284 350 olof
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or m2_addressed_s1 or m2_addressed_s2)
285 129 mohor
begin
286
  if(m2_in_progress)
287
    begin
288 350 olof
      if(m2_addressed_s1) begin
289 129 mohor
        m2_wb_ack_o <= s1_wb_ack_i;
290
        m2_wb_dat_o <= s1_wb_dat_i;
291
      end
292 350 olof
      else if(m2_addressed_s2) begin
293 129 mohor
        m2_wb_ack_o <= s2_wb_ack_i;
294
        m2_wb_dat_o <= s2_wb_dat_i;
295
      end
296
    end
297
  else
298
    m2_wb_ack_o <= 0;
299
end
300
 
301
 
302
// Generating Err for master 1
303 350 olof
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or m2_addressed_s1 or m2_addressed_s2 or
304 129 mohor
          m1_wb_cyc_i or m1_wb_stb_i)
305
begin
306
  if(m1_in_progress)  begin
307 350 olof
    if(m1_addressed_s1)
308 129 mohor
      m1_wb_err_o <= s1_wb_err_i;
309 350 olof
    else if(m1_addressed_s2)
310 129 mohor
      m1_wb_err_o <= s2_wb_err_i;
311
  end
312 350 olof
  else if(m1_wb_cyc_i & m1_wb_stb_i & ~m1_addressed_s1 & ~m1_addressed_s2)
313 129 mohor
    m1_wb_err_o <= 1'b1;
314
  else
315
    m1_wb_err_o <= 1'b0;
316
end
317
 
318
 
319
// Generating Err for master 2
320 350 olof
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or m2_addressed_s1 or m2_addressed_s2 or
321 129 mohor
          m2_wb_cyc_i or m2_wb_stb_i)
322
begin
323
  if(m2_in_progress)  begin
324 350 olof
    if(m2_addressed_s1)
325 129 mohor
      m2_wb_err_o <= s1_wb_err_i;
326 350 olof
    else if(m2_addressed_s2)
327 129 mohor
      m2_wb_err_o <= s2_wb_err_i;
328
  end
329 350 olof
  else if(m2_wb_cyc_i & m2_wb_stb_i & ~m2_addressed_s1 & ~m2_addressed_s2)
330 129 mohor
    m2_wb_err_o <= 1'b1;
331
  else
332
    m2_wb_err_o <= 1'b0;
333
end
334
 
335
 
336
assign m_wb_access_finished = m1_wb_ack_o | m1_wb_err_o | m2_wb_ack_o | m2_wb_err_o;
337
 
338
 
339
// Activity monitor
340
integer cnt;
341
always @ (posedge wb_clk_i or posedge wb_rst_i)
342
begin
343
  if(wb_rst_i)
344
    cnt <=#Tp 0;
345
  else
346
  if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i)
347
    cnt <=#Tp 0;
348
  else
349
  if(s1_wb_cyc_o | s2_wb_cyc_o)
350
    cnt <=#Tp cnt+1;
351
end
352
 
353
always @ (posedge wb_clk_i)
354
begin
355
  if(cnt==1000) begin
356 212 mohor
    $display("(%0t)(%m) ERROR: WB activity ??? ", $time);
357 129 mohor
    if(s1_wb_cyc_o) begin
358
      $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
359
      $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
360
      $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
361
      $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
362
    end
363 160 mohor
    else if(s2_wb_cyc_o) begin
364 129 mohor
      $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
365
      $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
366
      $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
367
      $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
368
    end
369
 
370
    $stop;
371
  end
372
end
373
 
374
 
375 160 mohor
always @ (posedge wb_clk_i)
376
begin
377
  if(s1_wb_err_i & s1_wb_cyc_o) begin
378
    $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
379
    $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
380
    $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
381
    $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
382
    $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
383
    $stop;
384
  end
385
  if(s2_wb_err_i & s2_wb_cyc_o) begin
386
    $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
387
    $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
388
    $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
389
    $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
390
    $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
391
    $stop;
392
  end
393
end
394 129 mohor
 
395 160 mohor
 
396
 
397 286 mohor
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.