OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_cop.v] - Blame information for rev 352

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 129 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_cop.v                                                   ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 129 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001, 2002 Authors                             ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 286 mohor
// Revision 1.3  2002/10/10 16:43:59  mohor
45
// Minor $display change.
46
//
47 212 mohor
// Revision 1.2  2002/09/09 12:54:13  mohor
48
// error acknowledge cycle termination added to display.
49
//
50 160 mohor
// Revision 1.1  2002/08/14 17:16:07  mohor
51
// Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
52
// interfaces:
53
// - Host connects to the master interface
54
// - Ethernet master (DMA) connects to the second master interface
55
// - Memory interface connects to the slave interface
56
// - Ethernet slave interface (access to registers and BDs) connects to second
57
//   slave interface
58 129 mohor
//
59
//
60
//
61
//
62 160 mohor
//
63 129 mohor
 
64
`include "timescale.v"
65
 
66
module eth_cop
67
(
68
  // WISHBONE common
69
  wb_clk_i, wb_rst_i,
70
 
71
  // WISHBONE MASTER 1
72
  m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i,  m1_wb_dat_o,
73
  m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o,
74
  m1_wb_err_o,
75
 
76
  // WISHBONE MASTER 2
77
  m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i,  m2_wb_dat_o,
78
  m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o,
79
  m2_wb_err_o,
80
 
81
  // WISHBONE slave 1
82
        s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o,  s1_wb_cyc_o,
83
        s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i,
84
        s1_wb_dat_o,
85
 
86
  // WISHBONE slave 2
87
        s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o,  s2_wb_cyc_o,
88
        s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
89
        s2_wb_dat_o
90
);
91
 
92 351 olof
parameter ETH_BASE     = 32'hd0000000;
93
parameter ETH_WIDTH    = 32'h800;
94
parameter MEMORY_BASE  = 32'h2000;
95
parameter MEMORY_WIDTH = 32'h10000;
96
 
97 129 mohor
// WISHBONE common
98
input wb_clk_i, wb_rst_i;
99
 
100
// WISHBONE MASTER 1
101
input  [31:0] m1_wb_adr_i, m1_wb_dat_i;
102
input   [3:0] m1_wb_sel_i;
103
input         m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i;
104
output [31:0] m1_wb_dat_o;
105
output        m1_wb_ack_o, m1_wb_err_o;
106
 
107
// WISHBONE MASTER 2
108
input  [31:0] m2_wb_adr_i, m2_wb_dat_i;
109
input   [3:0] m2_wb_sel_i;
110
input         m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i;
111
output [31:0] m2_wb_dat_o;
112
output        m2_wb_ack_o, m2_wb_err_o;
113
 
114
// WISHBONE slave 1
115
input  [31:0] s1_wb_dat_i;
116
input         s1_wb_ack_i, s1_wb_err_i;
117
output [31:0] s1_wb_adr_o, s1_wb_dat_o;
118
output  [3:0] s1_wb_sel_o;
119
output        s1_wb_we_o,  s1_wb_cyc_o, s1_wb_stb_o;
120
 
121
// WISHBONE slave 2
122
input  [31:0] s2_wb_dat_i;
123
input         s2_wb_ack_i, s2_wb_err_i;
124
output [31:0] s2_wb_adr_o, s2_wb_dat_o;
125
output  [3:0] s2_wb_sel_o;
126
output        s2_wb_we_o,  s2_wb_cyc_o, s2_wb_stb_o;
127
 
128
reg           m1_in_progress;
129
reg           m2_in_progress;
130
reg    [31:0] s1_wb_adr_o;
131
reg     [3:0] s1_wb_sel_o;
132
reg           s1_wb_we_o;
133
reg    [31:0] s1_wb_dat_o;
134
reg           s1_wb_cyc_o;
135
reg           s1_wb_stb_o;
136
reg    [31:0] s2_wb_adr_o;
137
reg     [3:0] s2_wb_sel_o;
138
reg           s2_wb_we_o;
139
reg    [31:0] s2_wb_dat_o;
140
reg           s2_wb_cyc_o;
141
reg           s2_wb_stb_o;
142
 
143
reg           m1_wb_ack_o;
144
reg    [31:0] m1_wb_dat_o;
145
reg           m2_wb_ack_o;
146
reg    [31:0] m2_wb_dat_o;
147
 
148
reg           m1_wb_err_o;
149
reg           m2_wb_err_o;
150
 
151
wire m_wb_access_finished;
152 351 olof
wire m1_addressed_s1 = (m1_wb_adr_i >= ETH_BASE) &
153
                       (m1_wb_adr_i < (ETH_BASE + ETH_WIDTH));
154
wire m1_addressed_s2 = (m1_wb_adr_i >= MEMORY_BASE) &
155
                       (m1_wb_adr_i < (MEMORY_BASE + MEMORY_WIDTH));
156
wire m2_addressed_s1 = (m2_wb_adr_i >= ETH_BASE) &
157
                       (m2_wb_adr_i < (ETH_BASE + ETH_WIDTH));
158
wire m2_addressed_s2 = (m2_wb_adr_i >= MEMORY_BASE) &
159
                       (m2_wb_adr_i < (MEMORY_BASE + MEMORY_WIDTH));
160 350 olof
 
161
wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (m1_addressed_s1 | m1_addressed_s2);
162
wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (m2_addressed_s1 | m2_addressed_s2);
163 129 mohor
 
164
always @ (posedge wb_clk_i or posedge wb_rst_i)
165
begin
166
  if(wb_rst_i)
167
    begin
168 352 olof
      m1_in_progress <= 0;
169
      m2_in_progress <= 0;
170
      s1_wb_adr_o    <= 0;
171
      s1_wb_sel_o    <= 0;
172
      s1_wb_we_o     <= 0;
173
      s1_wb_dat_o    <= 0;
174
      s1_wb_cyc_o    <= 0;
175
      s1_wb_stb_o    <= 0;
176
      s2_wb_adr_o    <= 0;
177
      s2_wb_sel_o    <= 0;
178
      s2_wb_we_o     <= 0;
179
      s2_wb_dat_o    <= 0;
180
      s2_wb_cyc_o    <= 0;
181
      s2_wb_stb_o    <= 0;
182 129 mohor
    end
183
  else
184
    begin
185
      case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished})  // synopsys_full_case synopsys_paralel_case
186
        5'b00_10_0, 5'b00_11_0 :
187
          begin
188 352 olof
            m1_in_progress <= 1'b1;  // idle: m1 or (m1 & m2) want access: m1 -> m
189 350 olof
            if(m1_addressed_s1)
190 129 mohor
              begin
191 352 olof
                s1_wb_adr_o <= m1_wb_adr_i;
192
                s1_wb_sel_o <= m1_wb_sel_i;
193
                s1_wb_we_o  <= m1_wb_we_i;
194
                s1_wb_dat_o <= m1_wb_dat_i;
195
                s1_wb_cyc_o <= 1'b1;
196
                s1_wb_stb_o <= 1'b1;
197 129 mohor
              end
198 350 olof
            else if(m1_addressed_s2)
199 129 mohor
              begin
200 352 olof
                s2_wb_adr_o <= m1_wb_adr_i;
201
                s2_wb_sel_o <= m1_wb_sel_i;
202
                s2_wb_we_o  <= m1_wb_we_i;
203
                s2_wb_dat_o <= m1_wb_dat_i;
204
                s2_wb_cyc_o <= 1'b1;
205
                s2_wb_stb_o <= 1'b1;
206 129 mohor
              end
207
            else
208
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
209
          end
210
        5'b00_01_0 :
211
          begin
212 352 olof
            m2_in_progress <= 1'b1;  // idle: m2 wants access: m2 -> m
213 350 olof
            if(m2_addressed_s1)
214 129 mohor
              begin
215 352 olof
                s1_wb_adr_o <= m2_wb_adr_i;
216
                s1_wb_sel_o <= m2_wb_sel_i;
217
                s1_wb_we_o  <= m2_wb_we_i;
218
                s1_wb_dat_o <= m2_wb_dat_i;
219
                s1_wb_cyc_o <= 1'b1;
220
                s1_wb_stb_o <= 1'b1;
221 129 mohor
              end
222 350 olof
            else if(m2_addressed_s2)
223 129 mohor
              begin
224 352 olof
                s2_wb_adr_o <= m2_wb_adr_i;
225
                s2_wb_sel_o <= m2_wb_sel_i;
226
                s2_wb_we_o  <= m2_wb_we_i;
227
                s2_wb_dat_o <= m2_wb_dat_i;
228
                s2_wb_cyc_o <= 1'b1;
229
                s2_wb_stb_o <= 1'b1;
230 129 mohor
              end
231
            else
232
              $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
233
          end
234
        5'b10_10_1, 5'b10_11_1 :
235
          begin
236 352 olof
            m1_in_progress <= 1'b0;  // m1 in progress. Cycle is finished. Send ack or err to m1.
237 350 olof
            if(m1_addressed_s1)
238 129 mohor
              begin
239 352 olof
                s1_wb_cyc_o <= 1'b0;
240
                s1_wb_stb_o <= 1'b0;
241 129 mohor
              end
242 350 olof
            else if(m1_addressed_s2)
243 129 mohor
              begin
244 352 olof
                s2_wb_cyc_o <= 1'b0;
245
                s2_wb_stb_o <= 1'b0;
246 129 mohor
              end
247
          end
248
        5'b01_01_1, 5'b01_11_1 :
249
          begin
250 352 olof
            m2_in_progress <= 1'b0;  // m2 in progress. Cycle is finished. Send ack or err to m2.
251 350 olof
            if(m2_addressed_s1)
252 129 mohor
              begin
253 352 olof
                s1_wb_cyc_o <= 1'b0;
254
                s1_wb_stb_o <= 1'b0;
255 129 mohor
              end
256 350 olof
            else if(m2_addressed_s2)
257 129 mohor
              begin
258 352 olof
                s2_wb_cyc_o <= 1'b0;
259
                s2_wb_stb_o <= 1'b0;
260 129 mohor
              end
261
          end
262
      endcase
263
    end
264
end
265
 
266
// Generating Ack for master 1
267 350 olof
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or m1_addressed_s1 or m1_addressed_s2)
268 129 mohor
begin
269
  if(m1_in_progress)
270
    begin
271 350 olof
      if(m1_addressed_s1) begin
272 129 mohor
        m1_wb_ack_o <= s1_wb_ack_i;
273
        m1_wb_dat_o <= s1_wb_dat_i;
274
      end
275 350 olof
      else if(m1_addressed_s2) begin
276 129 mohor
        m1_wb_ack_o <= s2_wb_ack_i;
277
        m1_wb_dat_o <= s2_wb_dat_i;
278
      end
279
    end
280
  else
281
    m1_wb_ack_o <= 0;
282
end
283
 
284
 
285
// Generating Ack for master 2
286 350 olof
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or m2_addressed_s1 or m2_addressed_s2)
287 129 mohor
begin
288
  if(m2_in_progress)
289
    begin
290 350 olof
      if(m2_addressed_s1) begin
291 129 mohor
        m2_wb_ack_o <= s1_wb_ack_i;
292
        m2_wb_dat_o <= s1_wb_dat_i;
293
      end
294 350 olof
      else if(m2_addressed_s2) begin
295 129 mohor
        m2_wb_ack_o <= s2_wb_ack_i;
296
        m2_wb_dat_o <= s2_wb_dat_i;
297
      end
298
    end
299
  else
300
    m2_wb_ack_o <= 0;
301
end
302
 
303
 
304
// Generating Err for master 1
305 350 olof
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or m2_addressed_s1 or m2_addressed_s2 or
306 129 mohor
          m1_wb_cyc_i or m1_wb_stb_i)
307
begin
308
  if(m1_in_progress)  begin
309 350 olof
    if(m1_addressed_s1)
310 129 mohor
      m1_wb_err_o <= s1_wb_err_i;
311 350 olof
    else if(m1_addressed_s2)
312 129 mohor
      m1_wb_err_o <= s2_wb_err_i;
313
  end
314 350 olof
  else if(m1_wb_cyc_i & m1_wb_stb_i & ~m1_addressed_s1 & ~m1_addressed_s2)
315 129 mohor
    m1_wb_err_o <= 1'b1;
316
  else
317
    m1_wb_err_o <= 1'b0;
318
end
319
 
320
 
321
// Generating Err for master 2
322 350 olof
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or m2_addressed_s1 or m2_addressed_s2 or
323 129 mohor
          m2_wb_cyc_i or m2_wb_stb_i)
324
begin
325
  if(m2_in_progress)  begin
326 350 olof
    if(m2_addressed_s1)
327 129 mohor
      m2_wb_err_o <= s1_wb_err_i;
328 350 olof
    else if(m2_addressed_s2)
329 129 mohor
      m2_wb_err_o <= s2_wb_err_i;
330
  end
331 350 olof
  else if(m2_wb_cyc_i & m2_wb_stb_i & ~m2_addressed_s1 & ~m2_addressed_s2)
332 129 mohor
    m2_wb_err_o <= 1'b1;
333
  else
334
    m2_wb_err_o <= 1'b0;
335
end
336
 
337
 
338
assign m_wb_access_finished = m1_wb_ack_o | m1_wb_err_o | m2_wb_ack_o | m2_wb_err_o;
339
 
340
 
341
// Activity monitor
342
integer cnt;
343
always @ (posedge wb_clk_i or posedge wb_rst_i)
344
begin
345
  if(wb_rst_i)
346 352 olof
    cnt <= 0;
347 129 mohor
  else
348
  if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i)
349 352 olof
    cnt <= 0;
350 129 mohor
  else
351
  if(s1_wb_cyc_o | s2_wb_cyc_o)
352 352 olof
    cnt <= cnt+1;
353 129 mohor
end
354
 
355
always @ (posedge wb_clk_i)
356
begin
357
  if(cnt==1000) begin
358 212 mohor
    $display("(%0t)(%m) ERROR: WB activity ??? ", $time);
359 129 mohor
    if(s1_wb_cyc_o) begin
360
      $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
361
      $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
362
      $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
363
      $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
364
    end
365 160 mohor
    else if(s2_wb_cyc_o) begin
366 129 mohor
      $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
367
      $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
368
      $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
369
      $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
370
    end
371
 
372
    $stop;
373
  end
374
end
375
 
376
 
377 160 mohor
always @ (posedge wb_clk_i)
378
begin
379
  if(s1_wb_err_i & s1_wb_cyc_o) begin
380
    $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
381
    $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
382
    $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
383
    $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
384
    $display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
385
    $stop;
386
  end
387
  if(s2_wb_err_i & s2_wb_cyc_o) begin
388
    $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
389
    $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
390
    $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
391
    $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
392
    $display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
393
    $stop;
394
  end
395
end
396 129 mohor
 
397 160 mohor
 
398
 
399 286 mohor
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.