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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_macstatus.v                                             ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10  2002/07/25 18:17:46  mohor
// InvalidSymbol generation changed.
//
// Revision 1.9  2002/04/22 13:51:44  mohor
// Short frame and ReceivedLengthOK were not detected correctly.
//
// Revision 1.8  2002/02/18 10:40:17  mohor
// Small fixes.
//
// Revision 1.7  2002/02/15 17:07:39  mohor
// Status was not written correctly when frames were discarted because of
// address mismatch.
//
// Revision 1.6  2002/02/11 09:18:21  mohor
// Tx status is written back to the BD.
//
// Revision 1.5  2002/02/08 16:21:54  mohor
// Rx status is written back to the BD.
//
// Revision 1.4  2002/01/23 10:28:16  mohor
// Link in the header changed.
//
// Revision 1.3  2001/10/19 08:43:51  mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2  2001/09/11 14:17:00  mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1  2001/08/06 14:44:29  mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
 
`include "timescale.v"
 
 
module eth_macstatus(
                      MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
                      MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
                      RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, ReceivedPauseFrm,
                      InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
                      r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
                      LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
                      RetryLimit, LateCollision, LateCollLatched, StartDefer, DeferLatched, TxStartFrm,
                      StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback
                    );
 
 
 
parameter Tp = 1;
 
 
input         MRxClk;
input         Reset;
input         RxCrcError;
input         MRxErr;
input         MRxDV;
 
input         RxStateSFD;
input   [1:0] RxStateData;
input         RxStatePreamble;
input         RxStateIdle;
input         Transmitting;
input  [15:0] RxByteCnt;
input         RxByteCntEq0;
input         RxByteCntGreat2;
input         RxByteCntMaxFrame;
input         ReceivedPauseFrm;
input   [3:0] MRxD;
input         Collision;
input   [5:0] CollValid;
input         r_RecSmall;
input  [15:0] r_MinFL;
input  [15:0] r_MaxFL;
input         r_HugEn;
input         StartTxDone;
input         StartTxAbort;
input   [3:0] RetryCnt;
input         MTxClk;
input         MaxCollisionOccured;
input         LateCollision;
input         StartDefer;
input         TxStartFrm;
input         StatePreamble;
input   [1:0] StateData;
input         CarrierSense;
input         TxUsedData;
input         Loopback;
 
 
output        ReceivedLengthOK;
output        ReceiveEnd;
output        ReceivedPacketGood;
output        InvalidSymbol;
output        LatchedCrcError;
output        RxLateCollision;
output        ShortFrame;
output        DribbleNibble;
output        ReceivedPacketTooBig;
output        LoadRxStatus;
output  [3:0] RetryCntLatched;
output        RetryLimit;
output        LateCollLatched;
output        DeferLatched;
output        CarrierSenseLost;
output        LatchedMRxErr;
 
 
reg           ReceiveEnd;
 
reg           LatchedCrcError;
reg           LatchedMRxErr;
reg           LoadRxStatus;
reg           InvalidSymbol;
reg     [3:0] RetryCntLatched;
reg           RetryLimit;
reg           LateCollLatched;
reg           DeferLatched;
reg           CarrierSenseLost;
 
wire          TakeSample;
wire          SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps 
 
// Crc error
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LatchedCrcError <=#Tp 1'b0;
  else
  if(RxStateSFD)
    LatchedCrcError <=#Tp 1'b0;
  else
  if(RxStateData[0])
    LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;
end
 
 
// LatchedMRxErr
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LatchedMRxErr <=#Tp 1'b0;
  else
  if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
    LatchedMRxErr <=#Tp 1'b1;
  else
    LatchedMRxErr <=#Tp 1'b0;
end
 
 
// ReceivedPacketGood
assign ReceivedPacketGood = ~LatchedCrcError;
 
 
// ReceivedLengthOK
assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];
 
 
 
 
 
// Time to take a sample
assign TakeSample = |RxStateData     & ~MRxDV & RxByteCntGreat2  |
                     RxStateData[0]  &  MRxDV & RxByteCntMaxFrame;
 
 
// LoadRxStatus
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LoadRxStatus <=#Tp 1'b0;
  else
    LoadRxStatus <=#Tp TakeSample;
end
 
 
 
// ReceiveEnd
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ReceiveEnd  <=#Tp 1'b0;
  else
    ReceiveEnd  <=#Tp LoadRxStatus;
end
 
 
// Invalid Symbol received during 100Mbps mode
assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;
 
 
// InvalidSymbol
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    InvalidSymbol <=#Tp 1'b0;
  else
  if(LoadRxStatus & ~SetInvalidSymbol)
    InvalidSymbol <=#Tp 1'b0;
  else
  if(SetInvalidSymbol)
    InvalidSymbol <=#Tp 1'b1;
end
 
 
// Late Collision
 
reg RxLateCollision;
reg RxColWindow;
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxLateCollision <=#Tp 1'b0;
  else
  if(LoadRxStatus)
    RxLateCollision <=#Tp 1'b0;
  else
  if(Collision & (~RxColWindow | r_RecSmall))
    RxLateCollision <=#Tp 1'b1;
end
 
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxColWindow <=#Tp 1'b1;
  else
  if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
    RxColWindow <=#Tp 1'b0;
  else
  if(RxStateIdle)
    RxColWindow <=#Tp 1'b1;
end
 
 
// ShortFrame
reg ShortFrame;
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ShortFrame <=#Tp 1'b0;
  else
  if(LoadRxStatus)
    ShortFrame <=#Tp 1'b0;
  else
  if(TakeSample)
    ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0];
end
 
 
// DribbleNibble
reg DribbleNibble;
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    DribbleNibble <=#Tp 1'b0;
  else
  if(RxStateSFD)
    DribbleNibble <=#Tp 1'b0;
  else
  if(~MRxDV & RxStateData[1])
    DribbleNibble <=#Tp 1'b1;
end
 
 
reg ReceivedPacketTooBig;
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ReceivedPacketTooBig <=#Tp 1'b0;
  else
  if(LoadRxStatus)
    ReceivedPacketTooBig <=#Tp 1'b0;
  else
  if(TakeSample)
    ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
end
 
 
 
// Latched Retry counter for tx status
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    RetryCntLatched <=#Tp 4'h0;
  else
  if(StartTxDone | StartTxAbort)
    RetryCntLatched <=#Tp RetryCnt;
end
 
 
// Latched Retransmission limit
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    RetryLimit <=#Tp 4'h0;
  else
  if(StartTxDone | StartTxAbort)
    RetryLimit <=#Tp MaxCollisionOccured;
end
 
 
// Latched Late Collision
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    LateCollLatched <=#Tp 1'b0;
  else
  if(StartTxDone | StartTxAbort)
    LateCollLatched <=#Tp LateCollision;
end
 
 
 
// Latched Defer state
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    DeferLatched <=#Tp 1'b0;
  else
  if(StartDefer & TxUsedData)
    DeferLatched <=#Tp 1'b1;
  else
  if(TxStartFrm)
    DeferLatched <=#Tp 1'b0;
end
 
 
// CarrierSenseLost
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    CarrierSenseLost <=#Tp 1'b0;
  else
  if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision)
    CarrierSenseLost <=#Tp 1'b1;
  else
  if(TxStartFrm)
    CarrierSenseLost <=#Tp 1'b0;
end
 
 
endmodule

Line No.	Rev	Author	Line
1	15	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_macstatus.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6	37	mohor	`//// http://www.opencores.org/projects/ethmac/ ////`
7	15	mohor	`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	146	mohor	`// Revision 1.10 2002/07/25 18:17:46 mohor`
45			`// InvalidSymbol generation changed.`
46			`//`
47	126	mohor	`// Revision 1.9 2002/04/22 13:51:44 mohor`
48			`// Short frame and ReceivedLengthOK were not detected correctly.`
49			`//`
50	101	mohor	`// Revision 1.8 2002/02/18 10:40:17 mohor`
51			`// Small fixes.`
52			`//`
53	70	mohor	`// Revision 1.7 2002/02/15 17:07:39 mohor`
54			`// Status was not written correctly when frames were discarted because of`
55			`// address mismatch.`
56			`//`
57	64	mohor	`// Revision 1.6 2002/02/11 09:18:21 mohor`
58			`// Tx status is written back to the BD.`
59			`//`
60	43	mohor	`// Revision 1.5 2002/02/08 16:21:54 mohor`
61			`// Rx status is written back to the BD.`
62			`//`
63	42	mohor	`// Revision 1.4 2002/01/23 10:28:16 mohor`
64			`// Link in the header changed.`
65			`//`
66	37	mohor	`// Revision 1.3 2001/10/19 08:43:51 mohor`
67			`// eth_timescale.v changed to timescale.v This is done because of the`
68			`// simulation of the few cores in a one joined project.`
69			`//`
70	22	mohor	`// Revision 1.2 2001/09/11 14:17:00 mohor`
71			`// Few little NCSIM warnings fixed.`
72			`//`
73	18	mohor	`// Revision 1.1 2001/08/06 14:44:29 mohor`
74			`// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).`
75			`// Include files fixed to contain no path.`
76			`// File names and module names changed ta have a eth_ prologue in the name.`
77			`// File eth_timescale.v is used to define timescale`
78			`// All pin names on the top module are changed to contain _I, _O or _OE at the end.`
79			`// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O`
80			`// and Mdo_OE. The bidirectional signal must be created on the top level. This`
81			`// is done due to the ASIC tools.`
82			`//`
83	15	mohor	`// Revision 1.1 2001/07/30 21:23:42 mohor`
84			`// Directory structure changed. Files checked and joind together.`
85			`//`
86			`//`
87			`//`
88			`//`
89			`//`
90
91	22	mohor	`include "timescale.v"
92	15	mohor
93
94			`module eth_macstatus(`
95	42	mohor	`MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,`
96	15	mohor	`MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,`
97	42	mohor	`RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, ReceivedPauseFrm,`
98			`InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,`
99			`r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,`
100	43	mohor	`LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,`
101			`RetryLimit, LateCollision, LateCollLatched, StartDefer, DeferLatched, TxStartFrm,`
102	146	mohor	`StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback`
103	15	mohor	`);`
104
105
106
107			`parameter Tp = 1;`
108
109
110			`input MRxClk;`
111			`input Reset;`
112			`input RxCrcError;`
113			`input MRxErr;`
114			`input MRxDV;`
115
116			`input RxStateSFD;`
117			`input [1:0] RxStateData;`
118			`input RxStatePreamble;`
119			`input RxStateIdle;`
120			`input Transmitting;`
121			`input [15:0] RxByteCnt;`
122			`input RxByteCntEq0;`
123			`input RxByteCntGreat2;`
124			`input RxByteCntMaxFrame;`
125			`input ReceivedPauseFrm;`
126	42	mohor	`input [3:0] MRxD;`
127			`input Collision;`
128			`input [5:0] CollValid;`
129			`input r_RecSmall;`
130			`input [15:0] r_MinFL;`
131			`input [15:0] r_MaxFL;`
132			`input r_HugEn;`
133	43	mohor	`input StartTxDone;`
134			`input StartTxAbort;`
135			`input [3:0] RetryCnt;`
136			`input MTxClk;`
137			`input MaxCollisionOccured;`
138			`input LateCollision;`
139			`input StartDefer;`
140			`input TxStartFrm;`
141			`input StatePreamble;`
142			`input [1:0] StateData;`
143			`input CarrierSense;`
144			`input TxUsedData;`
145	146	mohor	`input Loopback;`
146	15	mohor
147	43	mohor
148	15	mohor	`output ReceivedLengthOK;`
149			`output ReceiveEnd;`
150			`output ReceivedPacketGood;`
151	42	mohor	`output InvalidSymbol;`
152			`output LatchedCrcError;`
153			`output RxLateCollision;`
154			`output ShortFrame;`
155			`output DribbleNibble;`
156			`output ReceivedPacketTooBig;`
157			`output LoadRxStatus;`
158	43	mohor	`output [3:0] RetryCntLatched;`
159			`output RetryLimit;`
160			`output LateCollLatched;`
161			`output DeferLatched;`
162			`output CarrierSenseLost;`
163	126	mohor	`output LatchedMRxErr;`
164	15	mohor
165	43	mohor
166	15	mohor	`reg ReceiveEnd;`
167
168			`reg LatchedCrcError;`
169			`reg LatchedMRxErr;`
170	42	mohor	`reg LoadRxStatus;`
171			`reg InvalidSymbol;`
172	43	mohor	`reg [3:0] RetryCntLatched;`
173			`reg RetryLimit;`
174			`reg LateCollLatched;`
175			`reg DeferLatched;`
176			`reg CarrierSenseLost;`
177	15	mohor
178			`wire TakeSample;`
179	42	mohor	`wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps`
180	15	mohor
181			`// Crc error`
182			`always @ (posedge MRxClk or posedge Reset)`
183			`begin`
184			`if(Reset)`
185			`LatchedCrcError <=#Tp 1'b0;`
186			`else`
187	42	mohor	`if(RxStateSFD)`
188			`LatchedCrcError <=#Tp 1'b0;`
189			`else`
190			`if(RxStateData[0])`
191			`LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;`
192	15	mohor	`end`
193
194
195			`// LatchedMRxErr`
196			`always @ (posedge MRxClk or posedge Reset)`
197			`begin`
198			`if(Reset)`
199			`LatchedMRxErr <=#Tp 1'b0;`
200			`else`
201	18	mohor	`if(MRxErr & MRxDV & (RxStatePreamble \| RxStateSFD \| (\|RxStateData) \| RxStateIdle & ~Transmitting))`
202	15	mohor	`LatchedMRxErr <=#Tp 1'b1;`
203	126	mohor	`else`
204			`LatchedMRxErr <=#Tp 1'b0;`
205	15	mohor	`end`
206
207
208			`// ReceivedPacketGood`
209	126	mohor	`assign ReceivedPacketGood = ~LatchedCrcError;`
210	15	mohor
211
212			`// ReceivedLengthOK`
213	101	mohor	`assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];`
214	15	mohor
215
216
217	42	mohor
218
219			`// Time to take a sample`
220			`assign TakeSample = \|RxStateData & ~MRxDV & RxByteCntGreat2 \|`
221			`RxStateData[0] & MRxDV & RxByteCntMaxFrame;`
222
223
224			`// LoadRxStatus`
225	15	mohor	`always @ (posedge MRxClk or posedge Reset)`
226			`begin`
227			`if(Reset)`
228	42	mohor	`LoadRxStatus <=#Tp 1'b0;`
229	15	mohor	`else`
230	42	mohor	`LoadRxStatus <=#Tp TakeSample;`
231	15	mohor	`end`
232
233
234
235	42	mohor	`// ReceiveEnd`
236			`always @ (posedge MRxClk or posedge Reset)`
237			`begin`
238			`if(Reset)`
239			`ReceiveEnd <=#Tp 1'b0;`
240			`else`
241			`ReceiveEnd <=#Tp LoadRxStatus;`
242			`end`
243	15	mohor
244
245	42	mohor	`// Invalid Symbol received during 100Mbps mode`
246	126	mohor	`assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;`
247	42	mohor
248
249			`// InvalidSymbol`
250	15	mohor	`always @ (posedge MRxClk or posedge Reset)`
251			`begin`
252			`if(Reset)`
253	42	mohor	`InvalidSymbol <=#Tp 1'b0;`
254	15	mohor	`else`
255	42	mohor	`if(LoadRxStatus & ~SetInvalidSymbol)`
256			`InvalidSymbol <=#Tp 1'b0;`
257			`else`
258			`if(SetInvalidSymbol)`
259			`InvalidSymbol <=#Tp 1'b1;`
260	15	mohor	`end`
261
262
263	42	mohor	`// Late Collision`
264	15	mohor
265	42	mohor	`reg RxLateCollision;`
266			`reg RxColWindow;`
267			`// Collision Window`
268	15	mohor	`always @ (posedge MRxClk or posedge Reset)`
269			`begin`
270			`if(Reset)`
271	42	mohor	`RxLateCollision <=#Tp 1'b0;`
272	15	mohor	`else`
273	42	mohor	`if(LoadRxStatus)`
274			`RxLateCollision <=#Tp 1'b0;`
275			`else`
276			`if(Collision & (~RxColWindow \| r_RecSmall))`
277			`RxLateCollision <=#Tp 1'b1;`
278	15	mohor	`end`
279
280	42	mohor	`// Collision Window`
281			`always @ (posedge MRxClk or posedge Reset)`
282			`begin`
283			`if(Reset)`
284			`RxColWindow <=#Tp 1'b1;`
285			`else`
286			`if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])`
287			`RxColWindow <=#Tp 1'b0;`
288			`else`
289			`if(RxStateIdle)`
290			`RxColWindow <=#Tp 1'b1;`
291			`end`
292	15	mohor
293	42	mohor
294			`// ShortFrame`
295			`reg ShortFrame;`
296			`always @ (posedge MRxClk or posedge Reset)`
297			`begin`
298			`if(Reset)`
299			`ShortFrame <=#Tp 1'b0;`
300			`else`
301			`if(LoadRxStatus)`
302			`ShortFrame <=#Tp 1'b0;`
303			`else`
304			`if(TakeSample)`
305	101	mohor	`ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0];`
306	42	mohor	`end`
307
308
309			`// DribbleNibble`
310			`reg DribbleNibble;`
311			`always @ (posedge MRxClk or posedge Reset)`
312			`begin`
313			`if(Reset)`
314			`DribbleNibble <=#Tp 1'b0;`
315			`else`
316			`if(RxStateSFD)`
317			`DribbleNibble <=#Tp 1'b0;`
318			`else`
319			`if(~MRxDV & RxStateData[1])`
320			`DribbleNibble <=#Tp 1'b1;`
321			`end`
322
323
324			`reg ReceivedPacketTooBig;`
325			`always @ (posedge MRxClk or posedge Reset)`
326			`begin`
327			`if(Reset)`
328			`ReceivedPacketTooBig <=#Tp 1'b0;`
329			`else`
330			`if(LoadRxStatus)`
331			`ReceivedPacketTooBig <=#Tp 1'b0;`
332			`else`
333			`if(TakeSample)`
334			`ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];`
335			`end`
336
337	43	mohor
338
339			`// Latched Retry counter for tx status`
340			`always @ (posedge MTxClk or posedge Reset)`
341			`begin`
342			`if(Reset)`
343			`RetryCntLatched <=#Tp 4'h0;`
344			`else`
345			`if(StartTxDone \| StartTxAbort)`
346			`RetryCntLatched <=#Tp RetryCnt;`
347			`end`
348
349
350			`// Latched Retransmission limit`
351			`always @ (posedge MTxClk or posedge Reset)`
352			`begin`
353			`if(Reset)`
354			`RetryLimit <=#Tp 4'h0;`
355			`else`
356			`if(StartTxDone \| StartTxAbort)`
357			`RetryLimit <=#Tp MaxCollisionOccured;`
358			`end`
359
360
361			`// Latched Late Collision`
362			`always @ (posedge MTxClk or posedge Reset)`
363			`begin`
364			`if(Reset)`
365			`LateCollLatched <=#Tp 1'b0;`
366			`else`
367			`if(StartTxDone \| StartTxAbort)`
368			`LateCollLatched <=#Tp LateCollision;`
369			`end`
370
371
372
373			`// Latched Defer state`
374			`always @ (posedge MTxClk or posedge Reset)`
375			`begin`
376			`if(Reset)`
377			`DeferLatched <=#Tp 1'b0;`
378			`else`
379			`if(StartDefer & TxUsedData)`
380			`DeferLatched <=#Tp 1'b1;`
381			`else`
382			`if(TxStartFrm)`
383			`DeferLatched <=#Tp 1'b0;`
384			`end`
385
386
387			`// CarrierSenseLost`
388			`always @ (posedge MTxClk or posedge Reset)`
389			`begin`
390			`if(Reset)`
391			`CarrierSenseLost <=#Tp 1'b0;`
392			`else`
393	146	mohor	`if((StatePreamble \| (\|StateData)) & ~CarrierSense & ~Loopback & ~Collision)`
394	43	mohor	`CarrierSenseLost <=#Tp 1'b1;`
395			`else`
396			`if(TxStartFrm)`
397			`CarrierSenseLost <=#Tp 1'b0;`
398			`end`
399
400
401	15	mohor	`endmodule`

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