OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_macstatus.v] - Blame information for rev 18

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_macstatus.v                                             ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/cores/ethmac/                      ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001 Authors                                   ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 18 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
45
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
46
// Include files fixed to contain no path.
47
// File names and module names changed ta have a eth_ prologue in the name.
48
// File eth_timescale.v is used to define timescale
49
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
50
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
51
// and Mdo_OE. The bidirectional signal must be created on the top level. This
52
// is done due to the ASIC tools.
53
//
54 15 mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
55
// Directory structure changed. Files checked and joind together.
56
//
57
//
58
//
59
//
60
//
61
 
62
`include "eth_timescale.v"
63
 
64
 
65
module eth_macstatus(
66
                      MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, TransmitEnd, ReceivedPacketGood, RxCrcError,
67
                      MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
68
                      RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, ReceivedPauseFrm
69
                    );
70
 
71
 
72
 
73
parameter Tp = 1;
74
 
75
 
76
input         MRxClk;
77
input         Reset;
78
input         RxCrcError;
79
input         MRxErr;
80
input         MRxDV;
81
 
82
input         RxStateSFD;
83
input   [1:0] RxStateData;
84
input         RxStatePreamble;
85
input         RxStateIdle;
86
input         Transmitting;
87
input  [15:0] RxByteCnt;
88
input         RxByteCntEq0;
89
input         RxByteCntGreat2;
90
input         RxByteCntMaxFrame;
91
input         ReceivedPauseFrm;
92
 
93
output        ReceivedLengthOK;
94
output        ReceiveEnd;
95
output        ReceivedPacketGood;
96
output        TransmitEnd;
97
 
98
reg           ReceiveEnd;
99
 
100
reg           LatchedCrcError;
101
reg           LatchedMRxErr;
102
reg           PreloadRxStatus;
103
reg    [15:0] LatchedRxByteCnt;
104
 
105
wire          TakeSample;
106
 
107
 
108
// Crc error
109
always @ (posedge MRxClk or posedge Reset)
110
begin
111
  if(Reset)
112
    LatchedCrcError <=#Tp 1'b0;
113
  else
114
    begin
115
      if(RxStateSFD)
116
        LatchedCrcError <=#Tp 1'b0;
117
      else
118
      if(RxStateData[0])
119
        LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;
120
    end
121
end
122
 
123
 
124
// LatchedMRxErr
125
always @ (posedge MRxClk or posedge Reset)
126
begin
127
  if(Reset)
128
    LatchedMRxErr <=#Tp 1'b0;
129
  else
130
  if(~MRxErr & MRxDV & RxStateIdle & ~Transmitting)
131
    LatchedMRxErr <=#Tp 1'b0;
132
  else
133 18 mohor
  if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
134 15 mohor
    LatchedMRxErr <=#Tp 1'b1;
135
end
136
 
137
 
138
// ReceivedPacketGood
139
assign ReceivedPacketGood = ~LatchedCrcError & ~LatchedMRxErr;
140
 
141
 
142
// ReceivedLengthOK
143
assign ReceivedLengthOK = LatchedRxByteCnt[15:0] > 63 & LatchedRxByteCnt[15:0] < 1519;
144
 
145
 
146
 
147
// LatchedRxByteCnt[15:0]
148
always @ (posedge MRxClk or posedge Reset)
149
begin
150
  if(Reset)
151
    LatchedRxByteCnt[15:0] <=#Tp 16'h0;
152
  else
153
    begin
154
      if(RxStateSFD)
155
        LatchedRxByteCnt[15:0] <=#Tp RxByteCnt[15:0];
156
      else
157
      if(RxStateData[0])
158
        LatchedRxByteCnt[15:0] <=#Tp RxByteCnt[15:0];
159
    end
160
end
161
 
162
 
163
 
164
// Time to take a sample
165
assign TakeSample = |RxStateData     & ~MRxDV & RxByteCntGreat2  |
166
                     RxStateData[0]  &  MRxDV & RxByteCntMaxFrame;
167
 
168
 
169
// PreloadRxStatus
170
always @ (posedge MRxClk or posedge Reset)
171
begin
172
  if(Reset)
173
    PreloadRxStatus <=#Tp 1'b0;
174
  else
175
    PreloadRxStatus <=#Tp TakeSample;
176
end
177
 
178
 
179
 
180
// ReceiveEnd
181
always @ (posedge MRxClk or posedge Reset)
182
begin
183
  if(Reset)
184
    ReceiveEnd  <=#Tp 1'b0;
185
  else
186
    ReceiveEnd  <=#Tp PreloadRxStatus;
187
end
188
 
189
 
190
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.