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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_macstatus.v] - Blame information for rev 18

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1 15 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_macstatus.v                                             ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/cores/ethmac/                      ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
44 18 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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//
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// Revision 1.1  2001/07/30 21:23:42  mohor
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// Directory structure changed. Files checked and joind together.
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//
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//
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//
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//
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//
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`include "eth_timescale.v"
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module eth_macstatus(
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                      MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, TransmitEnd, ReceivedPacketGood, RxCrcError,
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                      MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
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                      RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, ReceivedPauseFrm
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                    );
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parameter Tp = 1;
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input         MRxClk;
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input         Reset;
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input         RxCrcError;
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input         MRxErr;
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input         MRxDV;
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input         RxStateSFD;
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input   [1:0] RxStateData;
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input         RxStatePreamble;
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input         RxStateIdle;
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input         Transmitting;
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input  [15:0] RxByteCnt;
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input         RxByteCntEq0;
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input         RxByteCntGreat2;
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input         RxByteCntMaxFrame;
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input         ReceivedPauseFrm;
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output        ReceivedLengthOK;
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output        ReceiveEnd;
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output        ReceivedPacketGood;
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output        TransmitEnd;
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reg           ReceiveEnd;
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reg           LatchedCrcError;
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reg           LatchedMRxErr;
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reg           PreloadRxStatus;
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reg    [15:0] LatchedRxByteCnt;
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wire          TakeSample;
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// Crc error
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always @ (posedge MRxClk or posedge Reset)
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begin
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  if(Reset)
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    LatchedCrcError <=#Tp 1'b0;
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  else
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    begin
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      if(RxStateSFD)
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        LatchedCrcError <=#Tp 1'b0;
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      else
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      if(RxStateData[0])
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        LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;
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    end
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end
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// LatchedMRxErr
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always @ (posedge MRxClk or posedge Reset)
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begin
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  if(Reset)
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    LatchedMRxErr <=#Tp 1'b0;
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  else
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  if(~MRxErr & MRxDV & RxStateIdle & ~Transmitting)
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    LatchedMRxErr <=#Tp 1'b0;
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  else
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  if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
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    LatchedMRxErr <=#Tp 1'b1;
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end
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// ReceivedPacketGood
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assign ReceivedPacketGood = ~LatchedCrcError & ~LatchedMRxErr;
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// ReceivedLengthOK
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assign ReceivedLengthOK = LatchedRxByteCnt[15:0] > 63 & LatchedRxByteCnt[15:0] < 1519;
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// LatchedRxByteCnt[15:0]
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always @ (posedge MRxClk or posedge Reset)
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begin
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  if(Reset)
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    LatchedRxByteCnt[15:0] <=#Tp 16'h0;
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  else
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    begin
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      if(RxStateSFD)
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        LatchedRxByteCnt[15:0] <=#Tp RxByteCnt[15:0];
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      else
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      if(RxStateData[0])
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        LatchedRxByteCnt[15:0] <=#Tp RxByteCnt[15:0];
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    end
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end
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// Time to take a sample
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assign TakeSample = |RxStateData     & ~MRxDV & RxByteCntGreat2  |
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                     RxStateData[0]  &  MRxDV & RxByteCntMaxFrame;
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// PreloadRxStatus
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always @ (posedge MRxClk or posedge Reset)
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begin
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  if(Reset)
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    PreloadRxStatus <=#Tp 1'b0;
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  else
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    PreloadRxStatus <=#Tp TakeSample;
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end
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// ReceiveEnd
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always @ (posedge MRxClk or posedge Reset)
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begin
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  if(Reset)
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    ReceiveEnd  <=#Tp 1'b0;
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  else
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    ReceiveEnd  <=#Tp PreloadRxStatus;
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end
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endmodule

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