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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_macstatus.v] - Blame information for rev 352

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1 15 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_macstatus.v                                             ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 15 mohor
////                                                              ////
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////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
11 168 mohor
////  All additional information is available in the Readme.txt   ////
12 15 mohor
////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
16 168 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 15 mohor
////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 333 igorm
// Revision 1.16  2005/02/21 10:42:11  igorm
45
// Defer indication fixed.
46
//
47 325 igorm
// Revision 1.15  2003/01/30 13:28:19  tadejm
48
// Defer indication changed.
49
//
50 276 tadejm
// Revision 1.14  2002/11/22 01:57:06  mohor
51
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
52
// synchronized.
53
//
54 261 mohor
// Revision 1.13  2002/11/13 22:30:58  tadejm
55
// Late collision is reported only when not in the full duplex.
56
// Sample is taken (for status) as soon as MRxDV is not valid (regardless
57
// of the received byte cnt).
58
//
59 242 tadejm
// Revision 1.12  2002/09/12 14:50:16  mohor
60
// CarrierSenseLost bug fixed when operating in full duplex mode.
61
//
62 168 mohor
// Revision 1.11  2002/09/04 18:38:03  mohor
63
// CarrierSenseLost status is not set when working in loopback mode.
64
//
65 146 mohor
// Revision 1.10  2002/07/25 18:17:46  mohor
66
// InvalidSymbol generation changed.
67
//
68 126 mohor
// Revision 1.9  2002/04/22 13:51:44  mohor
69
// Short frame and ReceivedLengthOK were not detected correctly.
70
//
71 101 mohor
// Revision 1.8  2002/02/18 10:40:17  mohor
72
// Small fixes.
73
//
74 70 mohor
// Revision 1.7  2002/02/15 17:07:39  mohor
75
// Status was not written correctly when frames were discarted because of
76
// address mismatch.
77
//
78 64 mohor
// Revision 1.6  2002/02/11 09:18:21  mohor
79
// Tx status is written back to the BD.
80
//
81 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
82
// Rx status is written back to the BD.
83
//
84 42 mohor
// Revision 1.4  2002/01/23 10:28:16  mohor
85
// Link in the header changed.
86
//
87 37 mohor
// Revision 1.3  2001/10/19 08:43:51  mohor
88
// eth_timescale.v changed to timescale.v This is done because of the
89
// simulation of the few cores in a one joined project.
90
//
91 22 mohor
// Revision 1.2  2001/09/11 14:17:00  mohor
92
// Few little NCSIM warnings fixed.
93
//
94 18 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
95
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
96
// Include files fixed to contain no path.
97
// File names and module names changed ta have a eth_ prologue in the name.
98
// File eth_timescale.v is used to define timescale
99
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
100
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
101
// and Mdo_OE. The bidirectional signal must be created on the top level. This
102
// is done due to the ASIC tools.
103
//
104 15 mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
105
// Directory structure changed. Files checked and joind together.
106
//
107
//
108
//
109
//
110
//
111
 
112 22 mohor
`include "timescale.v"
113 15 mohor
 
114
 
115
module eth_macstatus(
116 42 mohor
                      MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
117 15 mohor
                      MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
118 261 mohor
                      RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame,
119 42 mohor
                      InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
120
                      r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
121 43 mohor
                      LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
122 325 igorm
                      RetryLimit, LateCollision, LateCollLatched, DeferIndication, DeferLatched, RstDeferLatched, TxStartFrm,
123 168 mohor
                      StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback,
124
                      r_FullD
125 15 mohor
                    );
126
 
127
 
128
 
129
 
130
input         MRxClk;
131
input         Reset;
132
input         RxCrcError;
133
input         MRxErr;
134
input         MRxDV;
135
 
136
input         RxStateSFD;
137
input   [1:0] RxStateData;
138
input         RxStatePreamble;
139
input         RxStateIdle;
140
input         Transmitting;
141
input  [15:0] RxByteCnt;
142
input         RxByteCntEq0;
143
input         RxByteCntGreat2;
144
input         RxByteCntMaxFrame;
145 42 mohor
input   [3:0] MRxD;
146
input         Collision;
147
input   [5:0] CollValid;
148
input         r_RecSmall;
149
input  [15:0] r_MinFL;
150
input  [15:0] r_MaxFL;
151
input         r_HugEn;
152 43 mohor
input         StartTxDone;
153
input         StartTxAbort;
154
input   [3:0] RetryCnt;
155
input         MTxClk;
156
input         MaxCollisionOccured;
157
input         LateCollision;
158 276 tadejm
input         DeferIndication;
159 43 mohor
input         TxStartFrm;
160
input         StatePreamble;
161
input   [1:0] StateData;
162
input         CarrierSense;
163
input         TxUsedData;
164 146 mohor
input         Loopback;
165 168 mohor
input         r_FullD;
166 15 mohor
 
167 43 mohor
 
168 15 mohor
output        ReceivedLengthOK;
169
output        ReceiveEnd;
170
output        ReceivedPacketGood;
171 42 mohor
output        InvalidSymbol;
172
output        LatchedCrcError;
173
output        RxLateCollision;
174
output        ShortFrame;
175
output        DribbleNibble;
176
output        ReceivedPacketTooBig;
177
output        LoadRxStatus;
178 43 mohor
output  [3:0] RetryCntLatched;
179
output        RetryLimit;
180
output        LateCollLatched;
181
output        DeferLatched;
182 325 igorm
input         RstDeferLatched;
183 43 mohor
output        CarrierSenseLost;
184 126 mohor
output        LatchedMRxErr;
185 15 mohor
 
186 43 mohor
 
187 15 mohor
reg           ReceiveEnd;
188
 
189
reg           LatchedCrcError;
190
reg           LatchedMRxErr;
191 42 mohor
reg           LoadRxStatus;
192
reg           InvalidSymbol;
193 43 mohor
reg     [3:0] RetryCntLatched;
194
reg           RetryLimit;
195
reg           LateCollLatched;
196
reg           DeferLatched;
197
reg           CarrierSenseLost;
198 15 mohor
 
199
wire          TakeSample;
200 42 mohor
wire          SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps 
201 15 mohor
 
202
// Crc error
203
always @ (posedge MRxClk or posedge Reset)
204
begin
205
  if(Reset)
206 352 olof
    LatchedCrcError <= 1'b0;
207 15 mohor
  else
208 42 mohor
  if(RxStateSFD)
209 352 olof
    LatchedCrcError <= 1'b0;
210 42 mohor
  else
211
  if(RxStateData[0])
212 352 olof
    LatchedCrcError <= RxCrcError & ~RxByteCntEq0;
213 15 mohor
end
214
 
215
 
216
// LatchedMRxErr
217
always @ (posedge MRxClk or posedge Reset)
218
begin
219
  if(Reset)
220 352 olof
    LatchedMRxErr <= 1'b0;
221 15 mohor
  else
222 18 mohor
  if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
223 352 olof
    LatchedMRxErr <= 1'b1;
224 126 mohor
  else
225 352 olof
    LatchedMRxErr <= 1'b0;
226 15 mohor
end
227
 
228
 
229
// ReceivedPacketGood
230 126 mohor
assign ReceivedPacketGood = ~LatchedCrcError;
231 15 mohor
 
232
 
233
// ReceivedLengthOK
234 101 mohor
assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];
235 15 mohor
 
236
 
237
 
238 42 mohor
 
239
 
240
// Time to take a sample
241 242 tadejm
//assign TakeSample = |RxStateData     & ~MRxDV & RxByteCntGreat2  |
242
assign TakeSample = (|RxStateData)   & (~MRxDV)                    |
243
                      RxStateData[0] &   MRxDV & RxByteCntMaxFrame;
244 42 mohor
 
245
 
246
// LoadRxStatus
247 15 mohor
always @ (posedge MRxClk or posedge Reset)
248
begin
249
  if(Reset)
250 352 olof
    LoadRxStatus <= 1'b0;
251 15 mohor
  else
252 352 olof
    LoadRxStatus <= TakeSample;
253 15 mohor
end
254
 
255
 
256
 
257 42 mohor
// ReceiveEnd
258
always @ (posedge MRxClk or posedge Reset)
259
begin
260
  if(Reset)
261 352 olof
    ReceiveEnd  <= 1'b0;
262 42 mohor
  else
263 352 olof
    ReceiveEnd  <= LoadRxStatus;
264 42 mohor
end
265 15 mohor
 
266
 
267 42 mohor
// Invalid Symbol received during 100Mbps mode
268 126 mohor
assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;
269 42 mohor
 
270
 
271
// InvalidSymbol
272 15 mohor
always @ (posedge MRxClk or posedge Reset)
273
begin
274
  if(Reset)
275 352 olof
    InvalidSymbol <= 1'b0;
276 15 mohor
  else
277 42 mohor
  if(LoadRxStatus & ~SetInvalidSymbol)
278 352 olof
    InvalidSymbol <= 1'b0;
279 42 mohor
  else
280
  if(SetInvalidSymbol)
281 352 olof
    InvalidSymbol <= 1'b1;
282 15 mohor
end
283
 
284
 
285 42 mohor
// Late Collision
286 15 mohor
 
287 42 mohor
reg RxLateCollision;
288
reg RxColWindow;
289
// Collision Window
290 15 mohor
always @ (posedge MRxClk or posedge Reset)
291
begin
292
  if(Reset)
293 352 olof
    RxLateCollision <= 1'b0;
294 15 mohor
  else
295 42 mohor
  if(LoadRxStatus)
296 352 olof
    RxLateCollision <= 1'b0;
297 42 mohor
  else
298 242 tadejm
  if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall))
299 352 olof
    RxLateCollision <= 1'b1;
300 15 mohor
end
301
 
302 42 mohor
// Collision Window
303
always @ (posedge MRxClk or posedge Reset)
304
begin
305
  if(Reset)
306 352 olof
    RxColWindow <= 1'b1;
307 42 mohor
  else
308
  if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
309 352 olof
    RxColWindow <= 1'b0;
310 42 mohor
  else
311
  if(RxStateIdle)
312 352 olof
    RxColWindow <= 1'b1;
313 42 mohor
end
314 15 mohor
 
315 42 mohor
 
316
// ShortFrame
317
reg ShortFrame;
318
always @ (posedge MRxClk or posedge Reset)
319
begin
320
  if(Reset)
321 352 olof
    ShortFrame <= 1'b0;
322 42 mohor
  else
323
  if(LoadRxStatus)
324 352 olof
    ShortFrame <= 1'b0;
325 42 mohor
  else
326
  if(TakeSample)
327 352 olof
    ShortFrame <= RxByteCnt[15:0] < r_MinFL[15:0];
328 42 mohor
end
329
 
330
 
331
// DribbleNibble
332
reg DribbleNibble;
333
always @ (posedge MRxClk or posedge Reset)
334
begin
335
  if(Reset)
336 352 olof
    DribbleNibble <= 1'b0;
337 42 mohor
  else
338
  if(RxStateSFD)
339 352 olof
    DribbleNibble <= 1'b0;
340 42 mohor
  else
341
  if(~MRxDV & RxStateData[1])
342 352 olof
    DribbleNibble <= 1'b1;
343 42 mohor
end
344
 
345
 
346
reg ReceivedPacketTooBig;
347
always @ (posedge MRxClk or posedge Reset)
348
begin
349
  if(Reset)
350 352 olof
    ReceivedPacketTooBig <= 1'b0;
351 42 mohor
  else
352
  if(LoadRxStatus)
353 352 olof
    ReceivedPacketTooBig <= 1'b0;
354 42 mohor
  else
355
  if(TakeSample)
356 352 olof
    ReceivedPacketTooBig <= ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
357 42 mohor
end
358
 
359 43 mohor
 
360
 
361
// Latched Retry counter for tx status
362
always @ (posedge MTxClk or posedge Reset)
363
begin
364
  if(Reset)
365 352 olof
    RetryCntLatched <= 4'h0;
366 43 mohor
  else
367
  if(StartTxDone | StartTxAbort)
368 352 olof
    RetryCntLatched <= RetryCnt;
369 43 mohor
end
370
 
371
 
372
// Latched Retransmission limit
373
always @ (posedge MTxClk or posedge Reset)
374
begin
375
  if(Reset)
376 352 olof
    RetryLimit <= 1'h0;
377 43 mohor
  else
378
  if(StartTxDone | StartTxAbort)
379 352 olof
    RetryLimit <= MaxCollisionOccured;
380 43 mohor
end
381
 
382
 
383
// Latched Late Collision
384
always @ (posedge MTxClk or posedge Reset)
385
begin
386
  if(Reset)
387 352 olof
    LateCollLatched <= 1'b0;
388 43 mohor
  else
389
  if(StartTxDone | StartTxAbort)
390 352 olof
    LateCollLatched <= LateCollision;
391 43 mohor
end
392
 
393
 
394
 
395
// Latched Defer state
396
always @ (posedge MTxClk or posedge Reset)
397
begin
398
  if(Reset)
399 352 olof
    DeferLatched <= 1'b0;
400 43 mohor
  else
401 325 igorm
  if(DeferIndication)
402 352 olof
    DeferLatched <= 1'b1;
403 43 mohor
  else
404 325 igorm
  if(RstDeferLatched)
405 352 olof
    DeferLatched <= 1'b0;
406 43 mohor
end
407
 
408
 
409
// CarrierSenseLost
410
always @ (posedge MTxClk or posedge Reset)
411
begin
412
  if(Reset)
413 352 olof
    CarrierSenseLost <= 1'b0;
414 43 mohor
  else
415 168 mohor
  if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)
416 352 olof
    CarrierSenseLost <= 1'b1;
417 43 mohor
  else
418
  if(TxStartFrm)
419 352 olof
    CarrierSenseLost <= 1'b0;
420 43 mohor
end
421
 
422
 
423 15 mohor
endmodule

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