OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_miim.v] - Blame information for rev 354

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_miim.v                                                  ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001 Authors                                   ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 333 igorm
// Revision 1.6  2005/02/21 12:48:07  igorm
45
// Warning fixes.
46
//
47 330 igorm
// Revision 1.5  2003/05/16 10:08:27  mohor
48
// Busy was set 2 cycles too late. Reported by Dennis Scott.
49
//
50 284 mohor
// Revision 1.4  2002/08/14 18:32:10  mohor
51
// - Busy signal was not set on time when scan status operation was performed
52
// and clock was divided with more than 2.
53
// - Nvalid remains valid two more clocks (was previously cleared too soon).
54
//
55 133 mohor
// Revision 1.3  2002/01/23 10:28:16  mohor
56
// Link in the header changed.
57
//
58 37 mohor
// Revision 1.2  2001/10/19 08:43:51  mohor
59
// eth_timescale.v changed to timescale.v This is done because of the
60
// simulation of the few cores in a one joined project.
61
//
62 22 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
63
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
64
// Include files fixed to contain no path.
65
// File names and module names changed ta have a eth_ prologue in the name.
66
// File eth_timescale.v is used to define timescale
67
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
68
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
69
// and Mdo_OE. The bidirectional signal must be created on the top level. This
70
// is done due to the ASIC tools.
71
//
72 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
73
// Unconnected signals are now connected.
74
//
75
// Revision 1.1  2001/07/30 21:23:42  mohor
76
// Directory structure changed. Files checked and joind together.
77
//
78
// Revision 1.3  2001/06/01 22:28:56  mohor
79
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
80
//
81
//
82
 
83 22 mohor
`include "timescale.v"
84 15 mohor
 
85
 
86
module eth_miim
87
(
88
  Clk,
89
  Reset,
90
  Divider,
91
  NoPre,
92
  CtrlData,
93
  Rgad,
94
  Fiad,
95
  WCtrlData,
96
  RStat,
97
  ScanStat,
98
  Mdi,
99
  Mdo,
100
  MdoEn,
101
  Mdc,
102
  Busy,
103
  Prsd,
104
  LinkFail,
105
  Nvalid,
106
  WCtrlDataStart,
107
  RStatStart,
108
  UpdateMIIRX_DATAReg
109
);
110
 
111
 
112
 
113
input         Clk;                // Host Clock
114
input         Reset;              // General Reset
115
input   [7:0] Divider;            // Divider for the host clock
116
input  [15:0] CtrlData;           // Control Data (to be written to the PHY reg.)
117
input   [4:0] Rgad;               // Register Address (within the PHY)
118
input   [4:0] Fiad;               // PHY Address
119
input         NoPre;              // No Preamble (no 32-bit preamble)
120
input         WCtrlData;          // Write Control Data operation
121
input         RStat;              // Read Status operation
122
input         ScanStat;           // Scan Status operation
123
input         Mdi;                // MII Management Data In
124
 
125
output        Mdc;                // MII Management Data Clock
126
output        Mdo;                // MII Management Data Output
127
output        MdoEn;              // MII Management Data Output Enable
128
output        Busy;               // Busy Signal
129
output        LinkFail;           // Link Integrity Signal
130
output        Nvalid;             // Invalid Status (qualifier for the valid scan result)
131
 
132
output [15:0] Prsd;               // Read Status Data (data read from the PHY)
133
 
134
output        WCtrlDataStart;     // This signals resets the WCTRLDATA bit in the MIIM Command register
135
output        RStatStart;         // This signal resets the RSTAT BIT in the MIIM Command register
136
output        UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
137
 
138
 
139
reg           Nvalid;
140
reg           EndBusy_d;          // Pre-end Busy signal
141
reg           EndBusy;            // End Busy signal (stops the operation in progress)
142
 
143
reg           WCtrlData_q1;       // Write Control Data operation delayed 1 Clk cycle
144
reg           WCtrlData_q2;       // Write Control Data operation delayed 2 Clk cycles
145
reg           WCtrlData_q3;       // Write Control Data operation delayed 3 Clk cycles
146
reg           WCtrlDataStart;     // Start Write Control Data Command (positive edge detected)
147
reg           WCtrlDataStart_q;
148
reg           WCtrlDataStart_q1;  // Start Write Control Data Command delayed 1 Mdc cycle
149
reg           WCtrlDataStart_q2;  // Start Write Control Data Command delayed 2 Mdc cycles
150
 
151
reg           RStat_q1;           // Read Status operation delayed 1 Clk cycle
152
reg           RStat_q2;           // Read Status operation delayed 2 Clk cycles
153
reg           RStat_q3;           // Read Status operation delayed 3 Clk cycles
154
reg           RStatStart;         // Start Read Status Command (positive edge detected)
155
reg           RStatStart_q1;      // Start Read Status Command delayed 1 Mdc cycle
156
reg           RStatStart_q2;      // Start Read Status Command delayed 2 Mdc cycles
157
 
158
reg           ScanStat_q1;        // Scan Status operation delayed 1 cycle
159
reg           ScanStat_q2;        // Scan Status operation delayed 2 cycles
160
reg           SyncStatMdcEn;      // Scan Status operation delayed at least cycles and synchronized to MdcEn
161
 
162
wire          WriteDataOp;        // Write Data Operation (positive edge detected)
163
wire          ReadStatusOp;       // Read Status Operation (positive edge detected)
164
wire          ScanStatusOp;       // Scan Status Operation (positive edge detected)
165
wire          StartOp;            // Start Operation (start of any of the preceding operations)
166
wire          EndOp;              // End of Operation
167
 
168
reg           InProgress;         // Operation in progress
169
reg           InProgress_q1;      // Operation in progress delayed 1 Mdc cycle
170
reg           InProgress_q2;      // Operation in progress delayed 2 Mdc cycles
171
reg           InProgress_q3;      // Operation in progress delayed 3 Mdc cycles
172
 
173
reg           WriteOp;            // Write Operation Latch (When asserted, write operation is in progress)
174
reg     [6:0] BitCounter;         // Bit Counter
175
 
176
 
177
wire    [3:0] ByteSelect;         // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
178
wire          MdcEn;              // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
179
wire          ShiftedBit;         // This bit is output of the shift register and is connected to the Mdo signal
180 330 igorm
wire          MdcEn_n;
181 15 mohor
 
182
wire          LatchByte1_d2;
183
wire          LatchByte0_d2;
184
reg           LatchByte1_d;
185
reg           LatchByte0_d;
186
reg     [1:0] LatchByte;          // Latch Byte selects which part of Read Status Data is updated from the shift register
187
 
188
reg           UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
189
 
190
 
191
 
192
 
193
 
194
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
195
always @ (posedge Clk or posedge Reset)
196
begin
197
  if(Reset)
198
    begin
199 352 olof
      EndBusy_d <=  1'b0;
200
      EndBusy <=  1'b0;
201 15 mohor
    end
202
  else
203
    begin
204 352 olof
      EndBusy_d <=  ~InProgress_q2 & InProgress_q3;
205
      EndBusy   <=  EndBusy_d;
206 15 mohor
    end
207
end
208
 
209
 
210
// Update MII RX_DATA register
211
always @ (posedge Clk or posedge Reset)
212
begin
213
  if(Reset)
214 352 olof
    UpdateMIIRX_DATAReg <=  0;
215 15 mohor
  else
216
  if(EndBusy & ~WCtrlDataStart_q)
217 352 olof
    UpdateMIIRX_DATAReg <=  1;
218 15 mohor
  else
219 352 olof
    UpdateMIIRX_DATAReg <=  0;
220 15 mohor
end
221
 
222
 
223
 
224
// Generation of the delayed signals used for positive edge triggering.
225
always @ (posedge Clk or posedge Reset)
226
begin
227
  if(Reset)
228
    begin
229 352 olof
      WCtrlData_q1 <=  1'b0;
230
      WCtrlData_q2 <=  1'b0;
231
      WCtrlData_q3 <=  1'b0;
232 15 mohor
 
233 352 olof
      RStat_q1 <=  1'b0;
234
      RStat_q2 <=  1'b0;
235
      RStat_q3 <=  1'b0;
236 15 mohor
 
237 352 olof
      ScanStat_q1  <=  1'b0;
238
      ScanStat_q2  <=  1'b0;
239
      SyncStatMdcEn <=  1'b0;
240 15 mohor
    end
241
  else
242
    begin
243 352 olof
      WCtrlData_q1 <=  WCtrlData;
244
      WCtrlData_q2 <=  WCtrlData_q1;
245
      WCtrlData_q3 <=  WCtrlData_q2;
246 15 mohor
 
247 352 olof
      RStat_q1 <=  RStat;
248
      RStat_q2 <=  RStat_q1;
249
      RStat_q3 <=  RStat_q2;
250 15 mohor
 
251 352 olof
      ScanStat_q1  <=  ScanStat;
252
      ScanStat_q2  <=  ScanStat_q1;
253 15 mohor
      if(MdcEn)
254 352 olof
        SyncStatMdcEn  <=  ScanStat_q2;
255 15 mohor
    end
256
end
257
 
258
 
259
// Generation of the Start Commands (Write Control Data or Read Status)
260
always @ (posedge Clk or posedge Reset)
261
begin
262
  if(Reset)
263
    begin
264 352 olof
      WCtrlDataStart <=  1'b0;
265
      WCtrlDataStart_q <=  1'b0;
266
      RStatStart <=  1'b0;
267 15 mohor
    end
268
  else
269
    begin
270
      if(EndBusy)
271
        begin
272 352 olof
          WCtrlDataStart <=  1'b0;
273
          RStatStart <=  1'b0;
274 15 mohor
        end
275
      else
276
        begin
277
          if(WCtrlData_q2 & ~WCtrlData_q3)
278 352 olof
            WCtrlDataStart <=  1'b1;
279 15 mohor
          if(RStat_q2 & ~RStat_q3)
280 352 olof
            RStatStart <=  1'b1;
281
          WCtrlDataStart_q <=  WCtrlDataStart;
282 15 mohor
        end
283
    end
284
end
285
 
286
 
287
// Generation of the Nvalid signal (indicates when the status is invalid)
288
always @ (posedge Clk or posedge Reset)
289
begin
290
  if(Reset)
291 352 olof
    Nvalid <=  1'b0;
292 15 mohor
  else
293
    begin
294 133 mohor
      if(~InProgress_q2 & InProgress_q3)
295 15 mohor
        begin
296 352 olof
          Nvalid <=  1'b0;
297 15 mohor
        end
298
      else
299
        begin
300
          if(ScanStat_q2  & ~SyncStatMdcEn)
301 352 olof
            Nvalid <=  1'b1;
302 15 mohor
        end
303
    end
304
end
305
 
306
// Signals used for the generation of the Operation signals (positive edge)
307
always @ (posedge Clk or posedge Reset)
308
begin
309
  if(Reset)
310
    begin
311 352 olof
      WCtrlDataStart_q1 <=  1'b0;
312
      WCtrlDataStart_q2 <=  1'b0;
313 15 mohor
 
314 352 olof
      RStatStart_q1 <=  1'b0;
315
      RStatStart_q2 <=  1'b0;
316 15 mohor
 
317 352 olof
      InProgress_q1 <=  1'b0;
318
      InProgress_q2 <=  1'b0;
319
      InProgress_q3 <=  1'b0;
320 15 mohor
 
321 352 olof
          LatchByte0_d <=  1'b0;
322
          LatchByte1_d <=  1'b0;
323 15 mohor
 
324 352 olof
          LatchByte <=  2'b00;
325 15 mohor
    end
326
  else
327
    begin
328
      if(MdcEn)
329
        begin
330 352 olof
          WCtrlDataStart_q1 <=  WCtrlDataStart;
331
          WCtrlDataStart_q2 <=  WCtrlDataStart_q1;
332 15 mohor
 
333 352 olof
          RStatStart_q1 <=  RStatStart;
334
          RStatStart_q2 <=  RStatStart_q1;
335 15 mohor
 
336 352 olof
          LatchByte[0] <=  LatchByte0_d;
337
          LatchByte[1] <=  LatchByte1_d;
338 15 mohor
 
339 352 olof
          LatchByte0_d <=  LatchByte0_d2;
340
          LatchByte1_d <=  LatchByte1_d2;
341 15 mohor
 
342 352 olof
          InProgress_q1 <=  InProgress;
343
          InProgress_q2 <=  InProgress_q1;
344
          InProgress_q3 <=  InProgress_q2;
345 15 mohor
        end
346
    end
347
end
348
 
349
 
350
// Generation of the Operation signals
351
assign WriteDataOp  = WCtrlDataStart_q1 & ~WCtrlDataStart_q2;
352
assign ReadStatusOp = RStatStart_q1     & ~RStatStart_q2;
353
assign ScanStatusOp = SyncStatMdcEn     & ~InProgress & ~InProgress_q1 & ~InProgress_q2;
354
assign StartOp      = WriteDataOp | ReadStatusOp | ScanStatusOp;
355
 
356
// Busy
357 284 mohor
assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
358 15 mohor
 
359
 
360
// Generation of the InProgress signal (indicates when an operation is in progress)
361
// Generation of the WriteOp signal (indicates when a write is in progress)
362
always @ (posedge Clk or posedge Reset)
363
begin
364
  if(Reset)
365
    begin
366 352 olof
      InProgress <=  1'b0;
367
      WriteOp <=  1'b0;
368 15 mohor
    end
369
  else
370
    begin
371
      if(MdcEn)
372
        begin
373
          if(StartOp)
374
            begin
375
              if(~InProgress)
376 352 olof
                WriteOp <=  WriteDataOp;
377
              InProgress <=  1'b1;
378 15 mohor
            end
379
          else
380
            begin
381
              if(EndOp)
382
                begin
383 352 olof
                  InProgress <=  1'b0;
384
                  WriteOp <=  1'b0;
385 15 mohor
                end
386
            end
387
        end
388
    end
389
end
390
 
391
 
392
 
393
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
394
always @ (posedge Clk or posedge Reset)
395
begin
396
  if(Reset)
397 352 olof
    BitCounter[6:0] <=  7'h0;
398 15 mohor
  else
399
    begin
400
      if(MdcEn)
401
        begin
402
          if(InProgress)
403
            begin
404
              if(NoPre & ( BitCounter == 7'h0 ))
405 352 olof
                BitCounter[6:0] <=  7'h21;
406 15 mohor
              else
407 354 olof
                BitCounter[6:0] <=  BitCounter[6:0] + 1;
408 15 mohor
            end
409
          else
410 352 olof
            BitCounter[6:0] <=  7'h0;
411 15 mohor
        end
412
    end
413
end
414
 
415
 
416
// Operation ends when the Bit Counter reaches 63
417
assign EndOp = BitCounter==63;
418
 
419
assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20)));
420
assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);
421
assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);
422
assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);
423
 
424
 
425
// Latch Byte selects which part of Read Status Data is updated from the shift register
426
assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
427
assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
428
 
429
 
430
// Connecting the Clock Generator Module
431 352 olof
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
432 15 mohor
                   );
433
 
434
// Connecting the Shift Register Module
435 352 olof
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
436 15 mohor
                    .CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
437
                    .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
438
                   );
439
 
440
// Connecting the Output Control Module
441 352 olof
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
442 15 mohor
                          .ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
443
                          .Mdo(Mdo), .MdoEn(MdoEn)
444
                         );
445
 
446
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.