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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_receivecontrol.v] - Blame information for rev 15

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_receivecontrol.v                                        ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/cores/ethmac/                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1  2001/07/03 12:51:54  mohor
// Initial release of the MAC Control module.
//
//
//
//
//
 
 
`include "eth_timescale.v"
 
 
module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
                           RxEndFrm, RxFlow, ReceiveEnd, MAC, PassAll, DlyCrcEn, TxDoneIn,
                           TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
                           TxUsedDataOutDetected, Pause, ReceivedPauseFrm
                          );
 
parameter Tp = 1;
 
 
input       MTxClk;
input       MRxClk;
input       TxReset;
input       RxReset;
input [7:0] RxData;
input       RxValid;
input       RxStartFrm;
input       RxEndFrm;
input       RxFlow;
input       ReceiveEnd;
input [47:0]MAC;
input       PassAll;
input       DlyCrcEn;
input       TxDoneIn;
input       TxAbortIn;
input       TxStartFrmOut;
input       ReceivedLengthOK;
input       ReceivedPacketGood;
input       TxUsedDataOutDetected;
 
output      Pause;
output      ReceivedPauseFrm;
 
reg         Pause;
reg         AddressOK;                // Multicast or unicast address detected
reg         TypeLengthOK;             // Type/Length field contains 0x8808
reg         DetectionWindow;          // Detection of the PAUSE frame is possible within this window
reg         OpCodeOK;                 // PAUSE opcode detected (0x0001)
reg  [2:0]  DlyCrcCnt;
reg  [4:0]  ByteCnt;
reg [15:0]  AssembledTimerValue;
reg [15:0]  LatchedTimerValue;
reg         ReceivedPauseFrm;
reg         ReceivedPauseFrmWAddr;
reg         PauseTimerEq0_sync1;
reg         PauseTimerEq0_sync2;
reg [15:0]  PauseTimer;
reg         Divider2;
reg  [5:0]  SlotTimer;
 
wire [47:0] ReservedMulticast;        // 0x0180C2000001
wire [15:0] TypeLength;               // 0x8808
wire        ResetByteCnt;             // 
wire        IncrementByteCnt;         // 
wire        ByteCntEq0;               // ByteCnt = 0
wire        ByteCntEq1;               // ByteCnt = 1
wire        ByteCntEq2;               // ByteCnt = 2
wire        ByteCntEq3;               // ByteCnt = 3
wire        ByteCntEq4;               // ByteCnt = 4
wire        ByteCntEq5;               // ByteCnt = 5
wire        ByteCntEq12;              // ByteCnt = 12
wire        ByteCntEq13;              // ByteCnt = 13
wire        ByteCntEq14;              // ByteCnt = 14
wire        ByteCntEq15;              // ByteCnt = 15
wire        ByteCntEq16;              // ByteCnt = 16
wire        ByteCntEq17;              // ByteCnt = 17
wire        ByteCntEq18;              // ByteCnt = 18
wire        SetPauseTimer;            // 
wire        DecrementPauseTimer;      // 
wire        PauseTimerEq0;            // 
wire        ResetSlotTimer;           // 
wire        IncrementSlotTimer;       // 
wire        SlotFinished;             // 
 
 
 
// Reserved multicast address and Type/Length for PAUSE control
assign ReservedMulticast = 48'h0180C2000001;
assign TypeLength = 16'h8808;
 
 
// Address Detection (Multicast or unicast)
always @ (posedge MRxClk or posedge RxReset)
begin
  if(RxReset)
    AddressOK <= #Tp 1'b0;
  else
  if(DetectionWindow & ByteCntEq0)
    AddressOK <= #Tp  RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40];
  else
  if(DetectionWindow & ByteCntEq1)
    AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK;
  else
  if(DetectionWindow & ByteCntEq2)
    AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK;
  else
  if(DetectionWindow & ByteCntEq3)
    AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK;
  else
  if(DetectionWindow & ByteCntEq4)
    AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[15:8]  | RxData[7:0] == MAC[15:8])  & AddressOK;
  else
  if(DetectionWindow & ByteCntEq5)
    AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[7:0]   | RxData[7:0] == MAC[7:0])   & AddressOK;
  else
  if(ReceiveEnd)
    AddressOK <= #Tp 1'b0;
end
 
 
 
// TypeLengthOK (Type/Length Control frame detected)
always @ (posedge MRxClk or posedge RxReset )
begin
  if(RxReset)
    TypeLengthOK <= #Tp 1'b0;
  else
  if(DetectionWindow & ByteCntEq12)
    TypeLengthOK <= #Tp ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]);
  else
  if(DetectionWindow & ByteCntEq13)
    TypeLengthOK <= #Tp ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK;
  else
  if(ReceiveEnd)
    TypeLengthOK <= #Tp 1'b0;
end
 
 
 
// Latch Control Frame Opcode
always @ (posedge MRxClk or posedge RxReset )
begin
  if(RxReset)
    OpCodeOK <= #Tp 1'b0;
  else
  if(RxStartFrm)
    OpCodeOK <= #Tp 1'b0;
  else
    begin
      if(DetectionWindow & ByteCntEq14)
        OpCodeOK <= #Tp ByteCntEq14 & RxData[7:0] == 8'h00;
 
      if(DetectionWindow & ByteCntEq15)
        OpCodeOK <= #Tp ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK;
    end
end
 
 
// ReceivedPauseFrmWAddr (+Address Check)
always @ (posedge MRxClk or posedge RxReset )
begin
  if(RxReset)
    ReceivedPauseFrmWAddr <= #Tp 1'b0;
  else
  if(ReceiveEnd)
    ReceivedPauseFrmWAddr <= #Tp 1'b0;
  else
  if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK)
    ReceivedPauseFrmWAddr <= #Tp 1'b1;
end
 
 
 
// Assembling 16-bit timer value from two 8-bit data
always @ (posedge MRxClk or posedge RxReset )
begin
  if(RxReset)
    AssembledTimerValue[15:0] <= #Tp 16'h0;
  else
  if(RxStartFrm)
    AssembledTimerValue[15:0] <= #Tp 16'h0;
  else
    begin
      if(DetectionWindow & ByteCntEq16)
        AssembledTimerValue[15:8] <= #Tp RxData[7:0];
      if(DetectionWindow & ByteCntEq17)
        AssembledTimerValue[7:0] <= #Tp RxData[7:0];
    end
end
 
 
// Detection window (while PAUSE detection is possible)
always @ (posedge MRxClk or posedge RxReset )
begin
  if(RxReset)
    DetectionWindow <= #Tp 1'b1;
  else
  if(ByteCntEq18)
    DetectionWindow <= #Tp 1'b0;
  else
  if(ReceiveEnd)
    DetectionWindow <= #Tp 1'b1;
end
 
 
 
// Latching Timer Value
always @ (posedge MRxClk or posedge RxReset )
begin
  if(RxReset)
    LatchedTimerValue[15:0] <= #Tp 16'h0;
  else
  if(~PassAll & DetectionWindow &  ReceivedPauseFrmWAddr &  ByteCntEq18)
    LatchedTimerValue[15:0] <= #Tp AssembledTimerValue[15:0];
  else
  if(ReceiveEnd)
    LatchedTimerValue[15:0] <= #Tp 16'h0;
end
 
 
 
// Delayed CEC counter
always @ (posedge MRxClk or posedge RxReset)
begin
  if(RxReset)
    DlyCrcCnt <= #Tp 3'h0;
  else
  if(RxValid & RxEndFrm)
    DlyCrcCnt <= #Tp 3'h0;
  else
  if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])
    DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
end
 
 
assign ResetByteCnt = RxEndFrm;
assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
 
 
// Byte counter
always @ (posedge MRxClk or posedge RxReset)
begin
  if(RxReset)
    ByteCnt[4:0] <= #Tp 5'h0;
  else
  if(ResetByteCnt)
    ByteCnt[4:0] <= #Tp 5'h0;
  else
  if(IncrementByteCnt)
    ByteCnt[4:0] <= #Tp ByteCnt[4:0] + 1'b1;
end
 
 
assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;
assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;
assign ByteCntEq2 = RxValid & ByteCnt[4:0] == 5'h2;
assign ByteCntEq3 = RxValid & ByteCnt[4:0] == 5'h3;
assign ByteCntEq4 = RxValid & ByteCnt[4:0] == 5'h4;
assign ByteCntEq5 = RxValid & ByteCnt[4:0] == 5'h5;
assign ByteCntEq12 = RxValid & ByteCnt[4:0] == 5'h0C;
assign ByteCntEq13 = RxValid & ByteCnt[4:0] == 5'h0D;
assign ByteCntEq14 = RxValid & ByteCnt[4:0] == 5'h0E;
assign ByteCntEq15 = RxValid & ByteCnt[4:0] == 5'h0F;
assign ByteCntEq16 = RxValid & ByteCnt[4:0] == 5'h10;
assign ByteCntEq17 = RxValid & ByteCnt[4:0] == 5'h11;
assign ByteCntEq18 = RxValid & ByteCnt[4:0] == 5'h12 & DetectionWindow;
 
 
assign SetPauseTimer = ReceiveEnd & ReceivedPauseFrmWAddr & ReceivedPacketGood & ReceivedLengthOK & RxFlow;
assign DecrementPauseTimer = SlotFinished & |PauseTimer;
 
 
// PauseTimer[15:0]
always @ (posedge MRxClk or posedge RxReset)
begin
  if(RxReset)
    PauseTimer[15:0] <= #Tp 16'h0;
  else
  if(SetPauseTimer)
    PauseTimer[15:0] <= #Tp LatchedTimerValue[15:0];
  else
  if(DecrementPauseTimer)
    PauseTimer[15:0] <= #Tp PauseTimer[15:0] - 1'b1;
end
 
assign PauseTimerEq0 = ~(|PauseTimer[15:0]);
 
 
 
// Synchronization of the pause timer
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    begin
      PauseTimerEq0_sync1 <= #Tp 1'b1;
      PauseTimerEq0_sync2 <= #Tp 1'b1;
    end
  else
    begin
      PauseTimerEq0_sync1 <= #Tp PauseTimerEq0;
      PauseTimerEq0_sync2 <= #Tp PauseTimerEq0_sync1;
    end
end
 
 
// Pause signal generation
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    Pause <= #Tp 1'b0;
  else
  if((TxDoneIn | TxAbortIn | ~TxUsedDataOutDetected) & ~TxStartFrmOut)
    Pause <= #Tp RxFlow & ~PauseTimerEq0_sync2;
end
 
 
// Divider2 is used for incrementing the Slot timer every other clock
always @ (posedge MRxClk or posedge RxReset)
begin
  if(RxReset)
    Divider2 <= #Tp 1'b0;
  else
  if(|PauseTimer[15:0] & RxFlow)
    Divider2 <= #Tp ~Divider2;
  else
    Divider2 <= #Tp 1'b0;
end
 
 
assign ResetSlotTimer = RxReset;
assign IncrementSlotTimer =  Pause & RxFlow & Divider2;
 
 
// SlotTimer
always @ (posedge MRxClk or posedge RxReset)
begin
  if(RxReset)
    SlotTimer[5:0] <= #Tp 6'h0;
  else
  if(ResetSlotTimer)
    SlotTimer[5:0] <= #Tp 6'h0;
  else
  if(IncrementSlotTimer)
    SlotTimer[5:0] <= #Tp SlotTimer[5:0] + 1'b1;
end
 
 
assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer;  // Slot is 512 bits (64 bytes)
 
 
 
// Pause Frame received
always @ (posedge MRxClk or posedge RxReset)
begin
  if(RxReset)
    ReceivedPauseFrm <=#Tp 1'b0;
  else
  if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
    ReceivedPauseFrm <=#Tp 1'b1;
  else
  if(ReceiveEnd)
    ReceivedPauseFrm <=#Tp 1'b0;
end
 
 
endmodule

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_receivecontrol.v] - Blame information for rev 15

Line No.	Rev	Author	Line
1	15	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_receivecontrol.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/cores/ethmac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44			`// Revision 1.1 2001/07/30 21:23:42 mohor`
45			`// Directory structure changed. Files checked and joind together.`
46			`//`
47			`// Revision 1.1 2001/07/03 12:51:54 mohor`
48			`// Initial release of the MAC Control module.`
49			`//`
50			`//`
51			`//`
52			`//`
53			`//`
54
55
56			`include "eth_timescale.v"
57
58
59			`module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,`
60			`RxEndFrm, RxFlow, ReceiveEnd, MAC, PassAll, DlyCrcEn, TxDoneIn,`
61			`TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,`
62			`TxUsedDataOutDetected, Pause, ReceivedPauseFrm`
63			`);`
64
65			`parameter Tp = 1;`
66
67
68			`input MTxClk;`
69			`input MRxClk;`
70			`input TxReset;`
71			`input RxReset;`
72			`input [7:0] RxData;`
73			`input RxValid;`
74			`input RxStartFrm;`
75			`input RxEndFrm;`
76			`input RxFlow;`
77			`input ReceiveEnd;`
78			`input [47:0]MAC;`
79			`input PassAll;`
80			`input DlyCrcEn;`
81			`input TxDoneIn;`
82			`input TxAbortIn;`
83			`input TxStartFrmOut;`
84			`input ReceivedLengthOK;`
85			`input ReceivedPacketGood;`
86			`input TxUsedDataOutDetected;`
87
88			`output Pause;`
89			`output ReceivedPauseFrm;`
90
91			`reg Pause;`
92			`reg AddressOK; // Multicast or unicast address detected`
93			`reg TypeLengthOK; // Type/Length field contains 0x8808`
94			`reg DetectionWindow; // Detection of the PAUSE frame is possible within this window`
95			`reg OpCodeOK; // PAUSE opcode detected (0x0001)`
96			`reg [2:0] DlyCrcCnt;`
97			`reg [4:0] ByteCnt;`
98			`reg [15:0] AssembledTimerValue;`
99			`reg [15:0] LatchedTimerValue;`
100			`reg ReceivedPauseFrm;`
101			`reg ReceivedPauseFrmWAddr;`
102			`reg PauseTimerEq0_sync1;`
103			`reg PauseTimerEq0_sync2;`
104			`reg [15:0] PauseTimer;`
105			`reg Divider2;`
106			`reg [5:0] SlotTimer;`
107
108			`wire [47:0] ReservedMulticast; // 0x0180C2000001`
109			`wire [15:0] TypeLength; // 0x8808`
110			`wire ResetByteCnt; //`
111			`wire IncrementByteCnt; //`
112			`wire ByteCntEq0; // ByteCnt = 0`
113			`wire ByteCntEq1; // ByteCnt = 1`
114			`wire ByteCntEq2; // ByteCnt = 2`
115			`wire ByteCntEq3; // ByteCnt = 3`
116			`wire ByteCntEq4; // ByteCnt = 4`
117			`wire ByteCntEq5; // ByteCnt = 5`
118			`wire ByteCntEq12; // ByteCnt = 12`
119			`wire ByteCntEq13; // ByteCnt = 13`
120			`wire ByteCntEq14; // ByteCnt = 14`
121			`wire ByteCntEq15; // ByteCnt = 15`
122			`wire ByteCntEq16; // ByteCnt = 16`
123			`wire ByteCntEq17; // ByteCnt = 17`
124			`wire ByteCntEq18; // ByteCnt = 18`
125			`wire SetPauseTimer; //`
126			`wire DecrementPauseTimer; //`
127			`wire PauseTimerEq0; //`
128			`wire ResetSlotTimer; //`
129			`wire IncrementSlotTimer; //`
130			`wire SlotFinished; //`
131
132
133
134			`// Reserved multicast address and Type/Length for PAUSE control`
135			`assign ReservedMulticast = 48'h0180C2000001;`
136			`assign TypeLength = 16'h8808;`
137
138
139			`// Address Detection (Multicast or unicast)`
140			`always @ (posedge MRxClk or posedge RxReset)`
141			`begin`
142			`if(RxReset)`
143			`AddressOK <= #Tp 1'b0;`
144			`else`
145			`if(DetectionWindow & ByteCntEq0)`
146			`AddressOK <= #Tp RxData[7:0] == ReservedMulticast[47:40] \| RxData[7:0] == MAC[47:40];`
147			`else`
148			`if(DetectionWindow & ByteCntEq1)`
149			`AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[39:32] \| RxData[7:0] == MAC[39:32]) & AddressOK;`
150			`else`
151			`if(DetectionWindow & ByteCntEq2)`
152			`AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[31:24] \| RxData[7:0] == MAC[31:24]) & AddressOK;`
153			`else`
154			`if(DetectionWindow & ByteCntEq3)`
155			`AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[23:16] \| RxData[7:0] == MAC[23:16]) & AddressOK;`
156			`else`
157			`if(DetectionWindow & ByteCntEq4)`
158			`AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[15:8] \| RxData[7:0] == MAC[15:8]) & AddressOK;`
159			`else`
160			`if(DetectionWindow & ByteCntEq5)`
161			`AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[7:0] \| RxData[7:0] == MAC[7:0]) & AddressOK;`
162			`else`
163			`if(ReceiveEnd)`
164			`AddressOK <= #Tp 1'b0;`
165			`end`
166
167
168
169			`// TypeLengthOK (Type/Length Control frame detected)`
170			`always @ (posedge MRxClk or posedge RxReset )`
171			`begin`
172			`if(RxReset)`
173			`TypeLengthOK <= #Tp 1'b0;`
174			`else`
175			`if(DetectionWindow & ByteCntEq12)`
176			`TypeLengthOK <= #Tp ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]);`
177			`else`
178			`if(DetectionWindow & ByteCntEq13)`
179			`TypeLengthOK <= #Tp ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK;`
180			`else`
181			`if(ReceiveEnd)`
182			`TypeLengthOK <= #Tp 1'b0;`
183			`end`
184
185
186
187			`// Latch Control Frame Opcode`
188			`always @ (posedge MRxClk or posedge RxReset )`
189			`begin`
190			`if(RxReset)`
191			`OpCodeOK <= #Tp 1'b0;`
192			`else`
193			`if(RxStartFrm)`
194			`OpCodeOK <= #Tp 1'b0;`
195			`else`
196			`begin`
197			`if(DetectionWindow & ByteCntEq14)`
198			`OpCodeOK <= #Tp ByteCntEq14 & RxData[7:0] == 8'h00;`
199
200			`if(DetectionWindow & ByteCntEq15)`
201			`OpCodeOK <= #Tp ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK;`
202			`end`
203			`end`
204
205
206			`// ReceivedPauseFrmWAddr (+Address Check)`
207			`always @ (posedge MRxClk or posedge RxReset )`
208			`begin`
209			`if(RxReset)`
210			`ReceivedPauseFrmWAddr <= #Tp 1'b0;`
211			`else`
212			`if(ReceiveEnd)`
213			`ReceivedPauseFrmWAddr <= #Tp 1'b0;`
214			`else`
215			`if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK)`
216			`ReceivedPauseFrmWAddr <= #Tp 1'b1;`
217			`end`
218
219
220
221			`// Assembling 16-bit timer value from two 8-bit data`
222			`always @ (posedge MRxClk or posedge RxReset )`
223			`begin`
224			`if(RxReset)`
225			`AssembledTimerValue[15:0] <= #Tp 16'h0;`
226			`else`
227			`if(RxStartFrm)`
228			`AssembledTimerValue[15:0] <= #Tp 16'h0;`
229			`else`
230			`begin`
231			`if(DetectionWindow & ByteCntEq16)`
232			`AssembledTimerValue[15:8] <= #Tp RxData[7:0];`
233			`if(DetectionWindow & ByteCntEq17)`
234			`AssembledTimerValue[7:0] <= #Tp RxData[7:0];`
235			`end`
236			`end`
237
238
239			`// Detection window (while PAUSE detection is possible)`
240			`always @ (posedge MRxClk or posedge RxReset )`
241			`begin`
242			`if(RxReset)`
243			`DetectionWindow <= #Tp 1'b1;`
244			`else`
245			`if(ByteCntEq18)`
246			`DetectionWindow <= #Tp 1'b0;`
247			`else`
248			`if(ReceiveEnd)`
249			`DetectionWindow <= #Tp 1'b1;`
250			`end`
251
252
253
254			`// Latching Timer Value`
255			`always @ (posedge MRxClk or posedge RxReset )`
256			`begin`
257			`if(RxReset)`
258			`LatchedTimerValue[15:0] <= #Tp 16'h0;`
259			`else`
260			`if(~PassAll & DetectionWindow & ReceivedPauseFrmWAddr & ByteCntEq18)`
261			`LatchedTimerValue[15:0] <= #Tp AssembledTimerValue[15:0];`
262			`else`
263			`if(ReceiveEnd)`
264			`LatchedTimerValue[15:0] <= #Tp 16'h0;`
265			`end`
266
267
268
269			`// Delayed CEC counter`
270			`always @ (posedge MRxClk or posedge RxReset)`
271			`begin`
272			`if(RxReset)`
273			`DlyCrcCnt <= #Tp 3'h0;`
274			`else`
275			`if(RxValid & RxEndFrm)`
276			`DlyCrcCnt <= #Tp 3'h0;`
277			`else`
278			`if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])`
279			`DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;`
280			`end`
281
282
283			`assign ResetByteCnt = RxEndFrm;`
284			`assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn \| DlyCrcEn & DlyCrcCnt[2]);`
285
286
287			`// Byte counter`
288			`always @ (posedge MRxClk or posedge RxReset)`
289			`begin`
290			`if(RxReset)`
291			`ByteCnt[4:0] <= #Tp 5'h0;`
292			`else`
293			`if(ResetByteCnt)`
294			`ByteCnt[4:0] <= #Tp 5'h0;`
295			`else`
296			`if(IncrementByteCnt)`
297			`ByteCnt[4:0] <= #Tp ByteCnt[4:0] + 1'b1;`
298			`end`
299
300
301			`assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;`
302			`assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;`
303			`assign ByteCntEq2 = RxValid & ByteCnt[4:0] == 5'h2;`
304			`assign ByteCntEq3 = RxValid & ByteCnt[4:0] == 5'h3;`
305			`assign ByteCntEq4 = RxValid & ByteCnt[4:0] == 5'h4;`
306			`assign ByteCntEq5 = RxValid & ByteCnt[4:0] == 5'h5;`
307			`assign ByteCntEq12 = RxValid & ByteCnt[4:0] == 5'h0C;`
308			`assign ByteCntEq13 = RxValid & ByteCnt[4:0] == 5'h0D;`
309			`assign ByteCntEq14 = RxValid & ByteCnt[4:0] == 5'h0E;`
310			`assign ByteCntEq15 = RxValid & ByteCnt[4:0] == 5'h0F;`
311			`assign ByteCntEq16 = RxValid & ByteCnt[4:0] == 5'h10;`
312			`assign ByteCntEq17 = RxValid & ByteCnt[4:0] == 5'h11;`
313			`assign ByteCntEq18 = RxValid & ByteCnt[4:0] == 5'h12 & DetectionWindow;`
314
315
316			`assign SetPauseTimer = ReceiveEnd & ReceivedPauseFrmWAddr & ReceivedPacketGood & ReceivedLengthOK & RxFlow;`
317			`assign DecrementPauseTimer = SlotFinished & \|PauseTimer;`
318
319
320			`// PauseTimer[15:0]`
321			`always @ (posedge MRxClk or posedge RxReset)`
322			`begin`
323			`if(RxReset)`
324			`PauseTimer[15:0] <= #Tp 16'h0;`
325			`else`
326			`if(SetPauseTimer)`
327			`PauseTimer[15:0] <= #Tp LatchedTimerValue[15:0];`
328			`else`
329			`if(DecrementPauseTimer)`
330			`PauseTimer[15:0] <= #Tp PauseTimer[15:0] - 1'b1;`
331			`end`
332
333			`assign PauseTimerEq0 = ~(\|PauseTimer[15:0]);`
334
335
336
337			`// Synchronization of the pause timer`
338			`always @ (posedge MTxClk or posedge TxReset)`
339			`begin`
340			`if(TxReset)`
341			`begin`
342			`PauseTimerEq0_sync1 <= #Tp 1'b1;`
343			`PauseTimerEq0_sync2 <= #Tp 1'b1;`
344			`end`
345			`else`
346			`begin`
347			`PauseTimerEq0_sync1 <= #Tp PauseTimerEq0;`
348			`PauseTimerEq0_sync2 <= #Tp PauseTimerEq0_sync1;`
349			`end`
350			`end`
351
352
353			`// Pause signal generation`
354			`always @ (posedge MTxClk or posedge TxReset)`
355			`begin`
356			`if(TxReset)`
357			`Pause <= #Tp 1'b0;`
358			`else`
359			`if((TxDoneIn \| TxAbortIn \| ~TxUsedDataOutDetected) & ~TxStartFrmOut)`
360			`Pause <= #Tp RxFlow & ~PauseTimerEq0_sync2;`
361			`end`
362
363
364			`// Divider2 is used for incrementing the Slot timer every other clock`
365			`always @ (posedge MRxClk or posedge RxReset)`
366			`begin`
367			`if(RxReset)`
368			`Divider2 <= #Tp 1'b0;`
369			`else`
370			`if(\|PauseTimer[15:0] & RxFlow)`
371			`Divider2 <= #Tp ~Divider2;`
372			`else`
373			`Divider2 <= #Tp 1'b0;`
374			`end`
375
376
377			`assign ResetSlotTimer = RxReset;`
378			`assign IncrementSlotTimer = Pause & RxFlow & Divider2;`
379
380
381			`// SlotTimer`
382			`always @ (posedge MRxClk or posedge RxReset)`
383			`begin`
384			`if(RxReset)`
385			`SlotTimer[5:0] <= #Tp 6'h0;`
386			`else`
387			`if(ResetSlotTimer)`
388			`SlotTimer[5:0] <= #Tp 6'h0;`
389			`else`
390			`if(IncrementSlotTimer)`
391			`SlotTimer[5:0] <= #Tp SlotTimer[5:0] + 1'b1;`
392			`end`
393
394
395			`assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer; // Slot is 512 bits (64 bytes)`
396
397
398
399			`// Pause Frame received`
400			`always @ (posedge MRxClk or posedge RxReset)`
401			`begin`
402			`if(RxReset)`
403			`ReceivedPauseFrm <=#Tp 1'b0;`
404			`else`
405			`if(ByteCntEq16 & TypeLengthOK & OpCodeOK)`
406			`ReceivedPauseFrm <=#Tp 1'b1;`
407			`else`
408			`if(ReceiveEnd)`
409			`ReceivedPauseFrm <=#Tp 1'b0;`
410			`end`
411
412
413			`endmodule`