OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Blame information for rev 141

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_registers.v                                             ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001 Authors                                   ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 141 mohor
// Revision 1.17  2002/08/16 22:23:03  mohor
45
// Syntax error fixed.
46
//
47 140 mohor
// Revision 1.16  2002/08/16 22:14:22  mohor
48
// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
49
// changed from bit position 10 to 9.
50
//
51 139 mohor
// Revision 1.15  2002/08/14 18:26:37  mohor
52
// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
53
//
54 132 mohor
// Revision 1.14  2002/04/22 14:03:44  mohor
55
// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
56
// or not.
57
//
58 102 mohor
// Revision 1.13  2002/02/26 16:18:09  mohor
59
// Reset values are passed to registers through parameters
60
//
61 74 mohor
// Revision 1.12  2002/02/17 13:23:42  mohor
62
// Define missmatch fixed.
63
//
64 69 mohor
// Revision 1.11  2002/02/16 14:03:44  mohor
65
// Registered trimmed. Unused registers removed.
66
//
67 68 mohor
// Revision 1.10  2002/02/15 11:08:25  mohor
68
// File format fixed a bit.
69
//
70 56 mohor
// Revision 1.9  2002/02/14 20:19:41  billditt
71
// Modified for Address Checking,
72
// addition of eth_addrcheck.v
73
//
74
// Revision 1.8  2002/02/12 17:01:19  mohor
75
// HASH0 and HASH1 registers added. 
76
 
77 46 mohor
// Revision 1.7  2002/01/23 10:28:16  mohor
78
// Link in the header changed.
79
//
80 37 mohor
// Revision 1.6  2001/12/05 15:00:16  mohor
81
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
82
// instead of the number of RX descriptors).
83
//
84 34 mohor
// Revision 1.5  2001/12/05 10:22:19  mohor
85
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
86
//
87 32 mohor
// Revision 1.4  2001/10/19 08:43:51  mohor
88
// eth_timescale.v changed to timescale.v This is done because of the
89
// simulation of the few cores in a one joined project.
90
//
91 22 mohor
// Revision 1.3  2001/10/18 12:07:11  mohor
92
// Status signals changed, Adress decoding changed, interrupt controller
93
// added.
94
//
95 21 mohor
// Revision 1.2  2001/09/24 15:02:56  mohor
96
// Defines changed (All precede with ETH_). Small changes because some
97
// tools generate warnings when two operands are together. Synchronization
98
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
99
// demands).
100
//
101 20 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
102
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
103
// Include files fixed to contain no path.
104
// File names and module names changed ta have a eth_ prologue in the name.
105
// File eth_timescale.v is used to define timescale
106
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
107
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
108
// and Mdo_OE. The bidirectional signal must be created on the top level. This
109
// is done due to the ASIC tools.
110
//
111 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
112
// Unconnected signals are now connected.
113
//
114
// Revision 1.1  2001/07/30 21:23:42  mohor
115
// Directory structure changed. Files checked and joind together.
116
//
117
//
118
//
119
//
120
//
121
//
122
 
123
`include "eth_defines.v"
124 22 mohor
`include "timescale.v"
125 15 mohor
 
126
 
127 68 mohor
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
128 15 mohor
                      r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
129
                      r_Rst, r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
130 21 mohor
                      r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
131 74 mohor
                      TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, TxC_IRQ, RxC_IRQ,
132 21 mohor
                      r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
133 15 mohor
                      r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
134
                      r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
135
                      r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
136
                      LinkFail, r_MAC, WCtrlDataStart, RStatStart,
137 46 mohor
                      UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
138 56 mohor
                      r_HASH0, r_HASH1
139 15 mohor
                    );
140
 
141
parameter Tp = 1;
142
 
143
input [31:0] DataIn;
144 46 mohor
input [7:0] Address;
145 15 mohor
 
146
input Rw;
147
input Cs;
148
input Clk;
149
input Reset;
150
 
151
input WCtrlDataStart;
152
input RStatStart;
153
 
154
input UpdateMIIRX_DATAReg;
155
input [15:0] Prsd;
156
 
157
output [31:0] DataOut;
158
reg    [31:0] DataOut;
159
 
160
output r_RecSmall;
161
output r_Pad;
162
output r_HugEn;
163
output r_CrcEn;
164
output r_DlyCrcEn;
165
output r_Rst;
166
output r_FullD;
167
output r_ExDfrEn;
168
output r_NoBckof;
169
output r_LoopBck;
170
output r_IFG;
171
output r_Pro;
172
output r_Iam;
173
output r_Bro;
174
output r_NoPre;
175
output r_TxEn;
176
output r_RxEn;
177 52 billditt
output [31:0] r_HASH0;
178
output [31:0] r_HASH1;
179 15 mohor
 
180 21 mohor
input TxB_IRQ;
181
input TxE_IRQ;
182
input RxB_IRQ;
183 74 mohor
input RxE_IRQ;
184 21 mohor
input Busy_IRQ;
185 74 mohor
input TxC_IRQ;
186
input RxC_IRQ;
187 15 mohor
 
188
output [6:0] r_IPGT;
189
 
190
output [6:0] r_IPGR1;
191
 
192
output [6:0] r_IPGR2;
193
 
194
output [15:0] r_MinFL;
195
output [15:0] r_MaxFL;
196
 
197
output [3:0] r_MaxRet;
198
output [5:0] r_CollValid;
199
 
200
output r_TxFlow;
201
output r_RxFlow;
202
output r_PassAll;
203
 
204
output r_MiiMRst;
205
output r_MiiNoPre;
206
output [7:0] r_ClkDiv;
207
 
208
output r_WCtrlData;
209
output r_RStat;
210
output r_ScanStat;
211
 
212
output [4:0] r_RGAD;
213
output [4:0] r_FIAD;
214
 
215 21 mohor
output [15:0]r_CtrlData;
216 15 mohor
 
217
 
218
input NValid_stat;
219
input Busy_stat;
220
input LinkFail;
221
 
222 21 mohor
output [47:0]r_MAC;
223 34 mohor
output [7:0] r_TxBDNum;
224
output       TX_BD_NUM_Wr;
225 21 mohor
output       int_o;
226 15 mohor
 
227 21 mohor
reg          irq_txb;
228
reg          irq_txe;
229
reg          irq_rxb;
230 74 mohor
reg          irq_rxe;
231 21 mohor
reg          irq_busy;
232 74 mohor
reg          irq_txc;
233
reg          irq_rxc;
234 15 mohor
 
235
wire Write = Cs &  Rw;
236
wire Read  = Cs & ~Rw;
237
 
238 21 mohor
wire MODER_Wr       = (Address == `ETH_MODER_ADR       )  & Write;
239
wire INT_SOURCE_Wr  = (Address == `ETH_INT_SOURCE_ADR  )  & Write;
240
wire INT_MASK_Wr    = (Address == `ETH_INT_MASK_ADR    )  & Write;
241
wire IPGT_Wr        = (Address == `ETH_IPGT_ADR        )  & Write;
242
wire IPGR1_Wr       = (Address == `ETH_IPGR1_ADR       )  & Write;
243
wire IPGR2_Wr       = (Address == `ETH_IPGR2_ADR       )  & Write;
244
wire PACKETLEN_Wr   = (Address == `ETH_PACKETLEN_ADR   )  & Write;
245
wire COLLCONF_Wr    = (Address == `ETH_COLLCONF_ADR    )  & Write;
246
 
247
wire CTRLMODER_Wr   = (Address == `ETH_CTRLMODER_ADR   )  & Write;
248
wire MIIMODER_Wr    = (Address == `ETH_MIIMODER_ADR    )  & Write;
249
wire MIICOMMAND_Wr  = (Address == `ETH_MIICOMMAND_ADR  )  & Write;
250
wire MIIADDRESS_Wr  = (Address == `ETH_MIIADDRESS_ADR  )  & Write;
251
wire MIITX_DATA_Wr  = (Address == `ETH_MIITX_DATA_ADR  )  & Write;
252
wire MIIRX_DATA_Wr  = UpdateMIIRX_DATAReg;
253
wire MAC_ADDR0_Wr   = (Address == `ETH_MAC_ADDR0_ADR   )  & Write;
254
wire MAC_ADDR1_Wr   = (Address == `ETH_MAC_ADDR1_ADR   )  & Write;
255 52 billditt
wire HASH0_Wr       = (Address == `ETH_HASH0_ADR   )  & Write;
256
wire HASH1_Wr       = (Address == `ETH_HASH1_ADR   )  & Write;
257 34 mohor
assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR   )  & Write;
258 15 mohor
 
259
 
260
 
261
wire [31:0] MODEROut;
262
wire [31:0] INT_SOURCEOut;
263
wire [31:0] INT_MASKOut;
264
wire [31:0] IPGTOut;
265
wire [31:0] IPGR1Out;
266
wire [31:0] IPGR2Out;
267
wire [31:0] PACKETLENOut;
268
wire [31:0] COLLCONFOut;
269
wire [31:0] CTRLMODEROut;
270
wire [31:0] MIIMODEROut;
271
wire [31:0] MIICOMMANDOut;
272
wire [31:0] MIIADDRESSOut;
273
wire [31:0] MIITX_DATAOut;
274
wire [31:0] MIIRX_DATAOut;
275
wire [31:0] MIISTATUSOut;
276
wire [31:0] MAC_ADDR0Out;
277
wire [31:0] MAC_ADDR1Out;
278 34 mohor
wire [31:0] TX_BD_NUMOut;
279 52 billditt
wire [31:0] HASH0Out;
280
wire [31:0] HASH1Out;
281 15 mohor
 
282 46 mohor
 
283 139 mohor
// MODER Register
284
eth_register #(`ETH_MODER_WIDTH, `ETH_MODER_DEF)        MODER
285
  (
286
   .DataIn    (DataIn[`ETH_MODER_WIDTH-1:0]),
287
   .DataOut   (MODEROut[`ETH_MODER_WIDTH-1:0]),
288
   .Write     (MODER_Wr),
289
   .Clk       (Clk),
290
   .Reset     (Reset),
291 141 mohor
   .SyncReset (1'b0)
292 139 mohor
  );
293
assign MODEROut[31:`ETH_MODER_WIDTH] = 0;
294 15 mohor
 
295 139 mohor
// INT_MASK Register
296
eth_register #(`ETH_INT_MASK_WIDTH, `ETH_INT_MASK_DEF)  INT_MASK
297
  (
298
   .DataIn    (DataIn[`ETH_INT_MASK_WIDTH-1:0]),
299
   .DataOut   (INT_MASKOut[`ETH_INT_MASK_WIDTH-1:0]),
300
   .Write     (INT_MASK_Wr),
301
   .Clk       (Clk),
302
   .Reset     (Reset),
303 141 mohor
   .SyncReset (1'b0)
304 139 mohor
  );
305 141 mohor
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH] = 0;
306 52 billditt
 
307 139 mohor
// IPGT Register
308
eth_register #(`ETH_IPGT_WIDTH, `ETH_IPGT_DEF)          IPGT
309
  (
310
   .DataIn    (DataIn[`ETH_IPGT_WIDTH-1:0]),
311
   .DataOut   (IPGTOut[`ETH_IPGT_WIDTH-1:0]),
312
   .Write     (IPGT_Wr),
313
   .Clk       (Clk),
314
   .Reset     (Reset),
315 141 mohor
   .SyncReset (1'b0)
316 139 mohor
  );
317
assign IPGTOut[31:`ETH_IPGT_WIDTH] = 0;
318 52 billditt
 
319 139 mohor
// IPGR1 Register
320
eth_register #(`ETH_IPGR1_WIDTH, `ETH_IPGR1_DEF)        IPGR1
321
  (
322
   .DataIn    (DataIn[`ETH_IPGR1_WIDTH-1:0]),
323
   .DataOut   (IPGR1Out[`ETH_IPGR1_WIDTH-1:0]),
324
   .Write     (IPGR1_Wr),
325
   .Clk       (Clk),
326
   .Reset     (Reset),
327 141 mohor
   .SyncReset (1'b0)
328 139 mohor
  );
329
assign IPGR1Out[31:`ETH_IPGR1_WIDTH] = 0;
330 15 mohor
 
331 139 mohor
// IPGR2 Register
332
eth_register #(`ETH_IPGR2_WIDTH, `ETH_IPGR2_DEF)        IPGR2
333
  (
334
   .DataIn    (DataIn[`ETH_IPGR2_WIDTH-1:0]),
335
   .DataOut   (IPGR2Out[`ETH_IPGR2_WIDTH-1:0]),
336
   .Write     (IPGR2_Wr),
337
   .Clk       (Clk),
338
   .Reset     (Reset),
339 141 mohor
   .SyncReset (1'b0)
340 139 mohor
  );
341
assign IPGR2Out[31:`ETH_IPGR2_WIDTH] = 0;
342 15 mohor
 
343 139 mohor
// PACKETLEN Register
344
eth_register #(`ETH_PACKETLEN_WIDTH, `ETH_PACKETLEN_DEF) PACKETLEN
345
  (
346
   .DataIn    (DataIn),
347
   .DataOut   (PACKETLENOut),
348
   .Write     (PACKETLEN_Wr),
349
   .Clk       (Clk),
350
   .Reset     (Reset),
351 141 mohor
   .SyncReset (1'b0)
352 139 mohor
  );
353 15 mohor
 
354 139 mohor
// COLLCONF Register
355
eth_register #(6, `ETH_COLLCONF0_DEF)                   COLLCONF0
356
  (
357
   .DataIn    (DataIn[5:0]),
358
   .DataOut   (COLLCONFOut[5:0]),
359
   .Write     (COLLCONF_Wr),
360
   .Clk       (Clk),
361
   .Reset     (Reset),
362 141 mohor
   .SyncReset (1'b0)
363 139 mohor
  );
364 68 mohor
assign COLLCONFOut[15:6] = 0;
365 139 mohor
 
366
eth_register #(4, `ETH_COLLCONF1_DEF)                   COLLCONF1
367
  (
368
   .DataIn    (DataIn[19:16]),
369
   .DataOut   (COLLCONFOut[19:16]),
370
   .Write     (COLLCONF_Wr),
371
   .Clk       (Clk),
372
   .Reset     (Reset),
373 141 mohor
   .SyncReset (1'b0)
374 139 mohor
  );
375 68 mohor
assign COLLCONFOut[31:20] = 0;
376 15 mohor
 
377 139 mohor
// TX_BD_NUM Register
378
eth_register #(`ETH_TX_BD_NUM_WIDTH, `ETH_TX_BD_NUM_DEF) TX_BD_NUM
379
  (
380
   .DataIn    (DataIn[`ETH_TX_BD_NUM_WIDTH-1:0]),
381
   .DataOut   (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH-1:0]),
382
   .Write     (TX_BD_NUM_Wr),
383
   .Clk       (Clk),
384
   .Reset     (Reset),
385 141 mohor
   .SyncReset (1'b0)
386 139 mohor
  );
387
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH] = 0;
388 15 mohor
 
389 139 mohor
// CTRLMODER Register
390
eth_register #(`ETH_CTRLMODER_WIDTH, `ETH_CTRLMODER_DEF)  CTRLMODER2
391
  (
392
   .DataIn    (DataIn[`ETH_CTRLMODER_WIDTH-1:0]),
393
   .DataOut   (CTRLMODEROut[`ETH_CTRLMODER_WIDTH-1:0]),
394
   .Write     (CTRLMODER_Wr),
395
   .Clk       (Clk),
396
   .Reset     (Reset),
397 141 mohor
   .SyncReset (1'b0)
398 139 mohor
  );
399
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH] = 0;
400 15 mohor
 
401 139 mohor
// MIIMODER Register
402
eth_register #(`ETH_MIIMODER_WIDTH, `ETH_MIIMODER_DEF)    MIIMODER
403
  (
404
   .DataIn    (DataIn[`ETH_MIIMODER_WIDTH-1:0]),
405
   .DataOut   (MIIMODEROut[`ETH_MIIMODER_WIDTH-1:0]),
406
   .Write     (MIIMODER_Wr),
407
   .Clk       (Clk),
408
   .Reset     (Reset),
409 141 mohor
   .SyncReset (1'b0)
410 139 mohor
  );
411
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH] = 0;
412 68 mohor
 
413 139 mohor
// MIICOMMAND Register
414
eth_register #(1, 0)                                      MIICOMMAND0
415
  (
416
   .DataIn    (DataIn[0]),
417
   .DataOut   (MIICOMMANDOut[0]),
418
   .Write     (MIICOMMAND_Wr),
419
   .Clk       (Clk),
420
   .Reset     (Reset),
421 141 mohor
   .SyncReset (1'b0)
422 139 mohor
  );
423
 
424
eth_register #(1, 0)                                      MIICOMMAND1
425
  (
426
   .DataIn    (DataIn[1]),
427
   .DataOut   (MIICOMMANDOut[1]),
428
   .Write     (MIICOMMAND_Wr),
429
   .Clk       (Clk),
430
   .Reset     (Reset),
431
   .SyncReset (RStatStart)
432
  );
433
 
434
eth_register #(1, 0)                                      MIICOMMAND2
435
  (
436
   .DataIn    (DataIn[2]),
437
   .DataOut   (MIICOMMANDOut[2]),
438
   .Write     (MIICOMMAND_Wr),
439
   .Clk       (Clk),
440
   .Reset     (Reset),
441
   .SyncReset (WCtrlDataStart)
442
  );
443 15 mohor
assign MIICOMMANDOut[31:3] = 29'h0;
444
 
445 139 mohor
// MIIADDRESSRegister
446
eth_register #(5, `ETH_MIIADDRESS0_DEF)                   MIIADDRESS0
447
  (
448
   .DataIn    (DataIn[4:0]),
449
   .DataOut   (MIIADDRESSOut[4:0]),
450
   .Write     (MIIADDRESS_Wr),
451
   .Clk       (Clk),
452
   .Reset     (Reset),
453 141 mohor
   .SyncReset (1'b0)
454 139 mohor
  );
455 68 mohor
assign MIIADDRESSOut[7:5] = 0;
456 139 mohor
 
457
eth_register #(5, `ETH_MIIADDRESS1_DEF)                   MIIADDRESS1
458
  (
459
   .DataIn    (DataIn[12:8]),
460
   .DataOut   (MIIADDRESSOut[12:8]),
461
   .Write     (MIIADDRESS_Wr),
462
   .Clk       (Clk),
463
   .Reset     (Reset),
464 141 mohor
   .SyncReset (1'b0)
465 139 mohor
  );
466 68 mohor
assign MIIADDRESSOut[31:13] = 0;
467 15 mohor
 
468 139 mohor
// MIITX_DATA Register
469
eth_register #(`ETH_MIITX_DATA_WIDTH, `ETH_MIITX_DATA_DEF) MIITX_DATA
470
  (
471
   .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH-1:0]),
472 140 mohor
   .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH-1:0]),
473 139 mohor
   .Write     (MIITX_DATA_Wr),
474
   .Clk       (Clk),
475
   .Reset     (Reset),
476 141 mohor
   .SyncReset (1'b0)
477 139 mohor
  );
478
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH] = 0;
479 15 mohor
 
480 139 mohor
// MIIRX_DATA Register
481
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
482
  (
483
   .DataIn    (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
484
   .DataOut   (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
485
   .Write     (MIIRX_DATA_Wr),
486
   .Clk       (Clk),
487
   .Reset     (Reset),
488 141 mohor
   .SyncReset (1'b0)
489 139 mohor
  );
490
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
491 15 mohor
 
492 139 mohor
// MAC_ADDR0 Register
493
eth_register #(`ETH_MAC_ADDR0_WIDTH, `ETH_MAC_ADDR0_DEF)  MAC_ADDR0
494
  (
495
   .DataIn    (DataIn),
496
   .DataOut   (MAC_ADDR0Out),
497
   .Write     (MAC_ADDR0_Wr),
498
   .Clk       (Clk),
499
   .Reset     (Reset),
500 141 mohor
   .SyncReset (1'b0)
501 139 mohor
  );
502 68 mohor
 
503 139 mohor
// MAC_ADDR1 Register
504
eth_register #(`ETH_MAC_ADDR1_WIDTH, `ETH_MAC_ADDR1_DEF)  MAC_ADDR1
505
  (
506
   .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH-1:0]),
507
   .DataOut   (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH-1:0]),
508
   .Write     (MAC_ADDR1_Wr),
509
   .Clk       (Clk),
510
   .Reset     (Reset),
511 141 mohor
   .SyncReset (1'b0)
512 139 mohor
  );
513
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH] = 0;
514 68 mohor
 
515 139 mohor
// RXHASH0 Register
516
eth_register #(`ETH_HASH0_WIDTH, `ETH_HASH0_DEF)          RXHASH0
517
  (
518
   .DataIn    (DataIn),
519
   .DataOut   (HASH0Out),
520
   .Write     (HASH0_Wr),
521
   .Clk       (Clk),
522
   .Reset     (Reset),
523 141 mohor
   .SyncReset (1'b0)
524 139 mohor
  );
525 68 mohor
 
526 139 mohor
// RXHASH1 Register
527
eth_register #(`ETH_HASH1_WIDTH, `ETH_HASH1_DEF)          RXHASH1
528
  (
529
   .DataIn    (DataIn),
530
   .DataOut   (HASH1Out),
531
   .Write     (HASH1_Wr),
532
   .Clk       (Clk),
533
   .Reset     (Reset),
534 141 mohor
   .SyncReset (1'b0)
535 139 mohor
  );
536 68 mohor
 
537 15 mohor
 
538 139 mohor
// Reading data from registers
539
always @ (Address       or Read           or MODEROut       or INT_SOURCEOut  or
540
          INT_MASKOut   or IPGTOut        or IPGR1Out       or IPGR2Out       or
541
          PACKETLENOut  or COLLCONFOut    or CTRLMODEROut   or MIIMODEROut    or
542
          MIICOMMANDOut or MIIADDRESSOut  or MIITX_DATAOut  or MIIRX_DATAOut  or
543
          MIISTATUSOut  or MAC_ADDR0Out   or MAC_ADDR1Out   or TX_BD_NUMOut   or
544
          HASH0Out      or HASH1Out
545
         )
546 15 mohor
begin
547
  if(Read)  // read
548
    begin
549
      case(Address)
550 20 mohor
        `ETH_MODER_ADR        :  DataOut<=MODEROut;
551
        `ETH_INT_SOURCE_ADR   :  DataOut<=INT_SOURCEOut;
552
        `ETH_INT_MASK_ADR     :  DataOut<=INT_MASKOut;
553
        `ETH_IPGT_ADR         :  DataOut<=IPGTOut;
554
        `ETH_IPGR1_ADR        :  DataOut<=IPGR1Out;
555
        `ETH_IPGR2_ADR        :  DataOut<=IPGR2Out;
556
        `ETH_PACKETLEN_ADR    :  DataOut<=PACKETLENOut;
557
        `ETH_COLLCONF_ADR     :  DataOut<=COLLCONFOut;
558
        `ETH_CTRLMODER_ADR    :  DataOut<=CTRLMODEROut;
559
        `ETH_MIIMODER_ADR     :  DataOut<=MIIMODEROut;
560
        `ETH_MIICOMMAND_ADR   :  DataOut<=MIICOMMANDOut;
561
        `ETH_MIIADDRESS_ADR   :  DataOut<=MIIADDRESSOut;
562
        `ETH_MIITX_DATA_ADR   :  DataOut<=MIITX_DATAOut;
563
        `ETH_MIIRX_DATA_ADR   :  DataOut<=MIIRX_DATAOut;
564
        `ETH_MIISTATUS_ADR    :  DataOut<=MIISTATUSOut;
565
        `ETH_MAC_ADDR0_ADR    :  DataOut<=MAC_ADDR0Out;
566
        `ETH_MAC_ADDR1_ADR    :  DataOut<=MAC_ADDR1Out;
567 34 mohor
        `ETH_TX_BD_NUM_ADR    :  DataOut<=TX_BD_NUMOut;
568 56 mohor
        `ETH_HASH0_ADR        :  DataOut<=HASH0Out;
569
        `ETH_HASH1_ADR        :  DataOut<=HASH1Out;
570 15 mohor
        default:             DataOut<=32'h0;
571
      endcase
572
    end
573
  else
574
    DataOut<=32'h0;
575
end
576
 
577
 
578
assign r_RecSmall         = MODEROut[16];
579
assign r_Pad              = MODEROut[15];
580
assign r_HugEn            = MODEROut[14];
581
assign r_CrcEn            = MODEROut[13];
582
assign r_DlyCrcEn         = MODEROut[12];
583
assign r_Rst              = MODEROut[11];
584
assign r_FullD            = MODEROut[10];
585
assign r_ExDfrEn          = MODEROut[9];
586
assign r_NoBckof          = MODEROut[8];
587
assign r_LoopBck          = MODEROut[7];
588
assign r_IFG              = MODEROut[6];
589
assign r_Pro              = MODEROut[5];
590
assign r_Iam              = MODEROut[4];
591
assign r_Bro              = MODEROut[3];
592
assign r_NoPre            = MODEROut[2];
593
assign r_TxEn             = MODEROut[1];
594
assign r_RxEn             = MODEROut[0];
595
 
596
assign r_IPGT[6:0]        = IPGTOut[6:0];
597
 
598
assign r_IPGR1[6:0]       = IPGR1Out[6:0];
599
 
600
assign r_IPGR2[6:0]       = IPGR2Out[6:0];
601
 
602
assign r_MinFL[15:0]      = PACKETLENOut[31:16];
603
assign r_MaxFL[15:0]      = PACKETLENOut[15:0];
604
 
605 56 mohor
assign r_MaxRet[3:0]      = COLLCONFOut[19:16];
606
assign r_CollValid[5:0]   = COLLCONFOut[5:0];
607 15 mohor
 
608
assign r_TxFlow           = CTRLMODEROut[2];
609
assign r_RxFlow           = CTRLMODEROut[1];
610
assign r_PassAll          = CTRLMODEROut[0];
611
 
612 139 mohor
assign r_MiiMRst          = MIIMODEROut[9];
613 15 mohor
assign r_MiiNoPre         = MIIMODEROut[8];
614
assign r_ClkDiv[7:0]      = MIIMODEROut[7:0];
615
 
616
assign r_WCtrlData        = MIICOMMANDOut[2];
617
assign r_RStat            = MIICOMMANDOut[1];
618
assign r_ScanStat         = MIICOMMANDOut[0];
619
 
620
assign r_RGAD[4:0]        = MIIADDRESSOut[12:8];
621
assign r_FIAD[4:0]        = MIIADDRESSOut[4:0];
622
 
623
assign r_CtrlData[15:0]   = MIITX_DATAOut[15:0];
624
 
625 139 mohor
assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
626
assign MIISTATUSOut[2]    = NValid_stat         ;
627
assign MIISTATUSOut[1]    = Busy_stat           ;
628
assign MIISTATUSOut[0]    = LinkFail            ;
629 15 mohor
 
630
assign r_MAC[31:0]        = MAC_ADDR0Out[31:0];
631
assign r_MAC[47:32]       = MAC_ADDR1Out[15:0];
632 52 billditt
assign r_HASH1[31:0]      = HASH1Out;
633
assign r_HASH0[31:0]      = HASH0Out;
634 15 mohor
 
635 34 mohor
assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
636 15 mohor
 
637
 
638 21 mohor
// Interrupt generation
639
always @ (posedge Clk or posedge Reset)
640
begin
641
  if(Reset)
642
    irq_txb <= 1'b0;
643
  else
644 102 mohor
  if(TxB_IRQ)
645 21 mohor
    irq_txb <= #Tp 1'b1;
646
  else
647
  if(INT_SOURCE_Wr & DataIn[0])
648
    irq_txb <= #Tp 1'b0;
649
end
650
 
651
always @ (posedge Clk or posedge Reset)
652
begin
653
  if(Reset)
654
    irq_txe <= 1'b0;
655
  else
656 102 mohor
  if(TxE_IRQ)
657 21 mohor
    irq_txe <= #Tp 1'b1;
658
  else
659
  if(INT_SOURCE_Wr & DataIn[1])
660
    irq_txe <= #Tp 1'b0;
661
end
662
 
663
always @ (posedge Clk or posedge Reset)
664
begin
665
  if(Reset)
666
    irq_rxb <= 1'b0;
667
  else
668 102 mohor
  if(RxB_IRQ)
669 21 mohor
    irq_rxb <= #Tp 1'b1;
670
  else
671
  if(INT_SOURCE_Wr & DataIn[2])
672
    irq_rxb <= #Tp 1'b0;
673
end
674
 
675
always @ (posedge Clk or posedge Reset)
676
begin
677
  if(Reset)
678 74 mohor
    irq_rxe <= 1'b0;
679 21 mohor
  else
680 102 mohor
  if(RxE_IRQ)
681 74 mohor
    irq_rxe <= #Tp 1'b1;
682 21 mohor
  else
683
  if(INT_SOURCE_Wr & DataIn[3])
684 74 mohor
    irq_rxe <= #Tp 1'b0;
685 21 mohor
end
686
 
687
always @ (posedge Clk or posedge Reset)
688
begin
689
  if(Reset)
690
    irq_busy <= 1'b0;
691
  else
692 102 mohor
  if(Busy_IRQ)
693 21 mohor
    irq_busy <= #Tp 1'b1;
694
  else
695
  if(INT_SOURCE_Wr & DataIn[4])
696
    irq_busy <= #Tp 1'b0;
697
end
698
 
699 74 mohor
always @ (posedge Clk or posedge Reset)
700
begin
701
  if(Reset)
702
    irq_txc <= 1'b0;
703
  else
704 102 mohor
  if(TxC_IRQ)
705 74 mohor
    irq_txc <= #Tp 1'b1;
706
  else
707
  if(INT_SOURCE_Wr & DataIn[5])
708
    irq_txc <= #Tp 1'b0;
709
end
710
 
711
always @ (posedge Clk or posedge Reset)
712
begin
713
  if(Reset)
714
    irq_rxc <= 1'b0;
715
  else
716 102 mohor
  if(RxC_IRQ)
717 74 mohor
    irq_rxc <= #Tp 1'b1;
718
  else
719
  if(INT_SOURCE_Wr & DataIn[6])
720
    irq_rxc <= #Tp 1'b0;
721
end
722
 
723 21 mohor
// Generating interrupt signal
724 102 mohor
assign int_o = irq_txb  & INT_MASKOut[0] |
725
               irq_txe  & INT_MASKOut[1] |
726
               irq_rxb  & INT_MASKOut[2] |
727
               irq_rxe  & INT_MASKOut[3] |
728
               irq_busy & INT_MASKOut[4] |
729
               irq_txc  & INT_MASKOut[5] |
730
               irq_rxc  & INT_MASKOut[6] ;
731 21 mohor
 
732
// For reading interrupt status
733 139 mohor
assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
734 21 mohor
 
735
 
736
 
737 15 mohor
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.