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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Blame information for rev 261

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1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_registers.v                                             ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 147 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 15 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 261 mohor
// Revision 1.23  2002/11/19 18:13:49  mohor
45
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
46
//
47 253 mohor
// Revision 1.22  2002/11/14 18:37:20  mohor
48
// r_Rst signal does not reset any module any more and is removed from the design.
49
//
50 244 mohor
// Revision 1.21  2002/09/10 10:35:23  mohor
51
// Ethernet debug registers removed.
52
//
53 164 mohor
// Revision 1.20  2002/09/04 18:40:25  mohor
54
// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
55
// the control frames connected.
56
//
57 147 mohor
// Revision 1.19  2002/08/19 16:01:40  mohor
58
// Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
59
// r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
60
//
61 143 mohor
// Revision 1.18  2002/08/16 22:28:23  mohor
62
// Syntax error fixed.
63
//
64 141 mohor
// Revision 1.17  2002/08/16 22:23:03  mohor
65
// Syntax error fixed.
66
//
67 140 mohor
// Revision 1.16  2002/08/16 22:14:22  mohor
68
// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
69
// changed from bit position 10 to 9.
70
//
71 139 mohor
// Revision 1.15  2002/08/14 18:26:37  mohor
72
// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
73
//
74 132 mohor
// Revision 1.14  2002/04/22 14:03:44  mohor
75
// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
76
// or not.
77
//
78 102 mohor
// Revision 1.13  2002/02/26 16:18:09  mohor
79
// Reset values are passed to registers through parameters
80
//
81 74 mohor
// Revision 1.12  2002/02/17 13:23:42  mohor
82
// Define missmatch fixed.
83
//
84 69 mohor
// Revision 1.11  2002/02/16 14:03:44  mohor
85
// Registered trimmed. Unused registers removed.
86
//
87 68 mohor
// Revision 1.10  2002/02/15 11:08:25  mohor
88
// File format fixed a bit.
89
//
90 56 mohor
// Revision 1.9  2002/02/14 20:19:41  billditt
91
// Modified for Address Checking,
92
// addition of eth_addrcheck.v
93
//
94
// Revision 1.8  2002/02/12 17:01:19  mohor
95
// HASH0 and HASH1 registers added. 
96
 
97 46 mohor
// Revision 1.7  2002/01/23 10:28:16  mohor
98
// Link in the header changed.
99
//
100 37 mohor
// Revision 1.6  2001/12/05 15:00:16  mohor
101
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
102
// instead of the number of RX descriptors).
103
//
104 34 mohor
// Revision 1.5  2001/12/05 10:22:19  mohor
105
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
106
//
107 32 mohor
// Revision 1.4  2001/10/19 08:43:51  mohor
108
// eth_timescale.v changed to timescale.v This is done because of the
109
// simulation of the few cores in a one joined project.
110
//
111 22 mohor
// Revision 1.3  2001/10/18 12:07:11  mohor
112
// Status signals changed, Adress decoding changed, interrupt controller
113
// added.
114
//
115 21 mohor
// Revision 1.2  2001/09/24 15:02:56  mohor
116
// Defines changed (All precede with ETH_). Small changes because some
117
// tools generate warnings when two operands are together. Synchronization
118
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
119
// demands).
120
//
121 20 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
122
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
123
// Include files fixed to contain no path.
124
// File names and module names changed ta have a eth_ prologue in the name.
125
// File eth_timescale.v is used to define timescale
126
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
127
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
128
// and Mdo_OE. The bidirectional signal must be created on the top level. This
129
// is done due to the ASIC tools.
130
//
131 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
132
// Unconnected signals are now connected.
133
//
134
// Revision 1.1  2001/07/30 21:23:42  mohor
135
// Directory structure changed. Files checked and joind together.
136
//
137
//
138
//
139
//
140
//
141
//
142
 
143
`include "eth_defines.v"
144 22 mohor
`include "timescale.v"
145 15 mohor
 
146
 
147 68 mohor
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
148 15 mohor
                      r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
149 244 mohor
                      r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
150 21 mohor
                      r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
151 147 mohor
                      TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
152 21 mohor
                      r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
153 15 mohor
                      r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
154 253 mohor
                      r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
155 15 mohor
                      r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
156
                      LinkFail, r_MAC, WCtrlDataStart, RStatStart,
157 46 mohor
                      UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
158 147 mohor
                      r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
159 261 mohor
                      StartTxDone, TxClk, RxClk, SetPauseTimer
160 15 mohor
                    );
161
 
162
parameter Tp = 1;
163
 
164
input [31:0] DataIn;
165 46 mohor
input [7:0] Address;
166 15 mohor
 
167
input Rw;
168
input Cs;
169
input Clk;
170
input Reset;
171
 
172
input WCtrlDataStart;
173
input RStatStart;
174
 
175
input UpdateMIIRX_DATAReg;
176
input [15:0] Prsd;
177
 
178
output [31:0] DataOut;
179
reg    [31:0] DataOut;
180
 
181
output r_RecSmall;
182
output r_Pad;
183
output r_HugEn;
184
output r_CrcEn;
185
output r_DlyCrcEn;
186
output r_FullD;
187
output r_ExDfrEn;
188
output r_NoBckof;
189
output r_LoopBck;
190
output r_IFG;
191
output r_Pro;
192
output r_Iam;
193
output r_Bro;
194
output r_NoPre;
195
output r_TxEn;
196
output r_RxEn;
197 52 billditt
output [31:0] r_HASH0;
198
output [31:0] r_HASH1;
199 15 mohor
 
200 21 mohor
input TxB_IRQ;
201
input TxE_IRQ;
202
input RxB_IRQ;
203 74 mohor
input RxE_IRQ;
204 21 mohor
input Busy_IRQ;
205 15 mohor
 
206
output [6:0] r_IPGT;
207
 
208
output [6:0] r_IPGR1;
209
 
210
output [6:0] r_IPGR2;
211
 
212
output [15:0] r_MinFL;
213
output [15:0] r_MaxFL;
214
 
215
output [3:0] r_MaxRet;
216
output [5:0] r_CollValid;
217
 
218
output r_TxFlow;
219
output r_RxFlow;
220
output r_PassAll;
221
 
222
output r_MiiNoPre;
223
output [7:0] r_ClkDiv;
224
 
225
output r_WCtrlData;
226
output r_RStat;
227
output r_ScanStat;
228
 
229
output [4:0] r_RGAD;
230
output [4:0] r_FIAD;
231
 
232 21 mohor
output [15:0]r_CtrlData;
233 15 mohor
 
234
 
235
input NValid_stat;
236
input Busy_stat;
237
input LinkFail;
238
 
239 21 mohor
output [47:0]r_MAC;
240 34 mohor
output [7:0] r_TxBDNum;
241
output       TX_BD_NUM_Wr;
242 21 mohor
output       int_o;
243 147 mohor
output [15:0]r_TxPauseTV;
244
output       r_TxPauseRq;
245
input        RstTxPauseRq;
246
input        TxCtrlEndFrm;
247
input        StartTxDone;
248
input        TxClk;
249
input        RxClk;
250 261 mohor
input        SetPauseTimer;
251 15 mohor
 
252 21 mohor
reg          irq_txb;
253
reg          irq_txe;
254
reg          irq_rxb;
255 74 mohor
reg          irq_rxe;
256 21 mohor
reg          irq_busy;
257 74 mohor
reg          irq_txc;
258
reg          irq_rxc;
259 15 mohor
 
260 147 mohor
reg SetTxCIrq_txclk;
261
reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3;
262
reg SetTxCIrq;
263
reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
264
 
265
reg SetRxCIrq_rxclk;
266
reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
267
reg SetRxCIrq;
268 261 mohor
reg ResetRxCIrq_sync1;
269
reg ResetRxCIrq_sync2;
270
reg ResetRxCIrq_sync3;
271 147 mohor
 
272 15 mohor
wire Write = Cs &  Rw;
273
wire Read  = Cs & ~Rw;
274
 
275 21 mohor
wire MODER_Wr       = (Address == `ETH_MODER_ADR       )  & Write;
276
wire INT_SOURCE_Wr  = (Address == `ETH_INT_SOURCE_ADR  )  & Write;
277
wire INT_MASK_Wr    = (Address == `ETH_INT_MASK_ADR    )  & Write;
278
wire IPGT_Wr        = (Address == `ETH_IPGT_ADR        )  & Write;
279
wire IPGR1_Wr       = (Address == `ETH_IPGR1_ADR       )  & Write;
280
wire IPGR2_Wr       = (Address == `ETH_IPGR2_ADR       )  & Write;
281
wire PACKETLEN_Wr   = (Address == `ETH_PACKETLEN_ADR   )  & Write;
282
wire COLLCONF_Wr    = (Address == `ETH_COLLCONF_ADR    )  & Write;
283
 
284
wire CTRLMODER_Wr   = (Address == `ETH_CTRLMODER_ADR   )  & Write;
285
wire MIIMODER_Wr    = (Address == `ETH_MIIMODER_ADR    )  & Write;
286
wire MIICOMMAND_Wr  = (Address == `ETH_MIICOMMAND_ADR  )  & Write;
287
wire MIIADDRESS_Wr  = (Address == `ETH_MIIADDRESS_ADR  )  & Write;
288
wire MIITX_DATA_Wr  = (Address == `ETH_MIITX_DATA_ADR  )  & Write;
289
wire MIIRX_DATA_Wr  = UpdateMIIRX_DATAReg;
290
wire MAC_ADDR0_Wr   = (Address == `ETH_MAC_ADDR0_ADR   )  & Write;
291
wire MAC_ADDR1_Wr   = (Address == `ETH_MAC_ADDR1_ADR   )  & Write;
292 147 mohor
wire HASH0_Wr       = (Address == `ETH_HASH0_ADR       )  & Write;
293
wire HASH1_Wr       = (Address == `ETH_HASH1_ADR       )  & Write;
294
wire TXCTRL_Wr      = (Address == `ETH_TX_CTRL_ADR     )  & Write;
295
wire RXCTRL_Wr      = (Address == `ETH_RX_CTRL_ADR     )  & Write;
296 34 mohor
assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR   )  & Write;
297 15 mohor
 
298
 
299
 
300
wire [31:0] MODEROut;
301
wire [31:0] INT_SOURCEOut;
302
wire [31:0] INT_MASKOut;
303
wire [31:0] IPGTOut;
304
wire [31:0] IPGR1Out;
305
wire [31:0] IPGR2Out;
306
wire [31:0] PACKETLENOut;
307
wire [31:0] COLLCONFOut;
308
wire [31:0] CTRLMODEROut;
309
wire [31:0] MIIMODEROut;
310
wire [31:0] MIICOMMANDOut;
311
wire [31:0] MIIADDRESSOut;
312
wire [31:0] MIITX_DATAOut;
313
wire [31:0] MIIRX_DATAOut;
314
wire [31:0] MIISTATUSOut;
315
wire [31:0] MAC_ADDR0Out;
316
wire [31:0] MAC_ADDR1Out;
317 34 mohor
wire [31:0] TX_BD_NUMOut;
318 52 billditt
wire [31:0] HASH0Out;
319
wire [31:0] HASH1Out;
320 147 mohor
wire [31:0] TXCTRLOut;
321
wire [31:0] RXCTRLOut;
322 15 mohor
 
323 46 mohor
 
324 139 mohor
// MODER Register
325
eth_register #(`ETH_MODER_WIDTH, `ETH_MODER_DEF)        MODER
326
  (
327
   .DataIn    (DataIn[`ETH_MODER_WIDTH-1:0]),
328
   .DataOut   (MODEROut[`ETH_MODER_WIDTH-1:0]),
329
   .Write     (MODER_Wr),
330
   .Clk       (Clk),
331
   .Reset     (Reset),
332 141 mohor
   .SyncReset (1'b0)
333 139 mohor
  );
334
assign MODEROut[31:`ETH_MODER_WIDTH] = 0;
335 15 mohor
 
336 139 mohor
// INT_MASK Register
337
eth_register #(`ETH_INT_MASK_WIDTH, `ETH_INT_MASK_DEF)  INT_MASK
338
  (
339
   .DataIn    (DataIn[`ETH_INT_MASK_WIDTH-1:0]),
340
   .DataOut   (INT_MASKOut[`ETH_INT_MASK_WIDTH-1:0]),
341
   .Write     (INT_MASK_Wr),
342
   .Clk       (Clk),
343
   .Reset     (Reset),
344 141 mohor
   .SyncReset (1'b0)
345 139 mohor
  );
346 141 mohor
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH] = 0;
347 52 billditt
 
348 139 mohor
// IPGT Register
349
eth_register #(`ETH_IPGT_WIDTH, `ETH_IPGT_DEF)          IPGT
350
  (
351
   .DataIn    (DataIn[`ETH_IPGT_WIDTH-1:0]),
352
   .DataOut   (IPGTOut[`ETH_IPGT_WIDTH-1:0]),
353
   .Write     (IPGT_Wr),
354
   .Clk       (Clk),
355
   .Reset     (Reset),
356 141 mohor
   .SyncReset (1'b0)
357 139 mohor
  );
358
assign IPGTOut[31:`ETH_IPGT_WIDTH] = 0;
359 52 billditt
 
360 139 mohor
// IPGR1 Register
361
eth_register #(`ETH_IPGR1_WIDTH, `ETH_IPGR1_DEF)        IPGR1
362
  (
363
   .DataIn    (DataIn[`ETH_IPGR1_WIDTH-1:0]),
364
   .DataOut   (IPGR1Out[`ETH_IPGR1_WIDTH-1:0]),
365
   .Write     (IPGR1_Wr),
366
   .Clk       (Clk),
367
   .Reset     (Reset),
368 141 mohor
   .SyncReset (1'b0)
369 139 mohor
  );
370
assign IPGR1Out[31:`ETH_IPGR1_WIDTH] = 0;
371 15 mohor
 
372 139 mohor
// IPGR2 Register
373
eth_register #(`ETH_IPGR2_WIDTH, `ETH_IPGR2_DEF)        IPGR2
374
  (
375
   .DataIn    (DataIn[`ETH_IPGR2_WIDTH-1:0]),
376
   .DataOut   (IPGR2Out[`ETH_IPGR2_WIDTH-1:0]),
377
   .Write     (IPGR2_Wr),
378
   .Clk       (Clk),
379
   .Reset     (Reset),
380 141 mohor
   .SyncReset (1'b0)
381 139 mohor
  );
382
assign IPGR2Out[31:`ETH_IPGR2_WIDTH] = 0;
383 15 mohor
 
384 139 mohor
// PACKETLEN Register
385
eth_register #(`ETH_PACKETLEN_WIDTH, `ETH_PACKETLEN_DEF) PACKETLEN
386
  (
387
   .DataIn    (DataIn),
388
   .DataOut   (PACKETLENOut),
389
   .Write     (PACKETLEN_Wr),
390
   .Clk       (Clk),
391
   .Reset     (Reset),
392 141 mohor
   .SyncReset (1'b0)
393 139 mohor
  );
394 15 mohor
 
395 139 mohor
// COLLCONF Register
396
eth_register #(6, `ETH_COLLCONF0_DEF)                   COLLCONF0
397
  (
398
   .DataIn    (DataIn[5:0]),
399
   .DataOut   (COLLCONFOut[5:0]),
400
   .Write     (COLLCONF_Wr),
401
   .Clk       (Clk),
402
   .Reset     (Reset),
403 141 mohor
   .SyncReset (1'b0)
404 139 mohor
  );
405 68 mohor
assign COLLCONFOut[15:6] = 0;
406 139 mohor
 
407
eth_register #(4, `ETH_COLLCONF1_DEF)                   COLLCONF1
408
  (
409
   .DataIn    (DataIn[19:16]),
410
   .DataOut   (COLLCONFOut[19:16]),
411
   .Write     (COLLCONF_Wr),
412
   .Clk       (Clk),
413
   .Reset     (Reset),
414 141 mohor
   .SyncReset (1'b0)
415 139 mohor
  );
416 68 mohor
assign COLLCONFOut[31:20] = 0;
417 15 mohor
 
418 139 mohor
// TX_BD_NUM Register
419
eth_register #(`ETH_TX_BD_NUM_WIDTH, `ETH_TX_BD_NUM_DEF) TX_BD_NUM
420
  (
421
   .DataIn    (DataIn[`ETH_TX_BD_NUM_WIDTH-1:0]),
422
   .DataOut   (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH-1:0]),
423 143 mohor
   .Write     (TX_BD_NUM_Wr & (DataIn<='h80)),
424 139 mohor
   .Clk       (Clk),
425
   .Reset     (Reset),
426 141 mohor
   .SyncReset (1'b0)
427 139 mohor
  );
428
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH] = 0;
429 15 mohor
 
430 139 mohor
// CTRLMODER Register
431
eth_register #(`ETH_CTRLMODER_WIDTH, `ETH_CTRLMODER_DEF)  CTRLMODER2
432
  (
433
   .DataIn    (DataIn[`ETH_CTRLMODER_WIDTH-1:0]),
434
   .DataOut   (CTRLMODEROut[`ETH_CTRLMODER_WIDTH-1:0]),
435
   .Write     (CTRLMODER_Wr),
436
   .Clk       (Clk),
437
   .Reset     (Reset),
438 141 mohor
   .SyncReset (1'b0)
439 139 mohor
  );
440
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH] = 0;
441 15 mohor
 
442 139 mohor
// MIIMODER Register
443
eth_register #(`ETH_MIIMODER_WIDTH, `ETH_MIIMODER_DEF)    MIIMODER
444
  (
445
   .DataIn    (DataIn[`ETH_MIIMODER_WIDTH-1:0]),
446
   .DataOut   (MIIMODEROut[`ETH_MIIMODER_WIDTH-1:0]),
447
   .Write     (MIIMODER_Wr),
448
   .Clk       (Clk),
449
   .Reset     (Reset),
450 141 mohor
   .SyncReset (1'b0)
451 139 mohor
  );
452
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH] = 0;
453 68 mohor
 
454 139 mohor
// MIICOMMAND Register
455
eth_register #(1, 0)                                      MIICOMMAND0
456
  (
457
   .DataIn    (DataIn[0]),
458
   .DataOut   (MIICOMMANDOut[0]),
459
   .Write     (MIICOMMAND_Wr),
460
   .Clk       (Clk),
461
   .Reset     (Reset),
462 141 mohor
   .SyncReset (1'b0)
463 139 mohor
  );
464
 
465
eth_register #(1, 0)                                      MIICOMMAND1
466
  (
467
   .DataIn    (DataIn[1]),
468
   .DataOut   (MIICOMMANDOut[1]),
469
   .Write     (MIICOMMAND_Wr),
470
   .Clk       (Clk),
471
   .Reset     (Reset),
472
   .SyncReset (RStatStart)
473
  );
474
 
475
eth_register #(1, 0)                                      MIICOMMAND2
476
  (
477
   .DataIn    (DataIn[2]),
478
   .DataOut   (MIICOMMANDOut[2]),
479
   .Write     (MIICOMMAND_Wr),
480
   .Clk       (Clk),
481
   .Reset     (Reset),
482
   .SyncReset (WCtrlDataStart)
483
  );
484 15 mohor
assign MIICOMMANDOut[31:3] = 29'h0;
485
 
486 139 mohor
// MIIADDRESSRegister
487
eth_register #(5, `ETH_MIIADDRESS0_DEF)                   MIIADDRESS0
488
  (
489
   .DataIn    (DataIn[4:0]),
490
   .DataOut   (MIIADDRESSOut[4:0]),
491
   .Write     (MIIADDRESS_Wr),
492
   .Clk       (Clk),
493
   .Reset     (Reset),
494 141 mohor
   .SyncReset (1'b0)
495 139 mohor
  );
496 68 mohor
assign MIIADDRESSOut[7:5] = 0;
497 139 mohor
 
498
eth_register #(5, `ETH_MIIADDRESS1_DEF)                   MIIADDRESS1
499
  (
500
   .DataIn    (DataIn[12:8]),
501
   .DataOut   (MIIADDRESSOut[12:8]),
502
   .Write     (MIIADDRESS_Wr),
503
   .Clk       (Clk),
504
   .Reset     (Reset),
505 141 mohor
   .SyncReset (1'b0)
506 139 mohor
  );
507 68 mohor
assign MIIADDRESSOut[31:13] = 0;
508 15 mohor
 
509 139 mohor
// MIITX_DATA Register
510
eth_register #(`ETH_MIITX_DATA_WIDTH, `ETH_MIITX_DATA_DEF) MIITX_DATA
511
  (
512
   .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH-1:0]),
513 140 mohor
   .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH-1:0]),
514 139 mohor
   .Write     (MIITX_DATA_Wr),
515
   .Clk       (Clk),
516
   .Reset     (Reset),
517 141 mohor
   .SyncReset (1'b0)
518 139 mohor
  );
519
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH] = 0;
520 15 mohor
 
521 139 mohor
// MIIRX_DATA Register
522
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
523
  (
524
   .DataIn    (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
525
   .DataOut   (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
526
   .Write     (MIIRX_DATA_Wr),
527
   .Clk       (Clk),
528
   .Reset     (Reset),
529 141 mohor
   .SyncReset (1'b0)
530 139 mohor
  );
531
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
532 15 mohor
 
533 139 mohor
// MAC_ADDR0 Register
534
eth_register #(`ETH_MAC_ADDR0_WIDTH, `ETH_MAC_ADDR0_DEF)  MAC_ADDR0
535
  (
536
   .DataIn    (DataIn),
537
   .DataOut   (MAC_ADDR0Out),
538
   .Write     (MAC_ADDR0_Wr),
539
   .Clk       (Clk),
540
   .Reset     (Reset),
541 141 mohor
   .SyncReset (1'b0)
542 139 mohor
  );
543 68 mohor
 
544 139 mohor
// MAC_ADDR1 Register
545
eth_register #(`ETH_MAC_ADDR1_WIDTH, `ETH_MAC_ADDR1_DEF)  MAC_ADDR1
546
  (
547
   .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH-1:0]),
548
   .DataOut   (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH-1:0]),
549
   .Write     (MAC_ADDR1_Wr),
550
   .Clk       (Clk),
551
   .Reset     (Reset),
552 141 mohor
   .SyncReset (1'b0)
553 139 mohor
  );
554
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH] = 0;
555 68 mohor
 
556 139 mohor
// RXHASH0 Register
557
eth_register #(`ETH_HASH0_WIDTH, `ETH_HASH0_DEF)          RXHASH0
558
  (
559
   .DataIn    (DataIn),
560
   .DataOut   (HASH0Out),
561
   .Write     (HASH0_Wr),
562
   .Clk       (Clk),
563
   .Reset     (Reset),
564 141 mohor
   .SyncReset (1'b0)
565 139 mohor
  );
566 68 mohor
 
567 139 mohor
// RXHASH1 Register
568
eth_register #(`ETH_HASH1_WIDTH, `ETH_HASH1_DEF)          RXHASH1
569
  (
570
   .DataIn    (DataIn),
571
   .DataOut   (HASH1Out),
572
   .Write     (HASH1_Wr),
573
   .Clk       (Clk),
574
   .Reset     (Reset),
575 141 mohor
   .SyncReset (1'b0)
576 139 mohor
  );
577 68 mohor
 
578 15 mohor
 
579 147 mohor
// TXCTRL Register
580
eth_register #((`ETH_TX_CTRL_WIDTH-1), {(`ETH_TX_CTRL_WIDTH-1){1'b0}})      TXCTRL0
581
  (
582
   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH-2:0]),
583
   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH-2:0]),
584
   .Write     (TXCTRL_Wr),
585
   .Clk       (Clk),
586
   .Reset     (Reset),
587
   .SyncReset (1'b0)
588
  );
589
 
590
eth_register #(1, 1'b0)                                   TXCTRL1     // Request bit is synchronously reset
591
  (
592
   .DataIn    (DataIn[16]),
593
   .DataOut   (TXCTRLOut[16]),
594
   .Write     (TXCTRL_Wr),
595
   .Clk       (Clk),
596
   .Reset     (Reset),
597
   .SyncReset (RstTxPauseRq)
598
  );
599
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH] = 0;
600
 
601
 
602
// RXCTRL Register
603
eth_register #(`ETH_RX_CTRL_WIDTH, `ETH_RX_CTRL_DEF)      RXCTRL
604
  (
605
   .DataIn    (DataIn[`ETH_RX_CTRL_WIDTH-1:0]),
606
   .DataOut   (RXCTRLOut[`ETH_RX_CTRL_WIDTH-1:0]),
607
   .Write     (RXCTRL_Wr),
608
   .Clk       (Clk),
609
   .Reset     (Reset),
610
   .SyncReset (1'b0)
611
  );
612
assign RXCTRLOut[31:`ETH_RX_CTRL_WIDTH] = 0;
613
 
614
 
615 139 mohor
// Reading data from registers
616
always @ (Address       or Read           or MODEROut       or INT_SOURCEOut  or
617
          INT_MASKOut   or IPGTOut        or IPGR1Out       or IPGR2Out       or
618
          PACKETLENOut  or COLLCONFOut    or CTRLMODEROut   or MIIMODEROut    or
619
          MIICOMMANDOut or MIIADDRESSOut  or MIITX_DATAOut  or MIIRX_DATAOut  or
620
          MIISTATUSOut  or MAC_ADDR0Out   or MAC_ADDR1Out   or TX_BD_NUMOut   or
621 147 mohor
          HASH0Out      or HASH1Out       or TXCTRLOut      or RXCTRLOut
622 139 mohor
         )
623 15 mohor
begin
624
  if(Read)  // read
625
    begin
626
      case(Address)
627 20 mohor
        `ETH_MODER_ADR        :  DataOut<=MODEROut;
628
        `ETH_INT_SOURCE_ADR   :  DataOut<=INT_SOURCEOut;
629
        `ETH_INT_MASK_ADR     :  DataOut<=INT_MASKOut;
630
        `ETH_IPGT_ADR         :  DataOut<=IPGTOut;
631
        `ETH_IPGR1_ADR        :  DataOut<=IPGR1Out;
632
        `ETH_IPGR2_ADR        :  DataOut<=IPGR2Out;
633
        `ETH_PACKETLEN_ADR    :  DataOut<=PACKETLENOut;
634
        `ETH_COLLCONF_ADR     :  DataOut<=COLLCONFOut;
635
        `ETH_CTRLMODER_ADR    :  DataOut<=CTRLMODEROut;
636
        `ETH_MIIMODER_ADR     :  DataOut<=MIIMODEROut;
637
        `ETH_MIICOMMAND_ADR   :  DataOut<=MIICOMMANDOut;
638
        `ETH_MIIADDRESS_ADR   :  DataOut<=MIIADDRESSOut;
639
        `ETH_MIITX_DATA_ADR   :  DataOut<=MIITX_DATAOut;
640
        `ETH_MIIRX_DATA_ADR   :  DataOut<=MIIRX_DATAOut;
641
        `ETH_MIISTATUS_ADR    :  DataOut<=MIISTATUSOut;
642
        `ETH_MAC_ADDR0_ADR    :  DataOut<=MAC_ADDR0Out;
643
        `ETH_MAC_ADDR1_ADR    :  DataOut<=MAC_ADDR1Out;
644 34 mohor
        `ETH_TX_BD_NUM_ADR    :  DataOut<=TX_BD_NUMOut;
645 56 mohor
        `ETH_HASH0_ADR        :  DataOut<=HASH0Out;
646
        `ETH_HASH1_ADR        :  DataOut<=HASH1Out;
647 147 mohor
        `ETH_TX_CTRL_ADR      :  DataOut<=TXCTRLOut;
648
        `ETH_RX_CTRL_ADR      :  DataOut<=RXCTRLOut;
649
 
650 15 mohor
        default:             DataOut<=32'h0;
651
      endcase
652
    end
653
  else
654
    DataOut<=32'h0;
655
end
656
 
657
 
658
assign r_RecSmall         = MODEROut[16];
659
assign r_Pad              = MODEROut[15];
660
assign r_HugEn            = MODEROut[14];
661
assign r_CrcEn            = MODEROut[13];
662
assign r_DlyCrcEn         = MODEROut[12];
663 244 mohor
// assign r_Rst           = MODEROut[11];   This signal is not used any more
664 15 mohor
assign r_FullD            = MODEROut[10];
665
assign r_ExDfrEn          = MODEROut[9];
666
assign r_NoBckof          = MODEROut[8];
667
assign r_LoopBck          = MODEROut[7];
668
assign r_IFG              = MODEROut[6];
669
assign r_Pro              = MODEROut[5];
670
assign r_Iam              = MODEROut[4];
671
assign r_Bro              = MODEROut[3];
672
assign r_NoPre            = MODEROut[2];
673 143 mohor
assign r_TxEn             = MODEROut[1] & (TX_BD_NUMOut>0);     // Transmission is enabled when there is at least one TxBD.
674
assign r_RxEn             = MODEROut[0] & (TX_BD_NUMOut<'h80);  // Reception is enabled when there is  at least one RxBD.
675 15 mohor
 
676
assign r_IPGT[6:0]        = IPGTOut[6:0];
677
 
678
assign r_IPGR1[6:0]       = IPGR1Out[6:0];
679
 
680
assign r_IPGR2[6:0]       = IPGR2Out[6:0];
681
 
682
assign r_MinFL[15:0]      = PACKETLENOut[31:16];
683
assign r_MaxFL[15:0]      = PACKETLENOut[15:0];
684
 
685 56 mohor
assign r_MaxRet[3:0]      = COLLCONFOut[19:16];
686
assign r_CollValid[5:0]   = COLLCONFOut[5:0];
687 15 mohor
 
688
assign r_TxFlow           = CTRLMODEROut[2];
689
assign r_RxFlow           = CTRLMODEROut[1];
690
assign r_PassAll          = CTRLMODEROut[0];
691
 
692
assign r_MiiNoPre         = MIIMODEROut[8];
693
assign r_ClkDiv[7:0]      = MIIMODEROut[7:0];
694
 
695
assign r_WCtrlData        = MIICOMMANDOut[2];
696
assign r_RStat            = MIICOMMANDOut[1];
697
assign r_ScanStat         = MIICOMMANDOut[0];
698
 
699
assign r_RGAD[4:0]        = MIIADDRESSOut[12:8];
700
assign r_FIAD[4:0]        = MIIADDRESSOut[4:0];
701
 
702
assign r_CtrlData[15:0]   = MIITX_DATAOut[15:0];
703
 
704 139 mohor
assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
705
assign MIISTATUSOut[2]    = NValid_stat         ;
706
assign MIISTATUSOut[1]    = Busy_stat           ;
707
assign MIISTATUSOut[0]    = LinkFail            ;
708 15 mohor
 
709
assign r_MAC[31:0]        = MAC_ADDR0Out[31:0];
710
assign r_MAC[47:32]       = MAC_ADDR1Out[15:0];
711 52 billditt
assign r_HASH1[31:0]      = HASH1Out;
712
assign r_HASH0[31:0]      = HASH0Out;
713 15 mohor
 
714 147 mohor
assign r_TxBDNum[7:0]     = TX_BD_NUMOut[7:0];
715 15 mohor
 
716 147 mohor
assign r_TxPauseTV[15:0]  = TXCTRLOut[15:0];
717
assign r_TxPauseRq        = TXCTRLOut[16];
718 15 mohor
 
719 147 mohor
 
720
// Synchronizing TxC Interrupt
721
always @ (posedge TxClk or posedge Reset)
722
begin
723
  if(Reset)
724
    SetTxCIrq_txclk <=#Tp 1'b0;
725
  else
726
  if(TxCtrlEndFrm & StartTxDone & r_TxFlow)
727
    SetTxCIrq_txclk <=#Tp 1'b1;
728
  else
729
  if(ResetTxCIrq_sync2)
730
    SetTxCIrq_txclk <=#Tp 1'b0;
731
end
732
 
733
 
734
always @ (posedge Clk or posedge Reset)
735
begin
736
  if(Reset)
737
    SetTxCIrq_sync1 <=#Tp 1'b0;
738
  else
739
    SetTxCIrq_sync1 <=#Tp SetTxCIrq_txclk;
740
end
741
 
742
always @ (posedge Clk or posedge Reset)
743
begin
744
  if(Reset)
745
    SetTxCIrq_sync2 <=#Tp 1'b0;
746
  else
747
    SetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
748
end
749
 
750
always @ (posedge Clk or posedge Reset)
751
begin
752
  if(Reset)
753
    SetTxCIrq_sync3 <=#Tp 1'b0;
754
  else
755
    SetTxCIrq_sync3 <=#Tp SetTxCIrq_sync2;
756
end
757
 
758
always @ (posedge Clk or posedge Reset)
759
begin
760
  if(Reset)
761
    SetTxCIrq <=#Tp 1'b0;
762
  else
763
    SetTxCIrq <=#Tp SetTxCIrq_sync2 & ~SetTxCIrq_sync3;
764
end
765
 
766
always @ (posedge TxClk or posedge Reset)
767
begin
768
  if(Reset)
769
    ResetTxCIrq_sync1 <=#Tp 1'b0;
770
  else
771
    ResetTxCIrq_sync1 <=#Tp SetTxCIrq_sync2;
772
end
773
 
774
always @ (posedge TxClk or posedge Reset)
775
begin
776
  if(Reset)
777
    ResetTxCIrq_sync2 <=#Tp 1'b0;
778
  else
779
    ResetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
780
end
781
 
782
 
783
// Synchronizing RxC Interrupt
784
always @ (posedge RxClk or posedge Reset)
785
begin
786
  if(Reset)
787
    SetRxCIrq_rxclk <=#Tp 1'b0;
788
  else
789 261 mohor
  if(SetPauseTimer & r_RxFlow)
790 147 mohor
    SetRxCIrq_rxclk <=#Tp 1'b1;
791
  else
792 261 mohor
  if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
793 147 mohor
    SetRxCIrq_rxclk <=#Tp 1'b0;
794
end
795
 
796
 
797
always @ (posedge Clk or posedge Reset)
798
begin
799
  if(Reset)
800
    SetRxCIrq_sync1 <=#Tp 1'b0;
801
  else
802
    SetRxCIrq_sync1 <=#Tp SetRxCIrq_rxclk;
803
end
804
 
805
always @ (posedge Clk or posedge Reset)
806
begin
807
  if(Reset)
808
    SetRxCIrq_sync2 <=#Tp 1'b0;
809
  else
810
    SetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1;
811
end
812
 
813
always @ (posedge Clk or posedge Reset)
814
begin
815
  if(Reset)
816
    SetRxCIrq_sync3 <=#Tp 1'b0;
817
  else
818
    SetRxCIrq_sync3 <=#Tp SetRxCIrq_sync2;
819
end
820
 
821
always @ (posedge Clk or posedge Reset)
822
begin
823
  if(Reset)
824
    SetRxCIrq <=#Tp 1'b0;
825
  else
826
    SetRxCIrq <=#Tp SetRxCIrq_sync2 & ~SetRxCIrq_sync3;
827
end
828
 
829
always @ (posedge RxClk or posedge Reset)
830
begin
831
  if(Reset)
832
    ResetRxCIrq_sync1 <=#Tp 1'b0;
833
  else
834
    ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2;
835
end
836
 
837 261 mohor
always @ (posedge RxClk or posedge Reset)
838 147 mohor
begin
839
  if(Reset)
840
    ResetRxCIrq_sync2 <=#Tp 1'b0;
841
  else
842 261 mohor
    ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1;
843 147 mohor
end
844
 
845 261 mohor
always @ (posedge RxClk or posedge Reset)
846
begin
847
  if(Reset)
848
    ResetRxCIrq_sync3 <=#Tp 1'b0;
849
  else
850
    ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2;
851
end
852 147 mohor
 
853
 
854
 
855 21 mohor
// Interrupt generation
856
always @ (posedge Clk or posedge Reset)
857
begin
858
  if(Reset)
859
    irq_txb <= 1'b0;
860
  else
861 102 mohor
  if(TxB_IRQ)
862 21 mohor
    irq_txb <= #Tp 1'b1;
863
  else
864
  if(INT_SOURCE_Wr & DataIn[0])
865
    irq_txb <= #Tp 1'b0;
866
end
867
 
868
always @ (posedge Clk or posedge Reset)
869
begin
870
  if(Reset)
871
    irq_txe <= 1'b0;
872
  else
873 102 mohor
  if(TxE_IRQ)
874 21 mohor
    irq_txe <= #Tp 1'b1;
875
  else
876
  if(INT_SOURCE_Wr & DataIn[1])
877
    irq_txe <= #Tp 1'b0;
878
end
879
 
880
always @ (posedge Clk or posedge Reset)
881
begin
882
  if(Reset)
883
    irq_rxb <= 1'b0;
884
  else
885 102 mohor
  if(RxB_IRQ)
886 21 mohor
    irq_rxb <= #Tp 1'b1;
887
  else
888
  if(INT_SOURCE_Wr & DataIn[2])
889
    irq_rxb <= #Tp 1'b0;
890
end
891
 
892
always @ (posedge Clk or posedge Reset)
893
begin
894
  if(Reset)
895 74 mohor
    irq_rxe <= 1'b0;
896 21 mohor
  else
897 102 mohor
  if(RxE_IRQ)
898 74 mohor
    irq_rxe <= #Tp 1'b1;
899 21 mohor
  else
900
  if(INT_SOURCE_Wr & DataIn[3])
901 74 mohor
    irq_rxe <= #Tp 1'b0;
902 21 mohor
end
903
 
904
always @ (posedge Clk or posedge Reset)
905
begin
906
  if(Reset)
907
    irq_busy <= 1'b0;
908
  else
909 102 mohor
  if(Busy_IRQ)
910 21 mohor
    irq_busy <= #Tp 1'b1;
911
  else
912
  if(INT_SOURCE_Wr & DataIn[4])
913
    irq_busy <= #Tp 1'b0;
914
end
915
 
916 74 mohor
always @ (posedge Clk or posedge Reset)
917
begin
918
  if(Reset)
919
    irq_txc <= 1'b0;
920
  else
921 147 mohor
  if(SetTxCIrq)
922 74 mohor
    irq_txc <= #Tp 1'b1;
923
  else
924
  if(INT_SOURCE_Wr & DataIn[5])
925
    irq_txc <= #Tp 1'b0;
926
end
927
 
928
always @ (posedge Clk or posedge Reset)
929
begin
930
  if(Reset)
931
    irq_rxc <= 1'b0;
932
  else
933 147 mohor
  if(SetRxCIrq)
934 74 mohor
    irq_rxc <= #Tp 1'b1;
935
  else
936
  if(INT_SOURCE_Wr & DataIn[6])
937
    irq_rxc <= #Tp 1'b0;
938
end
939
 
940 21 mohor
// Generating interrupt signal
941 102 mohor
assign int_o = irq_txb  & INT_MASKOut[0] |
942
               irq_txe  & INT_MASKOut[1] |
943
               irq_rxb  & INT_MASKOut[2] |
944
               irq_rxe  & INT_MASKOut[3] |
945
               irq_busy & INT_MASKOut[4] |
946
               irq_txc  & INT_MASKOut[5] |
947
               irq_rxc  & INT_MASKOut[6] ;
948 21 mohor
 
949
// For reading interrupt status
950 139 mohor
assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
951 21 mohor
 
952
 
953
 
954 15 mohor
endmodule

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