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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Blame information for rev 283

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1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_registers.v                                             ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 147 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 15 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 283 mohor
// Revision 1.24  2002/11/22 01:57:06  mohor
45
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
46
// synchronized.
47
//
48 261 mohor
// Revision 1.23  2002/11/19 18:13:49  mohor
49
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
50
//
51 253 mohor
// Revision 1.22  2002/11/14 18:37:20  mohor
52
// r_Rst signal does not reset any module any more and is removed from the design.
53
//
54 244 mohor
// Revision 1.21  2002/09/10 10:35:23  mohor
55
// Ethernet debug registers removed.
56
//
57 164 mohor
// Revision 1.20  2002/09/04 18:40:25  mohor
58
// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
59
// the control frames connected.
60
//
61 147 mohor
// Revision 1.19  2002/08/19 16:01:40  mohor
62
// Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
63
// r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
64
//
65 143 mohor
// Revision 1.18  2002/08/16 22:28:23  mohor
66
// Syntax error fixed.
67
//
68 141 mohor
// Revision 1.17  2002/08/16 22:23:03  mohor
69
// Syntax error fixed.
70
//
71 140 mohor
// Revision 1.16  2002/08/16 22:14:22  mohor
72
// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
73
// changed from bit position 10 to 9.
74
//
75 139 mohor
// Revision 1.15  2002/08/14 18:26:37  mohor
76
// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
77
//
78 132 mohor
// Revision 1.14  2002/04/22 14:03:44  mohor
79
// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
80
// or not.
81
//
82 102 mohor
// Revision 1.13  2002/02/26 16:18:09  mohor
83
// Reset values are passed to registers through parameters
84
//
85 74 mohor
// Revision 1.12  2002/02/17 13:23:42  mohor
86
// Define missmatch fixed.
87
//
88 69 mohor
// Revision 1.11  2002/02/16 14:03:44  mohor
89
// Registered trimmed. Unused registers removed.
90
//
91 68 mohor
// Revision 1.10  2002/02/15 11:08:25  mohor
92
// File format fixed a bit.
93
//
94 56 mohor
// Revision 1.9  2002/02/14 20:19:41  billditt
95
// Modified for Address Checking,
96
// addition of eth_addrcheck.v
97
//
98
// Revision 1.8  2002/02/12 17:01:19  mohor
99
// HASH0 and HASH1 registers added. 
100
 
101 46 mohor
// Revision 1.7  2002/01/23 10:28:16  mohor
102
// Link in the header changed.
103
//
104 37 mohor
// Revision 1.6  2001/12/05 15:00:16  mohor
105
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
106
// instead of the number of RX descriptors).
107
//
108 34 mohor
// Revision 1.5  2001/12/05 10:22:19  mohor
109
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
110
//
111 32 mohor
// Revision 1.4  2001/10/19 08:43:51  mohor
112
// eth_timescale.v changed to timescale.v This is done because of the
113
// simulation of the few cores in a one joined project.
114
//
115 22 mohor
// Revision 1.3  2001/10/18 12:07:11  mohor
116
// Status signals changed, Adress decoding changed, interrupt controller
117
// added.
118
//
119 21 mohor
// Revision 1.2  2001/09/24 15:02:56  mohor
120
// Defines changed (All precede with ETH_). Small changes because some
121
// tools generate warnings when two operands are together. Synchronization
122
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
123
// demands).
124
//
125 20 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
126
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
127
// Include files fixed to contain no path.
128
// File names and module names changed ta have a eth_ prologue in the name.
129
// File eth_timescale.v is used to define timescale
130
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
131
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
132
// and Mdo_OE. The bidirectional signal must be created on the top level. This
133
// is done due to the ASIC tools.
134
//
135 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
136
// Unconnected signals are now connected.
137
//
138
// Revision 1.1  2001/07/30 21:23:42  mohor
139
// Directory structure changed. Files checked and joind together.
140
//
141
//
142
//
143
//
144
//
145
//
146
 
147
`include "eth_defines.v"
148 22 mohor
`include "timescale.v"
149 15 mohor
 
150
 
151 68 mohor
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
152 15 mohor
                      r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
153 244 mohor
                      r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
154 21 mohor
                      r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
155 147 mohor
                      TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
156 21 mohor
                      r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
157 15 mohor
                      r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
158 253 mohor
                      r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
159 15 mohor
                      r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
160
                      LinkFail, r_MAC, WCtrlDataStart, RStatStart,
161 46 mohor
                      UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
162 147 mohor
                      r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
163 261 mohor
                      StartTxDone, TxClk, RxClk, SetPauseTimer
164 15 mohor
                    );
165
 
166
parameter Tp = 1;
167
 
168
input [31:0] DataIn;
169 46 mohor
input [7:0] Address;
170 15 mohor
 
171
input Rw;
172
input Cs;
173
input Clk;
174
input Reset;
175
 
176
input WCtrlDataStart;
177
input RStatStart;
178
 
179
input UpdateMIIRX_DATAReg;
180
input [15:0] Prsd;
181
 
182
output [31:0] DataOut;
183
reg    [31:0] DataOut;
184
 
185
output r_RecSmall;
186
output r_Pad;
187
output r_HugEn;
188
output r_CrcEn;
189
output r_DlyCrcEn;
190
output r_FullD;
191
output r_ExDfrEn;
192
output r_NoBckof;
193
output r_LoopBck;
194
output r_IFG;
195
output r_Pro;
196
output r_Iam;
197
output r_Bro;
198
output r_NoPre;
199
output r_TxEn;
200
output r_RxEn;
201 52 billditt
output [31:0] r_HASH0;
202
output [31:0] r_HASH1;
203 15 mohor
 
204 21 mohor
input TxB_IRQ;
205
input TxE_IRQ;
206
input RxB_IRQ;
207 74 mohor
input RxE_IRQ;
208 21 mohor
input Busy_IRQ;
209 15 mohor
 
210
output [6:0] r_IPGT;
211
 
212
output [6:0] r_IPGR1;
213
 
214
output [6:0] r_IPGR2;
215
 
216
output [15:0] r_MinFL;
217
output [15:0] r_MaxFL;
218
 
219
output [3:0] r_MaxRet;
220
output [5:0] r_CollValid;
221
 
222
output r_TxFlow;
223
output r_RxFlow;
224
output r_PassAll;
225
 
226
output r_MiiNoPre;
227
output [7:0] r_ClkDiv;
228
 
229
output r_WCtrlData;
230
output r_RStat;
231
output r_ScanStat;
232
 
233
output [4:0] r_RGAD;
234
output [4:0] r_FIAD;
235
 
236 21 mohor
output [15:0]r_CtrlData;
237 15 mohor
 
238
 
239
input NValid_stat;
240
input Busy_stat;
241
input LinkFail;
242
 
243 21 mohor
output [47:0]r_MAC;
244 34 mohor
output [7:0] r_TxBDNum;
245
output       TX_BD_NUM_Wr;
246 21 mohor
output       int_o;
247 147 mohor
output [15:0]r_TxPauseTV;
248
output       r_TxPauseRq;
249
input        RstTxPauseRq;
250
input        TxCtrlEndFrm;
251
input        StartTxDone;
252
input        TxClk;
253
input        RxClk;
254 261 mohor
input        SetPauseTimer;
255 15 mohor
 
256 21 mohor
reg          irq_txb;
257
reg          irq_txe;
258
reg          irq_rxb;
259 74 mohor
reg          irq_rxe;
260 21 mohor
reg          irq_busy;
261 74 mohor
reg          irq_txc;
262
reg          irq_rxc;
263 15 mohor
 
264 147 mohor
reg SetTxCIrq_txclk;
265
reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3;
266
reg SetTxCIrq;
267
reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
268
 
269
reg SetRxCIrq_rxclk;
270
reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
271
reg SetRxCIrq;
272 261 mohor
reg ResetRxCIrq_sync1;
273
reg ResetRxCIrq_sync2;
274
reg ResetRxCIrq_sync3;
275 147 mohor
 
276 15 mohor
wire Write = Cs &  Rw;
277
wire Read  = Cs & ~Rw;
278
 
279 21 mohor
wire MODER_Wr       = (Address == `ETH_MODER_ADR       )  & Write;
280
wire INT_SOURCE_Wr  = (Address == `ETH_INT_SOURCE_ADR  )  & Write;
281
wire INT_MASK_Wr    = (Address == `ETH_INT_MASK_ADR    )  & Write;
282
wire IPGT_Wr        = (Address == `ETH_IPGT_ADR        )  & Write;
283
wire IPGR1_Wr       = (Address == `ETH_IPGR1_ADR       )  & Write;
284
wire IPGR2_Wr       = (Address == `ETH_IPGR2_ADR       )  & Write;
285
wire PACKETLEN_Wr   = (Address == `ETH_PACKETLEN_ADR   )  & Write;
286
wire COLLCONF_Wr    = (Address == `ETH_COLLCONF_ADR    )  & Write;
287
 
288
wire CTRLMODER_Wr   = (Address == `ETH_CTRLMODER_ADR   )  & Write;
289
wire MIIMODER_Wr    = (Address == `ETH_MIIMODER_ADR    )  & Write;
290
wire MIICOMMAND_Wr  = (Address == `ETH_MIICOMMAND_ADR  )  & Write;
291
wire MIIADDRESS_Wr  = (Address == `ETH_MIIADDRESS_ADR  )  & Write;
292
wire MIITX_DATA_Wr  = (Address == `ETH_MIITX_DATA_ADR  )  & Write;
293
wire MIIRX_DATA_Wr  = UpdateMIIRX_DATAReg;
294
wire MAC_ADDR0_Wr   = (Address == `ETH_MAC_ADDR0_ADR   )  & Write;
295
wire MAC_ADDR1_Wr   = (Address == `ETH_MAC_ADDR1_ADR   )  & Write;
296 147 mohor
wire HASH0_Wr       = (Address == `ETH_HASH0_ADR       )  & Write;
297
wire HASH1_Wr       = (Address == `ETH_HASH1_ADR       )  & Write;
298
wire TXCTRL_Wr      = (Address == `ETH_TX_CTRL_ADR     )  & Write;
299
wire RXCTRL_Wr      = (Address == `ETH_RX_CTRL_ADR     )  & Write;
300 283 mohor
assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR   )  & Write  & (DataIn<='h80);
301 15 mohor
 
302
 
303
 
304
wire [31:0] MODEROut;
305
wire [31:0] INT_SOURCEOut;
306
wire [31:0] INT_MASKOut;
307
wire [31:0] IPGTOut;
308
wire [31:0] IPGR1Out;
309
wire [31:0] IPGR2Out;
310
wire [31:0] PACKETLENOut;
311
wire [31:0] COLLCONFOut;
312
wire [31:0] CTRLMODEROut;
313
wire [31:0] MIIMODEROut;
314
wire [31:0] MIICOMMANDOut;
315
wire [31:0] MIIADDRESSOut;
316
wire [31:0] MIITX_DATAOut;
317
wire [31:0] MIIRX_DATAOut;
318
wire [31:0] MIISTATUSOut;
319
wire [31:0] MAC_ADDR0Out;
320
wire [31:0] MAC_ADDR1Out;
321 34 mohor
wire [31:0] TX_BD_NUMOut;
322 52 billditt
wire [31:0] HASH0Out;
323
wire [31:0] HASH1Out;
324 147 mohor
wire [31:0] TXCTRLOut;
325
wire [31:0] RXCTRLOut;
326 15 mohor
 
327 139 mohor
// MODER Register
328
eth_register #(`ETH_MODER_WIDTH, `ETH_MODER_DEF)        MODER
329
  (
330
   .DataIn    (DataIn[`ETH_MODER_WIDTH-1:0]),
331
   .DataOut   (MODEROut[`ETH_MODER_WIDTH-1:0]),
332
   .Write     (MODER_Wr),
333
   .Clk       (Clk),
334
   .Reset     (Reset),
335 141 mohor
   .SyncReset (1'b0)
336 139 mohor
  );
337
assign MODEROut[31:`ETH_MODER_WIDTH] = 0;
338 15 mohor
 
339 139 mohor
// INT_MASK Register
340
eth_register #(`ETH_INT_MASK_WIDTH, `ETH_INT_MASK_DEF)  INT_MASK
341
  (
342
   .DataIn    (DataIn[`ETH_INT_MASK_WIDTH-1:0]),
343
   .DataOut   (INT_MASKOut[`ETH_INT_MASK_WIDTH-1:0]),
344
   .Write     (INT_MASK_Wr),
345
   .Clk       (Clk),
346
   .Reset     (Reset),
347 141 mohor
   .SyncReset (1'b0)
348 139 mohor
  );
349 141 mohor
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH] = 0;
350 52 billditt
 
351 139 mohor
// IPGT Register
352
eth_register #(`ETH_IPGT_WIDTH, `ETH_IPGT_DEF)          IPGT
353
  (
354
   .DataIn    (DataIn[`ETH_IPGT_WIDTH-1:0]),
355
   .DataOut   (IPGTOut[`ETH_IPGT_WIDTH-1:0]),
356
   .Write     (IPGT_Wr),
357
   .Clk       (Clk),
358
   .Reset     (Reset),
359 141 mohor
   .SyncReset (1'b0)
360 139 mohor
  );
361
assign IPGTOut[31:`ETH_IPGT_WIDTH] = 0;
362 52 billditt
 
363 139 mohor
// IPGR1 Register
364
eth_register #(`ETH_IPGR1_WIDTH, `ETH_IPGR1_DEF)        IPGR1
365
  (
366
   .DataIn    (DataIn[`ETH_IPGR1_WIDTH-1:0]),
367
   .DataOut   (IPGR1Out[`ETH_IPGR1_WIDTH-1:0]),
368
   .Write     (IPGR1_Wr),
369
   .Clk       (Clk),
370
   .Reset     (Reset),
371 141 mohor
   .SyncReset (1'b0)
372 139 mohor
  );
373
assign IPGR1Out[31:`ETH_IPGR1_WIDTH] = 0;
374 15 mohor
 
375 139 mohor
// IPGR2 Register
376
eth_register #(`ETH_IPGR2_WIDTH, `ETH_IPGR2_DEF)        IPGR2
377
  (
378
   .DataIn    (DataIn[`ETH_IPGR2_WIDTH-1:0]),
379
   .DataOut   (IPGR2Out[`ETH_IPGR2_WIDTH-1:0]),
380
   .Write     (IPGR2_Wr),
381
   .Clk       (Clk),
382
   .Reset     (Reset),
383 141 mohor
   .SyncReset (1'b0)
384 139 mohor
  );
385
assign IPGR2Out[31:`ETH_IPGR2_WIDTH] = 0;
386 15 mohor
 
387 139 mohor
// PACKETLEN Register
388
eth_register #(`ETH_PACKETLEN_WIDTH, `ETH_PACKETLEN_DEF) PACKETLEN
389
  (
390
   .DataIn    (DataIn),
391
   .DataOut   (PACKETLENOut),
392
   .Write     (PACKETLEN_Wr),
393
   .Clk       (Clk),
394
   .Reset     (Reset),
395 141 mohor
   .SyncReset (1'b0)
396 139 mohor
  );
397 15 mohor
 
398 139 mohor
// COLLCONF Register
399
eth_register #(6, `ETH_COLLCONF0_DEF)                   COLLCONF0
400
  (
401
   .DataIn    (DataIn[5:0]),
402
   .DataOut   (COLLCONFOut[5:0]),
403
   .Write     (COLLCONF_Wr),
404
   .Clk       (Clk),
405
   .Reset     (Reset),
406 141 mohor
   .SyncReset (1'b0)
407 139 mohor
  );
408 68 mohor
assign COLLCONFOut[15:6] = 0;
409 139 mohor
 
410
eth_register #(4, `ETH_COLLCONF1_DEF)                   COLLCONF1
411
  (
412
   .DataIn    (DataIn[19:16]),
413
   .DataOut   (COLLCONFOut[19:16]),
414
   .Write     (COLLCONF_Wr),
415
   .Clk       (Clk),
416
   .Reset     (Reset),
417 141 mohor
   .SyncReset (1'b0)
418 139 mohor
  );
419 68 mohor
assign COLLCONFOut[31:20] = 0;
420 15 mohor
 
421 139 mohor
// TX_BD_NUM Register
422
eth_register #(`ETH_TX_BD_NUM_WIDTH, `ETH_TX_BD_NUM_DEF) TX_BD_NUM
423
  (
424
   .DataIn    (DataIn[`ETH_TX_BD_NUM_WIDTH-1:0]),
425
   .DataOut   (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH-1:0]),
426 283 mohor
   .Write     (TX_BD_NUM_Wr),
427 139 mohor
   .Clk       (Clk),
428
   .Reset     (Reset),
429 141 mohor
   .SyncReset (1'b0)
430 139 mohor
  );
431
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH] = 0;
432 15 mohor
 
433 139 mohor
// CTRLMODER Register
434
eth_register #(`ETH_CTRLMODER_WIDTH, `ETH_CTRLMODER_DEF)  CTRLMODER2
435
  (
436
   .DataIn    (DataIn[`ETH_CTRLMODER_WIDTH-1:0]),
437
   .DataOut   (CTRLMODEROut[`ETH_CTRLMODER_WIDTH-1:0]),
438
   .Write     (CTRLMODER_Wr),
439
   .Clk       (Clk),
440
   .Reset     (Reset),
441 141 mohor
   .SyncReset (1'b0)
442 139 mohor
  );
443
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH] = 0;
444 15 mohor
 
445 139 mohor
// MIIMODER Register
446
eth_register #(`ETH_MIIMODER_WIDTH, `ETH_MIIMODER_DEF)    MIIMODER
447
  (
448
   .DataIn    (DataIn[`ETH_MIIMODER_WIDTH-1:0]),
449
   .DataOut   (MIIMODEROut[`ETH_MIIMODER_WIDTH-1:0]),
450
   .Write     (MIIMODER_Wr),
451
   .Clk       (Clk),
452
   .Reset     (Reset),
453 141 mohor
   .SyncReset (1'b0)
454 139 mohor
  );
455
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH] = 0;
456 68 mohor
 
457 139 mohor
// MIICOMMAND Register
458
eth_register #(1, 0)                                      MIICOMMAND0
459
  (
460
   .DataIn    (DataIn[0]),
461
   .DataOut   (MIICOMMANDOut[0]),
462
   .Write     (MIICOMMAND_Wr),
463
   .Clk       (Clk),
464
   .Reset     (Reset),
465 141 mohor
   .SyncReset (1'b0)
466 139 mohor
  );
467
 
468
eth_register #(1, 0)                                      MIICOMMAND1
469
  (
470
   .DataIn    (DataIn[1]),
471
   .DataOut   (MIICOMMANDOut[1]),
472
   .Write     (MIICOMMAND_Wr),
473
   .Clk       (Clk),
474
   .Reset     (Reset),
475
   .SyncReset (RStatStart)
476
  );
477
 
478
eth_register #(1, 0)                                      MIICOMMAND2
479
  (
480
   .DataIn    (DataIn[2]),
481
   .DataOut   (MIICOMMANDOut[2]),
482
   .Write     (MIICOMMAND_Wr),
483
   .Clk       (Clk),
484
   .Reset     (Reset),
485
   .SyncReset (WCtrlDataStart)
486
  );
487 15 mohor
assign MIICOMMANDOut[31:3] = 29'h0;
488
 
489 139 mohor
// MIIADDRESSRegister
490
eth_register #(5, `ETH_MIIADDRESS0_DEF)                   MIIADDRESS0
491
  (
492
   .DataIn    (DataIn[4:0]),
493
   .DataOut   (MIIADDRESSOut[4:0]),
494
   .Write     (MIIADDRESS_Wr),
495
   .Clk       (Clk),
496
   .Reset     (Reset),
497 141 mohor
   .SyncReset (1'b0)
498 139 mohor
  );
499 68 mohor
assign MIIADDRESSOut[7:5] = 0;
500 139 mohor
 
501
eth_register #(5, `ETH_MIIADDRESS1_DEF)                   MIIADDRESS1
502
  (
503
   .DataIn    (DataIn[12:8]),
504
   .DataOut   (MIIADDRESSOut[12:8]),
505
   .Write     (MIIADDRESS_Wr),
506
   .Clk       (Clk),
507
   .Reset     (Reset),
508 141 mohor
   .SyncReset (1'b0)
509 139 mohor
  );
510 68 mohor
assign MIIADDRESSOut[31:13] = 0;
511 15 mohor
 
512 139 mohor
// MIITX_DATA Register
513
eth_register #(`ETH_MIITX_DATA_WIDTH, `ETH_MIITX_DATA_DEF) MIITX_DATA
514
  (
515
   .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH-1:0]),
516 140 mohor
   .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH-1:0]),
517 139 mohor
   .Write     (MIITX_DATA_Wr),
518
   .Clk       (Clk),
519
   .Reset     (Reset),
520 141 mohor
   .SyncReset (1'b0)
521 139 mohor
  );
522
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH] = 0;
523 15 mohor
 
524 139 mohor
// MIIRX_DATA Register
525
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
526
  (
527
   .DataIn    (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
528
   .DataOut   (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
529
   .Write     (MIIRX_DATA_Wr),
530
   .Clk       (Clk),
531
   .Reset     (Reset),
532 141 mohor
   .SyncReset (1'b0)
533 139 mohor
  );
534
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
535 15 mohor
 
536 139 mohor
// MAC_ADDR0 Register
537
eth_register #(`ETH_MAC_ADDR0_WIDTH, `ETH_MAC_ADDR0_DEF)  MAC_ADDR0
538
  (
539
   .DataIn    (DataIn),
540
   .DataOut   (MAC_ADDR0Out),
541
   .Write     (MAC_ADDR0_Wr),
542
   .Clk       (Clk),
543
   .Reset     (Reset),
544 141 mohor
   .SyncReset (1'b0)
545 139 mohor
  );
546 68 mohor
 
547 139 mohor
// MAC_ADDR1 Register
548
eth_register #(`ETH_MAC_ADDR1_WIDTH, `ETH_MAC_ADDR1_DEF)  MAC_ADDR1
549
  (
550
   .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH-1:0]),
551
   .DataOut   (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH-1:0]),
552
   .Write     (MAC_ADDR1_Wr),
553
   .Clk       (Clk),
554
   .Reset     (Reset),
555 141 mohor
   .SyncReset (1'b0)
556 139 mohor
  );
557
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH] = 0;
558 68 mohor
 
559 139 mohor
// RXHASH0 Register
560
eth_register #(`ETH_HASH0_WIDTH, `ETH_HASH0_DEF)          RXHASH0
561
  (
562
   .DataIn    (DataIn),
563
   .DataOut   (HASH0Out),
564
   .Write     (HASH0_Wr),
565
   .Clk       (Clk),
566
   .Reset     (Reset),
567 141 mohor
   .SyncReset (1'b0)
568 139 mohor
  );
569 68 mohor
 
570 139 mohor
// RXHASH1 Register
571
eth_register #(`ETH_HASH1_WIDTH, `ETH_HASH1_DEF)          RXHASH1
572
  (
573
   .DataIn    (DataIn),
574
   .DataOut   (HASH1Out),
575
   .Write     (HASH1_Wr),
576
   .Clk       (Clk),
577
   .Reset     (Reset),
578 141 mohor
   .SyncReset (1'b0)
579 139 mohor
  );
580 68 mohor
 
581 15 mohor
 
582 147 mohor
// TXCTRL Register
583
eth_register #((`ETH_TX_CTRL_WIDTH-1), {(`ETH_TX_CTRL_WIDTH-1){1'b0}})      TXCTRL0
584
  (
585
   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH-2:0]),
586
   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH-2:0]),
587
   .Write     (TXCTRL_Wr),
588
   .Clk       (Clk),
589
   .Reset     (Reset),
590
   .SyncReset (1'b0)
591
  );
592
 
593
eth_register #(1, 1'b0)                                   TXCTRL1     // Request bit is synchronously reset
594
  (
595
   .DataIn    (DataIn[16]),
596
   .DataOut   (TXCTRLOut[16]),
597
   .Write     (TXCTRL_Wr),
598
   .Clk       (Clk),
599
   .Reset     (Reset),
600
   .SyncReset (RstTxPauseRq)
601
  );
602
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH] = 0;
603
 
604
 
605
// RXCTRL Register
606
eth_register #(`ETH_RX_CTRL_WIDTH, `ETH_RX_CTRL_DEF)      RXCTRL
607
  (
608
   .DataIn    (DataIn[`ETH_RX_CTRL_WIDTH-1:0]),
609
   .DataOut   (RXCTRLOut[`ETH_RX_CTRL_WIDTH-1:0]),
610
   .Write     (RXCTRL_Wr),
611
   .Clk       (Clk),
612
   .Reset     (Reset),
613
   .SyncReset (1'b0)
614
  );
615
assign RXCTRLOut[31:`ETH_RX_CTRL_WIDTH] = 0;
616
 
617
 
618 139 mohor
// Reading data from registers
619
always @ (Address       or Read           or MODEROut       or INT_SOURCEOut  or
620
          INT_MASKOut   or IPGTOut        or IPGR1Out       or IPGR2Out       or
621
          PACKETLENOut  or COLLCONFOut    or CTRLMODEROut   or MIIMODEROut    or
622
          MIICOMMANDOut or MIIADDRESSOut  or MIITX_DATAOut  or MIIRX_DATAOut  or
623
          MIISTATUSOut  or MAC_ADDR0Out   or MAC_ADDR1Out   or TX_BD_NUMOut   or
624 147 mohor
          HASH0Out      or HASH1Out       or TXCTRLOut      or RXCTRLOut
625 139 mohor
         )
626 15 mohor
begin
627
  if(Read)  // read
628
    begin
629
      case(Address)
630 20 mohor
        `ETH_MODER_ADR        :  DataOut<=MODEROut;
631
        `ETH_INT_SOURCE_ADR   :  DataOut<=INT_SOURCEOut;
632
        `ETH_INT_MASK_ADR     :  DataOut<=INT_MASKOut;
633
        `ETH_IPGT_ADR         :  DataOut<=IPGTOut;
634
        `ETH_IPGR1_ADR        :  DataOut<=IPGR1Out;
635
        `ETH_IPGR2_ADR        :  DataOut<=IPGR2Out;
636
        `ETH_PACKETLEN_ADR    :  DataOut<=PACKETLENOut;
637
        `ETH_COLLCONF_ADR     :  DataOut<=COLLCONFOut;
638
        `ETH_CTRLMODER_ADR    :  DataOut<=CTRLMODEROut;
639
        `ETH_MIIMODER_ADR     :  DataOut<=MIIMODEROut;
640
        `ETH_MIICOMMAND_ADR   :  DataOut<=MIICOMMANDOut;
641
        `ETH_MIIADDRESS_ADR   :  DataOut<=MIIADDRESSOut;
642
        `ETH_MIITX_DATA_ADR   :  DataOut<=MIITX_DATAOut;
643
        `ETH_MIIRX_DATA_ADR   :  DataOut<=MIIRX_DATAOut;
644
        `ETH_MIISTATUS_ADR    :  DataOut<=MIISTATUSOut;
645
        `ETH_MAC_ADDR0_ADR    :  DataOut<=MAC_ADDR0Out;
646
        `ETH_MAC_ADDR1_ADR    :  DataOut<=MAC_ADDR1Out;
647 34 mohor
        `ETH_TX_BD_NUM_ADR    :  DataOut<=TX_BD_NUMOut;
648 56 mohor
        `ETH_HASH0_ADR        :  DataOut<=HASH0Out;
649
        `ETH_HASH1_ADR        :  DataOut<=HASH1Out;
650 147 mohor
        `ETH_TX_CTRL_ADR      :  DataOut<=TXCTRLOut;
651
        `ETH_RX_CTRL_ADR      :  DataOut<=RXCTRLOut;
652
 
653 15 mohor
        default:             DataOut<=32'h0;
654
      endcase
655
    end
656
  else
657
    DataOut<=32'h0;
658
end
659
 
660
 
661
assign r_RecSmall         = MODEROut[16];
662
assign r_Pad              = MODEROut[15];
663
assign r_HugEn            = MODEROut[14];
664
assign r_CrcEn            = MODEROut[13];
665
assign r_DlyCrcEn         = MODEROut[12];
666 244 mohor
// assign r_Rst           = MODEROut[11];   This signal is not used any more
667 15 mohor
assign r_FullD            = MODEROut[10];
668
assign r_ExDfrEn          = MODEROut[9];
669
assign r_NoBckof          = MODEROut[8];
670
assign r_LoopBck          = MODEROut[7];
671
assign r_IFG              = MODEROut[6];
672
assign r_Pro              = MODEROut[5];
673
assign r_Iam              = MODEROut[4];
674
assign r_Bro              = MODEROut[3];
675
assign r_NoPre            = MODEROut[2];
676 143 mohor
assign r_TxEn             = MODEROut[1] & (TX_BD_NUMOut>0);     // Transmission is enabled when there is at least one TxBD.
677
assign r_RxEn             = MODEROut[0] & (TX_BD_NUMOut<'h80);  // Reception is enabled when there is  at least one RxBD.
678 15 mohor
 
679
assign r_IPGT[6:0]        = IPGTOut[6:0];
680
 
681
assign r_IPGR1[6:0]       = IPGR1Out[6:0];
682
 
683
assign r_IPGR2[6:0]       = IPGR2Out[6:0];
684
 
685
assign r_MinFL[15:0]      = PACKETLENOut[31:16];
686
assign r_MaxFL[15:0]      = PACKETLENOut[15:0];
687
 
688 56 mohor
assign r_MaxRet[3:0]      = COLLCONFOut[19:16];
689
assign r_CollValid[5:0]   = COLLCONFOut[5:0];
690 15 mohor
 
691
assign r_TxFlow           = CTRLMODEROut[2];
692
assign r_RxFlow           = CTRLMODEROut[1];
693
assign r_PassAll          = CTRLMODEROut[0];
694
 
695
assign r_MiiNoPre         = MIIMODEROut[8];
696
assign r_ClkDiv[7:0]      = MIIMODEROut[7:0];
697
 
698
assign r_WCtrlData        = MIICOMMANDOut[2];
699
assign r_RStat            = MIICOMMANDOut[1];
700
assign r_ScanStat         = MIICOMMANDOut[0];
701
 
702
assign r_RGAD[4:0]        = MIIADDRESSOut[12:8];
703
assign r_FIAD[4:0]        = MIIADDRESSOut[4:0];
704
 
705
assign r_CtrlData[15:0]   = MIITX_DATAOut[15:0];
706
 
707 139 mohor
assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
708
assign MIISTATUSOut[2]    = NValid_stat         ;
709
assign MIISTATUSOut[1]    = Busy_stat           ;
710
assign MIISTATUSOut[0]    = LinkFail            ;
711 15 mohor
 
712
assign r_MAC[31:0]        = MAC_ADDR0Out[31:0];
713
assign r_MAC[47:32]       = MAC_ADDR1Out[15:0];
714 52 billditt
assign r_HASH1[31:0]      = HASH1Out;
715
assign r_HASH0[31:0]      = HASH0Out;
716 15 mohor
 
717 147 mohor
assign r_TxBDNum[7:0]     = TX_BD_NUMOut[7:0];
718 15 mohor
 
719 147 mohor
assign r_TxPauseTV[15:0]  = TXCTRLOut[15:0];
720
assign r_TxPauseRq        = TXCTRLOut[16];
721 15 mohor
 
722 147 mohor
 
723
// Synchronizing TxC Interrupt
724
always @ (posedge TxClk or posedge Reset)
725
begin
726
  if(Reset)
727
    SetTxCIrq_txclk <=#Tp 1'b0;
728
  else
729
  if(TxCtrlEndFrm & StartTxDone & r_TxFlow)
730
    SetTxCIrq_txclk <=#Tp 1'b1;
731
  else
732
  if(ResetTxCIrq_sync2)
733
    SetTxCIrq_txclk <=#Tp 1'b0;
734
end
735
 
736
 
737
always @ (posedge Clk or posedge Reset)
738
begin
739
  if(Reset)
740
    SetTxCIrq_sync1 <=#Tp 1'b0;
741
  else
742
    SetTxCIrq_sync1 <=#Tp SetTxCIrq_txclk;
743
end
744
 
745
always @ (posedge Clk or posedge Reset)
746
begin
747
  if(Reset)
748
    SetTxCIrq_sync2 <=#Tp 1'b0;
749
  else
750
    SetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
751
end
752
 
753
always @ (posedge Clk or posedge Reset)
754
begin
755
  if(Reset)
756
    SetTxCIrq_sync3 <=#Tp 1'b0;
757
  else
758
    SetTxCIrq_sync3 <=#Tp SetTxCIrq_sync2;
759
end
760
 
761
always @ (posedge Clk or posedge Reset)
762
begin
763
  if(Reset)
764
    SetTxCIrq <=#Tp 1'b0;
765
  else
766
    SetTxCIrq <=#Tp SetTxCIrq_sync2 & ~SetTxCIrq_sync3;
767
end
768
 
769
always @ (posedge TxClk or posedge Reset)
770
begin
771
  if(Reset)
772
    ResetTxCIrq_sync1 <=#Tp 1'b0;
773
  else
774
    ResetTxCIrq_sync1 <=#Tp SetTxCIrq_sync2;
775
end
776
 
777
always @ (posedge TxClk or posedge Reset)
778
begin
779
  if(Reset)
780
    ResetTxCIrq_sync2 <=#Tp 1'b0;
781
  else
782
    ResetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
783
end
784
 
785
 
786
// Synchronizing RxC Interrupt
787
always @ (posedge RxClk or posedge Reset)
788
begin
789
  if(Reset)
790
    SetRxCIrq_rxclk <=#Tp 1'b0;
791
  else
792 261 mohor
  if(SetPauseTimer & r_RxFlow)
793 147 mohor
    SetRxCIrq_rxclk <=#Tp 1'b1;
794
  else
795 261 mohor
  if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
796 147 mohor
    SetRxCIrq_rxclk <=#Tp 1'b0;
797
end
798
 
799
 
800
always @ (posedge Clk or posedge Reset)
801
begin
802
  if(Reset)
803
    SetRxCIrq_sync1 <=#Tp 1'b0;
804
  else
805
    SetRxCIrq_sync1 <=#Tp SetRxCIrq_rxclk;
806
end
807
 
808
always @ (posedge Clk or posedge Reset)
809
begin
810
  if(Reset)
811
    SetRxCIrq_sync2 <=#Tp 1'b0;
812
  else
813
    SetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1;
814
end
815
 
816
always @ (posedge Clk or posedge Reset)
817
begin
818
  if(Reset)
819
    SetRxCIrq_sync3 <=#Tp 1'b0;
820
  else
821
    SetRxCIrq_sync3 <=#Tp SetRxCIrq_sync2;
822
end
823
 
824
always @ (posedge Clk or posedge Reset)
825
begin
826
  if(Reset)
827
    SetRxCIrq <=#Tp 1'b0;
828
  else
829
    SetRxCIrq <=#Tp SetRxCIrq_sync2 & ~SetRxCIrq_sync3;
830
end
831
 
832
always @ (posedge RxClk or posedge Reset)
833
begin
834
  if(Reset)
835
    ResetRxCIrq_sync1 <=#Tp 1'b0;
836
  else
837
    ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2;
838
end
839
 
840 261 mohor
always @ (posedge RxClk or posedge Reset)
841 147 mohor
begin
842
  if(Reset)
843
    ResetRxCIrq_sync2 <=#Tp 1'b0;
844
  else
845 261 mohor
    ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1;
846 147 mohor
end
847
 
848 261 mohor
always @ (posedge RxClk or posedge Reset)
849
begin
850
  if(Reset)
851
    ResetRxCIrq_sync3 <=#Tp 1'b0;
852
  else
853
    ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2;
854
end
855 147 mohor
 
856
 
857
 
858 21 mohor
// Interrupt generation
859
always @ (posedge Clk or posedge Reset)
860
begin
861
  if(Reset)
862
    irq_txb <= 1'b0;
863
  else
864 102 mohor
  if(TxB_IRQ)
865 21 mohor
    irq_txb <= #Tp 1'b1;
866
  else
867
  if(INT_SOURCE_Wr & DataIn[0])
868
    irq_txb <= #Tp 1'b0;
869
end
870
 
871
always @ (posedge Clk or posedge Reset)
872
begin
873
  if(Reset)
874
    irq_txe <= 1'b0;
875
  else
876 102 mohor
  if(TxE_IRQ)
877 21 mohor
    irq_txe <= #Tp 1'b1;
878
  else
879
  if(INT_SOURCE_Wr & DataIn[1])
880
    irq_txe <= #Tp 1'b0;
881
end
882
 
883
always @ (posedge Clk or posedge Reset)
884
begin
885
  if(Reset)
886
    irq_rxb <= 1'b0;
887
  else
888 102 mohor
  if(RxB_IRQ)
889 21 mohor
    irq_rxb <= #Tp 1'b1;
890
  else
891
  if(INT_SOURCE_Wr & DataIn[2])
892
    irq_rxb <= #Tp 1'b0;
893
end
894
 
895
always @ (posedge Clk or posedge Reset)
896
begin
897
  if(Reset)
898 74 mohor
    irq_rxe <= 1'b0;
899 21 mohor
  else
900 102 mohor
  if(RxE_IRQ)
901 74 mohor
    irq_rxe <= #Tp 1'b1;
902 21 mohor
  else
903
  if(INT_SOURCE_Wr & DataIn[3])
904 74 mohor
    irq_rxe <= #Tp 1'b0;
905 21 mohor
end
906
 
907
always @ (posedge Clk or posedge Reset)
908
begin
909
  if(Reset)
910
    irq_busy <= 1'b0;
911
  else
912 102 mohor
  if(Busy_IRQ)
913 21 mohor
    irq_busy <= #Tp 1'b1;
914
  else
915
  if(INT_SOURCE_Wr & DataIn[4])
916
    irq_busy <= #Tp 1'b0;
917
end
918
 
919 74 mohor
always @ (posedge Clk or posedge Reset)
920
begin
921
  if(Reset)
922
    irq_txc <= 1'b0;
923
  else
924 147 mohor
  if(SetTxCIrq)
925 74 mohor
    irq_txc <= #Tp 1'b1;
926
  else
927
  if(INT_SOURCE_Wr & DataIn[5])
928
    irq_txc <= #Tp 1'b0;
929
end
930
 
931
always @ (posedge Clk or posedge Reset)
932
begin
933
  if(Reset)
934
    irq_rxc <= 1'b0;
935
  else
936 147 mohor
  if(SetRxCIrq)
937 74 mohor
    irq_rxc <= #Tp 1'b1;
938
  else
939
  if(INT_SOURCE_Wr & DataIn[6])
940
    irq_rxc <= #Tp 1'b0;
941
end
942
 
943 21 mohor
// Generating interrupt signal
944 102 mohor
assign int_o = irq_txb  & INT_MASKOut[0] |
945
               irq_txe  & INT_MASKOut[1] |
946
               irq_rxb  & INT_MASKOut[2] |
947
               irq_rxe  & INT_MASKOut[3] |
948
               irq_busy & INT_MASKOut[4] |
949
               irq_txc  & INT_MASKOut[5] |
950
               irq_rxc  & INT_MASKOut[6] ;
951 21 mohor
 
952
// For reading interrupt status
953 139 mohor
assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
954 21 mohor
 
955
 
956
 
957 15 mohor
endmodule

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