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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Blame information for rev 304

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1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_registers.v                                             ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 147 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 15 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 304 tadejm
// Revision 1.25  2003/04/18 16:26:25  mohor
45
// RxBDAddress was updated also when value to r_TxBDNum was written with
46
// greater value than allowed.
47
//
48 283 mohor
// Revision 1.24  2002/11/22 01:57:06  mohor
49
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
50
// synchronized.
51
//
52 261 mohor
// Revision 1.23  2002/11/19 18:13:49  mohor
53
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
54
//
55 253 mohor
// Revision 1.22  2002/11/14 18:37:20  mohor
56
// r_Rst signal does not reset any module any more and is removed from the design.
57
//
58 244 mohor
// Revision 1.21  2002/09/10 10:35:23  mohor
59
// Ethernet debug registers removed.
60
//
61 164 mohor
// Revision 1.20  2002/09/04 18:40:25  mohor
62
// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
63
// the control frames connected.
64
//
65 147 mohor
// Revision 1.19  2002/08/19 16:01:40  mohor
66
// Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
67
// r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
68
//
69 143 mohor
// Revision 1.18  2002/08/16 22:28:23  mohor
70
// Syntax error fixed.
71
//
72 141 mohor
// Revision 1.17  2002/08/16 22:23:03  mohor
73
// Syntax error fixed.
74
//
75 140 mohor
// Revision 1.16  2002/08/16 22:14:22  mohor
76
// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
77
// changed from bit position 10 to 9.
78
//
79 139 mohor
// Revision 1.15  2002/08/14 18:26:37  mohor
80
// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
81
//
82 132 mohor
// Revision 1.14  2002/04/22 14:03:44  mohor
83
// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
84
// or not.
85
//
86 102 mohor
// Revision 1.13  2002/02/26 16:18:09  mohor
87
// Reset values are passed to registers through parameters
88
//
89 74 mohor
// Revision 1.12  2002/02/17 13:23:42  mohor
90
// Define missmatch fixed.
91
//
92 69 mohor
// Revision 1.11  2002/02/16 14:03:44  mohor
93
// Registered trimmed. Unused registers removed.
94
//
95 68 mohor
// Revision 1.10  2002/02/15 11:08:25  mohor
96
// File format fixed a bit.
97
//
98 56 mohor
// Revision 1.9  2002/02/14 20:19:41  billditt
99
// Modified for Address Checking,
100
// addition of eth_addrcheck.v
101
//
102
// Revision 1.8  2002/02/12 17:01:19  mohor
103
// HASH0 and HASH1 registers added. 
104
 
105 46 mohor
// Revision 1.7  2002/01/23 10:28:16  mohor
106
// Link in the header changed.
107
//
108 37 mohor
// Revision 1.6  2001/12/05 15:00:16  mohor
109
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
110
// instead of the number of RX descriptors).
111
//
112 34 mohor
// Revision 1.5  2001/12/05 10:22:19  mohor
113
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
114
//
115 32 mohor
// Revision 1.4  2001/10/19 08:43:51  mohor
116
// eth_timescale.v changed to timescale.v This is done because of the
117
// simulation of the few cores in a one joined project.
118
//
119 22 mohor
// Revision 1.3  2001/10/18 12:07:11  mohor
120
// Status signals changed, Adress decoding changed, interrupt controller
121
// added.
122
//
123 21 mohor
// Revision 1.2  2001/09/24 15:02:56  mohor
124
// Defines changed (All precede with ETH_). Small changes because some
125
// tools generate warnings when two operands are together. Synchronization
126
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
127
// demands).
128
//
129 20 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
130
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
131
// Include files fixed to contain no path.
132
// File names and module names changed ta have a eth_ prologue in the name.
133
// File eth_timescale.v is used to define timescale
134
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
135
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
136
// and Mdo_OE. The bidirectional signal must be created on the top level. This
137
// is done due to the ASIC tools.
138
//
139 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
140
// Unconnected signals are now connected.
141
//
142
// Revision 1.1  2001/07/30 21:23:42  mohor
143
// Directory structure changed. Files checked and joind together.
144
//
145
//
146
//
147
//
148
//
149
//
150
 
151
`include "eth_defines.v"
152 22 mohor
`include "timescale.v"
153 15 mohor
 
154
 
155 68 mohor
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
156 15 mohor
                      r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
157 244 mohor
                      r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
158 21 mohor
                      r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
159 147 mohor
                      TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
160 21 mohor
                      r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
161 15 mohor
                      r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
162 253 mohor
                      r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
163 15 mohor
                      r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
164
                      LinkFail, r_MAC, WCtrlDataStart, RStatStart,
165 46 mohor
                      UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
166 147 mohor
                      r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
167 261 mohor
                      StartTxDone, TxClk, RxClk, SetPauseTimer
168 15 mohor
                    );
169
 
170
parameter Tp = 1;
171
 
172
input [31:0] DataIn;
173 46 mohor
input [7:0] Address;
174 15 mohor
 
175
input Rw;
176 304 tadejm
input [3:0] Cs;
177 15 mohor
input Clk;
178
input Reset;
179
 
180
input WCtrlDataStart;
181
input RStatStart;
182
 
183
input UpdateMIIRX_DATAReg;
184
input [15:0] Prsd;
185
 
186
output [31:0] DataOut;
187
reg    [31:0] DataOut;
188
 
189
output r_RecSmall;
190
output r_Pad;
191
output r_HugEn;
192
output r_CrcEn;
193
output r_DlyCrcEn;
194
output r_FullD;
195
output r_ExDfrEn;
196
output r_NoBckof;
197
output r_LoopBck;
198
output r_IFG;
199
output r_Pro;
200
output r_Iam;
201
output r_Bro;
202
output r_NoPre;
203
output r_TxEn;
204
output r_RxEn;
205 52 billditt
output [31:0] r_HASH0;
206
output [31:0] r_HASH1;
207 15 mohor
 
208 21 mohor
input TxB_IRQ;
209
input TxE_IRQ;
210
input RxB_IRQ;
211 74 mohor
input RxE_IRQ;
212 21 mohor
input Busy_IRQ;
213 15 mohor
 
214
output [6:0] r_IPGT;
215
 
216
output [6:0] r_IPGR1;
217
 
218
output [6:0] r_IPGR2;
219
 
220
output [15:0] r_MinFL;
221
output [15:0] r_MaxFL;
222
 
223
output [3:0] r_MaxRet;
224
output [5:0] r_CollValid;
225
 
226
output r_TxFlow;
227
output r_RxFlow;
228
output r_PassAll;
229
 
230
output r_MiiNoPre;
231
output [7:0] r_ClkDiv;
232
 
233
output r_WCtrlData;
234
output r_RStat;
235
output r_ScanStat;
236
 
237
output [4:0] r_RGAD;
238
output [4:0] r_FIAD;
239
 
240 21 mohor
output [15:0]r_CtrlData;
241 15 mohor
 
242
 
243
input NValid_stat;
244
input Busy_stat;
245
input LinkFail;
246
 
247 21 mohor
output [47:0]r_MAC;
248 34 mohor
output [7:0] r_TxBDNum;
249
output       TX_BD_NUM_Wr;
250 21 mohor
output       int_o;
251 147 mohor
output [15:0]r_TxPauseTV;
252
output       r_TxPauseRq;
253
input        RstTxPauseRq;
254
input        TxCtrlEndFrm;
255
input        StartTxDone;
256
input        TxClk;
257
input        RxClk;
258 261 mohor
input        SetPauseTimer;
259 15 mohor
 
260 21 mohor
reg          irq_txb;
261
reg          irq_txe;
262
reg          irq_rxb;
263 74 mohor
reg          irq_rxe;
264 21 mohor
reg          irq_busy;
265 74 mohor
reg          irq_txc;
266
reg          irq_rxc;
267 15 mohor
 
268 147 mohor
reg SetTxCIrq_txclk;
269
reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3;
270
reg SetTxCIrq;
271
reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
272
 
273
reg SetRxCIrq_rxclk;
274
reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
275
reg SetRxCIrq;
276 261 mohor
reg ResetRxCIrq_sync1;
277
reg ResetRxCIrq_sync2;
278
reg ResetRxCIrq_sync3;
279 147 mohor
 
280 304 tadejm
wire [3:0] Write =   Cs  & {4{Rw}};
281
wire       Read  = (|Cs) &   ~Rw;
282 15 mohor
 
283 304 tadejm
wire MODER_Wr       = (Address == `ETH_MODER_ADR       );
284
wire INT_SOURCE_Wr  = (Address == `ETH_INT_SOURCE_ADR  );
285
wire INT_MASK_Wr    = (Address == `ETH_INT_MASK_ADR    );
286
wire IPGT_Wr        = (Address == `ETH_IPGT_ADR        );
287
wire IPGR1_Wr       = (Address == `ETH_IPGR1_ADR       );
288
wire IPGR2_Wr       = (Address == `ETH_IPGR2_ADR       );
289
wire PACKETLEN_Wr   = (Address == `ETH_PACKETLEN_ADR   );
290
wire COLLCONF_Wr    = (Address == `ETH_COLLCONF_ADR    );
291 21 mohor
 
292 304 tadejm
wire CTRLMODER_Wr   = (Address == `ETH_CTRLMODER_ADR   );
293
wire MIIMODER_Wr    = (Address == `ETH_MIIMODER_ADR    );
294
wire MIICOMMAND_Wr  = (Address == `ETH_MIICOMMAND_ADR  );
295
wire MIIADDRESS_Wr  = (Address == `ETH_MIIADDRESS_ADR  );
296
wire MIITX_DATA_Wr  = (Address == `ETH_MIITX_DATA_ADR  );
297 21 mohor
wire MIIRX_DATA_Wr  = UpdateMIIRX_DATAReg;
298 304 tadejm
wire MAC_ADDR0_Wr   = (Address == `ETH_MAC_ADDR0_ADR   );
299
wire MAC_ADDR1_Wr   = (Address == `ETH_MAC_ADDR1_ADR   );
300
wire HASH0_Wr       = (Address == `ETH_HASH0_ADR       );
301
wire HASH1_Wr       = (Address == `ETH_HASH1_ADR       );
302
wire TXCTRL_Wr      = (Address == `ETH_TX_CTRL_ADR     );
303
wire RXCTRL_Wr      = (Address == `ETH_RX_CTRL_ADR     );
304
assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR   ) & (DataIn<='h80);
305 15 mohor
 
306
 
307
 
308
wire [31:0] MODEROut;
309
wire [31:0] INT_SOURCEOut;
310
wire [31:0] INT_MASKOut;
311
wire [31:0] IPGTOut;
312
wire [31:0] IPGR1Out;
313
wire [31:0] IPGR2Out;
314
wire [31:0] PACKETLENOut;
315
wire [31:0] COLLCONFOut;
316
wire [31:0] CTRLMODEROut;
317
wire [31:0] MIIMODEROut;
318
wire [31:0] MIICOMMANDOut;
319
wire [31:0] MIIADDRESSOut;
320
wire [31:0] MIITX_DATAOut;
321
wire [31:0] MIIRX_DATAOut;
322
wire [31:0] MIISTATUSOut;
323
wire [31:0] MAC_ADDR0Out;
324
wire [31:0] MAC_ADDR1Out;
325 34 mohor
wire [31:0] TX_BD_NUMOut;
326 52 billditt
wire [31:0] HASH0Out;
327
wire [31:0] HASH1Out;
328 147 mohor
wire [31:0] TXCTRLOut;
329
wire [31:0] RXCTRLOut;
330 15 mohor
 
331 139 mohor
// MODER Register
332 304 tadejm
eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0)        MODER_0
333 139 mohor
  (
334 304 tadejm
   .DataIn    (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
335
   .DataOut   (MODEROut[`ETH_MODER_WIDTH_0 - 1:0]),
336
   .Write     (MODER_Wr & Write[0]),
337 139 mohor
   .Clk       (Clk),
338
   .Reset     (Reset),
339 141 mohor
   .SyncReset (1'b0)
340 139 mohor
  );
341 304 tadejm
eth_register #(`ETH_MODER_WIDTH_1, `ETH_MODER_DEF_1)        MODER_1
342
  (
343
   .DataIn    (DataIn[`ETH_MODER_WIDTH_1 + 7:8]),
344
   .DataOut   (MODEROut[`ETH_MODER_WIDTH_1 + 7:8]),
345
   .Write     (MODER_Wr & Write[1]),
346
   .Clk       (Clk),
347
   .Reset     (Reset),
348
   .SyncReset (1'b0)
349
  );
350
eth_register #(`ETH_MODER_WIDTH_2, `ETH_MODER_DEF_2)        MODER_2
351
  (
352
   .DataIn    (DataIn[`ETH_MODER_WIDTH_2 + 15:16]),
353
   .DataOut   (MODEROut[`ETH_MODER_WIDTH_2 + 15:16]),
354
   .Write     (MODER_Wr & Write[2]),
355
   .Clk       (Clk),
356
   .Reset     (Reset),
357
   .SyncReset (1'b0)
358
  );
359
assign MODEROut[31:`ETH_MODER_WIDTH_2 + 16] = 0;
360 15 mohor
 
361 139 mohor
// INT_MASK Register
362 304 tadejm
eth_register #(`ETH_INT_MASK_WIDTH_0, `ETH_INT_MASK_DEF_0)  INT_MASK_0
363 139 mohor
  (
364 304 tadejm
   .DataIn    (DataIn[`ETH_INT_MASK_WIDTH_0 - 1:0]),
365
   .DataOut   (INT_MASKOut[`ETH_INT_MASK_WIDTH_0 - 1:0]),
366
   .Write     (INT_MASK_Wr & Write[0]),
367 139 mohor
   .Clk       (Clk),
368
   .Reset     (Reset),
369 141 mohor
   .SyncReset (1'b0)
370 139 mohor
  );
371 304 tadejm
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH_0] = 0;
372 52 billditt
 
373 139 mohor
// IPGT Register
374 304 tadejm
eth_register #(`ETH_IPGT_WIDTH_0, `ETH_IPGT_DEF_0)          IPGT_0
375 139 mohor
  (
376 304 tadejm
   .DataIn    (DataIn[`ETH_IPGT_WIDTH_0 - 1:0]),
377
   .DataOut   (IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0]),
378
   .Write     (IPGT_Wr & Write[0]),
379 139 mohor
   .Clk       (Clk),
380
   .Reset     (Reset),
381 141 mohor
   .SyncReset (1'b0)
382 139 mohor
  );
383 304 tadejm
assign IPGTOut[31:`ETH_IPGT_WIDTH_0] = 0;
384 52 billditt
 
385 139 mohor
// IPGR1 Register
386 304 tadejm
eth_register #(`ETH_IPGR1_WIDTH_0, `ETH_IPGR1_DEF_0)        IPGR1_0
387 139 mohor
  (
388 304 tadejm
   .DataIn    (DataIn[`ETH_IPGR1_WIDTH_0 - 1:0]),
389
   .DataOut   (IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0]),
390
   .Write     (IPGR1_Wr & Write[0]),
391 139 mohor
   .Clk       (Clk),
392
   .Reset     (Reset),
393 141 mohor
   .SyncReset (1'b0)
394 139 mohor
  );
395 304 tadejm
assign IPGR1Out[31:`ETH_IPGR1_WIDTH_0] = 0;
396 15 mohor
 
397 139 mohor
// IPGR2 Register
398 304 tadejm
eth_register #(`ETH_IPGR2_WIDTH_0, `ETH_IPGR2_DEF_0)        IPGR2_0
399 139 mohor
  (
400 304 tadejm
   .DataIn    (DataIn[`ETH_IPGR2_WIDTH_0 - 1:0]),
401
   .DataOut   (IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0]),
402
   .Write     (IPGR2_Wr & Write[0]),
403 139 mohor
   .Clk       (Clk),
404
   .Reset     (Reset),
405 141 mohor
   .SyncReset (1'b0)
406 139 mohor
  );
407 304 tadejm
assign IPGR2Out[31:`ETH_IPGR2_WIDTH_0] = 0;
408 15 mohor
 
409 139 mohor
// PACKETLEN Register
410 304 tadejm
eth_register #(`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0
411 139 mohor
  (
412 304 tadejm
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
413
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
414
   .Write     (PACKETLEN_Wr & Write[0]),
415 139 mohor
   .Clk       (Clk),
416
   .Reset     (Reset),
417 141 mohor
   .SyncReset (1'b0)
418 139 mohor
  );
419 304 tadejm
eth_register #(`ETH_PACKETLEN_WIDTH_1, `ETH_PACKETLEN_DEF_1) PACKETLEN_1
420
  (
421
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
422
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
423
   .Write     (PACKETLEN_Wr & Write[1]),
424
   .Clk       (Clk),
425
   .Reset     (Reset),
426
   .SyncReset (1'b0)
427
  );
428
eth_register #(`ETH_PACKETLEN_WIDTH_2, `ETH_PACKETLEN_DEF_2) PACKETLEN_2
429
  (
430
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
431
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
432
   .Write     (PACKETLEN_Wr & Write[2]),
433
   .Clk       (Clk),
434
   .Reset     (Reset),
435
   .SyncReset (1'b0)
436
  );
437
eth_register #(`ETH_PACKETLEN_WIDTH_3, `ETH_PACKETLEN_DEF_3) PACKETLEN_3
438
  (
439
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
440
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
441
   .Write     (PACKETLEN_Wr & Write[3]),
442
   .Clk       (Clk),
443
   .Reset     (Reset),
444
   .SyncReset (1'b0)
445
  );
446 15 mohor
 
447 139 mohor
// COLLCONF Register
448 304 tadejm
eth_register #(`ETH_COLLCONF_WIDTH_0, `ETH_COLLCONF_DEF_0)   COLLCONF_0
449 139 mohor
  (
450 304 tadejm
   .DataIn    (DataIn[`ETH_COLLCONF_WIDTH_0 - 1:0]),
451
   .DataOut   (COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0]),
452
   .Write     (COLLCONF_Wr & Write[0]),
453 139 mohor
   .Clk       (Clk),
454
   .Reset     (Reset),
455 141 mohor
   .SyncReset (1'b0)
456 139 mohor
  );
457 304 tadejm
eth_register #(`ETH_COLLCONF_WIDTH_2, `ETH_COLLCONF_DEF_2)   COLLCONF_2
458 139 mohor
  (
459 304 tadejm
   .DataIn    (DataIn[`ETH_COLLCONF_WIDTH_2 + 15:16]),
460
   .DataOut   (COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16]),
461
   .Write     (COLLCONF_Wr & Write[2]),
462 139 mohor
   .Clk       (Clk),
463
   .Reset     (Reset),
464 141 mohor
   .SyncReset (1'b0)
465 139 mohor
  );
466 304 tadejm
assign COLLCONFOut[15:`ETH_COLLCONF_WIDTH_0] = 0;
467
assign COLLCONFOut[31:`ETH_COLLCONF_WIDTH_2 + 16] = 0;
468 15 mohor
 
469 139 mohor
// TX_BD_NUM Register
470 304 tadejm
eth_register #(`ETH_TX_BD_NUM_WIDTH_0, `ETH_TX_BD_NUM_DEF_0) TX_BD_NUM_0
471 139 mohor
  (
472 304 tadejm
   .DataIn    (DataIn[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
473
   .DataOut   (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
474
   .Write     (TX_BD_NUM_Wr & Write[0]),
475 139 mohor
   .Clk       (Clk),
476
   .Reset     (Reset),
477 141 mohor
   .SyncReset (1'b0)
478 139 mohor
  );
479 304 tadejm
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH_0] = 0;
480 15 mohor
 
481 139 mohor
// CTRLMODER Register
482 304 tadejm
eth_register #(`ETH_CTRLMODER_WIDTH_0, `ETH_CTRLMODER_DEF_0)  CTRLMODER_0
483 139 mohor
  (
484 304 tadejm
   .DataIn    (DataIn[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
485
   .DataOut   (CTRLMODEROut[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
486
   .Write     (CTRLMODER_Wr & Write[0]),
487 139 mohor
   .Clk       (Clk),
488
   .Reset     (Reset),
489 141 mohor
   .SyncReset (1'b0)
490 139 mohor
  );
491 304 tadejm
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH_0] = 0;
492 15 mohor
 
493 139 mohor
// MIIMODER Register
494 304 tadejm
eth_register #(`ETH_MIIMODER_WIDTH_0, `ETH_MIIMODER_DEF_0)    MIIMODER_0
495 139 mohor
  (
496 304 tadejm
   .DataIn    (DataIn[`ETH_MIIMODER_WIDTH_0 - 1:0]),
497
   .DataOut   (MIIMODEROut[`ETH_MIIMODER_WIDTH_0 - 1:0]),
498
   .Write     (MIIMODER_Wr & Write[0]),
499 139 mohor
   .Clk       (Clk),
500
   .Reset     (Reset),
501 141 mohor
   .SyncReset (1'b0)
502 139 mohor
  );
503 304 tadejm
eth_register #(`ETH_MIIMODER_WIDTH_1, `ETH_MIIMODER_DEF_1)    MIIMODER_1
504
  (
505
   .DataIn    (DataIn[`ETH_MIIMODER_WIDTH_1 + 7:8]),
506
   .DataOut   (MIIMODEROut[`ETH_MIIMODER_WIDTH_1 + 7:8]),
507
   .Write     (MIIMODER_Wr & Write[1]),
508
   .Clk       (Clk),
509
   .Reset     (Reset),
510
   .SyncReset (1'b0)
511
  );
512
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH_1 + 8] = 0;
513 68 mohor
 
514 139 mohor
// MIICOMMAND Register
515
eth_register #(1, 0)                                      MIICOMMAND0
516
  (
517
   .DataIn    (DataIn[0]),
518
   .DataOut   (MIICOMMANDOut[0]),
519 304 tadejm
   .Write     (MIICOMMAND_Wr & Write[0]),
520 139 mohor
   .Clk       (Clk),
521
   .Reset     (Reset),
522 141 mohor
   .SyncReset (1'b0)
523 139 mohor
  );
524
eth_register #(1, 0)                                      MIICOMMAND1
525
  (
526
   .DataIn    (DataIn[1]),
527
   .DataOut   (MIICOMMANDOut[1]),
528 304 tadejm
   .Write     (MIICOMMAND_Wr & Write[0]),
529 139 mohor
   .Clk       (Clk),
530
   .Reset     (Reset),
531
   .SyncReset (RStatStart)
532
  );
533
eth_register #(1, 0)                                      MIICOMMAND2
534
  (
535
   .DataIn    (DataIn[2]),
536
   .DataOut   (MIICOMMANDOut[2]),
537 304 tadejm
   .Write     (MIICOMMAND_Wr & Write[0]),
538 139 mohor
   .Clk       (Clk),
539
   .Reset     (Reset),
540
   .SyncReset (WCtrlDataStart)
541
  );
542 304 tadejm
assign MIICOMMANDOut[31:`ETH_MIICOMMAND_WIDTH_0] = 29'h0;
543 15 mohor
 
544 139 mohor
// MIIADDRESSRegister
545 304 tadejm
eth_register #(`ETH_MIIADDRESS_WIDTH_0, `ETH_MIIADDRESS_DEF_0) MIIADDRESS_0
546 139 mohor
  (
547 304 tadejm
   .DataIn    (DataIn[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
548
   .DataOut   (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
549
   .Write     (MIIADDRESS_Wr & Write[0]),
550 139 mohor
   .Clk       (Clk),
551
   .Reset     (Reset),
552 141 mohor
   .SyncReset (1'b0)
553 139 mohor
  );
554 304 tadejm
eth_register #(`ETH_MIIADDRESS_WIDTH_1, `ETH_MIIADDRESS_DEF_1) MIIADDRESS_1
555 139 mohor
  (
556 304 tadejm
   .DataIn    (DataIn[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
557
   .DataOut   (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
558
   .Write     (MIIADDRESS_Wr & Write[1]),
559 139 mohor
   .Clk       (Clk),
560
   .Reset     (Reset),
561 141 mohor
   .SyncReset (1'b0)
562 139 mohor
  );
563 304 tadejm
assign MIIADDRESSOut[7:`ETH_MIIADDRESS_WIDTH_0] = 0;
564
assign MIIADDRESSOut[31:`ETH_MIIADDRESS_WIDTH_1 + 8] = 0;
565 15 mohor
 
566 139 mohor
// MIITX_DATA Register
567 304 tadejm
eth_register #(`ETH_MIITX_DATA_WIDTH_0, `ETH_MIITX_DATA_DEF_0) MIITX_DATA_0
568 139 mohor
  (
569 304 tadejm
   .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
570
   .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
571
   .Write     (MIITX_DATA_Wr & Write[0]),
572 139 mohor
   .Clk       (Clk),
573
   .Reset     (Reset),
574 141 mohor
   .SyncReset (1'b0)
575 139 mohor
  );
576 304 tadejm
eth_register #(`ETH_MIITX_DATA_WIDTH_1, `ETH_MIITX_DATA_DEF_1) MIITX_DATA_1
577
  (
578
   .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
579
   .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
580
   .Write     (MIITX_DATA_Wr & Write[1]),
581
   .Clk       (Clk),
582
   .Reset     (Reset),
583
   .SyncReset (1'b0)
584
  );
585
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH_1 + 8] = 0;
586 15 mohor
 
587 139 mohor
// MIIRX_DATA Register
588
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
589
  (
590
   .DataIn    (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
591
   .DataOut   (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
592 304 tadejm
   .Write     (MIIRX_DATA_Wr), // not written from WB
593 139 mohor
   .Clk       (Clk),
594
   .Reset     (Reset),
595 141 mohor
   .SyncReset (1'b0)
596 139 mohor
  );
597
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
598 15 mohor
 
599 139 mohor
// MAC_ADDR0 Register
600 304 tadejm
eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0)  MAC_ADDR0_0
601 139 mohor
  (
602 304 tadejm
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
603
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
604
   .Write     (MAC_ADDR0_Wr & Write[0]),
605 139 mohor
   .Clk       (Clk),
606
   .Reset     (Reset),
607 141 mohor
   .SyncReset (1'b0)
608 139 mohor
  );
609 304 tadejm
eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1)  MAC_ADDR0_1
610
  (
611
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
612
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
613
   .Write     (MAC_ADDR0_Wr & Write[1]),
614
   .Clk       (Clk),
615
   .Reset     (Reset),
616
   .SyncReset (1'b0)
617
  );
618
eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2)  MAC_ADDR0_2
619
  (
620
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
621
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
622
   .Write     (MAC_ADDR0_Wr & Write[2]),
623
   .Clk       (Clk),
624
   .Reset     (Reset),
625
   .SyncReset (1'b0)
626
  );
627
eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3)  MAC_ADDR0_3
628
  (
629
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
630
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
631
   .Write     (MAC_ADDR0_Wr & Write[3]),
632
   .Clk       (Clk),
633
   .Reset     (Reset),
634
   .SyncReset (1'b0)
635
  );
636 68 mohor
 
637 139 mohor
// MAC_ADDR1 Register
638 304 tadejm
eth_register #(`ETH_MAC_ADDR1_WIDTH_0, `ETH_MAC_ADDR1_DEF_0)  MAC_ADDR1_0
639 139 mohor
  (
640 304 tadejm
   .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
641
   .DataOut   (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
642
   .Write     (MAC_ADDR1_Wr & Write[0]),
643 139 mohor
   .Clk       (Clk),
644
   .Reset     (Reset),
645 141 mohor
   .SyncReset (1'b0)
646 139 mohor
  );
647 304 tadejm
eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1)  MAC_ADDR1_1
648
  (
649
   .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
650
   .DataOut   (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
651
   .Write     (MAC_ADDR1_Wr & Write[1]),
652
   .Clk       (Clk),
653
   .Reset     (Reset),
654
   .SyncReset (1'b0)
655
  );
656
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0;
657 68 mohor
 
658 139 mohor
// RXHASH0 Register
659 304 tadejm
eth_register #(`ETH_HASH0_WIDTH_0, `ETH_HASH0_DEF_0)          RXHASH0_0
660 139 mohor
  (
661 304 tadejm
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_0 - 1:0]),
662
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_0 - 1:0]),
663
   .Write     (HASH0_Wr & Write[0]),
664 139 mohor
   .Clk       (Clk),
665
   .Reset     (Reset),
666 141 mohor
   .SyncReset (1'b0)
667 139 mohor
  );
668 304 tadejm
eth_register #(`ETH_HASH0_WIDTH_1, `ETH_HASH0_DEF_1)          RXHASH0_1
669
  (
670
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_1 + 7:8]),
671
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_1 + 7:8]),
672
   .Write     (HASH0_Wr & Write[1]),
673
   .Clk       (Clk),
674
   .Reset     (Reset),
675
   .SyncReset (1'b0)
676
  );
677
eth_register #(`ETH_HASH0_WIDTH_2, `ETH_HASH0_DEF_2)          RXHASH0_2
678
  (
679
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_2 + 15:16]),
680
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_2 + 15:16]),
681
   .Write     (HASH0_Wr & Write[2]),
682
   .Clk       (Clk),
683
   .Reset     (Reset),
684
   .SyncReset (1'b0)
685
  );
686
eth_register #(`ETH_HASH0_WIDTH_3, `ETH_HASH0_DEF_3)          RXHASH0_3
687
  (
688
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_3 + 23:24]),
689
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_3 + 23:24]),
690
   .Write     (HASH0_Wr & Write[3]),
691
   .Clk       (Clk),
692
   .Reset     (Reset),
693
   .SyncReset (1'b0)
694
  );
695 68 mohor
 
696 139 mohor
// RXHASH1 Register
697 304 tadejm
eth_register #(`ETH_HASH1_WIDTH_0, `ETH_HASH1_DEF_0)          RXHASH1_0
698 139 mohor
  (
699 304 tadejm
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_0 - 1:0]),
700
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_0 - 1:0]),
701
   .Write     (HASH1_Wr & Write[0]),
702 139 mohor
   .Clk       (Clk),
703
   .Reset     (Reset),
704 141 mohor
   .SyncReset (1'b0)
705 139 mohor
  );
706 304 tadejm
eth_register #(`ETH_HASH1_WIDTH_1, `ETH_HASH1_DEF_1)          RXHASH1_1
707
  (
708
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_1 + 7:8]),
709
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_1 + 7:8]),
710
   .Write     (HASH1_Wr & Write[1]),
711
   .Clk       (Clk),
712
   .Reset     (Reset),
713
   .SyncReset (1'b0)
714
  );
715
eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2)          RXHASH1_2
716
  (
717
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_2 + 15:16]),
718
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]),
719
   .Write     (HASH1_Wr & Write[2]),
720
   .Clk       (Clk),
721
   .Reset     (Reset),
722
   .SyncReset (1'b0)
723
  );
724
eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3)          RXHASH1_3
725
  (
726
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_3 + 23:24]),
727
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]),
728
   .Write     (HASH1_Wr & Write[3]),
729
   .Clk       (Clk),
730
   .Reset     (Reset),
731
   .SyncReset (1'b0)
732
  );
733 68 mohor
 
734 147 mohor
// TXCTRL Register
735 304 tadejm
eth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0)  TXCTRL_0
736 147 mohor
  (
737 304 tadejm
   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
738
   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
739
   .Write     (TXCTRL_Wr & Write[0]),
740 147 mohor
   .Clk       (Clk),
741
   .Reset     (Reset),
742
   .SyncReset (1'b0)
743
  );
744 304 tadejm
eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1)  TXCTRL_1
745 147 mohor
  (
746 304 tadejm
   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
747
   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
748
   .Write     (TXCTRL_Wr & Write[1]),
749 147 mohor
   .Clk       (Clk),
750
   .Reset     (Reset),
751 304 tadejm
   .SyncReset (1'b0)
752
  );
753
eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2)  TXCTRL_2 // Request bit is synchronously reset
754
  (
755
   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
756
   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
757
   .Write     (TXCTRL_Wr & Write[2]),
758
   .Clk       (Clk),
759
   .Reset     (Reset),
760 147 mohor
   .SyncReset (RstTxPauseRq)
761
  );
762 304 tadejm
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;
763 147 mohor
 
764
// RXCTRL Register
765 304 tadejm
eth_register #(`ETH_RX_CTRL_WIDTH_0, `ETH_RX_CTRL_DEF_0)      RXCTRL_0
766 147 mohor
  (
767 304 tadejm
   .DataIn    (DataIn[`ETH_RX_CTRL_WIDTH_0 - 1:0]),
768
   .DataOut   (RXCTRLOut[`ETH_RX_CTRL_WIDTH_0 - 1:0]),
769
   .Write     (RXCTRL_Wr & Write[0]),
770 147 mohor
   .Clk       (Clk),
771
   .Reset     (Reset),
772
   .SyncReset (1'b0)
773
  );
774 304 tadejm
eth_register #(`ETH_RX_CTRL_WIDTH_1, `ETH_RX_CTRL_DEF_1)      RXCTRL_1
775
  (
776
   .DataIn    (DataIn[`ETH_RX_CTRL_WIDTH_1 + 7:8]),
777
   .DataOut   (RXCTRLOut[`ETH_RX_CTRL_WIDTH_1 + 7:8]),
778
   .Write     (RXCTRL_Wr & Write[1]),
779
   .Clk       (Clk),
780
   .Reset     (Reset),
781
   .SyncReset (1'b0)
782
  );
783
assign RXCTRLOut[31:`ETH_RX_CTRL_WIDTH_1 + 8] = 0;
784 147 mohor
 
785
 
786 139 mohor
// Reading data from registers
787
always @ (Address       or Read           or MODEROut       or INT_SOURCEOut  or
788
          INT_MASKOut   or IPGTOut        or IPGR1Out       or IPGR2Out       or
789
          PACKETLENOut  or COLLCONFOut    or CTRLMODEROut   or MIIMODEROut    or
790
          MIICOMMANDOut or MIIADDRESSOut  or MIITX_DATAOut  or MIIRX_DATAOut  or
791
          MIISTATUSOut  or MAC_ADDR0Out   or MAC_ADDR1Out   or TX_BD_NUMOut   or
792 147 mohor
          HASH0Out      or HASH1Out       or TXCTRLOut      or RXCTRLOut
793 139 mohor
         )
794 15 mohor
begin
795
  if(Read)  // read
796
    begin
797
      case(Address)
798 20 mohor
        `ETH_MODER_ADR        :  DataOut<=MODEROut;
799
        `ETH_INT_SOURCE_ADR   :  DataOut<=INT_SOURCEOut;
800
        `ETH_INT_MASK_ADR     :  DataOut<=INT_MASKOut;
801
        `ETH_IPGT_ADR         :  DataOut<=IPGTOut;
802
        `ETH_IPGR1_ADR        :  DataOut<=IPGR1Out;
803
        `ETH_IPGR2_ADR        :  DataOut<=IPGR2Out;
804
        `ETH_PACKETLEN_ADR    :  DataOut<=PACKETLENOut;
805
        `ETH_COLLCONF_ADR     :  DataOut<=COLLCONFOut;
806
        `ETH_CTRLMODER_ADR    :  DataOut<=CTRLMODEROut;
807
        `ETH_MIIMODER_ADR     :  DataOut<=MIIMODEROut;
808
        `ETH_MIICOMMAND_ADR   :  DataOut<=MIICOMMANDOut;
809
        `ETH_MIIADDRESS_ADR   :  DataOut<=MIIADDRESSOut;
810
        `ETH_MIITX_DATA_ADR   :  DataOut<=MIITX_DATAOut;
811
        `ETH_MIIRX_DATA_ADR   :  DataOut<=MIIRX_DATAOut;
812
        `ETH_MIISTATUS_ADR    :  DataOut<=MIISTATUSOut;
813
        `ETH_MAC_ADDR0_ADR    :  DataOut<=MAC_ADDR0Out;
814
        `ETH_MAC_ADDR1_ADR    :  DataOut<=MAC_ADDR1Out;
815 34 mohor
        `ETH_TX_BD_NUM_ADR    :  DataOut<=TX_BD_NUMOut;
816 56 mohor
        `ETH_HASH0_ADR        :  DataOut<=HASH0Out;
817
        `ETH_HASH1_ADR        :  DataOut<=HASH1Out;
818 147 mohor
        `ETH_TX_CTRL_ADR      :  DataOut<=TXCTRLOut;
819
        `ETH_RX_CTRL_ADR      :  DataOut<=RXCTRLOut;
820
 
821 15 mohor
        default:             DataOut<=32'h0;
822
      endcase
823
    end
824
  else
825
    DataOut<=32'h0;
826
end
827
 
828
 
829
assign r_RecSmall         = MODEROut[16];
830
assign r_Pad              = MODEROut[15];
831
assign r_HugEn            = MODEROut[14];
832
assign r_CrcEn            = MODEROut[13];
833
assign r_DlyCrcEn         = MODEROut[12];
834 244 mohor
// assign r_Rst           = MODEROut[11];   This signal is not used any more
835 15 mohor
assign r_FullD            = MODEROut[10];
836
assign r_ExDfrEn          = MODEROut[9];
837
assign r_NoBckof          = MODEROut[8];
838
assign r_LoopBck          = MODEROut[7];
839
assign r_IFG              = MODEROut[6];
840
assign r_Pro              = MODEROut[5];
841
assign r_Iam              = MODEROut[4];
842
assign r_Bro              = MODEROut[3];
843
assign r_NoPre            = MODEROut[2];
844 143 mohor
assign r_TxEn             = MODEROut[1] & (TX_BD_NUMOut>0);     // Transmission is enabled when there is at least one TxBD.
845
assign r_RxEn             = MODEROut[0] & (TX_BD_NUMOut<'h80);  // Reception is enabled when there is  at least one RxBD.
846 15 mohor
 
847
assign r_IPGT[6:0]        = IPGTOut[6:0];
848
 
849
assign r_IPGR1[6:0]       = IPGR1Out[6:0];
850
 
851
assign r_IPGR2[6:0]       = IPGR2Out[6:0];
852
 
853
assign r_MinFL[15:0]      = PACKETLENOut[31:16];
854
assign r_MaxFL[15:0]      = PACKETLENOut[15:0];
855
 
856 56 mohor
assign r_MaxRet[3:0]      = COLLCONFOut[19:16];
857
assign r_CollValid[5:0]   = COLLCONFOut[5:0];
858 15 mohor
 
859
assign r_TxFlow           = CTRLMODEROut[2];
860
assign r_RxFlow           = CTRLMODEROut[1];
861
assign r_PassAll          = CTRLMODEROut[0];
862
 
863
assign r_MiiNoPre         = MIIMODEROut[8];
864
assign r_ClkDiv[7:0]      = MIIMODEROut[7:0];
865
 
866
assign r_WCtrlData        = MIICOMMANDOut[2];
867
assign r_RStat            = MIICOMMANDOut[1];
868
assign r_ScanStat         = MIICOMMANDOut[0];
869
 
870
assign r_RGAD[4:0]        = MIIADDRESSOut[12:8];
871
assign r_FIAD[4:0]        = MIIADDRESSOut[4:0];
872
 
873
assign r_CtrlData[15:0]   = MIITX_DATAOut[15:0];
874
 
875 139 mohor
assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
876
assign MIISTATUSOut[2]    = NValid_stat         ;
877
assign MIISTATUSOut[1]    = Busy_stat           ;
878
assign MIISTATUSOut[0]    = LinkFail            ;
879 15 mohor
 
880
assign r_MAC[31:0]        = MAC_ADDR0Out[31:0];
881
assign r_MAC[47:32]       = MAC_ADDR1Out[15:0];
882 52 billditt
assign r_HASH1[31:0]      = HASH1Out;
883
assign r_HASH0[31:0]      = HASH0Out;
884 15 mohor
 
885 147 mohor
assign r_TxBDNum[7:0]     = TX_BD_NUMOut[7:0];
886 15 mohor
 
887 147 mohor
assign r_TxPauseTV[15:0]  = TXCTRLOut[15:0];
888
assign r_TxPauseRq        = TXCTRLOut[16];
889 15 mohor
 
890 147 mohor
 
891
// Synchronizing TxC Interrupt
892
always @ (posedge TxClk or posedge Reset)
893
begin
894
  if(Reset)
895
    SetTxCIrq_txclk <=#Tp 1'b0;
896
  else
897
  if(TxCtrlEndFrm & StartTxDone & r_TxFlow)
898
    SetTxCIrq_txclk <=#Tp 1'b1;
899
  else
900
  if(ResetTxCIrq_sync2)
901
    SetTxCIrq_txclk <=#Tp 1'b0;
902
end
903
 
904
 
905
always @ (posedge Clk or posedge Reset)
906
begin
907
  if(Reset)
908
    SetTxCIrq_sync1 <=#Tp 1'b0;
909
  else
910
    SetTxCIrq_sync1 <=#Tp SetTxCIrq_txclk;
911
end
912
 
913
always @ (posedge Clk or posedge Reset)
914
begin
915
  if(Reset)
916
    SetTxCIrq_sync2 <=#Tp 1'b0;
917
  else
918
    SetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
919
end
920
 
921
always @ (posedge Clk or posedge Reset)
922
begin
923
  if(Reset)
924
    SetTxCIrq_sync3 <=#Tp 1'b0;
925
  else
926
    SetTxCIrq_sync3 <=#Tp SetTxCIrq_sync2;
927
end
928
 
929
always @ (posedge Clk or posedge Reset)
930
begin
931
  if(Reset)
932
    SetTxCIrq <=#Tp 1'b0;
933
  else
934
    SetTxCIrq <=#Tp SetTxCIrq_sync2 & ~SetTxCIrq_sync3;
935
end
936
 
937
always @ (posedge TxClk or posedge Reset)
938
begin
939
  if(Reset)
940
    ResetTxCIrq_sync1 <=#Tp 1'b0;
941
  else
942
    ResetTxCIrq_sync1 <=#Tp SetTxCIrq_sync2;
943
end
944
 
945
always @ (posedge TxClk or posedge Reset)
946
begin
947
  if(Reset)
948
    ResetTxCIrq_sync2 <=#Tp 1'b0;
949
  else
950
    ResetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
951
end
952
 
953
 
954
// Synchronizing RxC Interrupt
955
always @ (posedge RxClk or posedge Reset)
956
begin
957
  if(Reset)
958
    SetRxCIrq_rxclk <=#Tp 1'b0;
959
  else
960 261 mohor
  if(SetPauseTimer & r_RxFlow)
961 147 mohor
    SetRxCIrq_rxclk <=#Tp 1'b1;
962
  else
963 261 mohor
  if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
964 147 mohor
    SetRxCIrq_rxclk <=#Tp 1'b0;
965
end
966
 
967
 
968
always @ (posedge Clk or posedge Reset)
969
begin
970
  if(Reset)
971
    SetRxCIrq_sync1 <=#Tp 1'b0;
972
  else
973
    SetRxCIrq_sync1 <=#Tp SetRxCIrq_rxclk;
974
end
975
 
976
always @ (posedge Clk or posedge Reset)
977
begin
978
  if(Reset)
979
    SetRxCIrq_sync2 <=#Tp 1'b0;
980
  else
981
    SetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1;
982
end
983
 
984
always @ (posedge Clk or posedge Reset)
985
begin
986
  if(Reset)
987
    SetRxCIrq_sync3 <=#Tp 1'b0;
988
  else
989
    SetRxCIrq_sync3 <=#Tp SetRxCIrq_sync2;
990
end
991
 
992
always @ (posedge Clk or posedge Reset)
993
begin
994
  if(Reset)
995
    SetRxCIrq <=#Tp 1'b0;
996
  else
997
    SetRxCIrq <=#Tp SetRxCIrq_sync2 & ~SetRxCIrq_sync3;
998
end
999
 
1000
always @ (posedge RxClk or posedge Reset)
1001
begin
1002
  if(Reset)
1003
    ResetRxCIrq_sync1 <=#Tp 1'b0;
1004
  else
1005
    ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2;
1006
end
1007
 
1008 261 mohor
always @ (posedge RxClk or posedge Reset)
1009 147 mohor
begin
1010
  if(Reset)
1011
    ResetRxCIrq_sync2 <=#Tp 1'b0;
1012
  else
1013 261 mohor
    ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1;
1014 147 mohor
end
1015
 
1016 261 mohor
always @ (posedge RxClk or posedge Reset)
1017
begin
1018
  if(Reset)
1019
    ResetRxCIrq_sync3 <=#Tp 1'b0;
1020
  else
1021
    ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2;
1022
end
1023 147 mohor
 
1024
 
1025
 
1026 21 mohor
// Interrupt generation
1027
always @ (posedge Clk or posedge Reset)
1028
begin
1029
  if(Reset)
1030
    irq_txb <= 1'b0;
1031
  else
1032 102 mohor
  if(TxB_IRQ)
1033 21 mohor
    irq_txb <= #Tp 1'b1;
1034
  else
1035 304 tadejm
  if(INT_SOURCE_Wr & Write[0] & DataIn[0])
1036 21 mohor
    irq_txb <= #Tp 1'b0;
1037
end
1038
 
1039
always @ (posedge Clk or posedge Reset)
1040
begin
1041
  if(Reset)
1042
    irq_txe <= 1'b0;
1043
  else
1044 102 mohor
  if(TxE_IRQ)
1045 21 mohor
    irq_txe <= #Tp 1'b1;
1046
  else
1047 304 tadejm
  if(INT_SOURCE_Wr & Write[0] & DataIn[1])
1048 21 mohor
    irq_txe <= #Tp 1'b0;
1049
end
1050
 
1051
always @ (posedge Clk or posedge Reset)
1052
begin
1053
  if(Reset)
1054
    irq_rxb <= 1'b0;
1055
  else
1056 102 mohor
  if(RxB_IRQ)
1057 21 mohor
    irq_rxb <= #Tp 1'b1;
1058
  else
1059 304 tadejm
  if(INT_SOURCE_Wr & Write[0] & DataIn[2])
1060 21 mohor
    irq_rxb <= #Tp 1'b0;
1061
end
1062
 
1063
always @ (posedge Clk or posedge Reset)
1064
begin
1065
  if(Reset)
1066 74 mohor
    irq_rxe <= 1'b0;
1067 21 mohor
  else
1068 102 mohor
  if(RxE_IRQ)
1069 74 mohor
    irq_rxe <= #Tp 1'b1;
1070 21 mohor
  else
1071 304 tadejm
  if(INT_SOURCE_Wr & Write[0] & DataIn[3])
1072 74 mohor
    irq_rxe <= #Tp 1'b0;
1073 21 mohor
end
1074
 
1075
always @ (posedge Clk or posedge Reset)
1076
begin
1077
  if(Reset)
1078
    irq_busy <= 1'b0;
1079
  else
1080 102 mohor
  if(Busy_IRQ)
1081 21 mohor
    irq_busy <= #Tp 1'b1;
1082
  else
1083 304 tadejm
  if(INT_SOURCE_Wr & Write[0] & DataIn[4])
1084 21 mohor
    irq_busy <= #Tp 1'b0;
1085
end
1086
 
1087 74 mohor
always @ (posedge Clk or posedge Reset)
1088
begin
1089
  if(Reset)
1090
    irq_txc <= 1'b0;
1091
  else
1092 147 mohor
  if(SetTxCIrq)
1093 74 mohor
    irq_txc <= #Tp 1'b1;
1094
  else
1095 304 tadejm
  if(INT_SOURCE_Wr & Write[0] & DataIn[5])
1096 74 mohor
    irq_txc <= #Tp 1'b0;
1097
end
1098
 
1099
always @ (posedge Clk or posedge Reset)
1100
begin
1101
  if(Reset)
1102
    irq_rxc <= 1'b0;
1103
  else
1104 147 mohor
  if(SetRxCIrq)
1105 74 mohor
    irq_rxc <= #Tp 1'b1;
1106
  else
1107 304 tadejm
  if(INT_SOURCE_Wr & Write[0] & DataIn[6])
1108 74 mohor
    irq_rxc <= #Tp 1'b0;
1109
end
1110
 
1111 21 mohor
// Generating interrupt signal
1112 102 mohor
assign int_o = irq_txb  & INT_MASKOut[0] |
1113
               irq_txe  & INT_MASKOut[1] |
1114
               irq_rxb  & INT_MASKOut[2] |
1115
               irq_rxe  & INT_MASKOut[3] |
1116
               irq_busy & INT_MASKOut[4] |
1117
               irq_txc  & INT_MASKOut[5] |
1118
               irq_rxc  & INT_MASKOut[6] ;
1119 21 mohor
 
1120
// For reading interrupt status
1121 304 tadejm
assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH_0){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
1122 21 mohor
 
1123
 
1124
 
1125 15 mohor
endmodule

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