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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Blame information for rev 320

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1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_registers.v                                             ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 147 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 15 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 320 igorm
// Revision 1.26  2003/11/12 18:24:59  tadejm
45
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
46
//
47 304 tadejm
// Revision 1.25  2003/04/18 16:26:25  mohor
48
// RxBDAddress was updated also when value to r_TxBDNum was written with
49
// greater value than allowed.
50
//
51 283 mohor
// Revision 1.24  2002/11/22 01:57:06  mohor
52
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
53
// synchronized.
54
//
55 261 mohor
// Revision 1.23  2002/11/19 18:13:49  mohor
56
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
57
//
58 253 mohor
// Revision 1.22  2002/11/14 18:37:20  mohor
59
// r_Rst signal does not reset any module any more and is removed from the design.
60
//
61 244 mohor
// Revision 1.21  2002/09/10 10:35:23  mohor
62
// Ethernet debug registers removed.
63
//
64 164 mohor
// Revision 1.20  2002/09/04 18:40:25  mohor
65
// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
66
// the control frames connected.
67
//
68 147 mohor
// Revision 1.19  2002/08/19 16:01:40  mohor
69
// Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
70
// r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
71
//
72 143 mohor
// Revision 1.18  2002/08/16 22:28:23  mohor
73
// Syntax error fixed.
74
//
75 141 mohor
// Revision 1.17  2002/08/16 22:23:03  mohor
76
// Syntax error fixed.
77
//
78 140 mohor
// Revision 1.16  2002/08/16 22:14:22  mohor
79
// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
80
// changed from bit position 10 to 9.
81
//
82 139 mohor
// Revision 1.15  2002/08/14 18:26:37  mohor
83
// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
84
//
85 132 mohor
// Revision 1.14  2002/04/22 14:03:44  mohor
86
// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
87
// or not.
88
//
89 102 mohor
// Revision 1.13  2002/02/26 16:18:09  mohor
90
// Reset values are passed to registers through parameters
91
//
92 74 mohor
// Revision 1.12  2002/02/17 13:23:42  mohor
93
// Define missmatch fixed.
94
//
95 69 mohor
// Revision 1.11  2002/02/16 14:03:44  mohor
96
// Registered trimmed. Unused registers removed.
97
//
98 68 mohor
// Revision 1.10  2002/02/15 11:08:25  mohor
99
// File format fixed a bit.
100
//
101 56 mohor
// Revision 1.9  2002/02/14 20:19:41  billditt
102
// Modified for Address Checking,
103
// addition of eth_addrcheck.v
104
//
105
// Revision 1.8  2002/02/12 17:01:19  mohor
106
// HASH0 and HASH1 registers added. 
107
 
108 46 mohor
// Revision 1.7  2002/01/23 10:28:16  mohor
109
// Link in the header changed.
110
//
111 37 mohor
// Revision 1.6  2001/12/05 15:00:16  mohor
112
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
113
// instead of the number of RX descriptors).
114
//
115 34 mohor
// Revision 1.5  2001/12/05 10:22:19  mohor
116
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
117
//
118 32 mohor
// Revision 1.4  2001/10/19 08:43:51  mohor
119
// eth_timescale.v changed to timescale.v This is done because of the
120
// simulation of the few cores in a one joined project.
121
//
122 22 mohor
// Revision 1.3  2001/10/18 12:07:11  mohor
123
// Status signals changed, Adress decoding changed, interrupt controller
124
// added.
125
//
126 21 mohor
// Revision 1.2  2001/09/24 15:02:56  mohor
127
// Defines changed (All precede with ETH_). Small changes because some
128
// tools generate warnings when two operands are together. Synchronization
129
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
130
// demands).
131
//
132 20 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
133
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
134
// Include files fixed to contain no path.
135
// File names and module names changed ta have a eth_ prologue in the name.
136
// File eth_timescale.v is used to define timescale
137
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
138
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
139
// and Mdo_OE. The bidirectional signal must be created on the top level. This
140
// is done due to the ASIC tools.
141
//
142 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
143
// Unconnected signals are now connected.
144
//
145
// Revision 1.1  2001/07/30 21:23:42  mohor
146
// Directory structure changed. Files checked and joind together.
147
//
148
//
149
//
150
//
151
//
152
//
153
 
154
`include "eth_defines.v"
155 22 mohor
`include "timescale.v"
156 15 mohor
 
157
 
158 68 mohor
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
159 15 mohor
                      r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
160 244 mohor
                      r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
161 21 mohor
                      r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
162 147 mohor
                      TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
163 21 mohor
                      r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
164 15 mohor
                      r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
165 253 mohor
                      r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
166 15 mohor
                      r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
167
                      LinkFail, r_MAC, WCtrlDataStart, RStatStart,
168 46 mohor
                      UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
169 147 mohor
                      r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
170 261 mohor
                      StartTxDone, TxClk, RxClk, SetPauseTimer
171 15 mohor
                    );
172
 
173
parameter Tp = 1;
174
 
175
input [31:0] DataIn;
176 46 mohor
input [7:0] Address;
177 15 mohor
 
178
input Rw;
179 304 tadejm
input [3:0] Cs;
180 15 mohor
input Clk;
181
input Reset;
182
 
183
input WCtrlDataStart;
184
input RStatStart;
185
 
186
input UpdateMIIRX_DATAReg;
187
input [15:0] Prsd;
188
 
189
output [31:0] DataOut;
190
reg    [31:0] DataOut;
191
 
192
output r_RecSmall;
193
output r_Pad;
194
output r_HugEn;
195
output r_CrcEn;
196
output r_DlyCrcEn;
197
output r_FullD;
198
output r_ExDfrEn;
199
output r_NoBckof;
200
output r_LoopBck;
201
output r_IFG;
202
output r_Pro;
203
output r_Iam;
204
output r_Bro;
205
output r_NoPre;
206
output r_TxEn;
207
output r_RxEn;
208 52 billditt
output [31:0] r_HASH0;
209
output [31:0] r_HASH1;
210 15 mohor
 
211 21 mohor
input TxB_IRQ;
212
input TxE_IRQ;
213
input RxB_IRQ;
214 74 mohor
input RxE_IRQ;
215 21 mohor
input Busy_IRQ;
216 15 mohor
 
217
output [6:0] r_IPGT;
218
 
219
output [6:0] r_IPGR1;
220
 
221
output [6:0] r_IPGR2;
222
 
223
output [15:0] r_MinFL;
224
output [15:0] r_MaxFL;
225
 
226
output [3:0] r_MaxRet;
227
output [5:0] r_CollValid;
228
 
229
output r_TxFlow;
230
output r_RxFlow;
231
output r_PassAll;
232
 
233
output r_MiiNoPre;
234
output [7:0] r_ClkDiv;
235
 
236
output r_WCtrlData;
237
output r_RStat;
238
output r_ScanStat;
239
 
240
output [4:0] r_RGAD;
241
output [4:0] r_FIAD;
242
 
243 21 mohor
output [15:0]r_CtrlData;
244 15 mohor
 
245
 
246
input NValid_stat;
247
input Busy_stat;
248
input LinkFail;
249
 
250 21 mohor
output [47:0]r_MAC;
251 34 mohor
output [7:0] r_TxBDNum;
252
output       TX_BD_NUM_Wr;
253 21 mohor
output       int_o;
254 147 mohor
output [15:0]r_TxPauseTV;
255
output       r_TxPauseRq;
256
input        RstTxPauseRq;
257
input        TxCtrlEndFrm;
258
input        StartTxDone;
259
input        TxClk;
260
input        RxClk;
261 261 mohor
input        SetPauseTimer;
262 15 mohor
 
263 21 mohor
reg          irq_txb;
264
reg          irq_txe;
265
reg          irq_rxb;
266 74 mohor
reg          irq_rxe;
267 21 mohor
reg          irq_busy;
268 74 mohor
reg          irq_txc;
269
reg          irq_rxc;
270 15 mohor
 
271 147 mohor
reg SetTxCIrq_txclk;
272
reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3;
273
reg SetTxCIrq;
274
reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
275
 
276
reg SetRxCIrq_rxclk;
277
reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
278
reg SetRxCIrq;
279 261 mohor
reg ResetRxCIrq_sync1;
280
reg ResetRxCIrq_sync2;
281
reg ResetRxCIrq_sync3;
282 147 mohor
 
283 304 tadejm
wire [3:0] Write =   Cs  & {4{Rw}};
284
wire       Read  = (|Cs) &   ~Rw;
285 15 mohor
 
286 320 igorm
wire MODER_Sel      = (Address == `ETH_MODER_ADR       );
287
wire INT_SOURCE_Sel = (Address == `ETH_INT_SOURCE_ADR  );
288
wire INT_MASK_Sel   = (Address == `ETH_INT_MASK_ADR    );
289
wire IPGT_Sel       = (Address == `ETH_IPGT_ADR        );
290
wire IPGR1_Sel      = (Address == `ETH_IPGR1_ADR       );
291
wire IPGR2_Sel      = (Address == `ETH_IPGR2_ADR       );
292
wire PACKETLEN_Sel  = (Address == `ETH_PACKETLEN_ADR   );
293
wire COLLCONF_Sel   = (Address == `ETH_COLLCONF_ADR    );
294 21 mohor
 
295 320 igorm
wire CTRLMODER_Sel  = (Address == `ETH_CTRLMODER_ADR   );
296
wire MIIMODER_Sel   = (Address == `ETH_MIIMODER_ADR    );
297
wire MIICOMMAND_Sel = (Address == `ETH_MIICOMMAND_ADR  );
298
wire MIIADDRESS_Sel = (Address == `ETH_MIIADDRESS_ADR  );
299
wire MIITX_DATA_Sel = (Address == `ETH_MIITX_DATA_ADR  );
300
wire MAC_ADDR0_Sel  = (Address == `ETH_MAC_ADDR0_ADR   );
301
wire MAC_ADDR1_Sel  = (Address == `ETH_MAC_ADDR1_ADR   );
302
wire HASH0_Sel      = (Address == `ETH_HASH0_ADR       );
303
wire HASH1_Sel      = (Address == `ETH_HASH1_ADR       );
304
wire TXCTRL_Sel     = (Address == `ETH_TX_CTRL_ADR     );
305
wire RXCTRL_Sel     = (Address == `ETH_RX_CTRL_ADR     );
306
wire TX_BD_NUM_Sel  = (Address == `ETH_TX_BD_NUM_ADR   );
307 15 mohor
 
308
 
309 320 igorm
wire [2:0] MODER_Wr;
310
wire [0:0] INT_SOURCE_Wr;
311
wire [0:0] INT_MASK_Wr;
312
wire [0:0] IPGT_Wr;
313
wire [0:0] IPGR1_Wr;
314
wire [0:0] IPGR2_Wr;
315
wire [3:0] PACKETLEN_Wr;
316
wire [2:0] COLLCONF_Wr;
317
wire [0:0] CTRLMODER_Wr;
318
wire [1:0] MIIMODER_Wr;
319
wire [0:0] MIICOMMAND_Wr;
320
wire [1:0] MIIADDRESS_Wr;
321
wire [1:0] MIITX_DATA_Wr;
322
wire       MIIRX_DATA_Wr;
323
wire [3:0] MAC_ADDR0_Wr;
324
wire [1:0] MAC_ADDR1_Wr;
325
wire [3:0] HASH0_Wr;
326
wire [3:0] HASH1_Wr;
327
wire [2:0] TXCTRL_Wr;
328
wire [1:0] RXCTRL_Wr;
329 15 mohor
 
330 320 igorm
assign MODER_Wr[0]       = Write[0]  & MODER_Sel;
331
assign MODER_Wr[1]       = Write[1]  & MODER_Sel;
332
assign MODER_Wr[2]       = Write[2]  & MODER_Sel;
333
assign INT_SOURCE_Wr[0]  = Write[0]  & INT_SOURCE_Sel;
334
assign INT_MASK_Wr[0]    = Write[0]  & INT_MASK_Sel;
335
assign IPGT_Wr[0]        = Write[0]  & IPGT_Sel;
336
assign IPGR1_Wr[0]       = Write[0]  & IPGR1_Sel;
337
assign IPGR2_Wr[0]       = Write[0]  & IPGR2_Sel;
338
assign PACKETLEN_Wr[0]   = Write[0]  & PACKETLEN_Sel;
339
assign PACKETLEN_Wr[1]   = Write[1]  & PACKETLEN_Sel;
340
assign PACKETLEN_Wr[2]   = Write[2]  & PACKETLEN_Sel;
341
assign PACKETLEN_Wr[3]   = Write[3]  & PACKETLEN_Sel;
342
assign COLLCONF_Wr[0]    = Write[0]  & COLLCONF_Sel;
343
assign COLLCONF_Wr[1]    = 1'b0;  // Not used
344
assign COLLCONF_Wr[2]    = Write[2]  & COLLCONF_Sel;
345
 
346
assign CTRLMODER_Wr[0]   = Write[0]  & CTRLMODER_Sel;
347
assign MIIMODER_Wr[0]    = Write[0]  & MIIMODER_Sel;
348
assign MIIMODER_Wr[1]    = Write[1]  & MIIMODER_Sel;
349
assign MIICOMMAND_Wr[0]  = Write[0]  & MIICOMMAND_Sel;
350
assign MIIADDRESS_Wr[0]  = Write[0]  & MIIADDRESS_Sel;
351
assign MIIADDRESS_Wr[1]  = Write[1]  & MIIADDRESS_Sel;
352
assign MIITX_DATA_Wr[0]  = Write[0]  & MIITX_DATA_Sel;
353
assign MIITX_DATA_Wr[1]  = Write[1]  & MIITX_DATA_Sel;
354
assign MIIRX_DATA_Wr     = UpdateMIIRX_DATAReg;
355
assign MAC_ADDR0_Wr[0]   = Write[0]  & MAC_ADDR0_Sel;
356
assign MAC_ADDR0_Wr[1]   = Write[1]  & MAC_ADDR0_Sel;
357
assign MAC_ADDR0_Wr[2]   = Write[2]  & MAC_ADDR0_Sel;
358
assign MAC_ADDR0_Wr[3]   = Write[3]  & MAC_ADDR0_Sel;
359
assign MAC_ADDR1_Wr[0]   = Write[0]  & MAC_ADDR1_Sel;
360
assign MAC_ADDR1_Wr[1]   = Write[1]  & MAC_ADDR1_Sel;
361
assign HASH0_Wr[0]       = Write[0]  & HASH0_Sel;
362
assign HASH0_Wr[1]       = Write[1]  & HASH0_Sel;
363
assign HASH0_Wr[2]       = Write[2]  & HASH0_Sel;
364
assign HASH0_Wr[3]       = Write[3]  & HASH0_Sel;
365
assign HASH1_Wr[0]       = Write[0]  & HASH1_Sel;
366
assign HASH1_Wr[1]       = Write[1]  & HASH1_Sel;
367
assign HASH1_Wr[2]       = Write[2]  & HASH1_Sel;
368
assign HASH1_Wr[3]       = Write[3]  & HASH1_Sel;
369
assign TXCTRL_Wr[0]      = Write[0]  & TXCTRL_Sel;
370
assign TXCTRL_Wr[1]      = Write[1]  & TXCTRL_Sel;
371
assign TXCTRL_Wr[2]      = Write[2]  & TXCTRL_Sel;
372
assign RXCTRL_Wr[0]      = Write[0]  & RXCTRL_Sel;
373
assign RXCTRL_Wr[1]      = Write[1]  & RXCTRL_Sel;
374
assign TX_BD_NUM_Wr      = Write[0]  & TX_BD_NUM_Sel & (DataIn<='h80);
375
 
376
 
377
 
378 15 mohor
wire [31:0] MODEROut;
379
wire [31:0] INT_SOURCEOut;
380
wire [31:0] INT_MASKOut;
381
wire [31:0] IPGTOut;
382
wire [31:0] IPGR1Out;
383
wire [31:0] IPGR2Out;
384
wire [31:0] PACKETLENOut;
385
wire [31:0] COLLCONFOut;
386
wire [31:0] CTRLMODEROut;
387
wire [31:0] MIIMODEROut;
388
wire [31:0] MIICOMMANDOut;
389
wire [31:0] MIIADDRESSOut;
390
wire [31:0] MIITX_DATAOut;
391
wire [31:0] MIIRX_DATAOut;
392
wire [31:0] MIISTATUSOut;
393
wire [31:0] MAC_ADDR0Out;
394
wire [31:0] MAC_ADDR1Out;
395 34 mohor
wire [31:0] TX_BD_NUMOut;
396 52 billditt
wire [31:0] HASH0Out;
397
wire [31:0] HASH1Out;
398 147 mohor
wire [31:0] TXCTRLOut;
399
wire [31:0] RXCTRLOut;
400 15 mohor
 
401 139 mohor
// MODER Register
402 304 tadejm
eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0)        MODER_0
403 139 mohor
  (
404 304 tadejm
   .DataIn    (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
405
   .DataOut   (MODEROut[`ETH_MODER_WIDTH_0 - 1:0]),
406 320 igorm
   .Write     (MODER_Wr[0]),
407 139 mohor
   .Clk       (Clk),
408
   .Reset     (Reset),
409 141 mohor
   .SyncReset (1'b0)
410 139 mohor
  );
411 304 tadejm
eth_register #(`ETH_MODER_WIDTH_1, `ETH_MODER_DEF_1)        MODER_1
412
  (
413
   .DataIn    (DataIn[`ETH_MODER_WIDTH_1 + 7:8]),
414
   .DataOut   (MODEROut[`ETH_MODER_WIDTH_1 + 7:8]),
415 320 igorm
   .Write     (MODER_Wr[1]),
416 304 tadejm
   .Clk       (Clk),
417
   .Reset     (Reset),
418
   .SyncReset (1'b0)
419
  );
420
eth_register #(`ETH_MODER_WIDTH_2, `ETH_MODER_DEF_2)        MODER_2
421
  (
422
   .DataIn    (DataIn[`ETH_MODER_WIDTH_2 + 15:16]),
423
   .DataOut   (MODEROut[`ETH_MODER_WIDTH_2 + 15:16]),
424 320 igorm
   .Write     (MODER_Wr[2]),
425 304 tadejm
   .Clk       (Clk),
426
   .Reset     (Reset),
427
   .SyncReset (1'b0)
428
  );
429
assign MODEROut[31:`ETH_MODER_WIDTH_2 + 16] = 0;
430 15 mohor
 
431 139 mohor
// INT_MASK Register
432 304 tadejm
eth_register #(`ETH_INT_MASK_WIDTH_0, `ETH_INT_MASK_DEF_0)  INT_MASK_0
433 139 mohor
  (
434 304 tadejm
   .DataIn    (DataIn[`ETH_INT_MASK_WIDTH_0 - 1:0]),
435
   .DataOut   (INT_MASKOut[`ETH_INT_MASK_WIDTH_0 - 1:0]),
436 320 igorm
   .Write     (INT_MASK_Wr[0]),
437 139 mohor
   .Clk       (Clk),
438
   .Reset     (Reset),
439 141 mohor
   .SyncReset (1'b0)
440 139 mohor
  );
441 304 tadejm
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH_0] = 0;
442 52 billditt
 
443 139 mohor
// IPGT Register
444 304 tadejm
eth_register #(`ETH_IPGT_WIDTH_0, `ETH_IPGT_DEF_0)          IPGT_0
445 139 mohor
  (
446 304 tadejm
   .DataIn    (DataIn[`ETH_IPGT_WIDTH_0 - 1:0]),
447
   .DataOut   (IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0]),
448 320 igorm
   .Write     (IPGT_Wr[0]),
449 139 mohor
   .Clk       (Clk),
450
   .Reset     (Reset),
451 141 mohor
   .SyncReset (1'b0)
452 139 mohor
  );
453 304 tadejm
assign IPGTOut[31:`ETH_IPGT_WIDTH_0] = 0;
454 52 billditt
 
455 139 mohor
// IPGR1 Register
456 304 tadejm
eth_register #(`ETH_IPGR1_WIDTH_0, `ETH_IPGR1_DEF_0)        IPGR1_0
457 139 mohor
  (
458 304 tadejm
   .DataIn    (DataIn[`ETH_IPGR1_WIDTH_0 - 1:0]),
459
   .DataOut   (IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0]),
460 320 igorm
   .Write     (IPGR1_Wr[0]),
461 139 mohor
   .Clk       (Clk),
462
   .Reset     (Reset),
463 141 mohor
   .SyncReset (1'b0)
464 139 mohor
  );
465 304 tadejm
assign IPGR1Out[31:`ETH_IPGR1_WIDTH_0] = 0;
466 15 mohor
 
467 139 mohor
// IPGR2 Register
468 304 tadejm
eth_register #(`ETH_IPGR2_WIDTH_0, `ETH_IPGR2_DEF_0)        IPGR2_0
469 139 mohor
  (
470 304 tadejm
   .DataIn    (DataIn[`ETH_IPGR2_WIDTH_0 - 1:0]),
471
   .DataOut   (IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0]),
472 320 igorm
   .Write     (IPGR2_Wr[0]),
473 139 mohor
   .Clk       (Clk),
474
   .Reset     (Reset),
475 141 mohor
   .SyncReset (1'b0)
476 139 mohor
  );
477 304 tadejm
assign IPGR2Out[31:`ETH_IPGR2_WIDTH_0] = 0;
478 15 mohor
 
479 139 mohor
// PACKETLEN Register
480 304 tadejm
eth_register #(`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0
481 139 mohor
  (
482 304 tadejm
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
483
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
484 320 igorm
   .Write     (PACKETLEN_Wr[0]),
485 139 mohor
   .Clk       (Clk),
486
   .Reset     (Reset),
487 141 mohor
   .SyncReset (1'b0)
488 139 mohor
  );
489 304 tadejm
eth_register #(`ETH_PACKETLEN_WIDTH_1, `ETH_PACKETLEN_DEF_1) PACKETLEN_1
490
  (
491
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
492
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
493 320 igorm
   .Write     (PACKETLEN_Wr[1]),
494 304 tadejm
   .Clk       (Clk),
495
   .Reset     (Reset),
496
   .SyncReset (1'b0)
497
  );
498
eth_register #(`ETH_PACKETLEN_WIDTH_2, `ETH_PACKETLEN_DEF_2) PACKETLEN_2
499
  (
500
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
501
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
502 320 igorm
   .Write     (PACKETLEN_Wr[2]),
503 304 tadejm
   .Clk       (Clk),
504
   .Reset     (Reset),
505
   .SyncReset (1'b0)
506
  );
507
eth_register #(`ETH_PACKETLEN_WIDTH_3, `ETH_PACKETLEN_DEF_3) PACKETLEN_3
508
  (
509
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
510
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
511 320 igorm
   .Write     (PACKETLEN_Wr[3]),
512 304 tadejm
   .Clk       (Clk),
513
   .Reset     (Reset),
514
   .SyncReset (1'b0)
515
  );
516 15 mohor
 
517 139 mohor
// COLLCONF Register
518 304 tadejm
eth_register #(`ETH_COLLCONF_WIDTH_0, `ETH_COLLCONF_DEF_0)   COLLCONF_0
519 139 mohor
  (
520 304 tadejm
   .DataIn    (DataIn[`ETH_COLLCONF_WIDTH_0 - 1:0]),
521
   .DataOut   (COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0]),
522 320 igorm
   .Write     (COLLCONF_Wr[0]),
523 139 mohor
   .Clk       (Clk),
524
   .Reset     (Reset),
525 141 mohor
   .SyncReset (1'b0)
526 139 mohor
  );
527 304 tadejm
eth_register #(`ETH_COLLCONF_WIDTH_2, `ETH_COLLCONF_DEF_2)   COLLCONF_2
528 139 mohor
  (
529 304 tadejm
   .DataIn    (DataIn[`ETH_COLLCONF_WIDTH_2 + 15:16]),
530
   .DataOut   (COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16]),
531 320 igorm
   .Write     (COLLCONF_Wr[2]),
532 139 mohor
   .Clk       (Clk),
533
   .Reset     (Reset),
534 141 mohor
   .SyncReset (1'b0)
535 139 mohor
  );
536 304 tadejm
assign COLLCONFOut[15:`ETH_COLLCONF_WIDTH_0] = 0;
537
assign COLLCONFOut[31:`ETH_COLLCONF_WIDTH_2 + 16] = 0;
538 15 mohor
 
539 139 mohor
// TX_BD_NUM Register
540 304 tadejm
eth_register #(`ETH_TX_BD_NUM_WIDTH_0, `ETH_TX_BD_NUM_DEF_0) TX_BD_NUM_0
541 139 mohor
  (
542 304 tadejm
   .DataIn    (DataIn[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
543
   .DataOut   (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
544 320 igorm
   .Write     (TX_BD_NUM_Wr),
545 139 mohor
   .Clk       (Clk),
546
   .Reset     (Reset),
547 141 mohor
   .SyncReset (1'b0)
548 139 mohor
  );
549 304 tadejm
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH_0] = 0;
550 15 mohor
 
551 139 mohor
// CTRLMODER Register
552 304 tadejm
eth_register #(`ETH_CTRLMODER_WIDTH_0, `ETH_CTRLMODER_DEF_0)  CTRLMODER_0
553 139 mohor
  (
554 304 tadejm
   .DataIn    (DataIn[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
555
   .DataOut   (CTRLMODEROut[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
556 320 igorm
   .Write     (CTRLMODER_Wr[0]),
557 139 mohor
   .Clk       (Clk),
558
   .Reset     (Reset),
559 141 mohor
   .SyncReset (1'b0)
560 139 mohor
  );
561 304 tadejm
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH_0] = 0;
562 15 mohor
 
563 139 mohor
// MIIMODER Register
564 304 tadejm
eth_register #(`ETH_MIIMODER_WIDTH_0, `ETH_MIIMODER_DEF_0)    MIIMODER_0
565 139 mohor
  (
566 304 tadejm
   .DataIn    (DataIn[`ETH_MIIMODER_WIDTH_0 - 1:0]),
567
   .DataOut   (MIIMODEROut[`ETH_MIIMODER_WIDTH_0 - 1:0]),
568 320 igorm
   .Write     (MIIMODER_Wr[0]),
569 139 mohor
   .Clk       (Clk),
570
   .Reset     (Reset),
571 141 mohor
   .SyncReset (1'b0)
572 139 mohor
  );
573 304 tadejm
eth_register #(`ETH_MIIMODER_WIDTH_1, `ETH_MIIMODER_DEF_1)    MIIMODER_1
574
  (
575
   .DataIn    (DataIn[`ETH_MIIMODER_WIDTH_1 + 7:8]),
576
   .DataOut   (MIIMODEROut[`ETH_MIIMODER_WIDTH_1 + 7:8]),
577 320 igorm
   .Write     (MIIMODER_Wr[1]),
578 304 tadejm
   .Clk       (Clk),
579
   .Reset     (Reset),
580
   .SyncReset (1'b0)
581
  );
582
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH_1 + 8] = 0;
583 68 mohor
 
584 139 mohor
// MIICOMMAND Register
585
eth_register #(1, 0)                                      MIICOMMAND0
586
  (
587
   .DataIn    (DataIn[0]),
588
   .DataOut   (MIICOMMANDOut[0]),
589 320 igorm
   .Write     (MIICOMMAND_Wr[0]),
590 139 mohor
   .Clk       (Clk),
591
   .Reset     (Reset),
592 141 mohor
   .SyncReset (1'b0)
593 139 mohor
  );
594
eth_register #(1, 0)                                      MIICOMMAND1
595
  (
596
   .DataIn    (DataIn[1]),
597
   .DataOut   (MIICOMMANDOut[1]),
598 320 igorm
   .Write     (MIICOMMAND_Wr[0]),
599 139 mohor
   .Clk       (Clk),
600
   .Reset     (Reset),
601
   .SyncReset (RStatStart)
602
  );
603
eth_register #(1, 0)                                      MIICOMMAND2
604
  (
605
   .DataIn    (DataIn[2]),
606
   .DataOut   (MIICOMMANDOut[2]),
607 320 igorm
   .Write     (MIICOMMAND_Wr[0]),
608 139 mohor
   .Clk       (Clk),
609
   .Reset     (Reset),
610
   .SyncReset (WCtrlDataStart)
611
  );
612 304 tadejm
assign MIICOMMANDOut[31:`ETH_MIICOMMAND_WIDTH_0] = 29'h0;
613 15 mohor
 
614 139 mohor
// MIIADDRESSRegister
615 304 tadejm
eth_register #(`ETH_MIIADDRESS_WIDTH_0, `ETH_MIIADDRESS_DEF_0) MIIADDRESS_0
616 139 mohor
  (
617 304 tadejm
   .DataIn    (DataIn[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
618
   .DataOut   (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
619 320 igorm
   .Write     (MIIADDRESS_Wr[0]),
620 139 mohor
   .Clk       (Clk),
621
   .Reset     (Reset),
622 141 mohor
   .SyncReset (1'b0)
623 139 mohor
  );
624 304 tadejm
eth_register #(`ETH_MIIADDRESS_WIDTH_1, `ETH_MIIADDRESS_DEF_1) MIIADDRESS_1
625 139 mohor
  (
626 304 tadejm
   .DataIn    (DataIn[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
627
   .DataOut   (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
628 320 igorm
   .Write     (MIIADDRESS_Wr[1]),
629 139 mohor
   .Clk       (Clk),
630
   .Reset     (Reset),
631 141 mohor
   .SyncReset (1'b0)
632 139 mohor
  );
633 304 tadejm
assign MIIADDRESSOut[7:`ETH_MIIADDRESS_WIDTH_0] = 0;
634
assign MIIADDRESSOut[31:`ETH_MIIADDRESS_WIDTH_1 + 8] = 0;
635 15 mohor
 
636 139 mohor
// MIITX_DATA Register
637 304 tadejm
eth_register #(`ETH_MIITX_DATA_WIDTH_0, `ETH_MIITX_DATA_DEF_0) MIITX_DATA_0
638 139 mohor
  (
639 304 tadejm
   .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
640
   .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
641 320 igorm
   .Write     (MIITX_DATA_Wr[0]),
642 139 mohor
   .Clk       (Clk),
643
   .Reset     (Reset),
644 141 mohor
   .SyncReset (1'b0)
645 139 mohor
  );
646 304 tadejm
eth_register #(`ETH_MIITX_DATA_WIDTH_1, `ETH_MIITX_DATA_DEF_1) MIITX_DATA_1
647
  (
648
   .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
649
   .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
650 320 igorm
   .Write     (MIITX_DATA_Wr[1]),
651 304 tadejm
   .Clk       (Clk),
652
   .Reset     (Reset),
653
   .SyncReset (1'b0)
654
  );
655
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH_1 + 8] = 0;
656 15 mohor
 
657 139 mohor
// MIIRX_DATA Register
658
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
659
  (
660
   .DataIn    (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
661
   .DataOut   (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
662 304 tadejm
   .Write     (MIIRX_DATA_Wr), // not written from WB
663 139 mohor
   .Clk       (Clk),
664
   .Reset     (Reset),
665 141 mohor
   .SyncReset (1'b0)
666 139 mohor
  );
667
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
668 15 mohor
 
669 139 mohor
// MAC_ADDR0 Register
670 304 tadejm
eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0)  MAC_ADDR0_0
671 139 mohor
  (
672 304 tadejm
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
673
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
674 320 igorm
   .Write     (MAC_ADDR0_Wr[0]),
675 139 mohor
   .Clk       (Clk),
676
   .Reset     (Reset),
677 141 mohor
   .SyncReset (1'b0)
678 139 mohor
  );
679 304 tadejm
eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1)  MAC_ADDR0_1
680
  (
681
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
682
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
683 320 igorm
   .Write     (MAC_ADDR0_Wr[1]),
684 304 tadejm
   .Clk       (Clk),
685
   .Reset     (Reset),
686
   .SyncReset (1'b0)
687
  );
688
eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2)  MAC_ADDR0_2
689
  (
690
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
691
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
692 320 igorm
   .Write     (MAC_ADDR0_Wr[2]),
693 304 tadejm
   .Clk       (Clk),
694
   .Reset     (Reset),
695
   .SyncReset (1'b0)
696
  );
697
eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3)  MAC_ADDR0_3
698
  (
699
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
700
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
701 320 igorm
   .Write     (MAC_ADDR0_Wr[3]),
702 304 tadejm
   .Clk       (Clk),
703
   .Reset     (Reset),
704
   .SyncReset (1'b0)
705
  );
706 68 mohor
 
707 139 mohor
// MAC_ADDR1 Register
708 304 tadejm
eth_register #(`ETH_MAC_ADDR1_WIDTH_0, `ETH_MAC_ADDR1_DEF_0)  MAC_ADDR1_0
709 139 mohor
  (
710 304 tadejm
   .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
711
   .DataOut   (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
712 320 igorm
   .Write     (MAC_ADDR1_Wr[0]),
713 139 mohor
   .Clk       (Clk),
714
   .Reset     (Reset),
715 141 mohor
   .SyncReset (1'b0)
716 139 mohor
  );
717 304 tadejm
eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1)  MAC_ADDR1_1
718
  (
719
   .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
720
   .DataOut   (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
721 320 igorm
   .Write     (MAC_ADDR1_Wr[1]),
722 304 tadejm
   .Clk       (Clk),
723
   .Reset     (Reset),
724
   .SyncReset (1'b0)
725
  );
726
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0;
727 68 mohor
 
728 139 mohor
// RXHASH0 Register
729 304 tadejm
eth_register #(`ETH_HASH0_WIDTH_0, `ETH_HASH0_DEF_0)          RXHASH0_0
730 139 mohor
  (
731 304 tadejm
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_0 - 1:0]),
732
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_0 - 1:0]),
733 320 igorm
   .Write     (HASH0_Wr[0]),
734 139 mohor
   .Clk       (Clk),
735
   .Reset     (Reset),
736 141 mohor
   .SyncReset (1'b0)
737 139 mohor
  );
738 304 tadejm
eth_register #(`ETH_HASH0_WIDTH_1, `ETH_HASH0_DEF_1)          RXHASH0_1
739
  (
740
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_1 + 7:8]),
741
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_1 + 7:8]),
742 320 igorm
   .Write     (HASH0_Wr[1]),
743 304 tadejm
   .Clk       (Clk),
744
   .Reset     (Reset),
745
   .SyncReset (1'b0)
746
  );
747
eth_register #(`ETH_HASH0_WIDTH_2, `ETH_HASH0_DEF_2)          RXHASH0_2
748
  (
749
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_2 + 15:16]),
750
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_2 + 15:16]),
751 320 igorm
   .Write     (HASH0_Wr[2]),
752 304 tadejm
   .Clk       (Clk),
753
   .Reset     (Reset),
754
   .SyncReset (1'b0)
755
  );
756
eth_register #(`ETH_HASH0_WIDTH_3, `ETH_HASH0_DEF_3)          RXHASH0_3
757
  (
758
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_3 + 23:24]),
759
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_3 + 23:24]),
760 320 igorm
   .Write     (HASH0_Wr[3]),
761 304 tadejm
   .Clk       (Clk),
762
   .Reset     (Reset),
763
   .SyncReset (1'b0)
764
  );
765 68 mohor
 
766 139 mohor
// RXHASH1 Register
767 304 tadejm
eth_register #(`ETH_HASH1_WIDTH_0, `ETH_HASH1_DEF_0)          RXHASH1_0
768 139 mohor
  (
769 304 tadejm
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_0 - 1:0]),
770
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_0 - 1:0]),
771 320 igorm
   .Write     (HASH1_Wr[0]),
772 139 mohor
   .Clk       (Clk),
773
   .Reset     (Reset),
774 141 mohor
   .SyncReset (1'b0)
775 139 mohor
  );
776 304 tadejm
eth_register #(`ETH_HASH1_WIDTH_1, `ETH_HASH1_DEF_1)          RXHASH1_1
777
  (
778
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_1 + 7:8]),
779
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_1 + 7:8]),
780 320 igorm
   .Write     (HASH1_Wr[1]),
781 304 tadejm
   .Clk       (Clk),
782
   .Reset     (Reset),
783
   .SyncReset (1'b0)
784
  );
785
eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2)          RXHASH1_2
786
  (
787
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_2 + 15:16]),
788
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]),
789 320 igorm
   .Write     (HASH1_Wr[2]),
790 304 tadejm
   .Clk       (Clk),
791
   .Reset     (Reset),
792
   .SyncReset (1'b0)
793
  );
794
eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3)          RXHASH1_3
795
  (
796
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_3 + 23:24]),
797
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]),
798 320 igorm
   .Write     (HASH1_Wr[3]),
799 304 tadejm
   .Clk       (Clk),
800
   .Reset     (Reset),
801
   .SyncReset (1'b0)
802
  );
803 68 mohor
 
804 147 mohor
// TXCTRL Register
805 304 tadejm
eth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0)  TXCTRL_0
806 147 mohor
  (
807 304 tadejm
   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
808
   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
809 320 igorm
   .Write     (TXCTRL_Wr[0]),
810 147 mohor
   .Clk       (Clk),
811
   .Reset     (Reset),
812
   .SyncReset (1'b0)
813
  );
814 304 tadejm
eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1)  TXCTRL_1
815 147 mohor
  (
816 304 tadejm
   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
817
   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
818 320 igorm
   .Write     (TXCTRL_Wr[1]),
819 147 mohor
   .Clk       (Clk),
820
   .Reset     (Reset),
821 304 tadejm
   .SyncReset (1'b0)
822
  );
823
eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2)  TXCTRL_2 // Request bit is synchronously reset
824
  (
825
   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
826
   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
827 320 igorm
   .Write     (TXCTRL_Wr[2]),
828 304 tadejm
   .Clk       (Clk),
829
   .Reset     (Reset),
830 147 mohor
   .SyncReset (RstTxPauseRq)
831
  );
832 304 tadejm
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;
833 147 mohor
 
834
// RXCTRL Register
835 304 tadejm
eth_register #(`ETH_RX_CTRL_WIDTH_0, `ETH_RX_CTRL_DEF_0)      RXCTRL_0
836 147 mohor
  (
837 304 tadejm
   .DataIn    (DataIn[`ETH_RX_CTRL_WIDTH_0 - 1:0]),
838
   .DataOut   (RXCTRLOut[`ETH_RX_CTRL_WIDTH_0 - 1:0]),
839 320 igorm
   .Write     (RXCTRL_Wr[0]),
840 147 mohor
   .Clk       (Clk),
841
   .Reset     (Reset),
842
   .SyncReset (1'b0)
843
  );
844 304 tadejm
eth_register #(`ETH_RX_CTRL_WIDTH_1, `ETH_RX_CTRL_DEF_1)      RXCTRL_1
845
  (
846
   .DataIn    (DataIn[`ETH_RX_CTRL_WIDTH_1 + 7:8]),
847
   .DataOut   (RXCTRLOut[`ETH_RX_CTRL_WIDTH_1 + 7:8]),
848 320 igorm
   .Write     (RXCTRL_Wr[1]),
849 304 tadejm
   .Clk       (Clk),
850
   .Reset     (Reset),
851
   .SyncReset (1'b0)
852
  );
853
assign RXCTRLOut[31:`ETH_RX_CTRL_WIDTH_1 + 8] = 0;
854 147 mohor
 
855
 
856 139 mohor
// Reading data from registers
857
always @ (Address       or Read           or MODEROut       or INT_SOURCEOut  or
858
          INT_MASKOut   or IPGTOut        or IPGR1Out       or IPGR2Out       or
859
          PACKETLENOut  or COLLCONFOut    or CTRLMODEROut   or MIIMODEROut    or
860
          MIICOMMANDOut or MIIADDRESSOut  or MIITX_DATAOut  or MIIRX_DATAOut  or
861
          MIISTATUSOut  or MAC_ADDR0Out   or MAC_ADDR1Out   or TX_BD_NUMOut   or
862 147 mohor
          HASH0Out      or HASH1Out       or TXCTRLOut      or RXCTRLOut
863 139 mohor
         )
864 15 mohor
begin
865
  if(Read)  // read
866
    begin
867
      case(Address)
868 20 mohor
        `ETH_MODER_ADR        :  DataOut<=MODEROut;
869
        `ETH_INT_SOURCE_ADR   :  DataOut<=INT_SOURCEOut;
870
        `ETH_INT_MASK_ADR     :  DataOut<=INT_MASKOut;
871
        `ETH_IPGT_ADR         :  DataOut<=IPGTOut;
872
        `ETH_IPGR1_ADR        :  DataOut<=IPGR1Out;
873
        `ETH_IPGR2_ADR        :  DataOut<=IPGR2Out;
874
        `ETH_PACKETLEN_ADR    :  DataOut<=PACKETLENOut;
875
        `ETH_COLLCONF_ADR     :  DataOut<=COLLCONFOut;
876
        `ETH_CTRLMODER_ADR    :  DataOut<=CTRLMODEROut;
877
        `ETH_MIIMODER_ADR     :  DataOut<=MIIMODEROut;
878
        `ETH_MIICOMMAND_ADR   :  DataOut<=MIICOMMANDOut;
879
        `ETH_MIIADDRESS_ADR   :  DataOut<=MIIADDRESSOut;
880
        `ETH_MIITX_DATA_ADR   :  DataOut<=MIITX_DATAOut;
881
        `ETH_MIIRX_DATA_ADR   :  DataOut<=MIIRX_DATAOut;
882
        `ETH_MIISTATUS_ADR    :  DataOut<=MIISTATUSOut;
883
        `ETH_MAC_ADDR0_ADR    :  DataOut<=MAC_ADDR0Out;
884
        `ETH_MAC_ADDR1_ADR    :  DataOut<=MAC_ADDR1Out;
885 34 mohor
        `ETH_TX_BD_NUM_ADR    :  DataOut<=TX_BD_NUMOut;
886 56 mohor
        `ETH_HASH0_ADR        :  DataOut<=HASH0Out;
887
        `ETH_HASH1_ADR        :  DataOut<=HASH1Out;
888 147 mohor
        `ETH_TX_CTRL_ADR      :  DataOut<=TXCTRLOut;
889
        `ETH_RX_CTRL_ADR      :  DataOut<=RXCTRLOut;
890
 
891 15 mohor
        default:             DataOut<=32'h0;
892
      endcase
893
    end
894
  else
895
    DataOut<=32'h0;
896
end
897
 
898
 
899
assign r_RecSmall         = MODEROut[16];
900
assign r_Pad              = MODEROut[15];
901
assign r_HugEn            = MODEROut[14];
902
assign r_CrcEn            = MODEROut[13];
903
assign r_DlyCrcEn         = MODEROut[12];
904 244 mohor
// assign r_Rst           = MODEROut[11];   This signal is not used any more
905 15 mohor
assign r_FullD            = MODEROut[10];
906
assign r_ExDfrEn          = MODEROut[9];
907
assign r_NoBckof          = MODEROut[8];
908
assign r_LoopBck          = MODEROut[7];
909
assign r_IFG              = MODEROut[6];
910
assign r_Pro              = MODEROut[5];
911
assign r_Iam              = MODEROut[4];
912
assign r_Bro              = MODEROut[3];
913
assign r_NoPre            = MODEROut[2];
914 143 mohor
assign r_TxEn             = MODEROut[1] & (TX_BD_NUMOut>0);     // Transmission is enabled when there is at least one TxBD.
915
assign r_RxEn             = MODEROut[0] & (TX_BD_NUMOut<'h80);  // Reception is enabled when there is  at least one RxBD.
916 15 mohor
 
917
assign r_IPGT[6:0]        = IPGTOut[6:0];
918
 
919
assign r_IPGR1[6:0]       = IPGR1Out[6:0];
920
 
921
assign r_IPGR2[6:0]       = IPGR2Out[6:0];
922
 
923
assign r_MinFL[15:0]      = PACKETLENOut[31:16];
924
assign r_MaxFL[15:0]      = PACKETLENOut[15:0];
925
 
926 56 mohor
assign r_MaxRet[3:0]      = COLLCONFOut[19:16];
927
assign r_CollValid[5:0]   = COLLCONFOut[5:0];
928 15 mohor
 
929
assign r_TxFlow           = CTRLMODEROut[2];
930
assign r_RxFlow           = CTRLMODEROut[1];
931
assign r_PassAll          = CTRLMODEROut[0];
932
 
933
assign r_MiiNoPre         = MIIMODEROut[8];
934
assign r_ClkDiv[7:0]      = MIIMODEROut[7:0];
935
 
936
assign r_WCtrlData        = MIICOMMANDOut[2];
937
assign r_RStat            = MIICOMMANDOut[1];
938
assign r_ScanStat         = MIICOMMANDOut[0];
939
 
940
assign r_RGAD[4:0]        = MIIADDRESSOut[12:8];
941
assign r_FIAD[4:0]        = MIIADDRESSOut[4:0];
942
 
943
assign r_CtrlData[15:0]   = MIITX_DATAOut[15:0];
944
 
945 139 mohor
assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
946
assign MIISTATUSOut[2]    = NValid_stat         ;
947
assign MIISTATUSOut[1]    = Busy_stat           ;
948
assign MIISTATUSOut[0]    = LinkFail            ;
949 15 mohor
 
950
assign r_MAC[31:0]        = MAC_ADDR0Out[31:0];
951
assign r_MAC[47:32]       = MAC_ADDR1Out[15:0];
952 52 billditt
assign r_HASH1[31:0]      = HASH1Out;
953
assign r_HASH0[31:0]      = HASH0Out;
954 15 mohor
 
955 147 mohor
assign r_TxBDNum[7:0]     = TX_BD_NUMOut[7:0];
956 15 mohor
 
957 147 mohor
assign r_TxPauseTV[15:0]  = TXCTRLOut[15:0];
958
assign r_TxPauseRq        = TXCTRLOut[16];
959 15 mohor
 
960 147 mohor
 
961
// Synchronizing TxC Interrupt
962
always @ (posedge TxClk or posedge Reset)
963
begin
964
  if(Reset)
965
    SetTxCIrq_txclk <=#Tp 1'b0;
966
  else
967
  if(TxCtrlEndFrm & StartTxDone & r_TxFlow)
968
    SetTxCIrq_txclk <=#Tp 1'b1;
969
  else
970
  if(ResetTxCIrq_sync2)
971
    SetTxCIrq_txclk <=#Tp 1'b0;
972
end
973
 
974
 
975
always @ (posedge Clk or posedge Reset)
976
begin
977
  if(Reset)
978
    SetTxCIrq_sync1 <=#Tp 1'b0;
979
  else
980
    SetTxCIrq_sync1 <=#Tp SetTxCIrq_txclk;
981
end
982
 
983
always @ (posedge Clk or posedge Reset)
984
begin
985
  if(Reset)
986
    SetTxCIrq_sync2 <=#Tp 1'b0;
987
  else
988
    SetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
989
end
990
 
991
always @ (posedge Clk or posedge Reset)
992
begin
993
  if(Reset)
994
    SetTxCIrq_sync3 <=#Tp 1'b0;
995
  else
996
    SetTxCIrq_sync3 <=#Tp SetTxCIrq_sync2;
997
end
998
 
999
always @ (posedge Clk or posedge Reset)
1000
begin
1001
  if(Reset)
1002
    SetTxCIrq <=#Tp 1'b0;
1003
  else
1004
    SetTxCIrq <=#Tp SetTxCIrq_sync2 & ~SetTxCIrq_sync3;
1005
end
1006
 
1007
always @ (posedge TxClk or posedge Reset)
1008
begin
1009
  if(Reset)
1010
    ResetTxCIrq_sync1 <=#Tp 1'b0;
1011
  else
1012
    ResetTxCIrq_sync1 <=#Tp SetTxCIrq_sync2;
1013
end
1014
 
1015
always @ (posedge TxClk or posedge Reset)
1016
begin
1017
  if(Reset)
1018
    ResetTxCIrq_sync2 <=#Tp 1'b0;
1019
  else
1020
    ResetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
1021
end
1022
 
1023
 
1024
// Synchronizing RxC Interrupt
1025
always @ (posedge RxClk or posedge Reset)
1026
begin
1027
  if(Reset)
1028
    SetRxCIrq_rxclk <=#Tp 1'b0;
1029
  else
1030 261 mohor
  if(SetPauseTimer & r_RxFlow)
1031 147 mohor
    SetRxCIrq_rxclk <=#Tp 1'b1;
1032
  else
1033 261 mohor
  if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
1034 147 mohor
    SetRxCIrq_rxclk <=#Tp 1'b0;
1035
end
1036
 
1037
 
1038
always @ (posedge Clk or posedge Reset)
1039
begin
1040
  if(Reset)
1041
    SetRxCIrq_sync1 <=#Tp 1'b0;
1042
  else
1043
    SetRxCIrq_sync1 <=#Tp SetRxCIrq_rxclk;
1044
end
1045
 
1046
always @ (posedge Clk or posedge Reset)
1047
begin
1048
  if(Reset)
1049
    SetRxCIrq_sync2 <=#Tp 1'b0;
1050
  else
1051
    SetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1;
1052
end
1053
 
1054
always @ (posedge Clk or posedge Reset)
1055
begin
1056
  if(Reset)
1057
    SetRxCIrq_sync3 <=#Tp 1'b0;
1058
  else
1059
    SetRxCIrq_sync3 <=#Tp SetRxCIrq_sync2;
1060
end
1061
 
1062
always @ (posedge Clk or posedge Reset)
1063
begin
1064
  if(Reset)
1065
    SetRxCIrq <=#Tp 1'b0;
1066
  else
1067
    SetRxCIrq <=#Tp SetRxCIrq_sync2 & ~SetRxCIrq_sync3;
1068
end
1069
 
1070
always @ (posedge RxClk or posedge Reset)
1071
begin
1072
  if(Reset)
1073
    ResetRxCIrq_sync1 <=#Tp 1'b0;
1074
  else
1075
    ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2;
1076
end
1077
 
1078 261 mohor
always @ (posedge RxClk or posedge Reset)
1079 147 mohor
begin
1080
  if(Reset)
1081
    ResetRxCIrq_sync2 <=#Tp 1'b0;
1082
  else
1083 261 mohor
    ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1;
1084 147 mohor
end
1085
 
1086 261 mohor
always @ (posedge RxClk or posedge Reset)
1087
begin
1088
  if(Reset)
1089
    ResetRxCIrq_sync3 <=#Tp 1'b0;
1090
  else
1091
    ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2;
1092
end
1093 147 mohor
 
1094
 
1095
 
1096 21 mohor
// Interrupt generation
1097
always @ (posedge Clk or posedge Reset)
1098
begin
1099
  if(Reset)
1100
    irq_txb <= 1'b0;
1101
  else
1102 102 mohor
  if(TxB_IRQ)
1103 21 mohor
    irq_txb <= #Tp 1'b1;
1104
  else
1105 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[0])
1106 21 mohor
    irq_txb <= #Tp 1'b0;
1107
end
1108
 
1109
always @ (posedge Clk or posedge Reset)
1110
begin
1111
  if(Reset)
1112
    irq_txe <= 1'b0;
1113
  else
1114 102 mohor
  if(TxE_IRQ)
1115 21 mohor
    irq_txe <= #Tp 1'b1;
1116
  else
1117 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[1])
1118 21 mohor
    irq_txe <= #Tp 1'b0;
1119
end
1120
 
1121
always @ (posedge Clk or posedge Reset)
1122
begin
1123
  if(Reset)
1124
    irq_rxb <= 1'b0;
1125
  else
1126 102 mohor
  if(RxB_IRQ)
1127 21 mohor
    irq_rxb <= #Tp 1'b1;
1128
  else
1129 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[2])
1130 21 mohor
    irq_rxb <= #Tp 1'b0;
1131
end
1132
 
1133
always @ (posedge Clk or posedge Reset)
1134
begin
1135
  if(Reset)
1136 74 mohor
    irq_rxe <= 1'b0;
1137 21 mohor
  else
1138 102 mohor
  if(RxE_IRQ)
1139 74 mohor
    irq_rxe <= #Tp 1'b1;
1140 21 mohor
  else
1141 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[3])
1142 74 mohor
    irq_rxe <= #Tp 1'b0;
1143 21 mohor
end
1144
 
1145
always @ (posedge Clk or posedge Reset)
1146
begin
1147
  if(Reset)
1148
    irq_busy <= 1'b0;
1149
  else
1150 102 mohor
  if(Busy_IRQ)
1151 21 mohor
    irq_busy <= #Tp 1'b1;
1152
  else
1153 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[4])
1154 21 mohor
    irq_busy <= #Tp 1'b0;
1155
end
1156
 
1157 74 mohor
always @ (posedge Clk or posedge Reset)
1158
begin
1159
  if(Reset)
1160
    irq_txc <= 1'b0;
1161
  else
1162 147 mohor
  if(SetTxCIrq)
1163 74 mohor
    irq_txc <= #Tp 1'b1;
1164
  else
1165 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[5])
1166 74 mohor
    irq_txc <= #Tp 1'b0;
1167
end
1168
 
1169
always @ (posedge Clk or posedge Reset)
1170
begin
1171
  if(Reset)
1172
    irq_rxc <= 1'b0;
1173
  else
1174 147 mohor
  if(SetRxCIrq)
1175 74 mohor
    irq_rxc <= #Tp 1'b1;
1176
  else
1177 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[6])
1178 74 mohor
    irq_rxc <= #Tp 1'b0;
1179
end
1180
 
1181 21 mohor
// Generating interrupt signal
1182 102 mohor
assign int_o = irq_txb  & INT_MASKOut[0] |
1183
               irq_txe  & INT_MASKOut[1] |
1184
               irq_rxb  & INT_MASKOut[2] |
1185
               irq_rxe  & INT_MASKOut[3] |
1186
               irq_busy & INT_MASKOut[4] |
1187
               irq_txc  & INT_MASKOut[5] |
1188
               irq_rxc  & INT_MASKOut[6] ;
1189 21 mohor
 
1190
// For reading interrupt status
1191 304 tadejm
assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH_0){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
1192 21 mohor
 
1193
 
1194
 
1195 15 mohor
endmodule

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