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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Blame information for rev 346

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1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_registers.v                                             ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 346 olof
////  http://www.opencores.org/project,ethmac                     ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 147 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 15 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 333 igorm
// Revision 1.28  2004/04/26 15:26:23  igorm
45
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
46
//   previous update of the core.
47
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
48
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
49
//   register. (thanks to Mathias and Torbjorn)
50
// - Multicast reception was fixed. Thanks to Ulrich Gries
51
//
52 321 igorm
// Revision 1.27  2004/04/26 11:42:17  igorm
53
// TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.
54
//
55 320 igorm
// Revision 1.26  2003/11/12 18:24:59  tadejm
56
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
57
//
58 304 tadejm
// Revision 1.25  2003/04/18 16:26:25  mohor
59
// RxBDAddress was updated also when value to r_TxBDNum was written with
60
// greater value than allowed.
61
//
62 283 mohor
// Revision 1.24  2002/11/22 01:57:06  mohor
63
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
64
// synchronized.
65
//
66 261 mohor
// Revision 1.23  2002/11/19 18:13:49  mohor
67
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
68
//
69 253 mohor
// Revision 1.22  2002/11/14 18:37:20  mohor
70
// r_Rst signal does not reset any module any more and is removed from the design.
71
//
72 244 mohor
// Revision 1.21  2002/09/10 10:35:23  mohor
73
// Ethernet debug registers removed.
74
//
75 164 mohor
// Revision 1.20  2002/09/04 18:40:25  mohor
76
// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
77
// the control frames connected.
78
//
79 147 mohor
// Revision 1.19  2002/08/19 16:01:40  mohor
80
// Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
81
// r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
82
//
83 143 mohor
// Revision 1.18  2002/08/16 22:28:23  mohor
84
// Syntax error fixed.
85
//
86 141 mohor
// Revision 1.17  2002/08/16 22:23:03  mohor
87
// Syntax error fixed.
88
//
89 140 mohor
// Revision 1.16  2002/08/16 22:14:22  mohor
90
// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
91
// changed from bit position 10 to 9.
92
//
93 139 mohor
// Revision 1.15  2002/08/14 18:26:37  mohor
94
// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
95
//
96 132 mohor
// Revision 1.14  2002/04/22 14:03:44  mohor
97
// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
98
// or not.
99
//
100 102 mohor
// Revision 1.13  2002/02/26 16:18:09  mohor
101
// Reset values are passed to registers through parameters
102
//
103 74 mohor
// Revision 1.12  2002/02/17 13:23:42  mohor
104
// Define missmatch fixed.
105
//
106 69 mohor
// Revision 1.11  2002/02/16 14:03:44  mohor
107
// Registered trimmed. Unused registers removed.
108
//
109 68 mohor
// Revision 1.10  2002/02/15 11:08:25  mohor
110
// File format fixed a bit.
111
//
112 56 mohor
// Revision 1.9  2002/02/14 20:19:41  billditt
113
// Modified for Address Checking,
114
// addition of eth_addrcheck.v
115
//
116
// Revision 1.8  2002/02/12 17:01:19  mohor
117
// HASH0 and HASH1 registers added. 
118
 
119 46 mohor
// Revision 1.7  2002/01/23 10:28:16  mohor
120
// Link in the header changed.
121
//
122 37 mohor
// Revision 1.6  2001/12/05 15:00:16  mohor
123
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
124
// instead of the number of RX descriptors).
125
//
126 34 mohor
// Revision 1.5  2001/12/05 10:22:19  mohor
127
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
128
//
129 32 mohor
// Revision 1.4  2001/10/19 08:43:51  mohor
130
// eth_timescale.v changed to timescale.v This is done because of the
131
// simulation of the few cores in a one joined project.
132
//
133 22 mohor
// Revision 1.3  2001/10/18 12:07:11  mohor
134
// Status signals changed, Adress decoding changed, interrupt controller
135
// added.
136
//
137 21 mohor
// Revision 1.2  2001/09/24 15:02:56  mohor
138
// Defines changed (All precede with ETH_). Small changes because some
139
// tools generate warnings when two operands are together. Synchronization
140
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
141
// demands).
142
//
143 20 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
144
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
145
// Include files fixed to contain no path.
146
// File names and module names changed ta have a eth_ prologue in the name.
147
// File eth_timescale.v is used to define timescale
148
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
149
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
150
// and Mdo_OE. The bidirectional signal must be created on the top level. This
151
// is done due to the ASIC tools.
152
//
153 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
154
// Unconnected signals are now connected.
155
//
156
// Revision 1.1  2001/07/30 21:23:42  mohor
157
// Directory structure changed. Files checked and joind together.
158
//
159
//
160
//
161
//
162
//
163
//
164
 
165
`include "eth_defines.v"
166 22 mohor
`include "timescale.v"
167 15 mohor
 
168
 
169 68 mohor
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
170 15 mohor
                      r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
171 244 mohor
                      r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
172 21 mohor
                      r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
173 147 mohor
                      TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
174 21 mohor
                      r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
175 15 mohor
                      r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
176 253 mohor
                      r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
177 15 mohor
                      r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
178
                      LinkFail, r_MAC, WCtrlDataStart, RStatStart,
179 321 igorm
                      UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o,
180 147 mohor
                      r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
181 261 mohor
                      StartTxDone, TxClk, RxClk, SetPauseTimer
182 15 mohor
                    );
183
 
184
parameter Tp = 1;
185
 
186
input [31:0] DataIn;
187 46 mohor
input [7:0] Address;
188 15 mohor
 
189
input Rw;
190 304 tadejm
input [3:0] Cs;
191 15 mohor
input Clk;
192
input Reset;
193
 
194
input WCtrlDataStart;
195
input RStatStart;
196
 
197
input UpdateMIIRX_DATAReg;
198
input [15:0] Prsd;
199
 
200
output [31:0] DataOut;
201
reg    [31:0] DataOut;
202
 
203
output r_RecSmall;
204
output r_Pad;
205
output r_HugEn;
206
output r_CrcEn;
207
output r_DlyCrcEn;
208
output r_FullD;
209
output r_ExDfrEn;
210
output r_NoBckof;
211
output r_LoopBck;
212
output r_IFG;
213
output r_Pro;
214
output r_Iam;
215
output r_Bro;
216
output r_NoPre;
217
output r_TxEn;
218
output r_RxEn;
219 52 billditt
output [31:0] r_HASH0;
220
output [31:0] r_HASH1;
221 15 mohor
 
222 21 mohor
input TxB_IRQ;
223
input TxE_IRQ;
224
input RxB_IRQ;
225 74 mohor
input RxE_IRQ;
226 21 mohor
input Busy_IRQ;
227 15 mohor
 
228
output [6:0] r_IPGT;
229
 
230
output [6:0] r_IPGR1;
231
 
232
output [6:0] r_IPGR2;
233
 
234
output [15:0] r_MinFL;
235
output [15:0] r_MaxFL;
236
 
237
output [3:0] r_MaxRet;
238
output [5:0] r_CollValid;
239
 
240
output r_TxFlow;
241
output r_RxFlow;
242
output r_PassAll;
243
 
244
output r_MiiNoPre;
245
output [7:0] r_ClkDiv;
246
 
247
output r_WCtrlData;
248
output r_RStat;
249
output r_ScanStat;
250
 
251
output [4:0] r_RGAD;
252
output [4:0] r_FIAD;
253
 
254 21 mohor
output [15:0]r_CtrlData;
255 15 mohor
 
256
 
257
input NValid_stat;
258
input Busy_stat;
259
input LinkFail;
260
 
261 21 mohor
output [47:0]r_MAC;
262 34 mohor
output [7:0] r_TxBDNum;
263 21 mohor
output       int_o;
264 147 mohor
output [15:0]r_TxPauseTV;
265
output       r_TxPauseRq;
266
input        RstTxPauseRq;
267
input        TxCtrlEndFrm;
268
input        StartTxDone;
269
input        TxClk;
270
input        RxClk;
271 261 mohor
input        SetPauseTimer;
272 15 mohor
 
273 21 mohor
reg          irq_txb;
274
reg          irq_txe;
275
reg          irq_rxb;
276 74 mohor
reg          irq_rxe;
277 21 mohor
reg          irq_busy;
278 74 mohor
reg          irq_txc;
279
reg          irq_rxc;
280 15 mohor
 
281 147 mohor
reg SetTxCIrq_txclk;
282
reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3;
283
reg SetTxCIrq;
284
reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
285
 
286
reg SetRxCIrq_rxclk;
287
reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
288
reg SetRxCIrq;
289 261 mohor
reg ResetRxCIrq_sync1;
290
reg ResetRxCIrq_sync2;
291
reg ResetRxCIrq_sync3;
292 147 mohor
 
293 304 tadejm
wire [3:0] Write =   Cs  & {4{Rw}};
294
wire       Read  = (|Cs) &   ~Rw;
295 15 mohor
 
296 320 igorm
wire MODER_Sel      = (Address == `ETH_MODER_ADR       );
297
wire INT_SOURCE_Sel = (Address == `ETH_INT_SOURCE_ADR  );
298
wire INT_MASK_Sel   = (Address == `ETH_INT_MASK_ADR    );
299
wire IPGT_Sel       = (Address == `ETH_IPGT_ADR        );
300
wire IPGR1_Sel      = (Address == `ETH_IPGR1_ADR       );
301
wire IPGR2_Sel      = (Address == `ETH_IPGR2_ADR       );
302
wire PACKETLEN_Sel  = (Address == `ETH_PACKETLEN_ADR   );
303
wire COLLCONF_Sel   = (Address == `ETH_COLLCONF_ADR    );
304 21 mohor
 
305 320 igorm
wire CTRLMODER_Sel  = (Address == `ETH_CTRLMODER_ADR   );
306
wire MIIMODER_Sel   = (Address == `ETH_MIIMODER_ADR    );
307
wire MIICOMMAND_Sel = (Address == `ETH_MIICOMMAND_ADR  );
308
wire MIIADDRESS_Sel = (Address == `ETH_MIIADDRESS_ADR  );
309
wire MIITX_DATA_Sel = (Address == `ETH_MIITX_DATA_ADR  );
310
wire MAC_ADDR0_Sel  = (Address == `ETH_MAC_ADDR0_ADR   );
311
wire MAC_ADDR1_Sel  = (Address == `ETH_MAC_ADDR1_ADR   );
312
wire HASH0_Sel      = (Address == `ETH_HASH0_ADR       );
313
wire HASH1_Sel      = (Address == `ETH_HASH1_ADR       );
314
wire TXCTRL_Sel     = (Address == `ETH_TX_CTRL_ADR     );
315
wire RXCTRL_Sel     = (Address == `ETH_RX_CTRL_ADR     );
316
wire TX_BD_NUM_Sel  = (Address == `ETH_TX_BD_NUM_ADR   );
317 15 mohor
 
318
 
319 320 igorm
wire [2:0] MODER_Wr;
320
wire [0:0] INT_SOURCE_Wr;
321
wire [0:0] INT_MASK_Wr;
322
wire [0:0] IPGT_Wr;
323
wire [0:0] IPGR1_Wr;
324
wire [0:0] IPGR2_Wr;
325
wire [3:0] PACKETLEN_Wr;
326
wire [2:0] COLLCONF_Wr;
327
wire [0:0] CTRLMODER_Wr;
328
wire [1:0] MIIMODER_Wr;
329
wire [0:0] MIICOMMAND_Wr;
330
wire [1:0] MIIADDRESS_Wr;
331
wire [1:0] MIITX_DATA_Wr;
332
wire       MIIRX_DATA_Wr;
333
wire [3:0] MAC_ADDR0_Wr;
334
wire [1:0] MAC_ADDR1_Wr;
335
wire [3:0] HASH0_Wr;
336
wire [3:0] HASH1_Wr;
337
wire [2:0] TXCTRL_Wr;
338 321 igorm
wire [0:0] TX_BD_NUM_Wr;
339 15 mohor
 
340 320 igorm
assign MODER_Wr[0]       = Write[0]  & MODER_Sel;
341
assign MODER_Wr[1]       = Write[1]  & MODER_Sel;
342
assign MODER_Wr[2]       = Write[2]  & MODER_Sel;
343
assign INT_SOURCE_Wr[0]  = Write[0]  & INT_SOURCE_Sel;
344
assign INT_MASK_Wr[0]    = Write[0]  & INT_MASK_Sel;
345
assign IPGT_Wr[0]        = Write[0]  & IPGT_Sel;
346
assign IPGR1_Wr[0]       = Write[0]  & IPGR1_Sel;
347
assign IPGR2_Wr[0]       = Write[0]  & IPGR2_Sel;
348
assign PACKETLEN_Wr[0]   = Write[0]  & PACKETLEN_Sel;
349
assign PACKETLEN_Wr[1]   = Write[1]  & PACKETLEN_Sel;
350
assign PACKETLEN_Wr[2]   = Write[2]  & PACKETLEN_Sel;
351
assign PACKETLEN_Wr[3]   = Write[3]  & PACKETLEN_Sel;
352
assign COLLCONF_Wr[0]    = Write[0]  & COLLCONF_Sel;
353
assign COLLCONF_Wr[1]    = 1'b0;  // Not used
354
assign COLLCONF_Wr[2]    = Write[2]  & COLLCONF_Sel;
355
 
356
assign CTRLMODER_Wr[0]   = Write[0]  & CTRLMODER_Sel;
357
assign MIIMODER_Wr[0]    = Write[0]  & MIIMODER_Sel;
358
assign MIIMODER_Wr[1]    = Write[1]  & MIIMODER_Sel;
359
assign MIICOMMAND_Wr[0]  = Write[0]  & MIICOMMAND_Sel;
360
assign MIIADDRESS_Wr[0]  = Write[0]  & MIIADDRESS_Sel;
361
assign MIIADDRESS_Wr[1]  = Write[1]  & MIIADDRESS_Sel;
362
assign MIITX_DATA_Wr[0]  = Write[0]  & MIITX_DATA_Sel;
363
assign MIITX_DATA_Wr[1]  = Write[1]  & MIITX_DATA_Sel;
364
assign MIIRX_DATA_Wr     = UpdateMIIRX_DATAReg;
365
assign MAC_ADDR0_Wr[0]   = Write[0]  & MAC_ADDR0_Sel;
366
assign MAC_ADDR0_Wr[1]   = Write[1]  & MAC_ADDR0_Sel;
367
assign MAC_ADDR0_Wr[2]   = Write[2]  & MAC_ADDR0_Sel;
368
assign MAC_ADDR0_Wr[3]   = Write[3]  & MAC_ADDR0_Sel;
369
assign MAC_ADDR1_Wr[0]   = Write[0]  & MAC_ADDR1_Sel;
370
assign MAC_ADDR1_Wr[1]   = Write[1]  & MAC_ADDR1_Sel;
371
assign HASH0_Wr[0]       = Write[0]  & HASH0_Sel;
372
assign HASH0_Wr[1]       = Write[1]  & HASH0_Sel;
373
assign HASH0_Wr[2]       = Write[2]  & HASH0_Sel;
374
assign HASH0_Wr[3]       = Write[3]  & HASH0_Sel;
375
assign HASH1_Wr[0]       = Write[0]  & HASH1_Sel;
376
assign HASH1_Wr[1]       = Write[1]  & HASH1_Sel;
377
assign HASH1_Wr[2]       = Write[2]  & HASH1_Sel;
378
assign HASH1_Wr[3]       = Write[3]  & HASH1_Sel;
379
assign TXCTRL_Wr[0]      = Write[0]  & TXCTRL_Sel;
380
assign TXCTRL_Wr[1]      = Write[1]  & TXCTRL_Sel;
381
assign TXCTRL_Wr[2]      = Write[2]  & TXCTRL_Sel;
382 321 igorm
assign TX_BD_NUM_Wr[0]   = Write[0]  & TX_BD_NUM_Sel & (DataIn<='h80);
383 320 igorm
 
384
 
385
 
386 15 mohor
wire [31:0] MODEROut;
387
wire [31:0] INT_SOURCEOut;
388
wire [31:0] INT_MASKOut;
389
wire [31:0] IPGTOut;
390
wire [31:0] IPGR1Out;
391
wire [31:0] IPGR2Out;
392
wire [31:0] PACKETLENOut;
393
wire [31:0] COLLCONFOut;
394
wire [31:0] CTRLMODEROut;
395
wire [31:0] MIIMODEROut;
396
wire [31:0] MIICOMMANDOut;
397
wire [31:0] MIIADDRESSOut;
398
wire [31:0] MIITX_DATAOut;
399
wire [31:0] MIIRX_DATAOut;
400
wire [31:0] MIISTATUSOut;
401
wire [31:0] MAC_ADDR0Out;
402
wire [31:0] MAC_ADDR1Out;
403 34 mohor
wire [31:0] TX_BD_NUMOut;
404 52 billditt
wire [31:0] HASH0Out;
405
wire [31:0] HASH1Out;
406 147 mohor
wire [31:0] TXCTRLOut;
407 15 mohor
 
408 139 mohor
// MODER Register
409 304 tadejm
eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0)        MODER_0
410 139 mohor
  (
411 304 tadejm
   .DataIn    (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
412
   .DataOut   (MODEROut[`ETH_MODER_WIDTH_0 - 1:0]),
413 320 igorm
   .Write     (MODER_Wr[0]),
414 139 mohor
   .Clk       (Clk),
415
   .Reset     (Reset),
416 141 mohor
   .SyncReset (1'b0)
417 139 mohor
  );
418 304 tadejm
eth_register #(`ETH_MODER_WIDTH_1, `ETH_MODER_DEF_1)        MODER_1
419
  (
420
   .DataIn    (DataIn[`ETH_MODER_WIDTH_1 + 7:8]),
421
   .DataOut   (MODEROut[`ETH_MODER_WIDTH_1 + 7:8]),
422 320 igorm
   .Write     (MODER_Wr[1]),
423 304 tadejm
   .Clk       (Clk),
424
   .Reset     (Reset),
425
   .SyncReset (1'b0)
426
  );
427
eth_register #(`ETH_MODER_WIDTH_2, `ETH_MODER_DEF_2)        MODER_2
428
  (
429
   .DataIn    (DataIn[`ETH_MODER_WIDTH_2 + 15:16]),
430
   .DataOut   (MODEROut[`ETH_MODER_WIDTH_2 + 15:16]),
431 320 igorm
   .Write     (MODER_Wr[2]),
432 304 tadejm
   .Clk       (Clk),
433
   .Reset     (Reset),
434
   .SyncReset (1'b0)
435
  );
436
assign MODEROut[31:`ETH_MODER_WIDTH_2 + 16] = 0;
437 15 mohor
 
438 139 mohor
// INT_MASK Register
439 304 tadejm
eth_register #(`ETH_INT_MASK_WIDTH_0, `ETH_INT_MASK_DEF_0)  INT_MASK_0
440 139 mohor
  (
441 304 tadejm
   .DataIn    (DataIn[`ETH_INT_MASK_WIDTH_0 - 1:0]),
442
   .DataOut   (INT_MASKOut[`ETH_INT_MASK_WIDTH_0 - 1:0]),
443 320 igorm
   .Write     (INT_MASK_Wr[0]),
444 139 mohor
   .Clk       (Clk),
445
   .Reset     (Reset),
446 141 mohor
   .SyncReset (1'b0)
447 139 mohor
  );
448 304 tadejm
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH_0] = 0;
449 52 billditt
 
450 139 mohor
// IPGT Register
451 304 tadejm
eth_register #(`ETH_IPGT_WIDTH_0, `ETH_IPGT_DEF_0)          IPGT_0
452 139 mohor
  (
453 304 tadejm
   .DataIn    (DataIn[`ETH_IPGT_WIDTH_0 - 1:0]),
454
   .DataOut   (IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0]),
455 320 igorm
   .Write     (IPGT_Wr[0]),
456 139 mohor
   .Clk       (Clk),
457
   .Reset     (Reset),
458 141 mohor
   .SyncReset (1'b0)
459 139 mohor
  );
460 304 tadejm
assign IPGTOut[31:`ETH_IPGT_WIDTH_0] = 0;
461 52 billditt
 
462 139 mohor
// IPGR1 Register
463 304 tadejm
eth_register #(`ETH_IPGR1_WIDTH_0, `ETH_IPGR1_DEF_0)        IPGR1_0
464 139 mohor
  (
465 304 tadejm
   .DataIn    (DataIn[`ETH_IPGR1_WIDTH_0 - 1:0]),
466
   .DataOut   (IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0]),
467 320 igorm
   .Write     (IPGR1_Wr[0]),
468 139 mohor
   .Clk       (Clk),
469
   .Reset     (Reset),
470 141 mohor
   .SyncReset (1'b0)
471 139 mohor
  );
472 304 tadejm
assign IPGR1Out[31:`ETH_IPGR1_WIDTH_0] = 0;
473 15 mohor
 
474 139 mohor
// IPGR2 Register
475 304 tadejm
eth_register #(`ETH_IPGR2_WIDTH_0, `ETH_IPGR2_DEF_0)        IPGR2_0
476 139 mohor
  (
477 304 tadejm
   .DataIn    (DataIn[`ETH_IPGR2_WIDTH_0 - 1:0]),
478
   .DataOut   (IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0]),
479 320 igorm
   .Write     (IPGR2_Wr[0]),
480 139 mohor
   .Clk       (Clk),
481
   .Reset     (Reset),
482 141 mohor
   .SyncReset (1'b0)
483 139 mohor
  );
484 304 tadejm
assign IPGR2Out[31:`ETH_IPGR2_WIDTH_0] = 0;
485 15 mohor
 
486 139 mohor
// PACKETLEN Register
487 304 tadejm
eth_register #(`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0
488 139 mohor
  (
489 304 tadejm
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
490
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
491 320 igorm
   .Write     (PACKETLEN_Wr[0]),
492 139 mohor
   .Clk       (Clk),
493
   .Reset     (Reset),
494 141 mohor
   .SyncReset (1'b0)
495 139 mohor
  );
496 304 tadejm
eth_register #(`ETH_PACKETLEN_WIDTH_1, `ETH_PACKETLEN_DEF_1) PACKETLEN_1
497
  (
498
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
499
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
500 320 igorm
   .Write     (PACKETLEN_Wr[1]),
501 304 tadejm
   .Clk       (Clk),
502
   .Reset     (Reset),
503
   .SyncReset (1'b0)
504
  );
505
eth_register #(`ETH_PACKETLEN_WIDTH_2, `ETH_PACKETLEN_DEF_2) PACKETLEN_2
506
  (
507
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
508
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
509 320 igorm
   .Write     (PACKETLEN_Wr[2]),
510 304 tadejm
   .Clk       (Clk),
511
   .Reset     (Reset),
512
   .SyncReset (1'b0)
513
  );
514
eth_register #(`ETH_PACKETLEN_WIDTH_3, `ETH_PACKETLEN_DEF_3) PACKETLEN_3
515
  (
516
   .DataIn    (DataIn[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
517
   .DataOut   (PACKETLENOut[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
518 320 igorm
   .Write     (PACKETLEN_Wr[3]),
519 304 tadejm
   .Clk       (Clk),
520
   .Reset     (Reset),
521
   .SyncReset (1'b0)
522
  );
523 15 mohor
 
524 139 mohor
// COLLCONF Register
525 304 tadejm
eth_register #(`ETH_COLLCONF_WIDTH_0, `ETH_COLLCONF_DEF_0)   COLLCONF_0
526 139 mohor
  (
527 304 tadejm
   .DataIn    (DataIn[`ETH_COLLCONF_WIDTH_0 - 1:0]),
528
   .DataOut   (COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0]),
529 320 igorm
   .Write     (COLLCONF_Wr[0]),
530 139 mohor
   .Clk       (Clk),
531
   .Reset     (Reset),
532 141 mohor
   .SyncReset (1'b0)
533 139 mohor
  );
534 304 tadejm
eth_register #(`ETH_COLLCONF_WIDTH_2, `ETH_COLLCONF_DEF_2)   COLLCONF_2
535 139 mohor
  (
536 304 tadejm
   .DataIn    (DataIn[`ETH_COLLCONF_WIDTH_2 + 15:16]),
537
   .DataOut   (COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16]),
538 320 igorm
   .Write     (COLLCONF_Wr[2]),
539 139 mohor
   .Clk       (Clk),
540
   .Reset     (Reset),
541 141 mohor
   .SyncReset (1'b0)
542 139 mohor
  );
543 304 tadejm
assign COLLCONFOut[15:`ETH_COLLCONF_WIDTH_0] = 0;
544
assign COLLCONFOut[31:`ETH_COLLCONF_WIDTH_2 + 16] = 0;
545 15 mohor
 
546 139 mohor
// TX_BD_NUM Register
547 304 tadejm
eth_register #(`ETH_TX_BD_NUM_WIDTH_0, `ETH_TX_BD_NUM_DEF_0) TX_BD_NUM_0
548 139 mohor
  (
549 304 tadejm
   .DataIn    (DataIn[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
550
   .DataOut   (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
551 321 igorm
   .Write     (TX_BD_NUM_Wr[0]),
552 139 mohor
   .Clk       (Clk),
553
   .Reset     (Reset),
554 141 mohor
   .SyncReset (1'b0)
555 139 mohor
  );
556 304 tadejm
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH_0] = 0;
557 15 mohor
 
558 139 mohor
// CTRLMODER Register
559 304 tadejm
eth_register #(`ETH_CTRLMODER_WIDTH_0, `ETH_CTRLMODER_DEF_0)  CTRLMODER_0
560 139 mohor
  (
561 304 tadejm
   .DataIn    (DataIn[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
562
   .DataOut   (CTRLMODEROut[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
563 320 igorm
   .Write     (CTRLMODER_Wr[0]),
564 139 mohor
   .Clk       (Clk),
565
   .Reset     (Reset),
566 141 mohor
   .SyncReset (1'b0)
567 139 mohor
  );
568 304 tadejm
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH_0] = 0;
569 15 mohor
 
570 139 mohor
// MIIMODER Register
571 304 tadejm
eth_register #(`ETH_MIIMODER_WIDTH_0, `ETH_MIIMODER_DEF_0)    MIIMODER_0
572 139 mohor
  (
573 304 tadejm
   .DataIn    (DataIn[`ETH_MIIMODER_WIDTH_0 - 1:0]),
574
   .DataOut   (MIIMODEROut[`ETH_MIIMODER_WIDTH_0 - 1:0]),
575 320 igorm
   .Write     (MIIMODER_Wr[0]),
576 139 mohor
   .Clk       (Clk),
577
   .Reset     (Reset),
578 141 mohor
   .SyncReset (1'b0)
579 139 mohor
  );
580 304 tadejm
eth_register #(`ETH_MIIMODER_WIDTH_1, `ETH_MIIMODER_DEF_1)    MIIMODER_1
581
  (
582
   .DataIn    (DataIn[`ETH_MIIMODER_WIDTH_1 + 7:8]),
583
   .DataOut   (MIIMODEROut[`ETH_MIIMODER_WIDTH_1 + 7:8]),
584 320 igorm
   .Write     (MIIMODER_Wr[1]),
585 304 tadejm
   .Clk       (Clk),
586
   .Reset     (Reset),
587
   .SyncReset (1'b0)
588
  );
589
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH_1 + 8] = 0;
590 68 mohor
 
591 139 mohor
// MIICOMMAND Register
592
eth_register #(1, 0)                                      MIICOMMAND0
593
  (
594
   .DataIn    (DataIn[0]),
595
   .DataOut   (MIICOMMANDOut[0]),
596 320 igorm
   .Write     (MIICOMMAND_Wr[0]),
597 139 mohor
   .Clk       (Clk),
598
   .Reset     (Reset),
599 141 mohor
   .SyncReset (1'b0)
600 139 mohor
  );
601
eth_register #(1, 0)                                      MIICOMMAND1
602
  (
603
   .DataIn    (DataIn[1]),
604
   .DataOut   (MIICOMMANDOut[1]),
605 320 igorm
   .Write     (MIICOMMAND_Wr[0]),
606 139 mohor
   .Clk       (Clk),
607
   .Reset     (Reset),
608
   .SyncReset (RStatStart)
609
  );
610
eth_register #(1, 0)                                      MIICOMMAND2
611
  (
612
   .DataIn    (DataIn[2]),
613
   .DataOut   (MIICOMMANDOut[2]),
614 320 igorm
   .Write     (MIICOMMAND_Wr[0]),
615 139 mohor
   .Clk       (Clk),
616
   .Reset     (Reset),
617
   .SyncReset (WCtrlDataStart)
618
  );
619 304 tadejm
assign MIICOMMANDOut[31:`ETH_MIICOMMAND_WIDTH_0] = 29'h0;
620 15 mohor
 
621 139 mohor
// MIIADDRESSRegister
622 304 tadejm
eth_register #(`ETH_MIIADDRESS_WIDTH_0, `ETH_MIIADDRESS_DEF_0) MIIADDRESS_0
623 139 mohor
  (
624 304 tadejm
   .DataIn    (DataIn[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
625
   .DataOut   (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
626 320 igorm
   .Write     (MIIADDRESS_Wr[0]),
627 139 mohor
   .Clk       (Clk),
628
   .Reset     (Reset),
629 141 mohor
   .SyncReset (1'b0)
630 139 mohor
  );
631 304 tadejm
eth_register #(`ETH_MIIADDRESS_WIDTH_1, `ETH_MIIADDRESS_DEF_1) MIIADDRESS_1
632 139 mohor
  (
633 304 tadejm
   .DataIn    (DataIn[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
634
   .DataOut   (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
635 320 igorm
   .Write     (MIIADDRESS_Wr[1]),
636 139 mohor
   .Clk       (Clk),
637
   .Reset     (Reset),
638 141 mohor
   .SyncReset (1'b0)
639 139 mohor
  );
640 304 tadejm
assign MIIADDRESSOut[7:`ETH_MIIADDRESS_WIDTH_0] = 0;
641
assign MIIADDRESSOut[31:`ETH_MIIADDRESS_WIDTH_1 + 8] = 0;
642 15 mohor
 
643 139 mohor
// MIITX_DATA Register
644 304 tadejm
eth_register #(`ETH_MIITX_DATA_WIDTH_0, `ETH_MIITX_DATA_DEF_0) MIITX_DATA_0
645 139 mohor
  (
646 304 tadejm
   .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
647
   .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
648 320 igorm
   .Write     (MIITX_DATA_Wr[0]),
649 139 mohor
   .Clk       (Clk),
650
   .Reset     (Reset),
651 141 mohor
   .SyncReset (1'b0)
652 139 mohor
  );
653 304 tadejm
eth_register #(`ETH_MIITX_DATA_WIDTH_1, `ETH_MIITX_DATA_DEF_1) MIITX_DATA_1
654
  (
655
   .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
656
   .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
657 320 igorm
   .Write     (MIITX_DATA_Wr[1]),
658 304 tadejm
   .Clk       (Clk),
659
   .Reset     (Reset),
660
   .SyncReset (1'b0)
661
  );
662
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH_1 + 8] = 0;
663 15 mohor
 
664 139 mohor
// MIIRX_DATA Register
665
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
666
  (
667
   .DataIn    (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
668
   .DataOut   (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
669 304 tadejm
   .Write     (MIIRX_DATA_Wr), // not written from WB
670 139 mohor
   .Clk       (Clk),
671
   .Reset     (Reset),
672 141 mohor
   .SyncReset (1'b0)
673 139 mohor
  );
674
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
675 15 mohor
 
676 139 mohor
// MAC_ADDR0 Register
677 304 tadejm
eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0)  MAC_ADDR0_0
678 139 mohor
  (
679 304 tadejm
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
680
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
681 320 igorm
   .Write     (MAC_ADDR0_Wr[0]),
682 139 mohor
   .Clk       (Clk),
683
   .Reset     (Reset),
684 141 mohor
   .SyncReset (1'b0)
685 139 mohor
  );
686 304 tadejm
eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1)  MAC_ADDR0_1
687
  (
688
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
689
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
690 320 igorm
   .Write     (MAC_ADDR0_Wr[1]),
691 304 tadejm
   .Clk       (Clk),
692
   .Reset     (Reset),
693
   .SyncReset (1'b0)
694
  );
695
eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2)  MAC_ADDR0_2
696
  (
697
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
698
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
699 320 igorm
   .Write     (MAC_ADDR0_Wr[2]),
700 304 tadejm
   .Clk       (Clk),
701
   .Reset     (Reset),
702
   .SyncReset (1'b0)
703
  );
704
eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3)  MAC_ADDR0_3
705
  (
706
   .DataIn    (DataIn[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
707
   .DataOut   (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
708 320 igorm
   .Write     (MAC_ADDR0_Wr[3]),
709 304 tadejm
   .Clk       (Clk),
710
   .Reset     (Reset),
711
   .SyncReset (1'b0)
712
  );
713 68 mohor
 
714 139 mohor
// MAC_ADDR1 Register
715 304 tadejm
eth_register #(`ETH_MAC_ADDR1_WIDTH_0, `ETH_MAC_ADDR1_DEF_0)  MAC_ADDR1_0
716 139 mohor
  (
717 304 tadejm
   .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
718
   .DataOut   (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
719 320 igorm
   .Write     (MAC_ADDR1_Wr[0]),
720 139 mohor
   .Clk       (Clk),
721
   .Reset     (Reset),
722 141 mohor
   .SyncReset (1'b0)
723 139 mohor
  );
724 304 tadejm
eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1)  MAC_ADDR1_1
725
  (
726
   .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
727
   .DataOut   (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
728 320 igorm
   .Write     (MAC_ADDR1_Wr[1]),
729 304 tadejm
   .Clk       (Clk),
730
   .Reset     (Reset),
731
   .SyncReset (1'b0)
732
  );
733
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0;
734 68 mohor
 
735 139 mohor
// RXHASH0 Register
736 304 tadejm
eth_register #(`ETH_HASH0_WIDTH_0, `ETH_HASH0_DEF_0)          RXHASH0_0
737 139 mohor
  (
738 304 tadejm
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_0 - 1:0]),
739
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_0 - 1:0]),
740 320 igorm
   .Write     (HASH0_Wr[0]),
741 139 mohor
   .Clk       (Clk),
742
   .Reset     (Reset),
743 141 mohor
   .SyncReset (1'b0)
744 139 mohor
  );
745 304 tadejm
eth_register #(`ETH_HASH0_WIDTH_1, `ETH_HASH0_DEF_1)          RXHASH0_1
746
  (
747
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_1 + 7:8]),
748
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_1 + 7:8]),
749 320 igorm
   .Write     (HASH0_Wr[1]),
750 304 tadejm
   .Clk       (Clk),
751
   .Reset     (Reset),
752
   .SyncReset (1'b0)
753
  );
754
eth_register #(`ETH_HASH0_WIDTH_2, `ETH_HASH0_DEF_2)          RXHASH0_2
755
  (
756
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_2 + 15:16]),
757
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_2 + 15:16]),
758 320 igorm
   .Write     (HASH0_Wr[2]),
759 304 tadejm
   .Clk       (Clk),
760
   .Reset     (Reset),
761
   .SyncReset (1'b0)
762
  );
763
eth_register #(`ETH_HASH0_WIDTH_3, `ETH_HASH0_DEF_3)          RXHASH0_3
764
  (
765
   .DataIn    (DataIn[`ETH_HASH0_WIDTH_3 + 23:24]),
766
   .DataOut   (HASH0Out[`ETH_HASH0_WIDTH_3 + 23:24]),
767 320 igorm
   .Write     (HASH0_Wr[3]),
768 304 tadejm
   .Clk       (Clk),
769
   .Reset     (Reset),
770
   .SyncReset (1'b0)
771
  );
772 68 mohor
 
773 139 mohor
// RXHASH1 Register
774 304 tadejm
eth_register #(`ETH_HASH1_WIDTH_0, `ETH_HASH1_DEF_0)          RXHASH1_0
775 139 mohor
  (
776 304 tadejm
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_0 - 1:0]),
777
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_0 - 1:0]),
778 320 igorm
   .Write     (HASH1_Wr[0]),
779 139 mohor
   .Clk       (Clk),
780
   .Reset     (Reset),
781 141 mohor
   .SyncReset (1'b0)
782 139 mohor
  );
783 304 tadejm
eth_register #(`ETH_HASH1_WIDTH_1, `ETH_HASH1_DEF_1)          RXHASH1_1
784
  (
785
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_1 + 7:8]),
786
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_1 + 7:8]),
787 320 igorm
   .Write     (HASH1_Wr[1]),
788 304 tadejm
   .Clk       (Clk),
789
   .Reset     (Reset),
790
   .SyncReset (1'b0)
791
  );
792
eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2)          RXHASH1_2
793
  (
794
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_2 + 15:16]),
795
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]),
796 320 igorm
   .Write     (HASH1_Wr[2]),
797 304 tadejm
   .Clk       (Clk),
798
   .Reset     (Reset),
799
   .SyncReset (1'b0)
800
  );
801
eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3)          RXHASH1_3
802
  (
803
   .DataIn    (DataIn[`ETH_HASH1_WIDTH_3 + 23:24]),
804
   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]),
805 320 igorm
   .Write     (HASH1_Wr[3]),
806 304 tadejm
   .Clk       (Clk),
807
   .Reset     (Reset),
808
   .SyncReset (1'b0)
809
  );
810 68 mohor
 
811 147 mohor
// TXCTRL Register
812 304 tadejm
eth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0)  TXCTRL_0
813 147 mohor
  (
814 304 tadejm
   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
815
   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
816 320 igorm
   .Write     (TXCTRL_Wr[0]),
817 147 mohor
   .Clk       (Clk),
818
   .Reset     (Reset),
819
   .SyncReset (1'b0)
820
  );
821 304 tadejm
eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1)  TXCTRL_1
822 147 mohor
  (
823 304 tadejm
   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
824
   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
825 320 igorm
   .Write     (TXCTRL_Wr[1]),
826 147 mohor
   .Clk       (Clk),
827
   .Reset     (Reset),
828 304 tadejm
   .SyncReset (1'b0)
829
  );
830
eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2)  TXCTRL_2 // Request bit is synchronously reset
831
  (
832
   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
833
   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
834 320 igorm
   .Write     (TXCTRL_Wr[2]),
835 304 tadejm
   .Clk       (Clk),
836
   .Reset     (Reset),
837 147 mohor
   .SyncReset (RstTxPauseRq)
838
  );
839 304 tadejm
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;
840 147 mohor
 
841
 
842
 
843 139 mohor
// Reading data from registers
844
always @ (Address       or Read           or MODEROut       or INT_SOURCEOut  or
845
          INT_MASKOut   or IPGTOut        or IPGR1Out       or IPGR2Out       or
846
          PACKETLENOut  or COLLCONFOut    or CTRLMODEROut   or MIIMODEROut    or
847
          MIICOMMANDOut or MIIADDRESSOut  or MIITX_DATAOut  or MIIRX_DATAOut  or
848
          MIISTATUSOut  or MAC_ADDR0Out   or MAC_ADDR1Out   or TX_BD_NUMOut   or
849 333 igorm
          HASH0Out      or HASH1Out       or TXCTRLOut
850 139 mohor
         )
851 15 mohor
begin
852
  if(Read)  // read
853
    begin
854
      case(Address)
855 20 mohor
        `ETH_MODER_ADR        :  DataOut<=MODEROut;
856
        `ETH_INT_SOURCE_ADR   :  DataOut<=INT_SOURCEOut;
857
        `ETH_INT_MASK_ADR     :  DataOut<=INT_MASKOut;
858
        `ETH_IPGT_ADR         :  DataOut<=IPGTOut;
859
        `ETH_IPGR1_ADR        :  DataOut<=IPGR1Out;
860
        `ETH_IPGR2_ADR        :  DataOut<=IPGR2Out;
861
        `ETH_PACKETLEN_ADR    :  DataOut<=PACKETLENOut;
862
        `ETH_COLLCONF_ADR     :  DataOut<=COLLCONFOut;
863
        `ETH_CTRLMODER_ADR    :  DataOut<=CTRLMODEROut;
864
        `ETH_MIIMODER_ADR     :  DataOut<=MIIMODEROut;
865
        `ETH_MIICOMMAND_ADR   :  DataOut<=MIICOMMANDOut;
866
        `ETH_MIIADDRESS_ADR   :  DataOut<=MIIADDRESSOut;
867
        `ETH_MIITX_DATA_ADR   :  DataOut<=MIITX_DATAOut;
868
        `ETH_MIIRX_DATA_ADR   :  DataOut<=MIIRX_DATAOut;
869
        `ETH_MIISTATUS_ADR    :  DataOut<=MIISTATUSOut;
870
        `ETH_MAC_ADDR0_ADR    :  DataOut<=MAC_ADDR0Out;
871
        `ETH_MAC_ADDR1_ADR    :  DataOut<=MAC_ADDR1Out;
872 34 mohor
        `ETH_TX_BD_NUM_ADR    :  DataOut<=TX_BD_NUMOut;
873 56 mohor
        `ETH_HASH0_ADR        :  DataOut<=HASH0Out;
874
        `ETH_HASH1_ADR        :  DataOut<=HASH1Out;
875 147 mohor
        `ETH_TX_CTRL_ADR      :  DataOut<=TXCTRLOut;
876
 
877 15 mohor
        default:             DataOut<=32'h0;
878
      endcase
879
    end
880
  else
881
    DataOut<=32'h0;
882
end
883
 
884
 
885
assign r_RecSmall         = MODEROut[16];
886
assign r_Pad              = MODEROut[15];
887
assign r_HugEn            = MODEROut[14];
888
assign r_CrcEn            = MODEROut[13];
889
assign r_DlyCrcEn         = MODEROut[12];
890 244 mohor
// assign r_Rst           = MODEROut[11];   This signal is not used any more
891 15 mohor
assign r_FullD            = MODEROut[10];
892
assign r_ExDfrEn          = MODEROut[9];
893
assign r_NoBckof          = MODEROut[8];
894
assign r_LoopBck          = MODEROut[7];
895
assign r_IFG              = MODEROut[6];
896
assign r_Pro              = MODEROut[5];
897
assign r_Iam              = MODEROut[4];
898
assign r_Bro              = MODEROut[3];
899
assign r_NoPre            = MODEROut[2];
900 143 mohor
assign r_TxEn             = MODEROut[1] & (TX_BD_NUMOut>0);     // Transmission is enabled when there is at least one TxBD.
901
assign r_RxEn             = MODEROut[0] & (TX_BD_NUMOut<'h80);  // Reception is enabled when there is  at least one RxBD.
902 15 mohor
 
903
assign r_IPGT[6:0]        = IPGTOut[6:0];
904
 
905
assign r_IPGR1[6:0]       = IPGR1Out[6:0];
906
 
907
assign r_IPGR2[6:0]       = IPGR2Out[6:0];
908
 
909
assign r_MinFL[15:0]      = PACKETLENOut[31:16];
910
assign r_MaxFL[15:0]      = PACKETLENOut[15:0];
911
 
912 56 mohor
assign r_MaxRet[3:0]      = COLLCONFOut[19:16];
913
assign r_CollValid[5:0]   = COLLCONFOut[5:0];
914 15 mohor
 
915
assign r_TxFlow           = CTRLMODEROut[2];
916
assign r_RxFlow           = CTRLMODEROut[1];
917
assign r_PassAll          = CTRLMODEROut[0];
918
 
919
assign r_MiiNoPre         = MIIMODEROut[8];
920
assign r_ClkDiv[7:0]      = MIIMODEROut[7:0];
921
 
922
assign r_WCtrlData        = MIICOMMANDOut[2];
923
assign r_RStat            = MIICOMMANDOut[1];
924
assign r_ScanStat         = MIICOMMANDOut[0];
925
 
926
assign r_RGAD[4:0]        = MIIADDRESSOut[12:8];
927
assign r_FIAD[4:0]        = MIIADDRESSOut[4:0];
928
 
929
assign r_CtrlData[15:0]   = MIITX_DATAOut[15:0];
930
 
931 139 mohor
assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
932
assign MIISTATUSOut[2]    = NValid_stat         ;
933
assign MIISTATUSOut[1]    = Busy_stat           ;
934
assign MIISTATUSOut[0]    = LinkFail            ;
935 15 mohor
 
936
assign r_MAC[31:0]        = MAC_ADDR0Out[31:0];
937
assign r_MAC[47:32]       = MAC_ADDR1Out[15:0];
938 52 billditt
assign r_HASH1[31:0]      = HASH1Out;
939
assign r_HASH0[31:0]      = HASH0Out;
940 15 mohor
 
941 147 mohor
assign r_TxBDNum[7:0]     = TX_BD_NUMOut[7:0];
942 15 mohor
 
943 147 mohor
assign r_TxPauseTV[15:0]  = TXCTRLOut[15:0];
944
assign r_TxPauseRq        = TXCTRLOut[16];
945 15 mohor
 
946 147 mohor
 
947
// Synchronizing TxC Interrupt
948
always @ (posedge TxClk or posedge Reset)
949
begin
950
  if(Reset)
951
    SetTxCIrq_txclk <=#Tp 1'b0;
952
  else
953
  if(TxCtrlEndFrm & StartTxDone & r_TxFlow)
954
    SetTxCIrq_txclk <=#Tp 1'b1;
955
  else
956
  if(ResetTxCIrq_sync2)
957
    SetTxCIrq_txclk <=#Tp 1'b0;
958
end
959
 
960
 
961
always @ (posedge Clk or posedge Reset)
962
begin
963
  if(Reset)
964
    SetTxCIrq_sync1 <=#Tp 1'b0;
965
  else
966
    SetTxCIrq_sync1 <=#Tp SetTxCIrq_txclk;
967
end
968
 
969
always @ (posedge Clk or posedge Reset)
970
begin
971
  if(Reset)
972
    SetTxCIrq_sync2 <=#Tp 1'b0;
973
  else
974
    SetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
975
end
976
 
977
always @ (posedge Clk or posedge Reset)
978
begin
979
  if(Reset)
980
    SetTxCIrq_sync3 <=#Tp 1'b0;
981
  else
982
    SetTxCIrq_sync3 <=#Tp SetTxCIrq_sync2;
983
end
984
 
985
always @ (posedge Clk or posedge Reset)
986
begin
987
  if(Reset)
988
    SetTxCIrq <=#Tp 1'b0;
989
  else
990
    SetTxCIrq <=#Tp SetTxCIrq_sync2 & ~SetTxCIrq_sync3;
991
end
992
 
993
always @ (posedge TxClk or posedge Reset)
994
begin
995
  if(Reset)
996
    ResetTxCIrq_sync1 <=#Tp 1'b0;
997
  else
998
    ResetTxCIrq_sync1 <=#Tp SetTxCIrq_sync2;
999
end
1000
 
1001
always @ (posedge TxClk or posedge Reset)
1002
begin
1003
  if(Reset)
1004
    ResetTxCIrq_sync2 <=#Tp 1'b0;
1005
  else
1006
    ResetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
1007
end
1008
 
1009
 
1010
// Synchronizing RxC Interrupt
1011
always @ (posedge RxClk or posedge Reset)
1012
begin
1013
  if(Reset)
1014
    SetRxCIrq_rxclk <=#Tp 1'b0;
1015
  else
1016 261 mohor
  if(SetPauseTimer & r_RxFlow)
1017 147 mohor
    SetRxCIrq_rxclk <=#Tp 1'b1;
1018
  else
1019 261 mohor
  if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
1020 147 mohor
    SetRxCIrq_rxclk <=#Tp 1'b0;
1021
end
1022
 
1023
 
1024
always @ (posedge Clk or posedge Reset)
1025
begin
1026
  if(Reset)
1027
    SetRxCIrq_sync1 <=#Tp 1'b0;
1028
  else
1029
    SetRxCIrq_sync1 <=#Tp SetRxCIrq_rxclk;
1030
end
1031
 
1032
always @ (posedge Clk or posedge Reset)
1033
begin
1034
  if(Reset)
1035
    SetRxCIrq_sync2 <=#Tp 1'b0;
1036
  else
1037
    SetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1;
1038
end
1039
 
1040
always @ (posedge Clk or posedge Reset)
1041
begin
1042
  if(Reset)
1043
    SetRxCIrq_sync3 <=#Tp 1'b0;
1044
  else
1045
    SetRxCIrq_sync3 <=#Tp SetRxCIrq_sync2;
1046
end
1047
 
1048
always @ (posedge Clk or posedge Reset)
1049
begin
1050
  if(Reset)
1051
    SetRxCIrq <=#Tp 1'b0;
1052
  else
1053
    SetRxCIrq <=#Tp SetRxCIrq_sync2 & ~SetRxCIrq_sync3;
1054
end
1055
 
1056
always @ (posedge RxClk or posedge Reset)
1057
begin
1058
  if(Reset)
1059
    ResetRxCIrq_sync1 <=#Tp 1'b0;
1060
  else
1061
    ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2;
1062
end
1063
 
1064 261 mohor
always @ (posedge RxClk or posedge Reset)
1065 147 mohor
begin
1066
  if(Reset)
1067
    ResetRxCIrq_sync2 <=#Tp 1'b0;
1068
  else
1069 261 mohor
    ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1;
1070 147 mohor
end
1071
 
1072 261 mohor
always @ (posedge RxClk or posedge Reset)
1073
begin
1074
  if(Reset)
1075
    ResetRxCIrq_sync3 <=#Tp 1'b0;
1076
  else
1077
    ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2;
1078
end
1079 147 mohor
 
1080
 
1081
 
1082 21 mohor
// Interrupt generation
1083
always @ (posedge Clk or posedge Reset)
1084
begin
1085
  if(Reset)
1086
    irq_txb <= 1'b0;
1087
  else
1088 102 mohor
  if(TxB_IRQ)
1089 21 mohor
    irq_txb <= #Tp 1'b1;
1090
  else
1091 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[0])
1092 21 mohor
    irq_txb <= #Tp 1'b0;
1093
end
1094
 
1095
always @ (posedge Clk or posedge Reset)
1096
begin
1097
  if(Reset)
1098
    irq_txe <= 1'b0;
1099
  else
1100 102 mohor
  if(TxE_IRQ)
1101 21 mohor
    irq_txe <= #Tp 1'b1;
1102
  else
1103 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[1])
1104 21 mohor
    irq_txe <= #Tp 1'b0;
1105
end
1106
 
1107
always @ (posedge Clk or posedge Reset)
1108
begin
1109
  if(Reset)
1110
    irq_rxb <= 1'b0;
1111
  else
1112 102 mohor
  if(RxB_IRQ)
1113 21 mohor
    irq_rxb <= #Tp 1'b1;
1114
  else
1115 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[2])
1116 21 mohor
    irq_rxb <= #Tp 1'b0;
1117
end
1118
 
1119
always @ (posedge Clk or posedge Reset)
1120
begin
1121
  if(Reset)
1122 74 mohor
    irq_rxe <= 1'b0;
1123 21 mohor
  else
1124 102 mohor
  if(RxE_IRQ)
1125 74 mohor
    irq_rxe <= #Tp 1'b1;
1126 21 mohor
  else
1127 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[3])
1128 74 mohor
    irq_rxe <= #Tp 1'b0;
1129 21 mohor
end
1130
 
1131
always @ (posedge Clk or posedge Reset)
1132
begin
1133
  if(Reset)
1134
    irq_busy <= 1'b0;
1135
  else
1136 102 mohor
  if(Busy_IRQ)
1137 21 mohor
    irq_busy <= #Tp 1'b1;
1138
  else
1139 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[4])
1140 21 mohor
    irq_busy <= #Tp 1'b0;
1141
end
1142
 
1143 74 mohor
always @ (posedge Clk or posedge Reset)
1144
begin
1145
  if(Reset)
1146
    irq_txc <= 1'b0;
1147
  else
1148 147 mohor
  if(SetTxCIrq)
1149 74 mohor
    irq_txc <= #Tp 1'b1;
1150
  else
1151 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[5])
1152 74 mohor
    irq_txc <= #Tp 1'b0;
1153
end
1154
 
1155
always @ (posedge Clk or posedge Reset)
1156
begin
1157
  if(Reset)
1158
    irq_rxc <= 1'b0;
1159
  else
1160 147 mohor
  if(SetRxCIrq)
1161 74 mohor
    irq_rxc <= #Tp 1'b1;
1162
  else
1163 320 igorm
  if(INT_SOURCE_Wr[0] & DataIn[6])
1164 74 mohor
    irq_rxc <= #Tp 1'b0;
1165
end
1166
 
1167 21 mohor
// Generating interrupt signal
1168 102 mohor
assign int_o = irq_txb  & INT_MASKOut[0] |
1169
               irq_txe  & INT_MASKOut[1] |
1170
               irq_rxb  & INT_MASKOut[2] |
1171
               irq_rxe  & INT_MASKOut[3] |
1172
               irq_busy & INT_MASKOut[4] |
1173
               irq_txc  & INT_MASKOut[5] |
1174
               irq_rxc  & INT_MASKOut[6] ;
1175 21 mohor
 
1176
// For reading interrupt status
1177 304 tadejm
assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH_0){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
1178 21 mohor
 
1179
 
1180
 
1181 15 mohor
endmodule

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