OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxethmac.v] - Blame information for rev 341

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_rxethmac.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 341 olof
////  http://www.opencores.org/projects,ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
11
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
12 341 olof
////      - Olof Kindgren (olof@opencores.org                     ////
13 15 mohor
////                                                              ////
14
////  All additional information is avaliable in the Readme.txt   ////
15
////  file.                                                       ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19 341 olof
//// Copyright (C) 2011 Authors                                   ////
20 15 mohor
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44 341 olof
// 2011-07-06 Olof Kindgren <olof@opencores.org>
45
// Add ByteCntEq0 to rxaddrcheck
46
//
47 15 mohor
// CVS Revision History
48
//
49 341 olof
//
50 15 mohor
// $Log: not supported by cvs2svn $
51 330 igorm
// Revision 1.12  2004/04/26 15:26:23  igorm
52
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
53
//   previous update of the core.
54
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
55
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
56
//   register. (thanks to Mathias and Torbjorn)
57
// - Multicast reception was fixed. Thanks to Ulrich Gries
58
//
59 321 igorm
// Revision 1.11  2004/03/17 09:32:15  igorm
60
// Multicast detection fixed. Only the LSB of the first byte is checked.
61
//
62 317 igorm
// Revision 1.10  2002/11/22 01:57:06  mohor
63
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
64
// synchronized.
65
//
66 261 mohor
// Revision 1.9  2002/11/19 17:35:35  mohor
67
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
68
// that a frame was received because of the promiscous mode.
69
//
70 250 mohor
// Revision 1.8  2002/02/16 07:15:27  mohor
71
// Testbench fixed, code simplified, unused signals removed.
72
//
73 65 mohor
// Revision 1.7  2002/02/15 13:44:28  mohor
74
// RxAbort is an output. No need to have is declared as wire.
75
//
76 62 mohor
// Revision 1.6  2002/02/15 11:17:48  mohor
77
// File format changed.
78
//
79 58 mohor
// Revision 1.5  2002/02/14 20:48:43  billditt
80
// Addition  of new module eth_addrcheck.v
81
//
82 53 billditt
// Revision 1.4  2002/01/23 10:28:16  mohor
83
// Link in the header changed.
84
//
85 37 mohor
// Revision 1.3  2001/10/19 08:43:51  mohor
86
// eth_timescale.v changed to timescale.v This is done because of the
87
// simulation of the few cores in a one joined project.
88
//
89 22 mohor
// Revision 1.2  2001/09/11 14:17:00  mohor
90
// Few little NCSIM warnings fixed.
91
//
92 18 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
93
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
94
// Include files fixed to contain no path.
95
// File names and module names changed ta have a eth_ prologue in the name.
96
// File eth_timescale.v is used to define timescale
97
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
98
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
99
// and Mdo_OE. The bidirectional signal must be created on the top level. This
100
// is done due to the ASIC tools.
101
//
102 15 mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
103
// Directory structure changed. Files checked and joind together.
104
//
105
// Revision 1.1  2001/06/27 21:26:19  mohor
106
// Initial release of the RxEthMAC module.
107
//
108
//
109
//
110
//
111
//
112
 
113 22 mohor
`include "timescale.v"
114 15 mohor
 
115
 
116
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
117 65 mohor
                     RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
118
                     ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
119 261 mohor
                     MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK
120 15 mohor
                    );
121
 
122
parameter Tp = 1;
123
 
124
 
125
 
126
input         MRxClk;
127
input         MRxDV;
128
input   [3:0] MRxD;
129
input         Transmitting;
130
input         HugEn;
131
input         DlyCrcEn;
132
input  [15:0] MaxFL;
133
input         r_IFG;
134
input         Reset;
135 53 billditt
input  [47:0] MAC;     //  Station Address  
136
input         r_Bro;   //  broadcast disable
137
input         r_Pro;   //  promiscuous enable 
138
input [31:0]  r_HASH0; //  lower 4 bytes Hash Table
139
input [31:0]  r_HASH1; //  upper 4 bytes Hash Table
140 261 mohor
input         PassAll;
141
input         ControlFrmAddressOK;
142
 
143 15 mohor
output  [7:0] RxData;
144
output        RxValid;
145
output        RxStartFrm;
146
output        RxEndFrm;
147
output [15:0] ByteCnt;
148
output        ByteCntEq0;
149
output        ByteCntGreat2;
150
output        ByteCntMaxFrame;
151
output        CrcError;
152
output        StateIdle;
153
output        StatePreamble;
154
output        StateSFD;
155
output  [1:0] StateData;
156 53 billditt
output        RxAbort;
157 250 mohor
output        AddressMiss;
158 15 mohor
 
159
reg     [7:0] RxData;
160
reg           RxValid;
161
reg           RxStartFrm;
162
reg           RxEndFrm;
163
reg           Broadcast;
164
reg           Multicast;
165 321 igorm
reg     [5:0] CrcHash;
166 15 mohor
reg           CrcHashGood;
167
reg           DelayData;
168
reg     [7:0] LatchedByte;
169
reg     [7:0] RxData_d;
170
reg           RxValid_d;
171
reg           RxStartFrm_d;
172
reg           RxEndFrm_d;
173
 
174
wire          MRxDEqD;
175
wire          MRxDEq5;
176
wire          StateDrop;
177
wire          ByteCntEq1;
178 53 billditt
wire          ByteCntEq2;
179
wire          ByteCntEq3;
180
wire          ByteCntEq4;
181
wire          ByteCntEq5;
182 15 mohor
wire          ByteCntEq6;
183 53 billditt
wire          ByteCntEq7;
184 15 mohor
wire          ByteCntSmall7;
185
wire   [31:0] Crc;
186
wire          Enable_Crc;
187
wire          Initialize_Crc;
188
wire    [3:0] Data_Crc;
189
wire          GenerateRxValid;
190
wire          GenerateRxStartFrm;
191
wire          GenerateRxEndFrm;
192
wire          DribbleRxEndFrm;
193
wire    [3:0] DlyCrcCnt;
194 330 igorm
wire          IFGCounterEq24;
195 15 mohor
 
196
assign MRxDEqD = MRxD == 4'hd;
197
assign MRxDEq5 = MRxD == 4'h5;
198
 
199
 
200
// Rx State Machine module
201
eth_rxstatem rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0),
202
                        .ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5),
203
                        .MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame),
204
                        .StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble),
205
                        .StateSFD(StateSFD), .StateDrop(StateDrop)
206
                       );
207
 
208
 
209
// Rx Counters module
210
eth_rxcounters rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
211
                            .StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
212
                            .StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
213
                            .DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
214
                            .HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
215 58 mohor
                            .ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
216
                            .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6),
217
                            .ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2),
218 15 mohor
                            .ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
219 330 igorm
                            .ByteCntOut(ByteCnt)
220 15 mohor
                           );
221
 
222 53 billditt
// Rx Address Check
223 15 mohor
 
224 58 mohor
eth_rxaddrcheck rxaddrcheck1
225 261 mohor
              (.MRxClk(MRxClk),         .Reset( Reset),             .RxData(RxData),
226
               .Broadcast (Broadcast),  .r_Bro (r_Bro),             .r_Pro(r_Pro),
227
               .ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7),    .ByteCntEq2(ByteCntEq2),
228
               .ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4),    .ByteCntEq5(ByteCntEq5),
229 341 olof
               .HASH0(r_HASH0),         .HASH1(r_HASH1),            .ByteCntEq0(ByteCntEq0),
230 321 igorm
               .CrcHash(CrcHash),       .CrcHashGood(CrcHashGood),  .StateData(StateData),
231 261 mohor
               .Multicast(Multicast),   .MAC(MAC),                  .RxAbort(RxAbort),
232
               .RxEndFrm(RxEndFrm),     .AddressMiss(AddressMiss),  .PassAll(PassAll),
233
               .ControlFrmAddressOK(ControlFrmAddressOK)
234 58 mohor
              );
235 15 mohor
 
236 53 billditt
 
237 15 mohor
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
238
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
239
 
240
assign Data_Crc[0] = MRxD[3];
241
assign Data_Crc[1] = MRxD[2];
242
assign Data_Crc[2] = MRxD[1];
243
assign Data_Crc[3] = MRxD[0];
244
 
245
 
246
// Connecting module Crc
247
eth_crc crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
248
               .Crc(Crc), .CrcError(CrcError)
249 58 mohor
              );
250 15 mohor
 
251
 
252
 
253
// Latching CRC for use in the hash table
254
 
255
always @ (posedge MRxClk)
256
begin
257
  CrcHashGood <= #Tp StateData[0] & ByteCntEq6;
258
end
259
 
260
always @ (posedge MRxClk)
261
begin
262
  if(Reset | StateIdle)
263 321 igorm
    CrcHash[5:0] <= #Tp 6'h0;
264 15 mohor
  else
265
  if(StateData[0] & ByteCntEq6)
266 321 igorm
    CrcHash[5:0] <= #Tp Crc[31:26];
267 15 mohor
end
268
 
269
 
270
// Output byte stream
271
always @ (posedge MRxClk or posedge Reset)
272
begin
273
  if(Reset)
274
    begin
275
      RxData_d[7:0]      <= #Tp 8'h0;
276
      DelayData          <= #Tp 1'b0;
277
      LatchedByte[7:0]   <= #Tp 8'h0;
278
      RxData[7:0]        <= #Tp 8'h0;
279
    end
280
  else
281
    begin
282 330 igorm
      LatchedByte[7:0]   <= #Tp {MRxD[3:0], LatchedByte[7:4]};  // Latched byte
283 15 mohor
      DelayData          <= #Tp StateData[0];
284
 
285
      if(GenerateRxValid)
286
        RxData_d[7:0] <= #Tp LatchedByte[7:0] & {8{|StateData}};  // Data goes through only in data state 
287
      else
288
      if(~DelayData)
289
        RxData_d[7:0] <= #Tp 8'h0;                                // Delaying data to be valid for two cycles. Zero when not active.
290
 
291
      RxData[7:0] <= #Tp RxData_d[7:0];                           // Output data byte
292
    end
293
end
294
 
295
 
296
 
297
always @ (posedge MRxClk or posedge Reset)
298
begin
299
  if(Reset)
300
    Broadcast <= #Tp 1'b0;
301
  else
302
    begin
303
      if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
304
        Broadcast <= #Tp 1'b0;
305
      else
306 18 mohor
      if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
307 15 mohor
        Broadcast <= #Tp 1'b1;
308 58 mohor
      else
309
      if(RxAbort | RxEndFrm)
310
        Broadcast <= #Tp 1'b0;
311 15 mohor
    end
312
end
313
 
314
 
315
always @ (posedge MRxClk or posedge Reset)
316
begin
317
  if(Reset)
318
    Multicast <= #Tp 1'b0;
319
  else
320
    begin
321 317 igorm
      if(StateData[0] & ByteCntEq1 & LatchedByte[0])
322 53 billditt
        Multicast <= #Tp 1'b1;
323 317 igorm
      else if(RxAbort | RxEndFrm)
324 58 mohor
      Multicast <= #Tp 1'b0;
325 15 mohor
    end
326
end
327
 
328
 
329
assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
330
 
331
always @ (posedge MRxClk or posedge Reset)
332
begin
333
  if(Reset)
334
    begin
335
      RxValid_d <= #Tp 1'b0;
336
      RxValid   <= #Tp 1'b0;
337
    end
338
  else
339
    begin
340
      RxValid_d <= #Tp GenerateRxValid;
341
      RxValid   <= #Tp RxValid_d;
342
    end
343
end
344
 
345
 
346
assign GenerateRxStartFrm = StateData[0] & (ByteCntEq1 & ~DlyCrcEn | DlyCrcCnt == 4'h3 & DlyCrcEn);
347
 
348
always @ (posedge MRxClk or posedge Reset)
349
begin
350
  if(Reset)
351
    begin
352
      RxStartFrm_d <= #Tp 1'b0;
353
      RxStartFrm   <= #Tp 1'b0;
354
    end
355
  else
356
    begin
357
      RxStartFrm_d <= #Tp GenerateRxStartFrm;
358
      RxStartFrm   <= #Tp RxStartFrm_d;
359
    end
360
end
361
 
362
 
363
assign GenerateRxEndFrm = StateData[0] & (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
364
assign DribbleRxEndFrm  = StateData[1] &  ~MRxDV & ByteCntGreat2;
365
 
366
 
367
always @ (posedge MRxClk or posedge Reset)
368
begin
369
  if(Reset)
370
    begin
371
      RxEndFrm_d <= #Tp 1'b0;
372
      RxEndFrm   <= #Tp 1'b0;
373
    end
374
  else
375
    begin
376
      RxEndFrm_d <= #Tp GenerateRxEndFrm;
377
      RxEndFrm   <= #Tp RxEndFrm_d | DribbleRxEndFrm;
378
    end
379
end
380
 
381
 
382
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.