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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_shiftreg.v] - Blame information for rev 37

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_shiftreg.v                                              ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/10/19 08:43:51  mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1  2001/08/06 14:44:29  mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3  2001/06/01 22:28:56  mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
 
`include "timescale.v"
 
 
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
                    LatchByte, ShiftedBit, Prsd, LinkFail);
 
 
parameter Tp=1;
 
input       Clk;              // Input clock (Host clock)
input       Reset;            // Reset signal
input       MdcEn_n;          // Enable signal is asserted for one Clk period before Mdc falls.
input       Mdi;              // MII input data
input [4:0] Fiad;             // PHY address
input [4:0] Rgad;             // Register address (within the selected PHY)
input [15:0]CtrlData;         // Control data (data to be written to the PHY)
input       WriteOp;          // The current operation is a PHY register write operation
input [3:0] ByteSelect;       // Byte select
input [1:0] LatchByte;        // Byte select for latching (read operation)
 
output      ShiftedBit;       // Bit shifted out of the shift register
output[15:0]Prsd;             // Read Status Data (data read from the PHY)
output      LinkFail;         // Link Integrity Signal
 
reg   [7:0] ShiftReg;         // Shift register for shifting the data in and out
reg   [15:0]Prsd;
reg         LinkFail;
 
 
 
 
// ShiftReg[7:0] :: Shift Register Data
always @ (posedge Clk or posedge Reset)
begin
  if(Reset)
    begin
      ShiftReg[7:0] <= #Tp 8'h0;
      Prsd[15:0] <= #Tp 16'h0;
      LinkFail <= #Tp 1'b0;
    end
  else
    begin
      if(MdcEn_n)
        begin
          if(|ByteSelect)
            begin
              case (ByteSelect[3:0])
                4'h1 :    ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
                4'h2 :    ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10};
                4'h4 :    ShiftReg[7:0] <= #Tp CtrlData[15:8];
                4'h8 :    ShiftReg[7:0] <= #Tp CtrlData[7:0];
                default : ShiftReg[7:0] <= #Tp 8'h0;
              endcase
            end
          else
            begin
              ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};
              if(LatchByte[0])
                begin
                  Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi};
                  if(Rgad == 5'h01)
                    LinkFail <= #Tp ~ShiftReg[1];  // because of shifting
                end
              else
                begin
                  if(LatchByte[1])
                    Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi};
                end
            end
        end
    end
end
 
 
assign ShiftedBit = ShiftReg[7];
 
 
endmodule

Line No.	Rev	Author	Line
1	15	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_shiftreg.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6	37	mohor	`//// http://www.opencores.org/projects/ethmac/ ////`
7	15	mohor	`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	37	mohor	`// Revision 1.2 2001/10/19 08:43:51 mohor`
45			`// eth_timescale.v changed to timescale.v This is done because of the`
46			`// simulation of the few cores in a one joined project.`
47			`//`
48	22	mohor	`// Revision 1.1 2001/08/06 14:44:29 mohor`
49			`// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).`
50			`// Include files fixed to contain no path.`
51			`// File names and module names changed ta have a eth_ prologue in the name.`
52			`// File eth_timescale.v is used to define timescale`
53			`// All pin names on the top module are changed to contain _I, _O or _OE at the end.`
54			`// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O`
55			`// and Mdo_OE. The bidirectional signal must be created on the top level. This`
56			`// is done due to the ASIC tools.`
57			`//`
58	15	mohor	`// Revision 1.1 2001/07/30 21:23:42 mohor`
59			`// Directory structure changed. Files checked and joind together.`
60			`//`
61			`// Revision 1.3 2001/06/01 22:28:56 mohor`
62			`// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.`
63			`//`
64			`//`
65
66	22	mohor	`include "timescale.v"
67	15	mohor
68
69			`module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,`
70			`LatchByte, ShiftedBit, Prsd, LinkFail);`
71
72
73			`parameter Tp=1;`
74
75			`input Clk; // Input clock (Host clock)`
76			`input Reset; // Reset signal`
77			`input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.`
78			`input Mdi; // MII input data`
79			`input [4:0] Fiad; // PHY address`
80			`input [4:0] Rgad; // Register address (within the selected PHY)`
81			`input [15:0]CtrlData; // Control data (data to be written to the PHY)`
82			`input WriteOp; // The current operation is a PHY register write operation`
83			`input [3:0] ByteSelect; // Byte select`
84			`input [1:0] LatchByte; // Byte select for latching (read operation)`
85
86			`output ShiftedBit; // Bit shifted out of the shift register`
87			`output[15:0]Prsd; // Read Status Data (data read from the PHY)`
88			`output LinkFail; // Link Integrity Signal`
89
90			`reg [7:0] ShiftReg; // Shift register for shifting the data in and out`
91			`reg [15:0]Prsd;`
92			`reg LinkFail;`
93
94
95
96
97			`// ShiftReg[7:0] :: Shift Register Data`
98			`always @ (posedge Clk or posedge Reset)`
99			`begin`
100			`if(Reset)`
101			`begin`
102			`ShiftReg[7:0] <= #Tp 8'h0;`
103			`Prsd[15:0] <= #Tp 16'h0;`
104			`LinkFail <= #Tp 1'b0;`
105			`end`
106			`else`
107			`begin`
108			`if(MdcEn_n)`
109			`begin`
110			`if(\|ByteSelect)`
111			`begin`
112			`case (ByteSelect[3:0])`
113			`4'h1 : ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};`
114			`4'h2 : ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10};`
115			`4'h4 : ShiftReg[7:0] <= #Tp CtrlData[15:8];`
116			`4'h8 : ShiftReg[7:0] <= #Tp CtrlData[7:0];`
117			`default : ShiftReg[7:0] <= #Tp 8'h0;`
118			`endcase`
119			`end`
120			`else`
121			`begin`
122			`ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};`
123			`if(LatchByte[0])`
124			`begin`
125			`Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi};`
126			`if(Rgad == 5'h01)`
127			`LinkFail <= #Tp ~ShiftReg[1]; // because of shifting`
128			`end`
129			`else`
130			`begin`
131			`if(LatchByte[1])`
132			`Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi};`
133			`end`
134			`end`
135			`end`
136			`end`
137			`end`
138
139
140			`assign ShiftedBit = ShiftReg[7];`
141
142
143			`endmodule`

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_shiftreg.v] - Blame information for rev 37