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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Blame information for rev 312

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_spram_256x32.v                                          ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/projects/ethmac/                   ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  All additional information is available in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001, 2002 Authors                             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
44 312 tadejm
// Revision 1.8  2003/12/04 14:59:13  simons
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// Lapsus fixed (!we -> ~we).
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//
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// Revision 1.7  2003/11/12 18:24:59  tadejm
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// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
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//
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// Revision 1.6  2003/10/17 07:46:15  markom
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// mbist signals updated according to newest convention
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//
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// Revision 1.5  2003/08/14 16:42:58  simons
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// Artisan ram instance added.
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//
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// Revision 1.4  2002/10/18 17:04:20  tadejm
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// Changed BIST scan signals.
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//
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// Revision 1.3  2002/10/10 16:29:30  mohor
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// BIST added.
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//
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// Revision 1.2  2002/09/23 18:24:31  mohor
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// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
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//
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// Revision 1.1  2002/07/23 16:36:09  mohor
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// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.
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//
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//
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//
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`include "eth_defines.v"
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`include "timescale.v"
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module eth_spram_256x32(
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        // Generic synchronous single-port RAM interface
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        clk, rst, ce, we, oe, addr, di, do
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`ifdef ETH_BIST
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  ,
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  // debug chain signals
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  mbist_si_i,       // bist scan serial in
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  mbist_so_o,       // bist scan serial out
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  mbist_ctrl_i        // bist chain shift control
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`endif
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);
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        //
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        // Generic synchronous single-port RAM interface
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        //
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        input           clk;  // Clock, rising edge
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        input           rst;  // Reset, active high
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        input           ce;   // Chip enable input, active high
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        input  [3:0]    we;   // Write enable input, active high
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        input           oe;   // Output enable input, active high
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        input  [7:0]    addr; // address bus inputs
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        input  [31:0]   di;   // input data bus
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        output [31:0]   do;   // output data bus
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`ifdef ETH_BIST
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  input   mbist_si_i;       // bist scan serial in
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  output  mbist_so_o;       // bist scan serial out
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  input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
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`endif
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`ifdef ETH_XILINX_RAMB4
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111 304 tadejm
    /*RAMB4_S16 ram0
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    (
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        .DO      (do[15:0]),
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        .ADDR    (addr),
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        .DI      (di[15:0]),
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        .EN      (ce),
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        .CLK     (clk),
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        .WE      (we),
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        .RST     (rst)
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    );
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    RAMB4_S16 ram1
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    (
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        .DO      (do[31:16]),
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        .ADDR    (addr),
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        .DI      (di[31:16]),
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        .EN      (ce),
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        .CLK     (clk),
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        .WE      (we),
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        .RST     (rst)
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    );*/
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    RAMB4_S8 ram0
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    (
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        .DO      (do[7:0]),
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        .ADDR    ({1'b0, addr}),
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        .DI      (di[7:0]),
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        .EN      (ce),
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        .CLK     (clk),
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        .WE      (we[0]),
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        .RST     (rst)
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    );
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144 304 tadejm
    RAMB4_S8 ram1
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    (
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        .DO      (do[15:8]),
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        .ADDR    ({1'b0, addr}),
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        .DI      (di[15:8]),
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        .EN      (ce),
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        .CLK     (clk),
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        .WE      (we[1]),
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        .RST     (rst)
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    );
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    RAMB4_S8 ram2
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    (
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        .DO      (do[23:16]),
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        .ADDR    ({1'b0, addr}),
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        .DI      (di[23:16]),
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        .EN      (ce),
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        .CLK     (clk),
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        .WE      (we[2]),
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        .RST     (rst)
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    );
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    RAMB4_S8 ram3
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    (
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        .DO      (do[31:24]),
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        .ADDR    ({1'b0, addr}),
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        .DI      (di[31:24]),
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        .EN      (ce),
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        .CLK     (clk),
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        .WE      (we[3]),
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        .RST     (rst)
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    );
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`else   // !ETH_XILINX_RAMB4
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`ifdef  ETH_VIRTUAL_SILICON_RAM
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  `ifdef ETH_BIST
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      //vs_hdsp_256x32_bist ram0_bist
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      vs_hdsp_256x32_bw_bist ram0_bist
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  `else
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      //vs_hdsp_256x32 ram0
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      vs_hdsp_256x32_bw ram0
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  `endif
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      (
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        .CK         (clk),
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        .CEN        (!ce),
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        .WEN        (~we),
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        .OEN        (!oe),
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        .ADR        (addr),
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        .DI         (di),
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        .DOUT       (do)
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      `ifdef ETH_BIST
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        ,
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        // debug chain signals
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        .mbist_si_i       (mbist_si_i),
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        .mbist_so_o       (mbist_so_o),
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        .mbist_ctrl_i       (mbist_ctrl_i)
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      `endif
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      );
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`else   // !ETH_VIRTUAL_SILICON_RAM
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`ifdef  ETH_ARTISAN_RAM
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  `ifdef ETH_BIST
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      //art_hssp_256x32_bist ram0_bist
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      art_hssp_256x32_bw_bist ram0_bist
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  `else
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      //art_hssp_256x32 ram0
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      art_hssp_256x32_bw ram0
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  `endif
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      (
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        .CLK        (clk),
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        .CEN        (!ce),
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        .WEN        (~we),
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        .OEN        (!oe),
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        .A          (addr),
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        .D          (di),
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        .Q          (do)
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      `ifdef ETH_BIST
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        ,
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        // debug chain signals
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        .mbist_si_i       (mbist_si_i),
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        .mbist_so_o       (mbist_so_o),
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        .mbist_ctrl_i       (mbist_ctrl_i)
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      `endif
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      );
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`else   // !ETH_ARTISAN_RAM
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        //
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        // Generic single-port synchronous RAM model
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        //
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        //
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        // Generic RAM's registers and wires
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        //
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        reg  [ 7: 0] mem0 [255:0]; // RAM content
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        reg  [15: 8] mem1 [255:0]; // RAM content
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        reg  [23:16] mem2 [255:0]; // RAM content
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        reg  [31:24] mem3 [255:0]; // RAM content
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        wire [31:0]  q;            // RAM output
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        reg  [7:0]   raddr;        // RAM read address
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        //
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        // Data output drivers
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        //
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        assign do = (oe & ce) ? q : {32{1'bz}};
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        //
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        // RAM read and write
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        //
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        // read operation
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        always@(posedge clk)
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          if (ce) // && !we)
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                raddr <= #1 addr;    // read address needs to be registered to read clock
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        assign #1 q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]};
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        // write operation
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        always@(posedge clk)
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        begin
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                if (ce && we[3])
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                        mem3[addr] <= #1 di[31:24];
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                if (ce && we[2])
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                        mem2[addr] <= #1 di[23:16];
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                if (ce && we[1])
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                        mem1[addr] <= #1 di[15: 8];
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                if (ce && we[0])
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                        mem0[addr] <= #1 di[ 7: 0];
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        end
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        // Task prints range of memory
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        // *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations. 
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        task print_ram;
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        input [7:0] start;
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        input [7:0] finish;
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        integer rnum;
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        begin
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                for (rnum=start;rnum<=finish;rnum=rnum+1)
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                        $display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
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        end
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        endtask
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287 297 simons
`endif  // !ETH_ARTISAN_RAM
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`endif  // !ETH_VIRTUAL_SILICON_RAM
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`endif  // !ETH_XILINX_RAMB4
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endmodule

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