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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_txethmac.v] - Blame information for rev 277

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1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_txethmac.v                                              ////
4 72 mohor
///                                                              ////
5 15 mohor
////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
11
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
12
////                                                              ////
13
////  All additional information is avaliable in the Readme.txt   ////
14
////  file.                                                       ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2001 Authors                                   ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
//
43
// CVS Revision History
44
//
45
// $Log: not supported by cvs2svn $
46 277 mohor
// Revision 1.7  2002/02/26 16:24:01  mohor
47
// RetryCntLatched was unused and removed from design
48
//
49 79 mohor
// Revision 1.6  2002/02/22 12:56:35  mohor
50
// Retry is not activated when a Tx Underrun occured
51
//
52 72 mohor
// Revision 1.5  2002/02/11 09:18:22  mohor
53
// Tx status is written back to the BD.
54
//
55 43 mohor
// Revision 1.4  2002/01/23 10:28:16  mohor
56
// Link in the header changed.
57
//
58 37 mohor
// Revision 1.3  2001/10/19 08:43:51  mohor
59
// eth_timescale.v changed to timescale.v This is done because of the
60
// simulation of the few cores in a one joined project.
61
//
62 22 mohor
// Revision 1.2  2001/09/11 14:17:00  mohor
63
// Few little NCSIM warnings fixed.
64
//
65 18 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
66
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
67
// Include files fixed to contain no path.
68
// File names and module names changed ta have a eth_ prologue in the name.
69
// File eth_timescale.v is used to define timescale
70
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
71
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
72
// and Mdo_OE. The bidirectional signal must be created on the top level. This
73
// is done due to the ASIC tools.
74
//
75 15 mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
76
// Directory structure changed. Files checked and joind together.
77
//
78
// Revision 1.3  2001/06/19 18:16:40  mohor
79
// TxClk changed to MTxClk (as discribed in the documentation).
80
// Crc changed so only one file can be used instead of two.
81
//
82
// Revision 1.2  2001/06/19 10:38:08  mohor
83
// Minor changes in header.
84
//
85
// Revision 1.1  2001/06/19 10:27:58  mohor
86
// TxEthMAC initial release.
87
//
88
//
89
//
90
 
91 22 mohor
`include "timescale.v"
92 15 mohor
 
93
 
94
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
95
                     Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
96
                     IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
97
                     MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
98 43 mohor
                     ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
99 277 mohor
                     LateCollision, DeferIndication, StatePreamble, StateData
100 43 mohor
 
101 15 mohor
                    );
102
 
103
parameter Tp = 1;
104
 
105
 
106
input MTxClk;                   // Transmit clock (from PHY)
107
input Reset;                    // Reset
108
input TxStartFrm;               // Transmit packet start frame
109
input TxEndFrm;                 // Transmit packet end frame
110
input TxUnderRun;               // Transmit packet under-run
111
input [7:0] TxData;             // Transmit packet data byte
112
input CarrierSense;             // Carrier sense (synchronized)
113
input Collision;                // Collision (synchronized)
114
input Pad;                      // Pad enable (from register)
115
input CrcEn;                    // Crc enable (from register)
116
input FullD;                    // Full duplex (from register)
117
input HugEn;                    // Huge packets enable (from register)
118
input DlyCrcEn;                 // Delayed Crc enabled (from register)
119
input [15:0] MinFL;             // Minimum frame length (from register)
120
input [15:0] MaxFL;             // Maximum frame length (from register)
121
input [6:0] IPGT;               // Back to back transmit inter packet gap parameter (from register)
122
input [6:0] IPGR1;              // Non back to back transmit inter packet gap parameter IPGR1 (from register)
123
input [6:0] IPGR2;              // Non back to back transmit inter packet gap parameter IPGR2 (from register)
124
input [5:0] CollValid;          // Valid collision window (from register)
125
input [3:0] MaxRet;             // Maximum retry number (from register)
126
input NoBckof;                  // No backoff (from register)
127
input ExDfrEn;                  // Excessive defferal enable (from register)
128
 
129
output [3:0] MTxD;              // Transmit nibble (to PHY)
130
output MTxEn;                   // Transmit enable (to PHY)
131
output MTxErr;                  // Transmit error (to PHY)
132
output TxDone;                  // Transmit packet done (to RISC)
133
output TxRetry;                 // Transmit packet retry (to RISC)
134
output TxAbort;                 // Transmit packet abort (to RISC)
135
output TxUsedData;              // Transmit packet used data (to RISC)
136
output WillTransmit;            // Will transmit (to RxEthMAC)
137
output ResetCollision;          // Reset Collision (for synchronizing collision)
138 43 mohor
output [3:0] RetryCnt;          // Latched Retry Counter for tx status purposes
139
output StartTxDone;
140
output StartTxAbort;
141
output MaxCollisionOccured;
142
output LateCollision;
143 277 mohor
output DeferIndication;
144 43 mohor
output StatePreamble;
145
output [1:0] StateData;
146 15 mohor
 
147
reg [3:0] MTxD;
148
reg MTxEn;
149
reg MTxErr;
150
reg TxDone;
151
reg TxRetry;
152
reg TxAbort;
153
reg TxUsedData;
154
reg WillTransmit;
155
reg ColWindow;
156
reg StopExcessiveDeferOccured;
157
reg [3:0] RetryCnt;
158
reg [3:0] MTxD_d;
159
reg StatusLatch;
160
reg PacketFinished_q;
161
reg PacketFinished;
162
 
163
 
164
wire ExcessiveDeferOccured;
165
wire StartIPG;
166
wire StartPreamble;
167
wire [1:0] StartData;
168
wire StartFCS;
169
wire StartJam;
170 277 mohor
wire StartDefer;
171 15 mohor
wire StartBackoff;
172
wire StateDefer;
173
wire StateIPG;
174
wire StateIdle;
175
wire StatePAD;
176
wire StateFCS;
177
wire StateJam;
178
wire StateBackOff;
179
wire StateSFD;
180
wire StartTxRetry;
181
wire UnderRun;
182
wire TooBig;
183
wire [31:0] Crc;
184
wire CrcError;
185
wire [2:0] DlyCrcCnt;
186
wire [15:0] NibCnt;
187
wire NibCntEq7;
188
wire NibCntEq15;
189
wire NibbleMinFl;
190
wire ExcessiveDefer;
191
wire [15:0] ByteCnt;
192
wire MaxFrame;
193
wire RetryMax;
194
wire RandomEq0;
195
wire RandomEqByteCnt;
196
wire PacketFinished_d;
197
 
198
 
199
 
200 18 mohor
assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
201 15 mohor
 
202
assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
203
 
204 277 mohor
assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn);
205 15 mohor
 
206
assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
207
 
208
assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
209
 
210 72 mohor
// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
211
assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
212 15 mohor
 
213
assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
214
 
215
assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
216
 
217
assign StateSFD = StatePreamble & NibCntEq15;
218
 
219
assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
220
 
221
 
222
// StopExcessiveDeferOccured
223
always @ (posedge MTxClk or posedge Reset)
224
begin
225
  if(Reset)
226
    StopExcessiveDeferOccured <= #Tp 1'b0;
227
  else
228
    begin
229
      if(~TxStartFrm)
230
        StopExcessiveDeferOccured <= #Tp 1'b0;
231
      else
232
      if(ExcessiveDeferOccured)
233
        StopExcessiveDeferOccured <= #Tp 1'b1;
234
    end
235
end
236
 
237
 
238
// Collision Window
239
always @ (posedge MTxClk or posedge Reset)
240
begin
241
  if(Reset)
242
    ColWindow <= #Tp 1'b1;
243
  else
244
    begin
245
      if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
246
        ColWindow <= #Tp 1'b0;
247
      else
248
      if(StateIdle | StateIPG)
249
        ColWindow <= #Tp 1'b1;
250
    end
251
end
252
 
253
 
254
// Start Window
255
always @ (posedge MTxClk or posedge Reset)
256
begin
257
  if(Reset)
258
    StatusLatch <= #Tp 1'b0;
259
  else
260
    begin
261
      if(~TxStartFrm)
262
        StatusLatch <= #Tp 1'b0;
263
      else
264
      if(ExcessiveDeferOccured | StateIdle)
265
        StatusLatch <= #Tp 1'b1;
266
     end
267
end
268
 
269
 
270
// Transmit packet used data
271
always @ (posedge MTxClk or posedge Reset)
272
begin
273
  if(Reset)
274
    TxUsedData <= #Tp 1'b0;
275
  else
276
    TxUsedData <= #Tp |StartData;
277
end
278
 
279
 
280
// Transmit packet done
281
always @ (posedge MTxClk or posedge Reset)
282
begin
283
  if(Reset)
284
    TxDone <= #Tp 1'b0;
285
  else
286
    begin
287
      if(TxStartFrm & ~StatusLatch)
288
        TxDone <= #Tp 1'b0;
289
      else
290
      if(StartTxDone)
291
        TxDone <= #Tp 1'b1;
292
    end
293
end
294
 
295
 
296
// Transmit packet retry
297
always @ (posedge MTxClk or posedge Reset)
298
begin
299
  if(Reset)
300
    TxRetry <= #Tp 1'b0;
301
  else
302
    begin
303
      if(TxStartFrm & ~StatusLatch)
304
        TxRetry <= #Tp 1'b0;
305
      else
306
      if(StartTxRetry)
307
        TxRetry <= #Tp 1'b1;
308
     end
309
end
310
 
311
 
312
// Transmit packet abort
313
always @ (posedge MTxClk or posedge Reset)
314
begin
315
  if(Reset)
316
    TxAbort <= #Tp 1'b0;
317
  else
318
    begin
319
      if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
320
        TxAbort <= #Tp 1'b0;
321
      else
322
      if(StartTxAbort)
323
        TxAbort <= #Tp 1'b1;
324
    end
325
end
326
 
327
 
328
// Retry counter
329
always @ (posedge MTxClk or posedge Reset)
330
begin
331
  if(Reset)
332
    RetryCnt[3:0] <= #Tp 4'h0;
333
  else
334
    begin
335
      if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
336
          | StateJam & NibCntEq7 & (~ColWindow | RetryMax))
337
        RetryCnt[3:0] <= #Tp 4'h0;
338
      else
339
      if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
340
        RetryCnt[3:0] <= #Tp RetryCnt[3:0] + 1'b1;
341
    end
342
end
343
 
344
 
345
assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
346
 
347
 
348
// Transmit nibble
349
always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
350
          Crc or NibCnt or NibCntEq15)
351
begin
352
  if(StateData[0])
353
    MTxD_d[3:0] = TxData[3:0];                                  // Lower nibble
354
  else
355
  if(StateData[1])
356
    MTxD_d[3:0] = TxData[7:4];                                  // Higher nibble
357
  else
358
  if(StateFCS)
359
    MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]};     // Crc
360
  else
361
  if(StateJam)
362
    MTxD_d[3:0] = 4'h9;                                         // Jam pattern
363
  else
364
  if(StatePreamble)
365
    if(NibCntEq15)
366
      MTxD_d[3:0] = 4'hd;                                       // SFD
367
    else
368
      MTxD_d[3:0] = 4'h5;                                       // Preamble
369
  else
370
    MTxD_d[3:0] = 4'h0;
371
end
372
 
373
 
374
// Transmit Enable
375
always @ (posedge MTxClk or posedge Reset)
376
begin
377
  if(Reset)
378
    MTxEn <= #Tp 1'b0;
379
  else
380 18 mohor
    MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
381 15 mohor
end
382
 
383
 
384
// Transmit nibble
385
always @ (posedge MTxClk or posedge Reset)
386
begin
387
  if(Reset)
388
    MTxD[3:0] <= #Tp 4'h0;
389
  else
390
    MTxD[3:0] <= #Tp MTxD_d[3:0];
391
end
392
 
393
 
394
// Transmit error
395
always @ (posedge MTxClk or posedge Reset)
396
begin
397
  if(Reset)
398
    MTxErr <= #Tp 1'b0;
399
  else
400
    MTxErr <= #Tp TooBig | UnderRun;
401
end
402
 
403
 
404
// WillTransmit
405
always @ (posedge MTxClk or posedge Reset)
406
begin
407
  if(Reset)
408
    WillTransmit <= #Tp  1'b0;
409
  else
410 18 mohor
    WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
411 15 mohor
end
412
 
413
 
414
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
415
 
416
 
417
// Packet finished
418
always @ (posedge MTxClk or posedge Reset)
419
begin
420
  if(Reset)
421
    begin
422
      PacketFinished <= #Tp 1'b0;
423
      PacketFinished_q  <= #Tp 1'b0;
424
    end
425
  else
426
    begin
427
      PacketFinished <= #Tp PacketFinished_d;
428
      PacketFinished_q  <= #Tp PacketFinished;
429
    end
430
end
431
 
432
 
433
// Connecting module Counters
434
eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
435
                            .StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
436
                            .StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
437
                            .StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
438
                            .Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
439
                            .PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
440
                            .StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
441
                            .NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
442
                            .DlyCrcCnt(DlyCrcCnt)
443
                           );
444
 
445
 
446
// Connecting module StateM
447
eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
448
                        .NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
449
                        .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
450
                        .UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
451
                        .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
452
                        .NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
453
                        .NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
454
                        .StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
455
                        .StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
456
                        .StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
457 277 mohor
                        .StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
458 15 mohor
                       );
459
 
460
 
461
wire Enable_Crc;
462
wire [3:0] Data_Crc;
463
wire Initialize_Crc;
464
 
465
assign Enable_Crc = ~StateFCS;
466
 
467
assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
468
assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
469
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
470
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
471
 
472 18 mohor
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
473 15 mohor
 
474
 
475
// Connecting module Crc
476
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
477
               .Crc(Crc), .CrcError(CrcError)
478
              );
479
 
480
 
481
// Connecting module Random
482
eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
483
                    .NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
484
 
485
 
486
 
487
 
488
endmodule

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