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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_txethmac.v] - Blame information for rev 37

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1 15 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_txethmac.v                                              ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
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////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
//
43
// CVS Revision History
44
//
45
// $Log: not supported by cvs2svn $
46 37 mohor
// Revision 1.3  2001/10/19 08:43:51  mohor
47
// eth_timescale.v changed to timescale.v This is done because of the
48
// simulation of the few cores in a one joined project.
49
//
50 22 mohor
// Revision 1.2  2001/09/11 14:17:00  mohor
51
// Few little NCSIM warnings fixed.
52
//
53 18 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
54
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
55
// Include files fixed to contain no path.
56
// File names and module names changed ta have a eth_ prologue in the name.
57
// File eth_timescale.v is used to define timescale
58
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
59
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
60
// and Mdo_OE. The bidirectional signal must be created on the top level. This
61
// is done due to the ASIC tools.
62
//
63 15 mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
64
// Directory structure changed. Files checked and joind together.
65
//
66
// Revision 1.3  2001/06/19 18:16:40  mohor
67
// TxClk changed to MTxClk (as discribed in the documentation).
68
// Crc changed so only one file can be used instead of two.
69
//
70
// Revision 1.2  2001/06/19 10:38:08  mohor
71
// Minor changes in header.
72
//
73
// Revision 1.1  2001/06/19 10:27:58  mohor
74
// TxEthMAC initial release.
75
//
76
//
77
//
78
 
79 22 mohor
`include "timescale.v"
80 15 mohor
 
81
 
82
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
83
                     Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
84
                     IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
85
                     MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
86
                     ResetCollision
87
                    );
88
 
89
parameter Tp = 1;
90
 
91
 
92
input MTxClk;                   // Transmit clock (from PHY)
93
input Reset;                    // Reset
94
input TxStartFrm;               // Transmit packet start frame
95
input TxEndFrm;                 // Transmit packet end frame
96
input TxUnderRun;               // Transmit packet under-run
97
input [7:0] TxData;             // Transmit packet data byte
98
input CarrierSense;             // Carrier sense (synchronized)
99
input Collision;                // Collision (synchronized)
100
input Pad;                      // Pad enable (from register)
101
input CrcEn;                    // Crc enable (from register)
102
input FullD;                    // Full duplex (from register)
103
input HugEn;                    // Huge packets enable (from register)
104
input DlyCrcEn;                 // Delayed Crc enabled (from register)
105
input [15:0] MinFL;             // Minimum frame length (from register)
106
input [15:0] MaxFL;             // Maximum frame length (from register)
107
input [6:0] IPGT;               // Back to back transmit inter packet gap parameter (from register)
108
input [6:0] IPGR1;              // Non back to back transmit inter packet gap parameter IPGR1 (from register)
109
input [6:0] IPGR2;              // Non back to back transmit inter packet gap parameter IPGR2 (from register)
110
input [5:0] CollValid;          // Valid collision window (from register)
111
input [3:0] MaxRet;             // Maximum retry number (from register)
112
input NoBckof;                  // No backoff (from register)
113
input ExDfrEn;                  // Excessive defferal enable (from register)
114
 
115
output [3:0] MTxD;              // Transmit nibble (to PHY)
116
output MTxEn;                   // Transmit enable (to PHY)
117
output MTxErr;                  // Transmit error (to PHY)
118
output TxDone;                  // Transmit packet done (to RISC)
119
output TxRetry;                 // Transmit packet retry (to RISC)
120
output TxAbort;                 // Transmit packet abort (to RISC)
121
output TxUsedData;              // Transmit packet used data (to RISC)
122
output WillTransmit;            // Will transmit (to RxEthMAC)
123
output ResetCollision;          // Reset Collision (for synchronizing collision)
124
 
125
reg [3:0] MTxD;
126
reg MTxEn;
127
reg MTxErr;
128
reg TxDone;
129
reg TxRetry;
130
reg TxAbort;
131
reg TxUsedData;
132
reg WillTransmit;
133
reg ColWindow;
134
reg StopExcessiveDeferOccured;
135
reg [3:0] RetryCnt;
136
reg [3:0] MTxD_d;
137
reg StatusLatch;
138
reg PacketFinished_q;
139
reg PacketFinished;
140
 
141
 
142
wire ExcessiveDeferOccured;
143
wire StartDefer;
144
wire StartIPG;
145
wire StartPreamble;
146
wire [1:0] StartData;
147
wire StartFCS;
148
wire StartJam;
149
wire StartBackoff;
150
wire StateDefer;
151
wire StateIPG;
152
wire StateIdle;
153
wire StatePreamble;
154
wire [1:0] StateData;
155
wire StatePAD;
156
wire StateFCS;
157
wire StateJam;
158
wire StateBackOff;
159
wire StateSFD;
160
wire StartTxRetry;
161
wire StartTxDone;
162
wire LateCollision;
163
wire MaxCollisionOccured;
164
wire UnderRun;
165
wire TooBig;
166
wire StartTxAbort;
167
wire [31:0] Crc;
168
wire CrcError;
169
wire [2:0] DlyCrcCnt;
170
wire [15:0] NibCnt;
171
wire NibCntEq7;
172
wire NibCntEq15;
173
wire NibbleMinFl;
174
wire ExcessiveDefer;
175
wire [15:0] ByteCnt;
176
wire MaxFrame;
177
wire RetryMax;
178
wire RandomEq0;
179
wire RandomEqByteCnt;
180
wire PacketFinished_d;
181
 
182
 
183
 
184 18 mohor
assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
185 15 mohor
 
186
assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
187
 
188
assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & ~Pad & ~CrcEn);
189
 
190
assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
191
 
192
assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
193
 
194
assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
195
 
196
assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
197
 
198
assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
199
 
200
assign StateSFD = StatePreamble & NibCntEq15;
201
 
202
assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
203
 
204
 
205
// StopExcessiveDeferOccured
206
always @ (posedge MTxClk or posedge Reset)
207
begin
208
  if(Reset)
209
    StopExcessiveDeferOccured <= #Tp 1'b0;
210
  else
211
    begin
212
      if(~TxStartFrm)
213
        StopExcessiveDeferOccured <= #Tp 1'b0;
214
      else
215
      if(ExcessiveDeferOccured)
216
        StopExcessiveDeferOccured <= #Tp 1'b1;
217
    end
218
end
219
 
220
 
221
// Collision Window
222
always @ (posedge MTxClk or posedge Reset)
223
begin
224
  if(Reset)
225
    ColWindow <= #Tp 1'b1;
226
  else
227
    begin
228
      if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
229
        ColWindow <= #Tp 1'b0;
230
      else
231
      if(StateIdle | StateIPG)
232
        ColWindow <= #Tp 1'b1;
233
    end
234
end
235
 
236
 
237
// Start Window
238
always @ (posedge MTxClk or posedge Reset)
239
begin
240
  if(Reset)
241
    StatusLatch <= #Tp 1'b0;
242
  else
243
    begin
244
      if(~TxStartFrm)
245
        StatusLatch <= #Tp 1'b0;
246
      else
247
      if(ExcessiveDeferOccured | StateIdle)
248
        StatusLatch <= #Tp 1'b1;
249
     end
250
end
251
 
252
 
253
// Transmit packet used data
254
always @ (posedge MTxClk or posedge Reset)
255
begin
256
  if(Reset)
257
    TxUsedData <= #Tp 1'b0;
258
  else
259
    TxUsedData <= #Tp |StartData;
260
end
261
 
262
 
263
// Transmit packet done
264
always @ (posedge MTxClk or posedge Reset)
265
begin
266
  if(Reset)
267
    TxDone <= #Tp 1'b0;
268
  else
269
    begin
270
      if(TxStartFrm & ~StatusLatch)
271
        TxDone <= #Tp 1'b0;
272
      else
273
      if(StartTxDone)
274
        TxDone <= #Tp 1'b1;
275
    end
276
end
277
 
278
 
279
// Transmit packet retry
280
always @ (posedge MTxClk or posedge Reset)
281
begin
282
  if(Reset)
283
    TxRetry <= #Tp 1'b0;
284
  else
285
    begin
286
      if(TxStartFrm & ~StatusLatch)
287
        TxRetry <= #Tp 1'b0;
288
      else
289
      if(StartTxRetry)
290
        TxRetry <= #Tp 1'b1;
291
     end
292
end
293
 
294
 
295
// Transmit packet abort
296
always @ (posedge MTxClk or posedge Reset)
297
begin
298
  if(Reset)
299
    TxAbort <= #Tp 1'b0;
300
  else
301
    begin
302
      if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
303
        TxAbort <= #Tp 1'b0;
304
      else
305
      if(StartTxAbort)
306
        TxAbort <= #Tp 1'b1;
307
    end
308
end
309
 
310
 
311
// Retry counter
312
always @ (posedge MTxClk or posedge Reset)
313
begin
314
  if(Reset)
315
    RetryCnt[3:0] <= #Tp 4'h0;
316
  else
317
    begin
318
      if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
319
          | StateJam & NibCntEq7 & (~ColWindow | RetryMax))
320
        RetryCnt[3:0] <= #Tp 4'h0;
321
      else
322
      if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
323
        RetryCnt[3:0] <= #Tp RetryCnt[3:0] + 1'b1;
324
    end
325
end
326
 
327
 
328
assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
329
 
330
 
331
// Transmit nibble
332
always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
333
          Crc or NibCnt or NibCntEq15)
334
begin
335
  if(StateData[0])
336
    MTxD_d[3:0] = TxData[3:0];                                  // Lower nibble
337
  else
338
  if(StateData[1])
339
    MTxD_d[3:0] = TxData[7:4];                                  // Higher nibble
340
  else
341
  if(StateFCS)
342
    MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]};     // Crc
343
  else
344
  if(StateJam)
345
    MTxD_d[3:0] = 4'h9;                                         // Jam pattern
346
  else
347
  if(StatePreamble)
348
    if(NibCntEq15)
349
      MTxD_d[3:0] = 4'hd;                                       // SFD
350
    else
351
      MTxD_d[3:0] = 4'h5;                                       // Preamble
352
  else
353
    MTxD_d[3:0] = 4'h0;
354
end
355
 
356
 
357
// Transmit Enable
358
always @ (posedge MTxClk or posedge Reset)
359
begin
360
  if(Reset)
361
    MTxEn <= #Tp 1'b0;
362
  else
363 18 mohor
    MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
364 15 mohor
end
365
 
366
 
367
// Transmit nibble
368
always @ (posedge MTxClk or posedge Reset)
369
begin
370
  if(Reset)
371
    MTxD[3:0] <= #Tp 4'h0;
372
  else
373
    MTxD[3:0] <= #Tp MTxD_d[3:0];
374
end
375
 
376
 
377
// Transmit error
378
always @ (posedge MTxClk or posedge Reset)
379
begin
380
  if(Reset)
381
    MTxErr <= #Tp 1'b0;
382
  else
383
    MTxErr <= #Tp TooBig | UnderRun;
384
end
385
 
386
 
387
// WillTransmit
388
always @ (posedge MTxClk or posedge Reset)
389
begin
390
  if(Reset)
391
    WillTransmit <= #Tp  1'b0;
392
  else
393 18 mohor
    WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
394 15 mohor
end
395
 
396
 
397
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
398
 
399
 
400
// Packet finished
401
always @ (posedge MTxClk or posedge Reset)
402
begin
403
  if(Reset)
404
    begin
405
      PacketFinished <= #Tp 1'b0;
406
      PacketFinished_q  <= #Tp 1'b0;
407
    end
408
  else
409
    begin
410
      PacketFinished <= #Tp PacketFinished_d;
411
      PacketFinished_q  <= #Tp PacketFinished;
412
    end
413
end
414
 
415
 
416
// Connecting module Counters
417
eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
418
                            .StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
419
                            .StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
420
                            .StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
421
                            .Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
422
                            .PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
423
                            .StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
424
                            .NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
425
                            .DlyCrcCnt(DlyCrcCnt)
426
                           );
427
 
428
 
429
// Connecting module StateM
430
eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
431
                        .NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
432
                        .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
433
                        .UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
434
                        .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
435
                        .NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
436
                        .NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
437
                        .StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
438
                        .StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
439
                        .StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
440
                        .StartDefer(StartDefer), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
441
                       );
442
 
443
 
444
wire Enable_Crc;
445
wire [3:0] Data_Crc;
446
wire Initialize_Crc;
447
 
448
assign Enable_Crc = ~StateFCS;
449
 
450
assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
451
assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
452
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
453
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
454
 
455 18 mohor
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
456 15 mohor
 
457
 
458
// Connecting module Crc
459
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
460
               .Crc(Crc), .CrcError(CrcError)
461
              );
462
 
463
 
464
// Connecting module Random
465
eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
466
                    .NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
467
 
468
 
469
 
470
 
471
endmodule

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