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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 229

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1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 166 mohor
////  All additional information is available in the Readme.txt   ////
12 38 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 229 mohor
// Revision 1.42  2002/10/18 17:04:20  tadejm
45
// Changed BIST scan signals.
46
//
47 227 tadejm
// Revision 1.41  2002/10/18 15:42:09  tadejm
48
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
49
//
50 226 tadejm
// Revision 1.40  2002/10/14 16:07:02  mohor
51
// TxStatus is written after last access to the TX fifo is finished (in case of abort
52
// or retry). TxDone is fixed.
53
//
54 221 mohor
// Revision 1.39  2002/10/11 15:35:20  mohor
55
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
56
// TxDone and TxRetry are generated after the current WISHBONE access is
57
// finished.
58
//
59 219 mohor
// Revision 1.38  2002/10/10 16:29:30  mohor
60
// BIST added.
61
//
62 210 mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
63
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
64
//
65 167 mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
66
// Reception is possible after RxPointer is read and not after BD is read. For
67
// that reason RxBDReady is changed to RxReady.
68
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
69
// comes, interrupt is generated.
70
//
71 166 mohor
// Revision 1.35  2002/09/10 10:35:23  mohor
72
// Ethernet debug registers removed.
73
//
74 164 mohor
// Revision 1.34  2002/09/08 16:31:49  mohor
75
// Async reset for WB_ACK_O removed (when core was in reset, it was
76
// impossible to access BDs).
77
// RxPointers and TxPointers names changed to be more descriptive.
78
// TxUnderRun synchronized.
79
//
80 159 mohor
// Revision 1.33  2002/09/04 18:47:57  mohor
81
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
82
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
83
// was not used OK.
84
//
85 150 mohor
// Revision 1.32  2002/08/14 19:31:48  mohor
86
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
87
// need to multiply or devide any more.
88
//
89 134 mohor
// Revision 1.31  2002/07/25 18:29:01  mohor
90
// WriteRxDataToMemory signal changed so end of frame (when last word is
91
// written to fifo) is changed.
92
//
93 127 mohor
// Revision 1.30  2002/07/23 15:28:31  mohor
94
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
95
//
96 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
97
// ShiftEnded synchronization changed.
98
//
99 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
100
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
101
//
102 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
103
// RxPointer bug fixed.
104
//
105 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
106
// Previous bug wasn't succesfully removed. Now fixed.
107
//
108 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
109
// Master state machine had a bug when switching from master write to
110
// master read.
111
//
112 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
113
// m_wb_cyc_o signal released after every single transfer.
114
//
115 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
116
// Outputs registered. Reset changed for eth_wishbone module.
117
//
118 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
119
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
120
// bug fixed.
121
//
122 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
123
// Small typo fixed.
124
//
125 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
126
// Any address can be used for Tx and Rx BD pointers. Address does not need
127
// to be aligned.
128
//
129 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
130
// Comments in Slovene language removed.
131
//
132 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
133
// casex changed with case, fifo reset changed.
134
//
135 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
136
// rx_fifo was not always cleared ok. Fixed.
137
//
138 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
139
// Status was not latched correctly sometimes. Fixed.
140
//
141 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
142
// Big Endian problem when sending frames fixed.
143
//
144 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
145
// Byte ordering changed (Big Endian used). casex changed with case because
146
// Xilinx Foundation had problems. Tested in HW. It WORKS.
147
//
148 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
149
// Small fixes for external/internal DMA missmatches.
150
//
151 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
152
// Interrupts changed
153
//
154 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
155
// Status was not written correctly when frames were discarted because of
156
// address mismatch.
157
//
158 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
159
// RxStartFrm cleared when abort or retry comes.
160
//
161 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
162
// Changes that were lost when updating from 1.5 to 1.8 fixed.
163
//
164 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
165
// Addition  of new module eth_addrcheck.v
166
//
167
// Revision 1.7  2002/02/12 17:03:47  mohor
168
// RxOverRun added to statuses.
169
//
170
// Revision 1.6  2002/02/11 09:18:22  mohor
171
// Tx status is written back to the BD.
172
//
173 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
174
// Rx status is written back to the BD.
175
//
176 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
177
// non-DMA host interface added. Select the right configutation in eth_defines.
178
//
179 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
180
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
181
// MHz. Statuses, overrun, control frame transmission and reception still  need
182
// to be fixed.
183
//
184 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
185
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
186
// added.
187
//
188 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
189
// Initial version. Equals to eth_wishbonedma.v at this moment.
190 38 mohor
//
191
//
192
//
193
 
194
`include "eth_defines.v"
195
`include "timescale.v"
196
 
197
 
198
module eth_wishbone
199
   (
200
 
201
    // WISHBONE common
202 40 mohor
    WB_CLK_I, WB_DAT_I, WB_DAT_O,
203 38 mohor
 
204
    // WISHBONE slave
205 77 mohor
                WB_ADR_I, WB_WE_I, WB_ACK_O,
206 40 mohor
    BDCs,
207 38 mohor
 
208 40 mohor
    Reset,
209
 
210 39 mohor
    // WISHBONE master
211
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
212
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
213
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
214
 
215 219 mohor
`ifdef ETH_WISHBONE_B3
216
    m_wb_cti_o, m_wb_bte_o,
217
`endif
218
 
219 38 mohor
    //TX
220 60 mohor
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
221 150 mohor
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
222 38 mohor
    PerPacketPad,
223
 
224
    //RX
225 40 mohor
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
226 38 mohor
 
227
    // Register
228 150 mohor
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr,
229 38 mohor
 
230
    // Interrupts
231 150 mohor
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
232 42 mohor
 
233 60 mohor
    // Rx Status
234 42 mohor
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
235 77 mohor
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
236 60 mohor
 
237
    // Tx Status
238 164 mohor
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
239
 
240 210 mohor
    // Bist
241
`ifdef ETH_BIST
242 227 tadejm
    ,
243
    // debug chain signals
244
    scanb_rst,      // bist scan reset
245
    scanb_clk,      // bist scan clock
246
    scanb_si,       // bist scan serial in
247
    scanb_so,       // bist scan serial out
248
    scanb_en        // bist scan shift enable
249 210 mohor
`endif
250
 
251
 
252
 
253 38 mohor
                );
254
 
255
 
256
parameter Tp = 1;
257
 
258 150 mohor
 
259 38 mohor
// WISHBONE common
260
input           WB_CLK_I;       // WISHBONE clock
261
input  [31:0]   WB_DAT_I;       // WISHBONE data input
262
output [31:0]   WB_DAT_O;       // WISHBONE data output
263
 
264
// WISHBONE slave
265
input   [9:2]   WB_ADR_I;       // WISHBONE address input
266
input           WB_WE_I;        // WISHBONE write enable input
267
input           BDCs;           // Buffer descriptors are selected
268
output          WB_ACK_O;       // WISHBONE acknowledge output
269
 
270 39 mohor
// WISHBONE master
271
output  [31:0]  m_wb_adr_o;     // 
272
output   [3:0]  m_wb_sel_o;     // 
273
output          m_wb_we_o;      // 
274
output  [31:0]  m_wb_dat_o;     // 
275
output          m_wb_cyc_o;     // 
276
output          m_wb_stb_o;     // 
277
input   [31:0]  m_wb_dat_i;     // 
278
input           m_wb_ack_i;     // 
279
input           m_wb_err_i;     // 
280
 
281 219 mohor
`ifdef ETH_WISHBONE_B3
282
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
283
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
284
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
285
`endif
286
 
287 40 mohor
input           Reset;       // Reset signal
288 39 mohor
 
289 60 mohor
// Rx Status signals
290 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
291
input           LatchedCrcError;  // CRC error
292
input           RxLateCollision;  // Late collision occured while receiving frame
293
input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
294
input           DribbleNibble;    // Extra nibble received
295
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
296
input    [15:0] RxLength;         // Length of the incoming frame
297
input           LoadRxStatus;     // Rx status was loaded
298 77 mohor
input           ReceivedPacketGood;// Received packet's length and CRC are good
299 39 mohor
 
300 60 mohor
// Tx Status signals
301
input     [3:0] RetryCntLatched;  // Latched Retry Counter
302
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
303
input           LateCollLatched;  // Late collision occured
304
input           DeferLatched;     // Defer indication (Frame was defered before sucessfully sent)
305
input           CarrierSenseLost; // Carrier Sense was lost during the frame transmission
306
 
307 38 mohor
// Tx
308
input           MTxClk;         // Transmit clock (from PHY)
309
input           TxUsedData;     // Transmit packet used data
310
input           TxRetry;        // Transmit packet retry
311
input           TxAbort;        // Transmit packet abort
312
input           TxDone;         // Transmission ended
313
output          TxStartFrm;     // Transmit packet start frame
314
output          TxEndFrm;       // Transmit packet end frame
315
output  [7:0]   TxData;         // Transmit packet data byte
316
output          TxUnderRun;     // Transmit packet under-run
317
output          PerPacketCrcEn; // Per packet crc enable
318
output          PerPacketPad;   // Per packet pading
319
 
320
// Rx
321
input           MRxClk;         // Receive clock (from PHY)
322
input   [7:0]   RxData;         // Received data byte (from PHY)
323
input           RxValid;        // 
324
input           RxStartFrm;     // 
325
input           RxEndFrm;       // 
326 40 mohor
input           RxAbort;        // This signal is set when address doesn't match.
327 38 mohor
 
328
//Register
329
input           r_TxEn;         // Transmit enable
330
input           r_RxEn;         // Receive enable
331
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
332
input           TX_BD_NUM_Wr;   // RxBDNumber written
333
 
334
// Interrupts
335
output TxB_IRQ;
336
output TxE_IRQ;
337
output RxB_IRQ;
338 77 mohor
output RxE_IRQ;
339 38 mohor
output Busy_IRQ;
340
 
341 77 mohor
 
342 210 mohor
// Bist
343
`ifdef ETH_BIST
344 227 tadejm
input   scanb_rst;      // bist scan reset
345
input   scanb_clk;      // bist scan clock
346
input   scanb_si;       // bist scan serial in
347
output  scanb_so;       // bist scan serial out
348
input   scanb_en;       // bist scan shift enable
349 210 mohor
`endif
350
 
351 77 mohor
reg TxB_IRQ;
352
reg TxE_IRQ;
353
reg RxB_IRQ;
354
reg RxE_IRQ;
355
 
356 38 mohor
reg             TxStartFrm;
357
reg             TxEndFrm;
358
reg     [7:0]   TxData;
359
 
360
reg             TxUnderRun;
361 60 mohor
reg             TxUnderRun_wb;
362 38 mohor
 
363
reg             TxBDRead;
364 39 mohor
wire            TxStatusWrite;
365 38 mohor
 
366
reg     [1:0]   TxValidBytesLatched;
367
 
368
reg    [15:0]   TxLength;
369 60 mohor
reg    [15:0]   LatchedTxLength;
370
reg   [14:11]   TxStatus;
371 38 mohor
 
372 60 mohor
reg   [14:13]   RxStatus;
373 38 mohor
 
374
reg             TxStartFrm_wb;
375
reg             TxRetry_wb;
376 39 mohor
reg             TxAbort_wb;
377 38 mohor
reg             TxDone_wb;
378
 
379
reg             TxDone_wb_q;
380
reg             TxAbort_wb_q;
381 39 mohor
reg             TxRetry_wb_q;
382 219 mohor
reg             TxRetryPacket;
383 221 mohor
reg             TxRetryPacket_NotCleared;
384
reg             TxDonePacket;
385
reg             TxDonePacket_NotCleared;
386 219 mohor
reg             TxAbortPacket;
387 221 mohor
reg             TxAbortPacket_NotCleared;
388 38 mohor
reg             RxBDReady;
389 166 mohor
reg             RxReady;
390 38 mohor
reg             TxBDReady;
391
 
392
reg             RxBDRead;
393 40 mohor
wire            RxStatusWrite;
394 38 mohor
 
395
reg    [31:0]   TxDataLatched;
396
reg     [1:0]   TxByteCnt;
397
reg             LastWord;
398 39 mohor
reg             ReadTxDataFromFifo_tck;
399 38 mohor
 
400
reg             BlockingTxStatusWrite;
401
reg             BlockingTxBDRead;
402
 
403 40 mohor
reg             Flop;
404 38 mohor
 
405
reg     [7:0]   TxBDAddress;
406
reg     [7:0]   RxBDAddress;
407
 
408
reg             TxRetrySync1;
409
reg             TxAbortSync1;
410 39 mohor
reg             TxDoneSync1;
411 38 mohor
 
412
reg             TxAbort_q;
413
reg             TxRetry_q;
414
reg             TxUsedData_q;
415
 
416
reg    [31:0]   RxDataLatched2;
417 82 mohor
 
418
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
419
 
420 38 mohor
reg     [1:0]   RxValidBytes;
421
reg     [1:0]   RxByteCnt;
422
reg             LastByteIn;
423
reg             ShiftWillEnd;
424
 
425 40 mohor
reg             WriteRxDataToFifo;
426 42 mohor
reg    [15:0]   LatchedRxLength;
427 64 mohor
reg             RxAbortLatched;
428 38 mohor
 
429 40 mohor
reg             ShiftEnded;
430 60 mohor
reg             RxOverrun;
431 38 mohor
 
432 40 mohor
reg             BDWrite;                    // BD Write Enable for access from WISHBONE side
433
reg             BDRead;                     // BD Read access from WISHBONE side
434 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
435
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
436 38 mohor
 
437 39 mohor
reg             TxEndFrm_wb;
438 38 mohor
 
439 39 mohor
wire            TxRetryPulse;
440 38 mohor
wire            TxDonePulse;
441
wire            TxAbortPulse;
442
 
443
wire            StartRxBDRead;
444
 
445
wire            StartTxBDRead;
446
 
447
wire            TxIRQEn;
448
wire            WrapTxStatusBit;
449
 
450 77 mohor
wire            RxIRQEn;
451 38 mohor
wire            WrapRxStatusBit;
452
 
453
wire    [1:0]   TxValidBytes;
454
 
455
wire    [7:0]   TempTxBDAddress;
456
wire    [7:0]   TempRxBDAddress;
457
 
458
wire            SetGotData;
459
wire            GotDataEvaluate;
460
 
461 106 mohor
reg             WB_ACK_O;
462 38 mohor
 
463 60 mohor
wire    [6:0]   RxStatusIn;
464
reg     [6:0]   RxStatusInLatched;
465 42 mohor
 
466 39 mohor
reg WbEn, WbEn_q;
467
reg RxEn, RxEn_q;
468
reg TxEn, TxEn_q;
469 38 mohor
 
470 39 mohor
wire ram_ce;
471
wire ram_we;
472
wire ram_oe;
473
reg [7:0]   ram_addr;
474
reg [31:0]  ram_di;
475
wire [31:0] ram_do;
476 38 mohor
 
477 39 mohor
wire StartTxPointerRead;
478
reg  TxPointerRead;
479
reg TxEn_needed;
480 40 mohor
reg RxEn_needed;
481 38 mohor
 
482 40 mohor
wire StartRxPointerRead;
483
reg RxPointerRead;
484 38 mohor
 
485 219 mohor
`ifdef ETH_WISHBONE_B3
486
assign m_wb_bte_o = 2'b00;    // Linear burst
487
`endif
488 39 mohor
 
489 219 mohor
 
490 159 mohor
always @ (posedge WB_CLK_I)
491 40 mohor
begin
492 159 mohor
  WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
493 40 mohor
end
494 39 mohor
 
495 106 mohor
assign WB_DAT_O = ram_do;
496 39 mohor
 
497 41 mohor
// Generic synchronous single-port RAM interface
498 119 mohor
eth_spram_256x32 bd_ram (
499 226 tadejm
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
500 210 mohor
`ifdef ETH_BIST
501 227 tadejm
  ,
502
  .scanb_rst      (scanb_rst),
503
  .scanb_clk      (scanb_clk),
504
  .scanb_si       (scanb_si),
505
  .scanb_so       (scanb_so),
506
  .scanb_en       (scanb_en)
507 210 mohor
`endif
508 39 mohor
);
509 41 mohor
 
510 39 mohor
assign ram_ce = 1'b1;
511 40 mohor
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
512 61 mohor
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
513 39 mohor
 
514
 
515 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
516 38 mohor
begin
517 40 mohor
  if(Reset)
518 39 mohor
    TxEn_needed <=#Tp 1'b0;
519 38 mohor
  else
520 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
521 39 mohor
    TxEn_needed <=#Tp 1'b1;
522
  else
523
  if(TxPointerRead & TxEn & TxEn_q)
524
    TxEn_needed <=#Tp 1'b0;
525 38 mohor
end
526
 
527 39 mohor
// Enabling access to the RAM for three devices.
528 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
529 39 mohor
begin
530 40 mohor
  if(Reset)
531 39 mohor
    begin
532
      WbEn <=#Tp 1'b1;
533
      RxEn <=#Tp 1'b0;
534
      TxEn <=#Tp 1'b0;
535
      ram_addr <=#Tp 8'h0;
536
      ram_di <=#Tp 32'h0;
537 77 mohor
      BDRead <=#Tp 1'b0;
538
      BDWrite <=#Tp 1'b0;
539 39 mohor
    end
540
  else
541
    begin
542
      // Switching between three stages depends on enable signals
543 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
544
        5'b100_10, 5'b100_11 :
545 39 mohor
          begin
546
            WbEn <=#Tp 1'b0;
547
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
548
            TxEn <=#Tp 1'b0;
549 40 mohor
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
550 39 mohor
            ram_di <=#Tp RxBDDataIn;
551
          end
552
        5'b100_01 :
553
          begin
554
            WbEn <=#Tp 1'b0;
555
            RxEn <=#Tp 1'b0;
556
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
557
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
558
            ram_di <=#Tp TxBDDataIn;
559
          end
560 90 mohor
        5'b010_00, 5'b010_10 :
561 39 mohor
          begin
562
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
563
            RxEn <=#Tp 1'b0;
564
            TxEn <=#Tp 1'b0;
565
            ram_addr <=#Tp WB_ADR_I[9:2];
566
            ram_di <=#Tp WB_DAT_I;
567 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
568
            BDRead <=#Tp BDCs & ~WB_WE_I;
569 39 mohor
          end
570 90 mohor
        5'b010_01, 5'b010_11 :
571 39 mohor
          begin
572
            WbEn <=#Tp 1'b0;
573
            RxEn <=#Tp 1'b0;
574
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
575
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
576
            ram_di <=#Tp TxBDDataIn;
577
          end
578 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
579 39 mohor
          begin
580
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
581
            RxEn <=#Tp 1'b0;
582
            TxEn <=#Tp 1'b0;
583
            ram_addr <=#Tp WB_ADR_I[9:2];
584
            ram_di <=#Tp WB_DAT_I;
585 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
586
            BDRead <=#Tp BDCs & ~WB_WE_I;
587 39 mohor
          end
588
        5'b100_00 :
589
          begin
590
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
591
          end
592
        5'b000_00 :
593
          begin
594
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
595
            RxEn <=#Tp 1'b0;
596
            TxEn <=#Tp 1'b0;
597
            ram_addr <=#Tp WB_ADR_I[9:2];
598
            ram_di <=#Tp WB_DAT_I;
599 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
600
            BDRead <=#Tp BDCs & ~WB_WE_I;
601 39 mohor
          end
602
      endcase
603
    end
604
end
605
 
606
 
607
// Delayed stage signals
608 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
609 39 mohor
begin
610 40 mohor
  if(Reset)
611 39 mohor
    begin
612
      WbEn_q <=#Tp 1'b0;
613
      RxEn_q <=#Tp 1'b0;
614
      TxEn_q <=#Tp 1'b0;
615
    end
616
  else
617
    begin
618
      WbEn_q <=#Tp WbEn;
619
      RxEn_q <=#Tp RxEn;
620
      TxEn_q <=#Tp TxEn;
621
    end
622
end
623
 
624 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
625 40 mohor
always @ (posedge MTxClk or posedge Reset)
626 38 mohor
begin
627 40 mohor
  if(Reset)
628 38 mohor
    Flop <=#Tp 1'b0;
629
  else
630
  if(TxDone | TxAbort | TxRetry_q)
631
    Flop <=#Tp 1'b0;
632
  else
633
  if(TxUsedData)
634
    Flop <=#Tp ~Flop;
635
end
636
 
637 39 mohor
wire ResetTxBDReady;
638
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
639 38 mohor
 
640
// Latching READY status of the Tx buffer descriptor
641 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
642 38 mohor
begin
643 40 mohor
  if(Reset)
644 38 mohor
    TxBDReady <=#Tp 1'b0;
645
  else
646 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
647
    TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
648
  else                                                // Only packets larger then 4 bytes are transmitted.
649 39 mohor
  if(ResetTxBDReady)
650 38 mohor
    TxBDReady <=#Tp 1'b0;
651
end
652
 
653
 
654 39 mohor
// Reading the Tx buffer descriptor
655 221 mohor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
656 39 mohor
 
657 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
658 38 mohor
begin
659 40 mohor
  if(Reset)
660 39 mohor
    TxBDRead <=#Tp 1'b1;
661 38 mohor
  else
662 110 mohor
  if(StartTxBDRead)
663 39 mohor
    TxBDRead <=#Tp 1'b1;
664 38 mohor
  else
665 39 mohor
  if(TxBDReady)
666
    TxBDRead <=#Tp 1'b0;
667 38 mohor
end
668
 
669
 
670 39 mohor
// Reading Tx BD pointer
671
assign StartTxPointerRead = TxBDRead & TxBDReady;
672 38 mohor
 
673 39 mohor
// Reading Tx BD Pointer
674 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
675 38 mohor
begin
676 40 mohor
  if(Reset)
677 39 mohor
    TxPointerRead <=#Tp 1'b0;
678 38 mohor
  else
679 39 mohor
  if(StartTxPointerRead)
680
    TxPointerRead <=#Tp 1'b1;
681 38 mohor
  else
682 39 mohor
  if(TxEn_q)
683
    TxPointerRead <=#Tp 1'b0;
684 38 mohor
end
685
 
686
 
687 39 mohor
// Writing status back to the Tx buffer descriptor
688 221 mohor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
689 38 mohor
 
690
 
691
 
692 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
693 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
694 38 mohor
begin
695 40 mohor
  if(Reset)
696 39 mohor
    BlockingTxStatusWrite <=#Tp 1'b0;
697 38 mohor
  else
698 39 mohor
  if(TxStatusWrite)
699
    BlockingTxStatusWrite <=#Tp 1'b1;
700 38 mohor
  else
701 39 mohor
  if(~TxDone_wb & ~TxAbort_wb)
702
    BlockingTxStatusWrite <=#Tp 1'b0;
703 38 mohor
end
704
 
705
 
706 159 mohor
reg BlockingTxStatusWrite_sync1;
707
reg BlockingTxStatusWrite_sync2;
708
 
709
// Synchronizing BlockingTxStatusWrite to MTxClk
710
always @ (posedge MTxClk or posedge Reset)
711
begin
712
  if(Reset)
713
    BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
714
  else
715
    BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
716
end
717
 
718
// Synchronizing BlockingTxStatusWrite to MTxClk
719
always @ (posedge MTxClk or posedge Reset)
720
begin
721
  if(Reset)
722
    BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
723
  else
724
    BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
725
end
726
 
727
 
728 39 mohor
// TxBDRead state is activated only once. 
729 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
730 39 mohor
begin
731 40 mohor
  if(Reset)
732 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
733
  else
734 110 mohor
  if(StartTxBDRead)
735 39 mohor
    BlockingTxBDRead <=#Tp 1'b1;
736
  else
737 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
738 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
739
end
740 38 mohor
 
741
 
742 39 mohor
// Latching status from the tx buffer descriptor
743
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
744 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
745 38 mohor
begin
746 40 mohor
  if(Reset)
747 60 mohor
    TxStatus <=#Tp 4'h0;
748 38 mohor
  else
749 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
750 60 mohor
    TxStatus <=#Tp ram_do[14:11];
751 38 mohor
end
752
 
753 40 mohor
reg ReadTxDataFromMemory;
754
wire WriteRxDataToMemory;
755 38 mohor
 
756 39 mohor
reg MasterWbTX;
757
reg MasterWbRX;
758
 
759
reg [31:0] m_wb_adr_o;
760
reg        m_wb_cyc_o;
761
reg        m_wb_stb_o;
762 96 mohor
reg  [3:0] m_wb_sel_o;
763 39 mohor
reg        m_wb_we_o;
764 40 mohor
 
765 39 mohor
wire TxLengthEq0;
766
wire TxLengthLt4;
767
 
768 150 mohor
reg BlockingIncrementTxPointer;
769 159 mohor
reg [31:2] TxPointerMSB;
770
reg [1:0]  TxPointerLSB;
771
reg [1:0]  TxPointerLSB_rst;
772
reg [31:2] RxPointerMSB;
773
reg [1:0]  RxPointerLSB_rst;
774 39 mohor
 
775 150 mohor
wire RxBurstAcc;
776
wire RxWordAcc;
777
wire RxHalfAcc;
778
wire RxByteAcc;
779
 
780 39 mohor
//Latching length from the buffer descriptor;
781 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
782 38 mohor
begin
783 40 mohor
  if(Reset)
784 39 mohor
    TxLength <=#Tp 16'h0;
785 38 mohor
  else
786 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
787
    TxLength <=#Tp ram_do[31:16];
788 38 mohor
  else
789 39 mohor
  if(MasterWbTX & m_wb_ack_i)
790
    begin
791
      if(TxLengthLt4)
792
        TxLength <=#Tp 16'h0;
793 150 mohor
      else
794 159 mohor
      if(TxPointerLSB_rst==2'h0)
795 96 mohor
        TxLength <=#Tp TxLength - 3'h4;    // Length is subtracted at the data request
796 39 mohor
      else
797 159 mohor
      if(TxPointerLSB_rst==2'h1)
798 150 mohor
        TxLength <=#Tp TxLength - 3'h3;    // Length is subtracted at the data request
799
      else
800 159 mohor
      if(TxPointerLSB_rst==2'h2)
801 150 mohor
        TxLength <=#Tp TxLength - 3'h2;    // Length is subtracted at the data request
802
      else
803 159 mohor
      if(TxPointerLSB_rst==2'h3)
804 150 mohor
        TxLength <=#Tp TxLength - 3'h1;    // Length is subtracted at the data request
805 39 mohor
    end
806 38 mohor
end
807
 
808 96 mohor
 
809
 
810 60 mohor
//Latching length from the buffer descriptor;
811
always @ (posedge WB_CLK_I or posedge Reset)
812
begin
813
  if(Reset)
814
    LatchedTxLength <=#Tp 16'h0;
815
  else
816
  if(TxEn & TxEn_q & TxBDRead)
817
    LatchedTxLength <=#Tp ram_do[31:16];
818
end
819
 
820 39 mohor
assign TxLengthEq0 = TxLength == 0;
821
assign TxLengthLt4 = TxLength < 4;
822 38 mohor
 
823 150 mohor
reg cyc_cleared;
824
reg IncrTxPointer;
825 39 mohor
 
826
 
827 159 mohor
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
828
// because TxPointerMSB is only used for word-aligned accesses.
829 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
830 38 mohor
begin
831 40 mohor
  if(Reset)
832 159 mohor
    TxPointerMSB <=#Tp 30'h0;
833 38 mohor
  else
834 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
835 159 mohor
    TxPointerMSB <=#Tp ram_do[31:2];
836 38 mohor
  else
837 150 mohor
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
838 159 mohor
    TxPointerMSB <=#Tp TxPointerMSB + 1'b1;     // TxPointer is word-aligned
839 38 mohor
end
840
 
841 96 mohor
 
842 159 mohor
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
843
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
844
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
845
// set by this two bits.
846 96 mohor
always @ (posedge WB_CLK_I or posedge Reset)
847
begin
848
  if(Reset)
849 159 mohor
    TxPointerLSB[1:0] <=#Tp 0;
850 96 mohor
  else
851
  if(TxEn & TxEn_q & TxPointerRead)
852 159 mohor
    TxPointerLSB[1:0] <=#Tp ram_do[1:0];
853 96 mohor
end
854
 
855
 
856 159 mohor
// Latching 2 MSB bits of the buffer descriptor. 
857
// After the read access, TxLength needs to be decremented for the number of the valid
858
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are 
859
// valid so this two bits are reset to zero. 
860 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
861
begin
862
  if(Reset)
863 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
864 150 mohor
  else
865
  if(TxEn & TxEn_q & TxPointerRead)
866 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
867 150 mohor
  else
868
  if(MasterWbTX & m_wb_ack_i)                 // After first access pointer is word alligned
869 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
870 150 mohor
end
871 96 mohor
 
872 150 mohor
 
873 159 mohor
reg  [3:0] RxByteSel;
874 39 mohor
wire MasterAccessFinished;
875 38 mohor
 
876 39 mohor
 
877 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
878 38 mohor
begin
879 40 mohor
  if(Reset)
880 39 mohor
    BlockingIncrementTxPointer <=#Tp 0;
881 38 mohor
  else
882 39 mohor
  if(MasterAccessFinished)
883
    BlockingIncrementTxPointer <=#Tp 0;
884 38 mohor
  else
885 150 mohor
  if(IncrTxPointer)
886 39 mohor
    BlockingIncrementTxPointer <=#Tp 1'b1;
887 38 mohor
end
888
 
889
 
890 39 mohor
wire TxBufferAlmostFull;
891
wire TxBufferFull;
892
wire TxBufferEmpty;
893
wire TxBufferAlmostEmpty;
894 40 mohor
wire SetReadTxDataFromMemory;
895 39 mohor
 
896 40 mohor
reg BlockReadTxDataFromMemory;
897 39 mohor
 
898 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
899 39 mohor
 
900 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
901 38 mohor
begin
902 40 mohor
  if(Reset)
903
    ReadTxDataFromMemory <=#Tp 1'b0;
904 38 mohor
  else
905 219 mohor
  if(TxLengthEq0 | TxAbortPacket | TxRetryPacket)
906 40 mohor
    ReadTxDataFromMemory <=#Tp 1'b0;
907 39 mohor
  else
908 40 mohor
  if(SetReadTxDataFromMemory)
909
    ReadTxDataFromMemory <=#Tp 1'b1;
910 38 mohor
end
911
 
912 226 tadejm
reg tx_burst_en;
913
reg rx_burst_en;
914 221 mohor
reg BlockingLastReadOn_Abort_Retry;
915
 
916
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory & ~BlockingLastReadOn_Abort_Retry;
917 226 tadejm
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
918 221 mohor
 
919 39 mohor
wire [31:0] TxData_wb;
920
wire ReadTxDataFromFifo_wb;
921 38 mohor
 
922 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
923 38 mohor
begin
924 40 mohor
  if(Reset)
925
    BlockReadTxDataFromMemory <=#Tp 1'b0;
926 38 mohor
  else
927 221 mohor
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (!(TxAbortPacket | TxRetryPacket)))
928 40 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b1;
929 219 mohor
  else
930 221 mohor
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
931 219 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b0;
932 39 mohor
end
933
 
934
 
935 221 mohor
always @ (posedge WB_CLK_I or posedge Reset)
936
begin
937
  if(Reset)
938
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
939
  else
940
  if(TxAbortPacket | TxRetryPacket)
941
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
942
  else
943
  if(((TxAbort_wb & !TxAbortPacket_NotCleared) | (TxRetry_wb & !TxRetryPacket_NotCleared)) & !TxBDReady)
944
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b1;
945
end
946 39 mohor
 
947 221 mohor
 
948
 
949
 
950 39 mohor
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
951 219 mohor
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
952
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
953 226 tadejm
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
954
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
955 159 mohor
 
956 226 tadejm
wire rx_burst;
957
wire enough_data_in_rxfifo_for_burst;
958
wire enough_data_in_rxfifo_for_burst_plus1;
959 229 mohor
 
960 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
961 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
962 39 mohor
begin
963 40 mohor
  if(Reset)
964 38 mohor
    begin
965 39 mohor
      MasterWbTX <=#Tp 1'b0;
966
      MasterWbRX <=#Tp 1'b0;
967
      m_wb_adr_o <=#Tp 32'h0;
968
      m_wb_cyc_o <=#Tp 1'b0;
969
      m_wb_stb_o <=#Tp 1'b0;
970
      m_wb_we_o  <=#Tp 1'b0;
971 96 mohor
      m_wb_sel_o <=#Tp 4'h0;
972 110 mohor
      cyc_cleared<=#Tp 1'b0;
973 226 tadejm
      tx_burst_cnt<=#Tp 0;
974
      rx_burst_cnt<=#Tp 0;
975 150 mohor
      IncrTxPointer<=#Tp 1'b0;
976 226 tadejm
      tx_burst_en<=#Tp 1'b1;
977
      rx_burst_en<=#Tp 1'b0;
978
      `ifdef ETH_WISHBONE_B3
979
        m_wb_cti_o <=#Tp 3'b0;
980
      `endif
981 38 mohor
    end
982 39 mohor
  else
983
    begin
984
      // Switching between two stages depends on enable signals
985 229 mohor
      casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst})  // synopsys parallel_case
986 226 tadejm
        8'b00_10_00_10,             // Idle and MRB needed
987 229 mohor
        8'b10_1x_10_1x,             // MRB continues
988 226 tadejm
        8'b10_10_01_10,             // Clear (previously MR) and MRB needed
989 229 mohor
        8'b01_1x_01_1x :            // Clear (previously MW) and MRB needed
990 39 mohor
          begin
991 226 tadejm
            MasterWbTX <=#Tp 1'b1;  // tx burst
992
            MasterWbRX <=#Tp 1'b0;
993
            m_wb_cyc_o <=#Tp 1'b1;
994
            m_wb_stb_o <=#Tp 1'b1;
995
            m_wb_we_o  <=#Tp 1'b0;
996
            m_wb_sel_o <=#Tp 4'hf;
997
            cyc_cleared<=#Tp 1'b0;
998
            IncrTxPointer<=#Tp 1'b1;
999
            tx_burst_cnt <=#Tp tx_burst_cnt+1;
1000
            if(tx_burst_cnt==0)
1001
              m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1002
            else
1003
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1004
 
1005
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
1006
              begin
1007
                tx_burst_en<=#Tp 1'b0;
1008
              `ifdef ETH_WISHBONE_B3
1009
                m_wb_cti_o <=#Tp 3'b111;
1010
              `endif
1011
              end
1012
            else
1013
              begin
1014
              `ifdef ETH_WISHBONE_B3
1015
                m_wb_cti_o <=#Tp 3'b010;
1016
              `endif
1017
              end
1018
          end
1019 229 mohor
        8'b00_x1_00_x1,             // Idle and MWB needed
1020
        8'b01_x1_10_x1,             // MWB continues
1021 226 tadejm
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
1022 229 mohor
        8'b10_x1_01_x1 :            // Clear (previously MR) and MWB needed
1023 226 tadejm
          begin
1024
            MasterWbTX <=#Tp 1'b0;  // rx burst
1025 39 mohor
            MasterWbRX <=#Tp 1'b1;
1026 226 tadejm
            m_wb_cyc_o <=#Tp 1'b1;
1027
            m_wb_stb_o <=#Tp 1'b1;
1028
            m_wb_we_o  <=#Tp 1'b1;
1029
            m_wb_sel_o <=#Tp RxByteSel;
1030
            IncrTxPointer<=#Tp 1'b0;
1031
            cyc_cleared<=#Tp 1'b0;
1032
            rx_burst_cnt <=#Tp rx_burst_cnt+1;
1033
 
1034
            if(rx_burst_cnt==0)
1035
              m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1036
            else
1037
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1038
 
1039
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
1040
              begin
1041
                rx_burst_en<=#Tp 1'b0;
1042
              `ifdef ETH_WISHBONE_B3
1043
                m_wb_cti_o <=#Tp 3'b111;
1044
              `endif
1045
              end
1046
            else
1047
              begin
1048
              `ifdef ETH_WISHBONE_B3
1049
                m_wb_cti_o <=#Tp 3'b010;
1050
              `endif
1051
              end
1052
          end
1053 229 mohor
        8'b00_x1_00_x0 :            // idle and MW is needed (data write to rx buffer)
1054 226 tadejm
          begin
1055
            MasterWbTX <=#Tp 1'b0;
1056
            MasterWbRX <=#Tp 1'b1;
1057 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1058 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1059
            m_wb_stb_o <=#Tp 1'b1;
1060
            m_wb_we_o  <=#Tp 1'b1;
1061 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1062 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1063 39 mohor
          end
1064 226 tadejm
        8'b00_10_00_00 :            // idle and MR is needed (data read from tx buffer)
1065 39 mohor
          begin
1066 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1067 39 mohor
            MasterWbRX <=#Tp 1'b0;
1068 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1069 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1070
            m_wb_stb_o <=#Tp 1'b1;
1071
            m_wb_we_o  <=#Tp 1'b0;
1072 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1073
            IncrTxPointer<=#Tp 1'b1;
1074 39 mohor
          end
1075 226 tadejm
        8'b10_10_01_00,             // MR and MR is needed (data read from tx buffer)
1076 229 mohor
        8'b01_1x_01_0x  :           // MW and MR is needed (data read from tx buffer)
1077 39 mohor
          begin
1078 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1079 39 mohor
            MasterWbRX <=#Tp 1'b0;
1080 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1081 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1082
            m_wb_stb_o <=#Tp 1'b1;
1083
            m_wb_we_o  <=#Tp 1'b0;
1084 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1085 110 mohor
            cyc_cleared<=#Tp 1'b0;
1086 150 mohor
            IncrTxPointer<=#Tp 1'b1;
1087 39 mohor
          end
1088 226 tadejm
        8'b01_01_01_00,             // MW and MW needed (data write to rx buffer)
1089 229 mohor
        8'b10_x1_01_x0  :           // MR and MW is needed (data write to rx buffer)
1090 39 mohor
          begin
1091 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1092 39 mohor
            MasterWbRX <=#Tp 1'b1;
1093 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1094 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1095
            m_wb_stb_o <=#Tp 1'b1;
1096 39 mohor
            m_wb_we_o  <=#Tp 1'b1;
1097 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1098 110 mohor
            cyc_cleared<=#Tp 1'b0;
1099 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1100 39 mohor
          end
1101 226 tadejm
        8'b01_01_10_00,             // MW and MW needed (cycle is cleared between previous and next access)
1102 229 mohor
        8'b01_1x_10_x0,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
1103 226 tadejm
        8'b10_10_10_00,             // MR and MR needed (cycle is cleared between previous and next access)
1104 229 mohor
        8'b10_x1_10_0x :            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
1105 39 mohor
          begin
1106 110 mohor
            m_wb_cyc_o <=#Tp 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
1107
            m_wb_stb_o <=#Tp 1'b0;
1108
            cyc_cleared<=#Tp 1'b1;
1109 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1110 226 tadejm
            tx_burst_cnt<=#Tp 0;
1111
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1112
            rx_burst_cnt<=#Tp 0;
1113
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1114
            `ifdef ETH_WISHBONE_B3
1115
              m_wb_cti_o <=#Tp 3'b0;
1116
            `endif
1117 110 mohor
          end
1118 229 mohor
        8'bxx_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1119
        8'bxx_00_01_00 :            // Between cyc_cleared request was cleared
1120 110 mohor
          begin
1121 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1122 39 mohor
            MasterWbRX <=#Tp 1'b0;
1123
            m_wb_cyc_o <=#Tp 1'b0;
1124
            m_wb_stb_o <=#Tp 1'b0;
1125 226 tadejm
            cyc_cleared<=#Tp 1'b0;
1126 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1127 226 tadejm
            rx_burst_cnt<=#Tp 0;
1128
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1129
            `ifdef ETH_WISHBONE_B3
1130
              m_wb_cti_o <=#Tp 3'b0;
1131
            `endif
1132 39 mohor
          end
1133 226 tadejm
        8'b00_00_00_00:             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1134 127 mohor
          begin
1135 226 tadejm
            tx_burst_cnt<=#Tp 0;
1136
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1137 127 mohor
          end
1138 226 tadejm
        default:                    // Don't touch
1139 82 mohor
          begin
1140
            MasterWbTX <=#Tp MasterWbTX;
1141
            MasterWbRX <=#Tp MasterWbRX;
1142
            m_wb_cyc_o <=#Tp m_wb_cyc_o;
1143
            m_wb_stb_o <=#Tp m_wb_stb_o;
1144 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_o;
1145 150 mohor
            IncrTxPointer<=#Tp IncrTxPointer;
1146 82 mohor
          end
1147 39 mohor
      endcase
1148
    end
1149 38 mohor
end
1150
 
1151 110 mohor
 
1152 39 mohor
wire TxFifoClear;
1153 96 mohor
 
1154 219 mohor
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
1155 38 mohor
 
1156 219 mohor
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
1157 150 mohor
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
1158 96 mohor
          .clk(WB_CLK_I),                                   .reset(Reset),
1159 226 tadejm
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
1160 96 mohor
          .clear(TxFifoClear),                              .full(TxBufferFull),
1161
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
1162 150 mohor
          .empty(TxBufferEmpty),                            .cnt(txfifo_cnt)
1163 96 mohor
        );
1164 39 mohor
 
1165
 
1166
reg StartOccured;
1167
reg TxStartFrm_sync1;
1168
reg TxStartFrm_sync2;
1169
reg TxStartFrm_syncb1;
1170
reg TxStartFrm_syncb2;
1171
 
1172
 
1173
 
1174
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1175 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1176 38 mohor
begin
1177 40 mohor
  if(Reset)
1178 39 mohor
    TxStartFrm_wb <=#Tp 1'b0;
1179 38 mohor
  else
1180 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1181
    TxStartFrm_wb <=#Tp 1'b1;
1182 38 mohor
  else
1183 39 mohor
  if(TxStartFrm_syncb2)
1184
    TxStartFrm_wb <=#Tp 1'b0;
1185 38 mohor
end
1186
 
1187 39 mohor
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
1188 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1189 38 mohor
begin
1190 40 mohor
  if(Reset)
1191 39 mohor
    StartOccured <=#Tp 1'b0;
1192 38 mohor
  else
1193 39 mohor
  if(TxStartFrm_wb)
1194
    StartOccured <=#Tp 1'b1;
1195 38 mohor
  else
1196 39 mohor
  if(ResetTxBDReady)
1197
    StartOccured <=#Tp 1'b0;
1198 38 mohor
end
1199
 
1200 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1201 40 mohor
always @ (posedge MTxClk or posedge Reset)
1202 39 mohor
begin
1203 40 mohor
  if(Reset)
1204 39 mohor
    TxStartFrm_sync1 <=#Tp 1'b0;
1205
  else
1206
    TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
1207
end
1208 38 mohor
 
1209 40 mohor
always @ (posedge MTxClk or posedge Reset)
1210 39 mohor
begin
1211 40 mohor
  if(Reset)
1212 39 mohor
    TxStartFrm_sync2 <=#Tp 1'b0;
1213
  else
1214
    TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
1215
end
1216
 
1217 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1218 38 mohor
begin
1219 40 mohor
  if(Reset)
1220 39 mohor
    TxStartFrm_syncb1 <=#Tp 1'b0;
1221 38 mohor
  else
1222 39 mohor
    TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
1223 38 mohor
end
1224
 
1225 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1226 38 mohor
begin
1227 40 mohor
  if(Reset)
1228 39 mohor
    TxStartFrm_syncb2 <=#Tp 1'b0;
1229 38 mohor
  else
1230 39 mohor
    TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
1231
end
1232
 
1233 40 mohor
always @ (posedge MTxClk or posedge Reset)
1234 39 mohor
begin
1235 40 mohor
  if(Reset)
1236 39 mohor
    TxStartFrm <=#Tp 1'b0;
1237 38 mohor
  else
1238 39 mohor
  if(TxStartFrm_sync2)
1239 61 mohor
    TxStartFrm <=#Tp 1'b1;
1240 39 mohor
  else
1241 61 mohor
  if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry | TxAbort))
1242 39 mohor
    TxStartFrm <=#Tp 1'b0;
1243 38 mohor
end
1244 39 mohor
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1245 38 mohor
 
1246
 
1247 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1248 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1249 38 mohor
begin
1250 40 mohor
  if(Reset)
1251 39 mohor
    TxEndFrm_wb <=#Tp 1'b0;
1252 38 mohor
  else
1253 221 mohor
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
1254 39 mohor
    TxEndFrm_wb <=#Tp 1'b1;
1255 38 mohor
  else
1256 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1257
    TxEndFrm_wb <=#Tp 1'b0;
1258 38 mohor
end
1259
 
1260
 
1261
// Marks which bytes are valid within the word.
1262 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1263 38 mohor
 
1264 39 mohor
reg LatchValidBytes;
1265
reg LatchValidBytes_q;
1266 38 mohor
 
1267 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1268 38 mohor
begin
1269 40 mohor
  if(Reset)
1270 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1271 38 mohor
  else
1272 39 mohor
  if(TxLengthLt4 & TxBDReady)
1273
    LatchValidBytes <=#Tp 1'b1;
1274 38 mohor
  else
1275 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1276 38 mohor
end
1277
 
1278 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1279 38 mohor
begin
1280 40 mohor
  if(Reset)
1281 39 mohor
    LatchValidBytes_q <=#Tp 1'b0;
1282 38 mohor
  else
1283 39 mohor
    LatchValidBytes_q <=#Tp LatchValidBytes;
1284 38 mohor
end
1285
 
1286
 
1287 39 mohor
// Latching valid bytes
1288 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1289 38 mohor
begin
1290 40 mohor
  if(Reset)
1291 39 mohor
    TxValidBytesLatched <=#Tp 2'h0;
1292 38 mohor
  else
1293 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1294
    TxValidBytesLatched <=#Tp TxValidBytes;
1295
  else
1296
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1297
    TxValidBytesLatched <=#Tp 2'h0;
1298 38 mohor
end
1299
 
1300
 
1301
assign TxIRQEn          = TxStatus[14];
1302 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1303
assign PerPacketPad     = TxStatus[12];
1304
assign PerPacketCrcEn   = TxStatus[11];
1305 38 mohor
 
1306
 
1307 77 mohor
assign RxIRQEn         = RxStatus[14];
1308 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1309 38 mohor
 
1310
 
1311
// Temporary Tx and Rx buffer descriptor address 
1312 39 mohor
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite     & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
1313 134 mohor
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum<<1)     | // Using first Rx BD
1314 39 mohor
                              {8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
1315 38 mohor
 
1316
 
1317
// Latching Tx buffer descriptor address
1318 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1319 38 mohor
begin
1320 40 mohor
  if(Reset)
1321 38 mohor
    TxBDAddress <=#Tp 8'h0;
1322
  else
1323
  if(TxStatusWrite)
1324
    TxBDAddress <=#Tp TempTxBDAddress;
1325
end
1326
 
1327
 
1328
// Latching Rx buffer descriptor address
1329 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1330 38 mohor
begin
1331 40 mohor
  if(Reset)
1332 134 mohor
    RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF<<1;
1333 38 mohor
  else
1334 77 mohor
  if(TX_BD_NUM_Wr)                        // When r_TxBDNum is updated, RxBDAddress is also
1335 134 mohor
    RxBDAddress <=#Tp WB_DAT_I[7:0]<<1;
1336 38 mohor
  else
1337
  if(RxStatusWrite)
1338
    RxBDAddress <=#Tp TempRxBDAddress;
1339
end
1340
 
1341 60 mohor
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
1342 38 mohor
 
1343 60 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 6'h0, RxStatusInLatched};
1344
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1345 38 mohor
 
1346 60 mohor
 
1347 38 mohor
// Signals used for various purposes
1348 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1349 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1350
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1351
 
1352
 
1353
 
1354 39 mohor
// Generating delayed signals
1355 40 mohor
always @ (posedge MTxClk or posedge Reset)
1356 38 mohor
begin
1357 40 mohor
  if(Reset)
1358 39 mohor
    begin
1359
      TxAbort_q      <=#Tp 1'b0;
1360
      TxRetry_q      <=#Tp 1'b0;
1361
      TxUsedData_q   <=#Tp 1'b0;
1362
    end
1363 38 mohor
  else
1364 39 mohor
    begin
1365
      TxAbort_q      <=#Tp TxAbort;
1366
      TxRetry_q      <=#Tp TxRetry;
1367
      TxUsedData_q   <=#Tp TxUsedData;
1368
    end
1369 38 mohor
end
1370
 
1371
// Generating delayed signals
1372 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1373 38 mohor
begin
1374 40 mohor
  if(Reset)
1375 38 mohor
    begin
1376 39 mohor
      TxDone_wb_q   <=#Tp 1'b0;
1377
      TxAbort_wb_q  <=#Tp 1'b0;
1378 40 mohor
      TxRetry_wb_q  <=#Tp 1'b0;
1379 38 mohor
    end
1380
  else
1381
    begin
1382 39 mohor
      TxDone_wb_q   <=#Tp TxDone_wb;
1383
      TxAbort_wb_q  <=#Tp TxAbort_wb;
1384 40 mohor
      TxRetry_wb_q  <=#Tp TxRetry_wb;
1385 38 mohor
    end
1386
end
1387
 
1388
 
1389 219 mohor
reg TxAbortPacketBlocked;
1390
always @ (posedge WB_CLK_I or posedge Reset)
1391
begin
1392
  if(Reset)
1393
    TxAbortPacket <=#Tp 1'b0;
1394
  else
1395 226 tadejm
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxAbortPacketBlocked |
1396
     TxAbort_wb & !MasterWbTX & !TxAbortPacketBlocked)
1397 219 mohor
    TxAbortPacket <=#Tp 1'b1;
1398
  else
1399
    TxAbortPacket <=#Tp 1'b0;
1400
end
1401
 
1402
 
1403
always @ (posedge WB_CLK_I or posedge Reset)
1404
begin
1405
  if(Reset)
1406 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1407
  else
1408 226 tadejm
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1409
     TxAbort_wb & !MasterWbTX)
1410 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b1;
1411
  else
1412
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1413
end
1414
 
1415
 
1416
always @ (posedge WB_CLK_I or posedge Reset)
1417
begin
1418
  if(Reset)
1419 219 mohor
    TxAbortPacketBlocked <=#Tp 1'b0;
1420
  else
1421
  if(TxAbortPacket)
1422
    TxAbortPacketBlocked <=#Tp 1'b1;
1423
  else
1424
  if(!TxAbort_wb & TxAbort_wb_q)
1425
    TxAbortPacketBlocked <=#Tp 1'b0;
1426
end
1427
 
1428
 
1429
reg TxRetryPacketBlocked;
1430
always @ (posedge WB_CLK_I or posedge Reset)
1431
begin
1432
  if(Reset)
1433
    TxRetryPacket <=#Tp 1'b0;
1434
  else
1435 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
1436
     TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1437 219 mohor
    TxRetryPacket <=#Tp 1'b1;
1438
  else
1439
    TxRetryPacket <=#Tp 1'b0;
1440
end
1441
 
1442
 
1443
always @ (posedge WB_CLK_I or posedge Reset)
1444
begin
1445
  if(Reset)
1446 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1447
  else
1448 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1449
     TxRetry_wb & !MasterWbTX)
1450 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b1;
1451
  else
1452
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1453
end
1454
 
1455
 
1456
always @ (posedge WB_CLK_I or posedge Reset)
1457
begin
1458
  if(Reset)
1459 219 mohor
    TxRetryPacketBlocked <=#Tp 1'b0;
1460
  else
1461
  if(TxRetryPacket)
1462
    TxRetryPacketBlocked <=#Tp 1'b1;
1463
  else
1464
  if(!TxRetry_wb & TxRetry_wb_q)
1465
    TxRetryPacketBlocked <=#Tp 1'b0;
1466
end
1467
 
1468
 
1469 221 mohor
reg TxDonePacketBlocked;
1470
always @ (posedge WB_CLK_I or posedge Reset)
1471
begin
1472
  if(Reset)
1473
    TxDonePacket <=#Tp 1'b0;
1474
  else
1475 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
1476
     TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
1477 221 mohor
    TxDonePacket <=#Tp 1'b1;
1478
  else
1479
    TxDonePacket <=#Tp 1'b0;
1480
end
1481
 
1482
 
1483
always @ (posedge WB_CLK_I or posedge Reset)
1484
begin
1485
  if(Reset)
1486
    TxDonePacket_NotCleared <=#Tp 1'b0;
1487
  else
1488 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1489
     TxDone_wb & !MasterWbTX)
1490 221 mohor
    TxDonePacket_NotCleared <=#Tp 1'b1;
1491
  else
1492
    TxDonePacket_NotCleared <=#Tp 1'b0;
1493
end
1494
 
1495
 
1496
always @ (posedge WB_CLK_I or posedge Reset)
1497
begin
1498
  if(Reset)
1499
    TxDonePacketBlocked <=#Tp 1'b0;
1500
  else
1501
  if(TxDonePacket)
1502
    TxDonePacketBlocked <=#Tp 1'b1;
1503
  else
1504
  if(!TxDone_wb & TxDone_wb_q)
1505
    TxDonePacketBlocked <=#Tp 1'b0;
1506
end
1507
 
1508
 
1509 38 mohor
// Sinchronizing and evaluating tx data
1510 39 mohor
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
1511 219 mohor
assign SetGotData = (TxStartFrm_wb);
1512 38 mohor
 
1513
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
1514 40 mohor
//assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1515
assign GotDataEvaluate = (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1516 38 mohor
 
1517
 
1518
// Indication of the last word
1519 40 mohor
always @ (posedge MTxClk or posedge Reset)
1520 38 mohor
begin
1521 40 mohor
  if(Reset)
1522 38 mohor
    LastWord <=#Tp 1'b0;
1523
  else
1524
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1525
    LastWord <=#Tp 1'b0;
1526
  else
1527
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1528 39 mohor
    LastWord <=#Tp TxEndFrm_wb;
1529 38 mohor
end
1530
 
1531
 
1532
// Tx end frame generation
1533 40 mohor
always @ (posedge MTxClk or posedge Reset)
1534 38 mohor
begin
1535 40 mohor
  if(Reset)
1536 38 mohor
    TxEndFrm <=#Tp 1'b0;
1537
  else
1538 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1539 38 mohor
    TxEndFrm <=#Tp 1'b0;
1540
  else
1541
  if(Flop & LastWord)
1542
    begin
1543 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1544 38 mohor
        1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
1545
        2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
1546
        3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
1547
 
1548
        default : TxEndFrm <=#Tp 1'b0;
1549
      endcase
1550
    end
1551
end
1552
 
1553
 
1554
// Tx data selection (latching)
1555 40 mohor
always @ (posedge MTxClk or posedge Reset)
1556 38 mohor
begin
1557 40 mohor
  if(Reset)
1558 96 mohor
    TxData <=#Tp 0;
1559 38 mohor
  else
1560 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1561 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1562 96 mohor
      2'h0 : TxData <=#Tp TxData_wb[31:24];                  // Big Endian Byte Ordering
1563
      2'h1 : TxData <=#Tp TxData_wb[23:16];                  // Big Endian Byte Ordering
1564
      2'h2 : TxData <=#Tp TxData_wb[15:08];                  // Big Endian Byte Ordering
1565
      2'h3 : TxData <=#Tp TxData_wb[07:00];                  // Big Endian Byte Ordering
1566
    endcase
1567 38 mohor
  else
1568 159 mohor
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1569 96 mohor
    TxData <=#Tp TxData_wb[31:24];                           // Big Endian Byte Ordering
1570
  else
1571 38 mohor
  if(TxUsedData & Flop)
1572
    begin
1573 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1574 226 tadejm
 
1575 82 mohor
        1 : TxData <=#Tp TxDataLatched[23:16];
1576
        2 : TxData <=#Tp TxDataLatched[15:8];
1577
        3 : TxData <=#Tp TxDataLatched[7:0];
1578 38 mohor
      endcase
1579
    end
1580
end
1581
 
1582
 
1583
// Latching tx data
1584 40 mohor
always @ (posedge MTxClk or posedge Reset)
1585 38 mohor
begin
1586 40 mohor
  if(Reset)
1587 38 mohor
    TxDataLatched[31:0] <=#Tp 32'h0;
1588
  else
1589 96 mohor
 if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1590 39 mohor
    TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
1591 38 mohor
end
1592
 
1593
 
1594
// Tx under run
1595 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1596 38 mohor
begin
1597 40 mohor
  if(Reset)
1598 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1599 38 mohor
  else
1600 39 mohor
  if(TxAbortPulse)
1601 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1602
  else
1603
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1604
    TxUnderRun_wb <=#Tp 1'b1;
1605
end
1606
 
1607
 
1608 159 mohor
reg TxUnderRun_sync1;
1609
 
1610 60 mohor
// Tx under run
1611
always @ (posedge MTxClk or posedge Reset)
1612
begin
1613
  if(Reset)
1614 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b0;
1615 43 mohor
  else
1616 60 mohor
  if(TxUnderRun_wb)
1617 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b1;
1618 60 mohor
  else
1619 159 mohor
  if(BlockingTxStatusWrite_sync2)
1620
    TxUnderRun_sync1 <=#Tp 1'b0;
1621
end
1622
 
1623
// Tx under run
1624
always @ (posedge MTxClk or posedge Reset)
1625
begin
1626
  if(Reset)
1627 60 mohor
    TxUnderRun <=#Tp 1'b0;
1628 159 mohor
  else
1629
  if(BlockingTxStatusWrite_sync2)
1630
    TxUnderRun <=#Tp 1'b0;
1631
  else
1632
  if(TxUnderRun_sync1)
1633
    TxUnderRun <=#Tp 1'b1;
1634 38 mohor
end
1635
 
1636
 
1637
// Tx Byte counter
1638 40 mohor
always @ (posedge MTxClk or posedge Reset)
1639 38 mohor
begin
1640 40 mohor
  if(Reset)
1641 38 mohor
    TxByteCnt <=#Tp 2'h0;
1642
  else
1643
  if(TxAbort_q | TxRetry_q)
1644
    TxByteCnt <=#Tp 2'h0;
1645
  else
1646
  if(TxStartFrm & ~TxUsedData)
1647 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1648 96 mohor
      2'h0 : TxByteCnt <=#Tp 2'h1;
1649
      2'h1 : TxByteCnt <=#Tp 2'h2;
1650
      2'h2 : TxByteCnt <=#Tp 2'h3;
1651
      2'h3 : TxByteCnt <=#Tp 2'h0;
1652
    endcase
1653 38 mohor
  else
1654
  if(TxUsedData & Flop)
1655 96 mohor
    TxByteCnt <=#Tp TxByteCnt + 1'b1;
1656 38 mohor
end
1657
 
1658 39 mohor
 
1659 150 mohor
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1660
reg ReadTxDataFromFifo_sync1;
1661
reg ReadTxDataFromFifo_sync2;
1662
reg ReadTxDataFromFifo_sync3;
1663
reg ReadTxDataFromFifo_syncb1;
1664
reg ReadTxDataFromFifo_syncb2;
1665
reg ReadTxDataFromFifo_syncb3;
1666
 
1667
 
1668
always @ (posedge MTxClk or posedge Reset)
1669
begin
1670
  if(Reset)
1671
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1672
  else
1673 96 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1674 39 mohor
     ReadTxDataFromFifo_tck <=#Tp 1'b1;
1675 150 mohor
  else
1676
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1677
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1678 38 mohor
end
1679
 
1680 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1681 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1682 38 mohor
begin
1683 40 mohor
  if(Reset)
1684 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
1685 38 mohor
  else
1686 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
1687
end
1688 38 mohor
 
1689 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1690 38 mohor
begin
1691 40 mohor
  if(Reset)
1692 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
1693 38 mohor
  else
1694 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
1695 38 mohor
end
1696
 
1697 40 mohor
always @ (posedge MTxClk or posedge Reset)
1698 38 mohor
begin
1699 40 mohor
  if(Reset)
1700 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
1701 38 mohor
  else
1702 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
1703 38 mohor
end
1704
 
1705 40 mohor
always @ (posedge MTxClk or posedge Reset)
1706 38 mohor
begin
1707 40 mohor
  if(Reset)
1708 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
1709 38 mohor
  else
1710 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
1711 38 mohor
end
1712
 
1713 150 mohor
always @ (posedge MTxClk or posedge Reset)
1714
begin
1715
  if(Reset)
1716
    ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
1717
  else
1718
    ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
1719
end
1720
 
1721 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1722 38 mohor
begin
1723 40 mohor
  if(Reset)
1724 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
1725 38 mohor
  else
1726 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
1727 38 mohor
end
1728
 
1729 39 mohor
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
1730
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1731 38 mohor
 
1732
 
1733 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1734 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1735 38 mohor
begin
1736 40 mohor
  if(Reset)
1737 39 mohor
    TxRetrySync1 <=#Tp 1'b0;
1738 38 mohor
  else
1739 39 mohor
    TxRetrySync1 <=#Tp TxRetry;
1740 38 mohor
end
1741
 
1742 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1743 38 mohor
begin
1744 40 mohor
  if(Reset)
1745 39 mohor
    TxRetry_wb <=#Tp 1'b0;
1746 38 mohor
  else
1747 39 mohor
    TxRetry_wb <=#Tp TxRetrySync1;
1748 38 mohor
end
1749
 
1750
 
1751 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1752 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1753 38 mohor
begin
1754 40 mohor
  if(Reset)
1755 39 mohor
    TxDoneSync1 <=#Tp 1'b0;
1756 38 mohor
  else
1757 39 mohor
    TxDoneSync1 <=#Tp TxDone;
1758 38 mohor
end
1759
 
1760 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1761 38 mohor
begin
1762 40 mohor
  if(Reset)
1763 39 mohor
    TxDone_wb <=#Tp 1'b0;
1764 38 mohor
  else
1765 39 mohor
    TxDone_wb <=#Tp TxDoneSync1;
1766 38 mohor
end
1767
 
1768 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1769 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1770 38 mohor
begin
1771 40 mohor
  if(Reset)
1772 39 mohor
    TxAbortSync1 <=#Tp 1'b0;
1773 38 mohor
  else
1774 39 mohor
    TxAbortSync1 <=#Tp TxAbort;
1775 38 mohor
end
1776
 
1777 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1778 38 mohor
begin
1779 40 mohor
  if(Reset)
1780 38 mohor
    TxAbort_wb <=#Tp 1'b0;
1781
  else
1782 39 mohor
    TxAbort_wb <=#Tp TxAbortSync1;
1783 38 mohor
end
1784
 
1785
 
1786 150 mohor
reg RxAbortSync1;
1787
reg RxAbortSync2;
1788
reg RxAbortSync3;
1789
reg RxAbortSync4;
1790
reg RxAbortSyncb1;
1791
reg RxAbortSyncb2;
1792 39 mohor
 
1793 150 mohor
//assign StartRxBDRead = RxStatusWrite | RxAbortLatched;
1794
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
1795
 
1796 40 mohor
// Reading the Rx buffer descriptor
1797
always @ (posedge WB_CLK_I or posedge Reset)
1798
begin
1799
  if(Reset)
1800
    RxBDRead <=#Tp 1'b1;
1801
  else
1802 166 mohor
  if(StartRxBDRead & ~RxReady)
1803 40 mohor
    RxBDRead <=#Tp 1'b1;
1804
  else
1805
  if(RxBDReady)
1806
    RxBDRead <=#Tp 1'b0;
1807
end
1808 39 mohor
 
1809
 
1810 38 mohor
// Reading of the next receive buffer descriptor starts after reception status is
1811
// written to the previous one.
1812
 
1813
// Latching READY status of the Rx buffer descriptor
1814 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1815 38 mohor
begin
1816 40 mohor
  if(Reset)
1817 38 mohor
    RxBDReady <=#Tp 1'b0;
1818
  else
1819 166 mohor
  if(RxPointerRead)
1820 150 mohor
    RxBDReady <=#Tp 1'b0;
1821
  else
1822 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1823
    RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
1824 38 mohor
end
1825
 
1826 40 mohor
// Latching Rx buffer descriptor status
1827
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
1828
always @ (posedge WB_CLK_I or posedge Reset)
1829 38 mohor
begin
1830 40 mohor
  if(Reset)
1831 60 mohor
    RxStatus <=#Tp 2'h0;
1832 38 mohor
  else
1833 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1834 60 mohor
    RxStatus <=#Tp ram_do[14:13];
1835 38 mohor
end
1836
 
1837
 
1838 166 mohor
// RxReady generation
1839
always @ (posedge WB_CLK_I or posedge Reset)
1840
begin
1841
  if(Reset)
1842
    RxReady <=#Tp 1'b0;
1843
  else
1844
  if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3)
1845
    RxReady <=#Tp 1'b0;
1846
  else
1847
  if(RxEn & RxEn_q & RxPointerRead)
1848
    RxReady <=#Tp 1'b1;
1849
end
1850 38 mohor
 
1851
 
1852 40 mohor
// Reading Rx BD pointer
1853
 
1854
 
1855
assign StartRxPointerRead = RxBDRead & RxBDReady;
1856
 
1857
// Reading Tx BD Pointer
1858
always @ (posedge WB_CLK_I or posedge Reset)
1859 38 mohor
begin
1860 40 mohor
  if(Reset)
1861
    RxPointerRead <=#Tp 1'b0;
1862 38 mohor
  else
1863 40 mohor
  if(StartRxPointerRead)
1864
    RxPointerRead <=#Tp 1'b1;
1865 38 mohor
  else
1866 166 mohor
  if(RxEn & RxEn_q)
1867 40 mohor
    RxPointerRead <=#Tp 1'b0;
1868 38 mohor
end
1869
 
1870 113 mohor
 
1871 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
1872
always @ (posedge WB_CLK_I or posedge Reset)
1873
begin
1874
  if(Reset)
1875 159 mohor
    RxPointerMSB <=#Tp 30'h0;
1876 40 mohor
  else
1877
  if(RxEn & RxEn_q & RxPointerRead)
1878 159 mohor
    RxPointerMSB <=#Tp ram_do[31:2];
1879 40 mohor
  else
1880 113 mohor
  if(MasterWbRX & m_wb_ack_i)
1881 159 mohor
      RxPointerMSB <=#Tp RxPointerMSB + 1; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
1882 40 mohor
end
1883 38 mohor
 
1884
 
1885 96 mohor
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
1886 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1887
begin
1888
  if(Reset)
1889 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp 0;
1890 96 mohor
  else
1891 159 mohor
  if(MasterWbRX & m_wb_ack_i)                 // After first write all RxByteSel are active
1892
    RxPointerLSB_rst[1:0] <=#Tp 0;
1893 96 mohor
  else
1894
  if(RxEn & RxEn_q & RxPointerRead)
1895 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
1896 96 mohor
end
1897
 
1898
 
1899 159 mohor
always @ (RxPointerLSB_rst)
1900 96 mohor
begin
1901 159 mohor
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
1902
    2'h0 : RxByteSel[3:0] = 4'hf;
1903
    2'h1 : RxByteSel[3:0] = 4'h7;
1904
    2'h2 : RxByteSel[3:0] = 4'h3;
1905
    2'h3 : RxByteSel[3:0] = 4'h1;
1906 96 mohor
  endcase
1907
end
1908
 
1909
 
1910
always @ (posedge WB_CLK_I or posedge Reset)
1911
begin
1912
  if(Reset)
1913 40 mohor
    RxEn_needed <=#Tp 1'b0;
1914 38 mohor
  else
1915 166 mohor
  if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
1916 40 mohor
    RxEn_needed <=#Tp 1'b1;
1917 38 mohor
  else
1918 40 mohor
  if(RxPointerRead & RxEn & RxEn_q)
1919
    RxEn_needed <=#Tp 1'b0;
1920 38 mohor
end
1921
 
1922
 
1923 40 mohor
// Reception status is written back to the buffer descriptor after the end of frame is detected.
1924
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
1925 38 mohor
 
1926 42 mohor
reg RxStatusWriteLatched;
1927
reg RxStatusWrite_rck;
1928
 
1929
always @ (posedge WB_CLK_I or posedge Reset)
1930
begin
1931
  if(Reset)
1932
    RxStatusWriteLatched <=#Tp 1'b0;
1933
  else
1934 87 mohor
  if(RxStatusWrite & ~RxStatusWrite_rck)
1935 42 mohor
    RxStatusWriteLatched <=#Tp 1'b1;
1936
  else
1937
  if(RxStatusWrite_rck)
1938
    RxStatusWriteLatched <=#Tp 1'b0;
1939
end
1940
 
1941
 
1942
always @ (posedge MRxClk or posedge Reset)
1943
begin
1944
  if(Reset)
1945
    RxStatusWrite_rck <=#Tp 1'b0;
1946
  else
1947 87 mohor
  if(RxStatusWriteLatched)
1948
    RxStatusWrite_rck <=#Tp 1'b1;
1949
  else
1950
    RxStatusWrite_rck <=#Tp 1'b0;
1951 42 mohor
end
1952
 
1953
 
1954 40 mohor
reg RxEnableWindow;
1955 38 mohor
 
1956
// Indicating that last byte is being reveived
1957 40 mohor
always @ (posedge MRxClk or posedge Reset)
1958 38 mohor
begin
1959 40 mohor
  if(Reset)
1960 38 mohor
    LastByteIn <=#Tp 1'b0;
1961
  else
1962 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
1963 38 mohor
    LastByteIn <=#Tp 1'b0;
1964
  else
1965 166 mohor
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
1966 38 mohor
    LastByteIn <=#Tp 1'b1;
1967
end
1968
 
1969 159 mohor
reg ShiftEnded_rck;
1970 40 mohor
reg ShiftEndedSync1;
1971
reg ShiftEndedSync2;
1972 118 mohor
reg ShiftEndedSync3;
1973
reg ShiftEndedSync_c1;
1974
reg ShiftEndedSync_c2;
1975
 
1976 40 mohor
wire StartShiftWillEnd;
1977 96 mohor
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
1978 38 mohor
 
1979
// Indicating that data reception will end
1980 40 mohor
always @ (posedge MRxClk or posedge Reset)
1981 38 mohor
begin
1982 40 mohor
  if(Reset)
1983 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1984
  else
1985 159 mohor
  if(ShiftEnded_rck | RxAbort)
1986 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1987
  else
1988 40 mohor
  if(StartShiftWillEnd)
1989 38 mohor
    ShiftWillEnd <=#Tp 1'b1;
1990
end
1991
 
1992
 
1993 40 mohor
 
1994 38 mohor
// Receive byte counter
1995 40 mohor
always @ (posedge MRxClk or posedge Reset)
1996 38 mohor
begin
1997 40 mohor
  if(Reset)
1998 38 mohor
    RxByteCnt <=#Tp 2'h0;
1999
  else
2000 159 mohor
  if(ShiftEnded_rck | RxAbort)
2001 38 mohor
    RxByteCnt <=#Tp 2'h0;
2002 97 lampret
  else
2003 166 mohor
  if(RxValid & RxStartFrm & RxReady)
2004 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2005 96 mohor
      2'h0 : RxByteCnt <=#Tp 2'h1;
2006
      2'h1 : RxByteCnt <=#Tp 2'h2;
2007
      2'h2 : RxByteCnt <=#Tp 2'h3;
2008
      2'h3 : RxByteCnt <=#Tp 2'h0;
2009
    endcase
2010 38 mohor
  else
2011 166 mohor
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
2012 40 mohor
    RxByteCnt <=#Tp RxByteCnt + 1'b1;
2013 38 mohor
end
2014
 
2015
 
2016
// Indicates how many bytes are valid within the last word
2017 40 mohor
always @ (posedge MRxClk or posedge Reset)
2018 38 mohor
begin
2019 40 mohor
  if(Reset)
2020 38 mohor
    RxValidBytes <=#Tp 2'h1;
2021
  else
2022 96 mohor
  if(RxValid & RxStartFrm)
2023 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2024 96 mohor
      2'h0 : RxValidBytes <=#Tp 2'h1;
2025
      2'h1 : RxValidBytes <=#Tp 2'h2;
2026
      2'h2 : RxValidBytes <=#Tp 2'h3;
2027
      2'h3 : RxValidBytes <=#Tp 2'h0;
2028
    endcase
2029 38 mohor
  else
2030 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
2031 38 mohor
    RxValidBytes <=#Tp RxValidBytes + 1;
2032
end
2033
 
2034
 
2035 40 mohor
always @ (posedge MRxClk or posedge Reset)
2036 38 mohor
begin
2037 40 mohor
  if(Reset)
2038
    RxDataLatched1       <=#Tp 24'h0;
2039 38 mohor
  else
2040 166 mohor
  if(RxValid & RxReady & ~LastByteIn)
2041 96 mohor
    if(RxStartFrm)
2042 40 mohor
    begin
2043 159 mohor
      case(RxPointerLSB_rst)     // synopsys parallel_case
2044 96 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2045
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2046
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2047
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2048
      endcase
2049
    end
2050
    else if (RxEnableWindow)
2051
    begin
2052 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
2053 82 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2054
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2055
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2056 40 mohor
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2057
      endcase
2058
    end
2059 38 mohor
end
2060
 
2061 40 mohor
wire SetWriteRxDataToFifo;
2062 38 mohor
 
2063 40 mohor
// Assembling data that will be written to the rx_fifo
2064
always @ (posedge MRxClk or posedge Reset)
2065 38 mohor
begin
2066 40 mohor
  if(Reset)
2067
    RxDataLatched2 <=#Tp 32'h0;
2068 38 mohor
  else
2069 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
2070 82 mohor
    RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData};              // Big Endian Byte Ordering
2071 38 mohor
  else
2072 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
2073 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
2074 82 mohor
 
2075
      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
2076
      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
2077
      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};
2078 40 mohor
    endcase
2079 38 mohor
end
2080
 
2081
 
2082 40 mohor
reg WriteRxDataToFifoSync1;
2083
reg WriteRxDataToFifoSync2;
2084 150 mohor
reg WriteRxDataToFifoSync3;
2085 38 mohor
 
2086
 
2087 40 mohor
// Indicating start of the reception process
2088 166 mohor
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
2089
                              (RxValid & RxReady &  RxStartFrm & (&RxPointerLSB_rst))           |
2090
                              (ShiftWillEnd & LastByteIn & (&RxByteCnt));
2091 38 mohor
 
2092 150 mohor
always @ (posedge MRxClk or posedge Reset)
2093
begin
2094
  if(Reset)
2095
    WriteRxDataToFifo <=#Tp 1'b0;
2096
  else
2097
  if(SetWriteRxDataToFifo & ~RxAbort)
2098
    WriteRxDataToFifo <=#Tp 1'b1;
2099
  else
2100
  if(WriteRxDataToFifoSync2 | RxAbort)
2101
    WriteRxDataToFifo <=#Tp 1'b0;
2102
end
2103 40 mohor
 
2104 150 mohor
 
2105
 
2106
always @ (posedge WB_CLK_I or posedge Reset)
2107
begin
2108
  if(Reset)
2109
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2110
  else
2111
  if(WriteRxDataToFifo)
2112
    WriteRxDataToFifoSync1 <=#Tp 1'b1;
2113
  else
2114
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2115
end
2116
 
2117
always @ (posedge WB_CLK_I or posedge Reset)
2118
begin
2119
  if(Reset)
2120
    WriteRxDataToFifoSync2 <=#Tp 1'b0;
2121
  else
2122
    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
2123
end
2124
 
2125
always @ (posedge WB_CLK_I or posedge Reset)
2126
begin
2127
  if(Reset)
2128
    WriteRxDataToFifoSync3 <=#Tp 1'b0;
2129
  else
2130
    WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
2131
end
2132
 
2133
wire WriteRxDataToFifo_wb;
2134
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
2135
 
2136
 
2137 90 mohor
reg LatchedRxStartFrm;
2138
reg SyncRxStartFrm;
2139
reg SyncRxStartFrm_q;
2140 150 mohor
reg SyncRxStartFrm_q2;
2141 90 mohor
wire RxFifoReset;
2142 40 mohor
 
2143 90 mohor
always @ (posedge MRxClk or posedge Reset)
2144
begin
2145
  if(Reset)
2146
    LatchedRxStartFrm <=#Tp 0;
2147
  else
2148 150 mohor
  if(RxStartFrm & ~SyncRxStartFrm_q)
2149 90 mohor
    LatchedRxStartFrm <=#Tp 1;
2150
  else
2151 150 mohor
  if(SyncRxStartFrm_q)
2152 90 mohor
    LatchedRxStartFrm <=#Tp 0;
2153
end
2154
 
2155
 
2156
always @ (posedge WB_CLK_I or posedge Reset)
2157
begin
2158
  if(Reset)
2159
    SyncRxStartFrm <=#Tp 0;
2160
  else
2161
  if(LatchedRxStartFrm)
2162
    SyncRxStartFrm <=#Tp 1;
2163
  else
2164
    SyncRxStartFrm <=#Tp 0;
2165
end
2166
 
2167
 
2168
always @ (posedge WB_CLK_I or posedge Reset)
2169
begin
2170
  if(Reset)
2171
    SyncRxStartFrm_q <=#Tp 0;
2172
  else
2173
    SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
2174
end
2175
 
2176 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2177
begin
2178
  if(Reset)
2179
    SyncRxStartFrm_q2 <=#Tp 0;
2180
  else
2181
    SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
2182
end
2183 90 mohor
 
2184
 
2185 150 mohor
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
2186 90 mohor
 
2187 150 mohor
 
2188 219 mohor
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
2189 88 mohor
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
2190
         .clk(WB_CLK_I),                                .reset(Reset),
2191 219 mohor
         .write(WriteRxDataToFifo_wb & ~RxBufferFull),  .read(MasterWbRX & m_wb_ack_i),
2192 90 mohor
         .clear(RxFifoReset),                           .full(RxBufferFull),
2193 118 mohor
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
2194 150 mohor
         .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)
2195 88 mohor
        );
2196 40 mohor
 
2197 226 tadejm
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
2198
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
2199 219 mohor
assign WriteRxDataToMemory = ~RxBufferEmpty;
2200 226 tadejm
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
2201 40 mohor
 
2202
 
2203
// Generation of the end-of-frame signal
2204
always @ (posedge MRxClk or posedge Reset)
2205 38 mohor
begin
2206 40 mohor
  if(Reset)
2207 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2208 38 mohor
  else
2209 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
2210 159 mohor
    ShiftEnded_rck <=#Tp 1'b1;
2211 38 mohor
  else
2212 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
2213 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2214 38 mohor
end
2215
 
2216 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2217
begin
2218
  if(Reset)
2219
    ShiftEndedSync1 <=#Tp 1'b0;
2220
  else
2221 159 mohor
    ShiftEndedSync1 <=#Tp ShiftEnded_rck;
2222 40 mohor
end
2223 38 mohor
 
2224 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2225 38 mohor
begin
2226 40 mohor
  if(Reset)
2227
    ShiftEndedSync2 <=#Tp 1'b0;
2228 38 mohor
  else
2229 90 mohor
    ShiftEndedSync2 <=#Tp ShiftEndedSync1;
2230 40 mohor
end
2231 38 mohor
 
2232 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2233
begin
2234
  if(Reset)
2235
    ShiftEndedSync3 <=#Tp 1'b0;
2236
  else
2237
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
2238
    ShiftEndedSync3 <=#Tp 1'b1;
2239
  else
2240
  if(ShiftEnded)
2241
    ShiftEndedSync3 <=#Tp 1'b0;
2242
end
2243 38 mohor
 
2244 40 mohor
// Generation of the end-of-frame signal
2245
always @ (posedge WB_CLK_I or posedge Reset)
2246 38 mohor
begin
2247 40 mohor
  if(Reset)
2248
    ShiftEnded <=#Tp 1'b0;
2249 38 mohor
  else
2250 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2251 40 mohor
    ShiftEnded <=#Tp 1'b1;
2252 38 mohor
  else
2253 40 mohor
  if(RxStatusWrite)
2254
    ShiftEnded <=#Tp 1'b0;
2255 38 mohor
end
2256
 
2257 118 mohor
always @ (posedge MRxClk or posedge Reset)
2258
begin
2259
  if(Reset)
2260
    ShiftEndedSync_c1 <=#Tp 1'b0;
2261
  else
2262
    ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
2263
end
2264 38 mohor
 
2265 118 mohor
always @ (posedge MRxClk or posedge Reset)
2266
begin
2267
  if(Reset)
2268
    ShiftEndedSync_c2 <=#Tp 1'b0;
2269
  else
2270
    ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
2271
end
2272
 
2273 40 mohor
// Generation of the end-of-frame signal
2274
always @ (posedge MRxClk or posedge Reset)
2275 38 mohor
begin
2276 40 mohor
  if(Reset)
2277
    RxEnableWindow <=#Tp 1'b0;
2278 38 mohor
  else
2279 40 mohor
  if(RxStartFrm)
2280
    RxEnableWindow <=#Tp 1'b1;
2281 38 mohor
  else
2282 40 mohor
  if(RxEndFrm | RxAbort)
2283
    RxEnableWindow <=#Tp 1'b0;
2284 38 mohor
end
2285
 
2286
 
2287 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2288 38 mohor
begin
2289 40 mohor
  if(Reset)
2290
    RxAbortSync1 <=#Tp 1'b0;
2291 38 mohor
  else
2292 150 mohor
    RxAbortSync1 <=#Tp RxAbortLatched;
2293 40 mohor
end
2294
 
2295
always @ (posedge WB_CLK_I or posedge Reset)
2296
begin
2297
  if(Reset)
2298
    RxAbortSync2 <=#Tp 1'b0;
2299 38 mohor
  else
2300 40 mohor
    RxAbortSync2 <=#Tp RxAbortSync1;
2301 38 mohor
end
2302
 
2303 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2304
begin
2305
  if(Reset)
2306
    RxAbortSync3 <=#Tp 1'b0;
2307
  else
2308
    RxAbortSync3 <=#Tp RxAbortSync2;
2309
end
2310
 
2311
always @ (posedge WB_CLK_I or posedge Reset)
2312
begin
2313
  if(Reset)
2314
    RxAbortSync4 <=#Tp 1'b0;
2315
  else
2316
    RxAbortSync4 <=#Tp RxAbortSync3;
2317
end
2318
 
2319 40 mohor
always @ (posedge MRxClk or posedge Reset)
2320
begin
2321
  if(Reset)
2322
    RxAbortSyncb1 <=#Tp 1'b0;
2323
  else
2324
    RxAbortSyncb1 <=#Tp RxAbortSync2;
2325
end
2326 38 mohor
 
2327 40 mohor
always @ (posedge MRxClk or posedge Reset)
2328 38 mohor
begin
2329 40 mohor
  if(Reset)
2330
    RxAbortSyncb2 <=#Tp 1'b0;
2331 38 mohor
  else
2332 40 mohor
    RxAbortSyncb2 <=#Tp RxAbortSyncb1;
2333 38 mohor
end
2334
 
2335
 
2336 64 mohor
always @ (posedge MRxClk or posedge Reset)
2337
begin
2338
  if(Reset)
2339
    RxAbortLatched <=#Tp 1'b0;
2340
  else
2341 150 mohor
  if(RxAbortSyncb2)
2342
    RxAbortLatched <=#Tp 1'b0;
2343
  else
2344 64 mohor
  if(RxAbort)
2345
    RxAbortLatched <=#Tp 1'b1;
2346
end
2347 40 mohor
 
2348 64 mohor
 
2349 42 mohor
always @ (posedge MRxClk or posedge Reset)
2350
begin
2351
  if(Reset)
2352
    LatchedRxLength[15:0] <=#Tp 16'h0;
2353
  else
2354 150 mohor
  if(LoadRxStatus)
2355 42 mohor
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
2356
end
2357
 
2358
 
2359 60 mohor
assign RxStatusIn = {RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
2360 42 mohor
 
2361
always @ (posedge MRxClk or posedge Reset)
2362
begin
2363
  if(Reset)
2364
    RxStatusInLatched <=#Tp 'h0;
2365
  else
2366 150 mohor
  if(LoadRxStatus)
2367 42 mohor
    RxStatusInLatched <=#Tp RxStatusIn;
2368
end
2369
 
2370
 
2371 60 mohor
// Rx overrun
2372
always @ (posedge WB_CLK_I or posedge Reset)
2373
begin
2374
  if(Reset)
2375
    RxOverrun <=#Tp 1'b0;
2376
  else
2377
  if(RxStatusWrite)
2378
    RxOverrun <=#Tp 1'b0;
2379
  else
2380
  if(RxBufferFull & WriteRxDataToFifo_wb)
2381
    RxOverrun <=#Tp 1'b1;
2382
end
2383 48 mohor
 
2384 77 mohor
 
2385
 
2386
wire TxError;
2387
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2388
 
2389
wire RxError;
2390
assign RxError = |RxStatusInLatched[6:0];
2391
 
2392
// Tx Done Interrupt
2393
always @ (posedge WB_CLK_I or posedge Reset)
2394
begin
2395
  if(Reset)
2396
    TxB_IRQ <=#Tp 1'b0;
2397
  else
2398
  if(TxStatusWrite & TxIRQEn)
2399
    TxB_IRQ <=#Tp ~TxError;
2400
  else
2401
    TxB_IRQ <=#Tp 1'b0;
2402
end
2403
 
2404
 
2405
// Tx Error Interrupt
2406
always @ (posedge WB_CLK_I or posedge Reset)
2407
begin
2408
  if(Reset)
2409
    TxE_IRQ <=#Tp 1'b0;
2410
  else
2411
  if(TxStatusWrite & TxIRQEn)
2412
    TxE_IRQ <=#Tp TxError;
2413
  else
2414
    TxE_IRQ <=#Tp 1'b0;
2415
end
2416
 
2417
 
2418
// Rx Done Interrupt
2419
always @ (posedge WB_CLK_I or posedge Reset)
2420
begin
2421
  if(Reset)
2422
    RxB_IRQ <=#Tp 1'b0;
2423
  else
2424
  if(RxStatusWrite & RxIRQEn)
2425 167 mohor
    RxB_IRQ <=#Tp ReceivedPacketGood & ~RxError;
2426 77 mohor
  else
2427
    RxB_IRQ <=#Tp 1'b0;
2428
end
2429
 
2430
 
2431
// Rx Error Interrupt
2432
always @ (posedge WB_CLK_I or posedge Reset)
2433
begin
2434
  if(Reset)
2435
    RxE_IRQ <=#Tp 1'b0;
2436
  else
2437
  if(RxStatusWrite & RxIRQEn)
2438
    RxE_IRQ <=#Tp RxError;
2439
  else
2440
    RxE_IRQ <=#Tp 1'b0;
2441
end
2442
 
2443
 
2444 166 mohor
// Busy Interrupt
2445 77 mohor
 
2446 166 mohor
reg Busy_IRQ_rck;
2447
reg Busy_IRQ_sync1;
2448
reg Busy_IRQ_sync2;
2449
reg Busy_IRQ_sync3;
2450
reg Busy_IRQ_syncb1;
2451
reg Busy_IRQ_syncb2;
2452 77 mohor
 
2453
 
2454 166 mohor
always @ (posedge MRxClk or posedge Reset)
2455
begin
2456
  if(Reset)
2457
    Busy_IRQ_rck <=#Tp 1'b0;
2458
  else
2459
  if(RxValid & RxStartFrm & ~RxReady)
2460
    Busy_IRQ_rck <=#Tp 1'b1;
2461
  else
2462
  if(Busy_IRQ_syncb2)
2463
    Busy_IRQ_rck <=#Tp 1'b0;
2464
end
2465 77 mohor
 
2466 166 mohor
always @ (posedge WB_CLK_I)
2467
begin
2468
    Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
2469
    Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
2470
    Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
2471
end
2472
 
2473
always @ (posedge MRxClk)
2474
begin
2475
    Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
2476
    Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
2477
end
2478
 
2479
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
2480
 
2481
 
2482 60 mohor
 
2483
// TX
2484 61 mohor
// bit 15 ready
2485
// bit 14 interrupt
2486
// bit 13 wrap
2487
// bit 12 pad
2488
// bit 11 crc
2489
// bit 10 last
2490
// bit 9  pause request (control frame)
2491
// bit 8  TxUnderRun          
2492
// bit 7-4 RetryCntLatched    
2493
// bit 3  retransmittion limit
2494
// bit 2  LateCollLatched        
2495
// bit 1  DeferLatched        
2496
// bit 0  CarrierSenseLost    
2497 60 mohor
 
2498
 
2499
// RX
2500
// bit 15 od rx je empty
2501 61 mohor
// bit 14 od rx je interrupt
2502 60 mohor
// bit 13 od rx je wrap
2503
// bit 12 od rx je reserved
2504
// bit 11 od rx je reserved
2505
// bit 10 od rx je reserved
2506
// bit 9  od rx je reserved
2507
// bit 8  od rx je reserved
2508 110 mohor
// bit 7  od rx je Miss
2509 60 mohor
// bit 6  od rx je RxOverrun
2510
// bit 5  od rx je InvalidSymbol
2511
// bit 4  od rx je DribbleNibble
2512
// bit 3  od rx je ReceivedPacketTooBig
2513
// bit 2  od rx je ShortFrame
2514
// bit 1  od rx je LatchedCrcError
2515
// bit 0  od rx je RxLateCollision
2516
 
2517 110 mohor
 
2518 38 mohor
endmodule
2519
 

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