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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 239

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1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 166 mohor
////  All additional information is available in the Readme.txt   ////
12 38 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 239 tadejm
// Revision 1.43  2002/10/18 20:53:34  mohor
45
// case changed to casex.
46
//
47 229 mohor
// Revision 1.42  2002/10/18 17:04:20  tadejm
48
// Changed BIST scan signals.
49
//
50 227 tadejm
// Revision 1.41  2002/10/18 15:42:09  tadejm
51
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
52
//
53 226 tadejm
// Revision 1.40  2002/10/14 16:07:02  mohor
54
// TxStatus is written after last access to the TX fifo is finished (in case of abort
55
// or retry). TxDone is fixed.
56
//
57 221 mohor
// Revision 1.39  2002/10/11 15:35:20  mohor
58
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
59
// TxDone and TxRetry are generated after the current WISHBONE access is
60
// finished.
61
//
62 219 mohor
// Revision 1.38  2002/10/10 16:29:30  mohor
63
// BIST added.
64
//
65 210 mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
66
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
67
//
68 167 mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
69
// Reception is possible after RxPointer is read and not after BD is read. For
70
// that reason RxBDReady is changed to RxReady.
71
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
72
// comes, interrupt is generated.
73
//
74 166 mohor
// Revision 1.35  2002/09/10 10:35:23  mohor
75
// Ethernet debug registers removed.
76
//
77 164 mohor
// Revision 1.34  2002/09/08 16:31:49  mohor
78
// Async reset for WB_ACK_O removed (when core was in reset, it was
79
// impossible to access BDs).
80
// RxPointers and TxPointers names changed to be more descriptive.
81
// TxUnderRun synchronized.
82
//
83 159 mohor
// Revision 1.33  2002/09/04 18:47:57  mohor
84
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
85
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
86
// was not used OK.
87
//
88 150 mohor
// Revision 1.32  2002/08/14 19:31:48  mohor
89
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
90
// need to multiply or devide any more.
91
//
92 134 mohor
// Revision 1.31  2002/07/25 18:29:01  mohor
93
// WriteRxDataToMemory signal changed so end of frame (when last word is
94
// written to fifo) is changed.
95
//
96 127 mohor
// Revision 1.30  2002/07/23 15:28:31  mohor
97
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
98
//
99 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
100
// ShiftEnded synchronization changed.
101
//
102 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
103
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
104
//
105 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
106
// RxPointer bug fixed.
107
//
108 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
109
// Previous bug wasn't succesfully removed. Now fixed.
110
//
111 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
112
// Master state machine had a bug when switching from master write to
113
// master read.
114
//
115 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
116
// m_wb_cyc_o signal released after every single transfer.
117
//
118 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
119
// Outputs registered. Reset changed for eth_wishbone module.
120
//
121 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
122
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
123
// bug fixed.
124
//
125 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
126
// Small typo fixed.
127
//
128 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
129
// Any address can be used for Tx and Rx BD pointers. Address does not need
130
// to be aligned.
131
//
132 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
133
// Comments in Slovene language removed.
134
//
135 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
136
// casex changed with case, fifo reset changed.
137
//
138 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
139
// rx_fifo was not always cleared ok. Fixed.
140
//
141 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
142
// Status was not latched correctly sometimes. Fixed.
143
//
144 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
145
// Big Endian problem when sending frames fixed.
146
//
147 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
148
// Byte ordering changed (Big Endian used). casex changed with case because
149
// Xilinx Foundation had problems. Tested in HW. It WORKS.
150
//
151 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
152
// Small fixes for external/internal DMA missmatches.
153
//
154 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
155
// Interrupts changed
156
//
157 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
158
// Status was not written correctly when frames were discarted because of
159
// address mismatch.
160
//
161 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
162
// RxStartFrm cleared when abort or retry comes.
163
//
164 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
165
// Changes that were lost when updating from 1.5 to 1.8 fixed.
166
//
167 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
168
// Addition  of new module eth_addrcheck.v
169
//
170
// Revision 1.7  2002/02/12 17:03:47  mohor
171
// RxOverRun added to statuses.
172
//
173
// Revision 1.6  2002/02/11 09:18:22  mohor
174
// Tx status is written back to the BD.
175
//
176 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
177
// Rx status is written back to the BD.
178
//
179 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
180
// non-DMA host interface added. Select the right configutation in eth_defines.
181
//
182 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
183
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
184
// MHz. Statuses, overrun, control frame transmission and reception still  need
185
// to be fixed.
186
//
187 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
188
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
189
// added.
190
//
191 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
192
// Initial version. Equals to eth_wishbonedma.v at this moment.
193 38 mohor
//
194
//
195
//
196
 
197
`include "eth_defines.v"
198
`include "timescale.v"
199
 
200
 
201
module eth_wishbone
202
   (
203
 
204
    // WISHBONE common
205 40 mohor
    WB_CLK_I, WB_DAT_I, WB_DAT_O,
206 38 mohor
 
207
    // WISHBONE slave
208 77 mohor
                WB_ADR_I, WB_WE_I, WB_ACK_O,
209 40 mohor
    BDCs,
210 38 mohor
 
211 40 mohor
    Reset,
212
 
213 39 mohor
    // WISHBONE master
214
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
215
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
216
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
217
 
218 219 mohor
`ifdef ETH_WISHBONE_B3
219
    m_wb_cti_o, m_wb_bte_o,
220
`endif
221
 
222 38 mohor
    //TX
223 60 mohor
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
224 150 mohor
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
225 38 mohor
    PerPacketPad,
226
 
227
    //RX
228 40 mohor
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
229 38 mohor
 
230
    // Register
231 150 mohor
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr,
232 38 mohor
 
233
    // Interrupts
234 150 mohor
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
235 42 mohor
 
236 60 mohor
    // Rx Status
237 42 mohor
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
238 77 mohor
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
239 60 mohor
 
240
    // Tx Status
241 164 mohor
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
242
 
243 210 mohor
    // Bist
244
`ifdef ETH_BIST
245 227 tadejm
    ,
246
    // debug chain signals
247
    scanb_rst,      // bist scan reset
248
    scanb_clk,      // bist scan clock
249
    scanb_si,       // bist scan serial in
250
    scanb_so,       // bist scan serial out
251
    scanb_en        // bist scan shift enable
252 210 mohor
`endif
253
 
254
 
255
 
256 38 mohor
                );
257
 
258
 
259
parameter Tp = 1;
260
 
261 150 mohor
 
262 38 mohor
// WISHBONE common
263
input           WB_CLK_I;       // WISHBONE clock
264
input  [31:0]   WB_DAT_I;       // WISHBONE data input
265
output [31:0]   WB_DAT_O;       // WISHBONE data output
266
 
267
// WISHBONE slave
268
input   [9:2]   WB_ADR_I;       // WISHBONE address input
269
input           WB_WE_I;        // WISHBONE write enable input
270
input           BDCs;           // Buffer descriptors are selected
271
output          WB_ACK_O;       // WISHBONE acknowledge output
272
 
273 39 mohor
// WISHBONE master
274
output  [31:0]  m_wb_adr_o;     // 
275
output   [3:0]  m_wb_sel_o;     // 
276
output          m_wb_we_o;      // 
277
output  [31:0]  m_wb_dat_o;     // 
278
output          m_wb_cyc_o;     // 
279
output          m_wb_stb_o;     // 
280
input   [31:0]  m_wb_dat_i;     // 
281
input           m_wb_ack_i;     // 
282
input           m_wb_err_i;     // 
283
 
284 219 mohor
`ifdef ETH_WISHBONE_B3
285
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
286
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
287
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
288
`endif
289
 
290 40 mohor
input           Reset;       // Reset signal
291 39 mohor
 
292 60 mohor
// Rx Status signals
293 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
294
input           LatchedCrcError;  // CRC error
295
input           RxLateCollision;  // Late collision occured while receiving frame
296
input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
297
input           DribbleNibble;    // Extra nibble received
298
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
299
input    [15:0] RxLength;         // Length of the incoming frame
300
input           LoadRxStatus;     // Rx status was loaded
301 77 mohor
input           ReceivedPacketGood;// Received packet's length and CRC are good
302 39 mohor
 
303 60 mohor
// Tx Status signals
304
input     [3:0] RetryCntLatched;  // Latched Retry Counter
305
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
306
input           LateCollLatched;  // Late collision occured
307
input           DeferLatched;     // Defer indication (Frame was defered before sucessfully sent)
308
input           CarrierSenseLost; // Carrier Sense was lost during the frame transmission
309
 
310 38 mohor
// Tx
311
input           MTxClk;         // Transmit clock (from PHY)
312
input           TxUsedData;     // Transmit packet used data
313
input           TxRetry;        // Transmit packet retry
314
input           TxAbort;        // Transmit packet abort
315
input           TxDone;         // Transmission ended
316
output          TxStartFrm;     // Transmit packet start frame
317
output          TxEndFrm;       // Transmit packet end frame
318
output  [7:0]   TxData;         // Transmit packet data byte
319
output          TxUnderRun;     // Transmit packet under-run
320
output          PerPacketCrcEn; // Per packet crc enable
321
output          PerPacketPad;   // Per packet pading
322
 
323
// Rx
324
input           MRxClk;         // Receive clock (from PHY)
325
input   [7:0]   RxData;         // Received data byte (from PHY)
326
input           RxValid;        // 
327
input           RxStartFrm;     // 
328
input           RxEndFrm;       // 
329 40 mohor
input           RxAbort;        // This signal is set when address doesn't match.
330 38 mohor
 
331
//Register
332
input           r_TxEn;         // Transmit enable
333
input           r_RxEn;         // Receive enable
334
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
335
input           TX_BD_NUM_Wr;   // RxBDNumber written
336
 
337
// Interrupts
338
output TxB_IRQ;
339
output TxE_IRQ;
340
output RxB_IRQ;
341 77 mohor
output RxE_IRQ;
342 38 mohor
output Busy_IRQ;
343
 
344 77 mohor
 
345 210 mohor
// Bist
346
`ifdef ETH_BIST
347 227 tadejm
input   scanb_rst;      // bist scan reset
348
input   scanb_clk;      // bist scan clock
349
input   scanb_si;       // bist scan serial in
350
output  scanb_so;       // bist scan serial out
351
input   scanb_en;       // bist scan shift enable
352 210 mohor
`endif
353
 
354 77 mohor
reg TxB_IRQ;
355
reg TxE_IRQ;
356
reg RxB_IRQ;
357
reg RxE_IRQ;
358
 
359 38 mohor
reg             TxStartFrm;
360
reg             TxEndFrm;
361
reg     [7:0]   TxData;
362
 
363
reg             TxUnderRun;
364 60 mohor
reg             TxUnderRun_wb;
365 38 mohor
 
366
reg             TxBDRead;
367 39 mohor
wire            TxStatusWrite;
368 38 mohor
 
369
reg     [1:0]   TxValidBytesLatched;
370
 
371
reg    [15:0]   TxLength;
372 60 mohor
reg    [15:0]   LatchedTxLength;
373
reg   [14:11]   TxStatus;
374 38 mohor
 
375 60 mohor
reg   [14:13]   RxStatus;
376 38 mohor
 
377
reg             TxStartFrm_wb;
378
reg             TxRetry_wb;
379 39 mohor
reg             TxAbort_wb;
380 38 mohor
reg             TxDone_wb;
381
 
382
reg             TxDone_wb_q;
383
reg             TxAbort_wb_q;
384 39 mohor
reg             TxRetry_wb_q;
385 219 mohor
reg             TxRetryPacket;
386 221 mohor
reg             TxRetryPacket_NotCleared;
387
reg             TxDonePacket;
388
reg             TxDonePacket_NotCleared;
389 219 mohor
reg             TxAbortPacket;
390 221 mohor
reg             TxAbortPacket_NotCleared;
391 38 mohor
reg             RxBDReady;
392 166 mohor
reg             RxReady;
393 38 mohor
reg             TxBDReady;
394
 
395
reg             RxBDRead;
396 40 mohor
wire            RxStatusWrite;
397 38 mohor
 
398
reg    [31:0]   TxDataLatched;
399
reg     [1:0]   TxByteCnt;
400
reg             LastWord;
401 39 mohor
reg             ReadTxDataFromFifo_tck;
402 38 mohor
 
403
reg             BlockingTxStatusWrite;
404
reg             BlockingTxBDRead;
405
 
406 40 mohor
reg             Flop;
407 38 mohor
 
408
reg     [7:0]   TxBDAddress;
409
reg     [7:0]   RxBDAddress;
410
 
411
reg             TxRetrySync1;
412
reg             TxAbortSync1;
413 39 mohor
reg             TxDoneSync1;
414 38 mohor
 
415
reg             TxAbort_q;
416
reg             TxRetry_q;
417
reg             TxUsedData_q;
418
 
419
reg    [31:0]   RxDataLatched2;
420 82 mohor
 
421
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
422
 
423 38 mohor
reg     [1:0]   RxValidBytes;
424
reg     [1:0]   RxByteCnt;
425
reg             LastByteIn;
426
reg             ShiftWillEnd;
427
 
428 40 mohor
reg             WriteRxDataToFifo;
429 42 mohor
reg    [15:0]   LatchedRxLength;
430 64 mohor
reg             RxAbortLatched;
431 38 mohor
 
432 40 mohor
reg             ShiftEnded;
433 60 mohor
reg             RxOverrun;
434 38 mohor
 
435 40 mohor
reg             BDWrite;                    // BD Write Enable for access from WISHBONE side
436
reg             BDRead;                     // BD Read access from WISHBONE side
437 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
438
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
439 38 mohor
 
440 39 mohor
reg             TxEndFrm_wb;
441 38 mohor
 
442 39 mohor
wire            TxRetryPulse;
443 38 mohor
wire            TxDonePulse;
444
wire            TxAbortPulse;
445
 
446
wire            StartRxBDRead;
447
 
448
wire            StartTxBDRead;
449
 
450
wire            TxIRQEn;
451
wire            WrapTxStatusBit;
452
 
453 77 mohor
wire            RxIRQEn;
454 38 mohor
wire            WrapRxStatusBit;
455
 
456
wire    [1:0]   TxValidBytes;
457
 
458
wire    [7:0]   TempTxBDAddress;
459
wire    [7:0]   TempRxBDAddress;
460
 
461
wire            SetGotData;
462
wire            GotDataEvaluate;
463
 
464 106 mohor
reg             WB_ACK_O;
465 38 mohor
 
466 60 mohor
wire    [6:0]   RxStatusIn;
467
reg     [6:0]   RxStatusInLatched;
468 42 mohor
 
469 39 mohor
reg WbEn, WbEn_q;
470
reg RxEn, RxEn_q;
471
reg TxEn, TxEn_q;
472 38 mohor
 
473 39 mohor
wire ram_ce;
474
wire ram_we;
475
wire ram_oe;
476
reg [7:0]   ram_addr;
477
reg [31:0]  ram_di;
478
wire [31:0] ram_do;
479 38 mohor
 
480 39 mohor
wire StartTxPointerRead;
481
reg  TxPointerRead;
482
reg TxEn_needed;
483 40 mohor
reg RxEn_needed;
484 38 mohor
 
485 40 mohor
wire StartRxPointerRead;
486
reg RxPointerRead;
487 38 mohor
 
488 219 mohor
`ifdef ETH_WISHBONE_B3
489
assign m_wb_bte_o = 2'b00;    // Linear burst
490
`endif
491 39 mohor
 
492 219 mohor
 
493 159 mohor
always @ (posedge WB_CLK_I)
494 40 mohor
begin
495 159 mohor
  WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
496 40 mohor
end
497 39 mohor
 
498 106 mohor
assign WB_DAT_O = ram_do;
499 39 mohor
 
500 41 mohor
// Generic synchronous single-port RAM interface
501 119 mohor
eth_spram_256x32 bd_ram (
502 226 tadejm
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
503 210 mohor
`ifdef ETH_BIST
504 227 tadejm
  ,
505
  .scanb_rst      (scanb_rst),
506
  .scanb_clk      (scanb_clk),
507
  .scanb_si       (scanb_si),
508
  .scanb_so       (scanb_so),
509
  .scanb_en       (scanb_en)
510 210 mohor
`endif
511 39 mohor
);
512 41 mohor
 
513 39 mohor
assign ram_ce = 1'b1;
514 40 mohor
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
515 61 mohor
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
516 39 mohor
 
517
 
518 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
519 38 mohor
begin
520 40 mohor
  if(Reset)
521 39 mohor
    TxEn_needed <=#Tp 1'b0;
522 38 mohor
  else
523 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
524 39 mohor
    TxEn_needed <=#Tp 1'b1;
525
  else
526
  if(TxPointerRead & TxEn & TxEn_q)
527
    TxEn_needed <=#Tp 1'b0;
528 38 mohor
end
529
 
530 39 mohor
// Enabling access to the RAM for three devices.
531 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
532 39 mohor
begin
533 40 mohor
  if(Reset)
534 39 mohor
    begin
535
      WbEn <=#Tp 1'b1;
536
      RxEn <=#Tp 1'b0;
537
      TxEn <=#Tp 1'b0;
538
      ram_addr <=#Tp 8'h0;
539
      ram_di <=#Tp 32'h0;
540 77 mohor
      BDRead <=#Tp 1'b0;
541
      BDWrite <=#Tp 1'b0;
542 39 mohor
    end
543
  else
544
    begin
545
      // Switching between three stages depends on enable signals
546 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
547
        5'b100_10, 5'b100_11 :
548 39 mohor
          begin
549
            WbEn <=#Tp 1'b0;
550
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
551
            TxEn <=#Tp 1'b0;
552 40 mohor
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
553 39 mohor
            ram_di <=#Tp RxBDDataIn;
554
          end
555
        5'b100_01 :
556
          begin
557
            WbEn <=#Tp 1'b0;
558
            RxEn <=#Tp 1'b0;
559
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
560
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
561
            ram_di <=#Tp TxBDDataIn;
562
          end
563 90 mohor
        5'b010_00, 5'b010_10 :
564 39 mohor
          begin
565
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
566
            RxEn <=#Tp 1'b0;
567
            TxEn <=#Tp 1'b0;
568
            ram_addr <=#Tp WB_ADR_I[9:2];
569
            ram_di <=#Tp WB_DAT_I;
570 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
571
            BDRead <=#Tp BDCs & ~WB_WE_I;
572 39 mohor
          end
573 90 mohor
        5'b010_01, 5'b010_11 :
574 39 mohor
          begin
575
            WbEn <=#Tp 1'b0;
576
            RxEn <=#Tp 1'b0;
577
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
578
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
579
            ram_di <=#Tp TxBDDataIn;
580
          end
581 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
582 39 mohor
          begin
583
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
584
            RxEn <=#Tp 1'b0;
585
            TxEn <=#Tp 1'b0;
586
            ram_addr <=#Tp WB_ADR_I[9:2];
587
            ram_di <=#Tp WB_DAT_I;
588 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
589
            BDRead <=#Tp BDCs & ~WB_WE_I;
590 39 mohor
          end
591
        5'b100_00 :
592
          begin
593
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
594
          end
595
        5'b000_00 :
596
          begin
597
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
598
            RxEn <=#Tp 1'b0;
599
            TxEn <=#Tp 1'b0;
600
            ram_addr <=#Tp WB_ADR_I[9:2];
601
            ram_di <=#Tp WB_DAT_I;
602 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
603
            BDRead <=#Tp BDCs & ~WB_WE_I;
604 39 mohor
          end
605
      endcase
606
    end
607
end
608
 
609
 
610
// Delayed stage signals
611 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
612 39 mohor
begin
613 40 mohor
  if(Reset)
614 39 mohor
    begin
615
      WbEn_q <=#Tp 1'b0;
616
      RxEn_q <=#Tp 1'b0;
617
      TxEn_q <=#Tp 1'b0;
618
    end
619
  else
620
    begin
621
      WbEn_q <=#Tp WbEn;
622
      RxEn_q <=#Tp RxEn;
623
      TxEn_q <=#Tp TxEn;
624
    end
625
end
626
 
627 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
628 40 mohor
always @ (posedge MTxClk or posedge Reset)
629 38 mohor
begin
630 40 mohor
  if(Reset)
631 38 mohor
    Flop <=#Tp 1'b0;
632
  else
633
  if(TxDone | TxAbort | TxRetry_q)
634
    Flop <=#Tp 1'b0;
635
  else
636
  if(TxUsedData)
637
    Flop <=#Tp ~Flop;
638
end
639
 
640 39 mohor
wire ResetTxBDReady;
641
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
642 38 mohor
 
643
// Latching READY status of the Tx buffer descriptor
644 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
645 38 mohor
begin
646 40 mohor
  if(Reset)
647 38 mohor
    TxBDReady <=#Tp 1'b0;
648
  else
649 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
650
    TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
651
  else                                                // Only packets larger then 4 bytes are transmitted.
652 39 mohor
  if(ResetTxBDReady)
653 38 mohor
    TxBDReady <=#Tp 1'b0;
654
end
655
 
656
 
657 39 mohor
// Reading the Tx buffer descriptor
658 221 mohor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
659 39 mohor
 
660 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
661 38 mohor
begin
662 40 mohor
  if(Reset)
663 39 mohor
    TxBDRead <=#Tp 1'b1;
664 38 mohor
  else
665 110 mohor
  if(StartTxBDRead)
666 39 mohor
    TxBDRead <=#Tp 1'b1;
667 38 mohor
  else
668 39 mohor
  if(TxBDReady)
669
    TxBDRead <=#Tp 1'b0;
670 38 mohor
end
671
 
672
 
673 39 mohor
// Reading Tx BD pointer
674
assign StartTxPointerRead = TxBDRead & TxBDReady;
675 38 mohor
 
676 39 mohor
// Reading Tx BD Pointer
677 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
678 38 mohor
begin
679 40 mohor
  if(Reset)
680 39 mohor
    TxPointerRead <=#Tp 1'b0;
681 38 mohor
  else
682 39 mohor
  if(StartTxPointerRead)
683
    TxPointerRead <=#Tp 1'b1;
684 38 mohor
  else
685 39 mohor
  if(TxEn_q)
686
    TxPointerRead <=#Tp 1'b0;
687 38 mohor
end
688
 
689
 
690 39 mohor
// Writing status back to the Tx buffer descriptor
691 221 mohor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
692 38 mohor
 
693
 
694
 
695 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
696 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
697 38 mohor
begin
698 40 mohor
  if(Reset)
699 39 mohor
    BlockingTxStatusWrite <=#Tp 1'b0;
700 38 mohor
  else
701 39 mohor
  if(TxStatusWrite)
702
    BlockingTxStatusWrite <=#Tp 1'b1;
703 38 mohor
  else
704 39 mohor
  if(~TxDone_wb & ~TxAbort_wb)
705
    BlockingTxStatusWrite <=#Tp 1'b0;
706 38 mohor
end
707
 
708
 
709 159 mohor
reg BlockingTxStatusWrite_sync1;
710
reg BlockingTxStatusWrite_sync2;
711
 
712
// Synchronizing BlockingTxStatusWrite to MTxClk
713
always @ (posedge MTxClk or posedge Reset)
714
begin
715
  if(Reset)
716
    BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
717
  else
718
    BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
719
end
720
 
721
// Synchronizing BlockingTxStatusWrite to MTxClk
722
always @ (posedge MTxClk or posedge Reset)
723
begin
724
  if(Reset)
725
    BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
726
  else
727
    BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
728
end
729
 
730
 
731 39 mohor
// TxBDRead state is activated only once. 
732 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
733 39 mohor
begin
734 40 mohor
  if(Reset)
735 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
736
  else
737 110 mohor
  if(StartTxBDRead)
738 39 mohor
    BlockingTxBDRead <=#Tp 1'b1;
739
  else
740 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
741 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
742
end
743 38 mohor
 
744
 
745 39 mohor
// Latching status from the tx buffer descriptor
746
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
747 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
748 38 mohor
begin
749 40 mohor
  if(Reset)
750 60 mohor
    TxStatus <=#Tp 4'h0;
751 38 mohor
  else
752 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
753 60 mohor
    TxStatus <=#Tp ram_do[14:11];
754 38 mohor
end
755
 
756 40 mohor
reg ReadTxDataFromMemory;
757
wire WriteRxDataToMemory;
758 38 mohor
 
759 39 mohor
reg MasterWbTX;
760
reg MasterWbRX;
761
 
762
reg [31:0] m_wb_adr_o;
763
reg        m_wb_cyc_o;
764
reg        m_wb_stb_o;
765 96 mohor
reg  [3:0] m_wb_sel_o;
766 39 mohor
reg        m_wb_we_o;
767 40 mohor
 
768 39 mohor
wire TxLengthEq0;
769
wire TxLengthLt4;
770
 
771 150 mohor
reg BlockingIncrementTxPointer;
772 159 mohor
reg [31:2] TxPointerMSB;
773
reg [1:0]  TxPointerLSB;
774
reg [1:0]  TxPointerLSB_rst;
775
reg [31:2] RxPointerMSB;
776
reg [1:0]  RxPointerLSB_rst;
777 39 mohor
 
778 150 mohor
wire RxBurstAcc;
779
wire RxWordAcc;
780
wire RxHalfAcc;
781
wire RxByteAcc;
782
 
783 39 mohor
//Latching length from the buffer descriptor;
784 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
785 38 mohor
begin
786 40 mohor
  if(Reset)
787 39 mohor
    TxLength <=#Tp 16'h0;
788 38 mohor
  else
789 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
790
    TxLength <=#Tp ram_do[31:16];
791 38 mohor
  else
792 39 mohor
  if(MasterWbTX & m_wb_ack_i)
793
    begin
794
      if(TxLengthLt4)
795
        TxLength <=#Tp 16'h0;
796 150 mohor
      else
797 159 mohor
      if(TxPointerLSB_rst==2'h0)
798 96 mohor
        TxLength <=#Tp TxLength - 3'h4;    // Length is subtracted at the data request
799 39 mohor
      else
800 159 mohor
      if(TxPointerLSB_rst==2'h1)
801 150 mohor
        TxLength <=#Tp TxLength - 3'h3;    // Length is subtracted at the data request
802
      else
803 159 mohor
      if(TxPointerLSB_rst==2'h2)
804 150 mohor
        TxLength <=#Tp TxLength - 3'h2;    // Length is subtracted at the data request
805
      else
806 159 mohor
      if(TxPointerLSB_rst==2'h3)
807 150 mohor
        TxLength <=#Tp TxLength - 3'h1;    // Length is subtracted at the data request
808 39 mohor
    end
809 38 mohor
end
810
 
811 96 mohor
 
812
 
813 60 mohor
//Latching length from the buffer descriptor;
814
always @ (posedge WB_CLK_I or posedge Reset)
815
begin
816
  if(Reset)
817
    LatchedTxLength <=#Tp 16'h0;
818
  else
819
  if(TxEn & TxEn_q & TxBDRead)
820
    LatchedTxLength <=#Tp ram_do[31:16];
821
end
822
 
823 39 mohor
assign TxLengthEq0 = TxLength == 0;
824
assign TxLengthLt4 = TxLength < 4;
825 38 mohor
 
826 150 mohor
reg cyc_cleared;
827
reg IncrTxPointer;
828 39 mohor
 
829
 
830 159 mohor
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
831
// because TxPointerMSB is only used for word-aligned accesses.
832 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
833 38 mohor
begin
834 40 mohor
  if(Reset)
835 159 mohor
    TxPointerMSB <=#Tp 30'h0;
836 38 mohor
  else
837 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
838 159 mohor
    TxPointerMSB <=#Tp ram_do[31:2];
839 38 mohor
  else
840 150 mohor
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
841 159 mohor
    TxPointerMSB <=#Tp TxPointerMSB + 1'b1;     // TxPointer is word-aligned
842 38 mohor
end
843
 
844 96 mohor
 
845 159 mohor
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
846
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
847
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
848
// set by this two bits.
849 96 mohor
always @ (posedge WB_CLK_I or posedge Reset)
850
begin
851
  if(Reset)
852 159 mohor
    TxPointerLSB[1:0] <=#Tp 0;
853 96 mohor
  else
854
  if(TxEn & TxEn_q & TxPointerRead)
855 159 mohor
    TxPointerLSB[1:0] <=#Tp ram_do[1:0];
856 96 mohor
end
857
 
858
 
859 159 mohor
// Latching 2 MSB bits of the buffer descriptor. 
860
// After the read access, TxLength needs to be decremented for the number of the valid
861
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are 
862
// valid so this two bits are reset to zero. 
863 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
864
begin
865
  if(Reset)
866 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
867 150 mohor
  else
868
  if(TxEn & TxEn_q & TxPointerRead)
869 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
870 150 mohor
  else
871
  if(MasterWbTX & m_wb_ack_i)                 // After first access pointer is word alligned
872 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
873 150 mohor
end
874 96 mohor
 
875 150 mohor
 
876 159 mohor
reg  [3:0] RxByteSel;
877 39 mohor
wire MasterAccessFinished;
878 38 mohor
 
879 39 mohor
 
880 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
881 38 mohor
begin
882 40 mohor
  if(Reset)
883 39 mohor
    BlockingIncrementTxPointer <=#Tp 0;
884 38 mohor
  else
885 39 mohor
  if(MasterAccessFinished)
886
    BlockingIncrementTxPointer <=#Tp 0;
887 38 mohor
  else
888 150 mohor
  if(IncrTxPointer)
889 39 mohor
    BlockingIncrementTxPointer <=#Tp 1'b1;
890 38 mohor
end
891
 
892
 
893 39 mohor
wire TxBufferAlmostFull;
894
wire TxBufferFull;
895
wire TxBufferEmpty;
896
wire TxBufferAlmostEmpty;
897 40 mohor
wire SetReadTxDataFromMemory;
898 39 mohor
 
899 40 mohor
reg BlockReadTxDataFromMemory;
900 39 mohor
 
901 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
902 39 mohor
 
903 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
904 38 mohor
begin
905 40 mohor
  if(Reset)
906
    ReadTxDataFromMemory <=#Tp 1'b0;
907 38 mohor
  else
908 219 mohor
  if(TxLengthEq0 | TxAbortPacket | TxRetryPacket)
909 40 mohor
    ReadTxDataFromMemory <=#Tp 1'b0;
910 39 mohor
  else
911 40 mohor
  if(SetReadTxDataFromMemory)
912
    ReadTxDataFromMemory <=#Tp 1'b1;
913 38 mohor
end
914
 
915 226 tadejm
reg tx_burst_en;
916
reg rx_burst_en;
917 221 mohor
reg BlockingLastReadOn_Abort_Retry;
918
 
919
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory & ~BlockingLastReadOn_Abort_Retry;
920 226 tadejm
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
921 221 mohor
 
922 39 mohor
wire [31:0] TxData_wb;
923
wire ReadTxDataFromFifo_wb;
924 38 mohor
 
925 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
926 38 mohor
begin
927 40 mohor
  if(Reset)
928
    BlockReadTxDataFromMemory <=#Tp 1'b0;
929 38 mohor
  else
930 221 mohor
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (!(TxAbortPacket | TxRetryPacket)))
931 40 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b1;
932 219 mohor
  else
933 221 mohor
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
934 219 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b0;
935 39 mohor
end
936
 
937
 
938 221 mohor
always @ (posedge WB_CLK_I or posedge Reset)
939
begin
940
  if(Reset)
941
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
942
  else
943
  if(TxAbortPacket | TxRetryPacket)
944
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
945
  else
946
  if(((TxAbort_wb & !TxAbortPacket_NotCleared) | (TxRetry_wb & !TxRetryPacket_NotCleared)) & !TxBDReady)
947
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b1;
948
end
949 39 mohor
 
950 221 mohor
 
951
 
952
 
953 39 mohor
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
954 219 mohor
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
955
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
956 226 tadejm
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
957
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
958 159 mohor
 
959 226 tadejm
wire rx_burst;
960
wire enough_data_in_rxfifo_for_burst;
961
wire enough_data_in_rxfifo_for_burst_plus1;
962 229 mohor
 
963 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
964 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
965 39 mohor
begin
966 40 mohor
  if(Reset)
967 38 mohor
    begin
968 39 mohor
      MasterWbTX <=#Tp 1'b0;
969
      MasterWbRX <=#Tp 1'b0;
970
      m_wb_adr_o <=#Tp 32'h0;
971
      m_wb_cyc_o <=#Tp 1'b0;
972
      m_wb_stb_o <=#Tp 1'b0;
973
      m_wb_we_o  <=#Tp 1'b0;
974 96 mohor
      m_wb_sel_o <=#Tp 4'h0;
975 110 mohor
      cyc_cleared<=#Tp 1'b0;
976 226 tadejm
      tx_burst_cnt<=#Tp 0;
977
      rx_burst_cnt<=#Tp 0;
978 150 mohor
      IncrTxPointer<=#Tp 1'b0;
979 226 tadejm
      tx_burst_en<=#Tp 1'b1;
980
      rx_burst_en<=#Tp 1'b0;
981
      `ifdef ETH_WISHBONE_B3
982
        m_wb_cti_o <=#Tp 3'b0;
983
      `endif
984 38 mohor
    end
985 39 mohor
  else
986
    begin
987
      // Switching between two stages depends on enable signals
988 229 mohor
      casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst})  // synopsys parallel_case
989 226 tadejm
        8'b00_10_00_10,             // Idle and MRB needed
990 229 mohor
        8'b10_1x_10_1x,             // MRB continues
991 226 tadejm
        8'b10_10_01_10,             // Clear (previously MR) and MRB needed
992 229 mohor
        8'b01_1x_01_1x :            // Clear (previously MW) and MRB needed
993 39 mohor
          begin
994 226 tadejm
            MasterWbTX <=#Tp 1'b1;  // tx burst
995
            MasterWbRX <=#Tp 1'b0;
996
            m_wb_cyc_o <=#Tp 1'b1;
997
            m_wb_stb_o <=#Tp 1'b1;
998
            m_wb_we_o  <=#Tp 1'b0;
999
            m_wb_sel_o <=#Tp 4'hf;
1000
            cyc_cleared<=#Tp 1'b0;
1001
            IncrTxPointer<=#Tp 1'b1;
1002
            tx_burst_cnt <=#Tp tx_burst_cnt+1;
1003
            if(tx_burst_cnt==0)
1004
              m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1005
            else
1006
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1007
 
1008
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
1009
              begin
1010
                tx_burst_en<=#Tp 1'b0;
1011
              `ifdef ETH_WISHBONE_B3
1012
                m_wb_cti_o <=#Tp 3'b111;
1013
              `endif
1014
              end
1015
            else
1016
              begin
1017
              `ifdef ETH_WISHBONE_B3
1018
                m_wb_cti_o <=#Tp 3'b010;
1019
              `endif
1020
              end
1021
          end
1022 229 mohor
        8'b00_x1_00_x1,             // Idle and MWB needed
1023
        8'b01_x1_10_x1,             // MWB continues
1024 226 tadejm
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
1025 229 mohor
        8'b10_x1_01_x1 :            // Clear (previously MR) and MWB needed
1026 226 tadejm
          begin
1027
            MasterWbTX <=#Tp 1'b0;  // rx burst
1028 39 mohor
            MasterWbRX <=#Tp 1'b1;
1029 226 tadejm
            m_wb_cyc_o <=#Tp 1'b1;
1030
            m_wb_stb_o <=#Tp 1'b1;
1031
            m_wb_we_o  <=#Tp 1'b1;
1032
            m_wb_sel_o <=#Tp RxByteSel;
1033
            IncrTxPointer<=#Tp 1'b0;
1034
            cyc_cleared<=#Tp 1'b0;
1035
            rx_burst_cnt <=#Tp rx_burst_cnt+1;
1036
 
1037
            if(rx_burst_cnt==0)
1038
              m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1039
            else
1040
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1041
 
1042
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
1043
              begin
1044
                rx_burst_en<=#Tp 1'b0;
1045
              `ifdef ETH_WISHBONE_B3
1046
                m_wb_cti_o <=#Tp 3'b111;
1047
              `endif
1048
              end
1049
            else
1050
              begin
1051
              `ifdef ETH_WISHBONE_B3
1052
                m_wb_cti_o <=#Tp 3'b010;
1053
              `endif
1054
              end
1055
          end
1056 229 mohor
        8'b00_x1_00_x0 :            // idle and MW is needed (data write to rx buffer)
1057 226 tadejm
          begin
1058
            MasterWbTX <=#Tp 1'b0;
1059
            MasterWbRX <=#Tp 1'b1;
1060 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1061 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1062
            m_wb_stb_o <=#Tp 1'b1;
1063
            m_wb_we_o  <=#Tp 1'b1;
1064 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1065 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1066 39 mohor
          end
1067 226 tadejm
        8'b00_10_00_00 :            // idle and MR is needed (data read from tx buffer)
1068 39 mohor
          begin
1069 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1070 39 mohor
            MasterWbRX <=#Tp 1'b0;
1071 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1072 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1073
            m_wb_stb_o <=#Tp 1'b1;
1074
            m_wb_we_o  <=#Tp 1'b0;
1075 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1076
            IncrTxPointer<=#Tp 1'b1;
1077 39 mohor
          end
1078 226 tadejm
        8'b10_10_01_00,             // MR and MR is needed (data read from tx buffer)
1079 229 mohor
        8'b01_1x_01_0x  :           // MW and MR is needed (data read from tx buffer)
1080 39 mohor
          begin
1081 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1082 39 mohor
            MasterWbRX <=#Tp 1'b0;
1083 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1084 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1085
            m_wb_stb_o <=#Tp 1'b1;
1086
            m_wb_we_o  <=#Tp 1'b0;
1087 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1088 110 mohor
            cyc_cleared<=#Tp 1'b0;
1089 150 mohor
            IncrTxPointer<=#Tp 1'b1;
1090 39 mohor
          end
1091 226 tadejm
        8'b01_01_01_00,             // MW and MW needed (data write to rx buffer)
1092 229 mohor
        8'b10_x1_01_x0  :           // MR and MW is needed (data write to rx buffer)
1093 39 mohor
          begin
1094 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1095 39 mohor
            MasterWbRX <=#Tp 1'b1;
1096 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1097 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1098
            m_wb_stb_o <=#Tp 1'b1;
1099 39 mohor
            m_wb_we_o  <=#Tp 1'b1;
1100 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1101 110 mohor
            cyc_cleared<=#Tp 1'b0;
1102 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1103 39 mohor
          end
1104 226 tadejm
        8'b01_01_10_00,             // MW and MW needed (cycle is cleared between previous and next access)
1105 229 mohor
        8'b01_1x_10_x0,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
1106 226 tadejm
        8'b10_10_10_00,             // MR and MR needed (cycle is cleared between previous and next access)
1107 229 mohor
        8'b10_x1_10_0x :            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
1108 39 mohor
          begin
1109 110 mohor
            m_wb_cyc_o <=#Tp 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
1110
            m_wb_stb_o <=#Tp 1'b0;
1111
            cyc_cleared<=#Tp 1'b1;
1112 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1113 226 tadejm
            tx_burst_cnt<=#Tp 0;
1114
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1115
            rx_burst_cnt<=#Tp 0;
1116
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1117
            `ifdef ETH_WISHBONE_B3
1118
              m_wb_cti_o <=#Tp 3'b0;
1119
            `endif
1120 110 mohor
          end
1121 229 mohor
        8'bxx_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1122
        8'bxx_00_01_00 :            // Between cyc_cleared request was cleared
1123 110 mohor
          begin
1124 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1125 39 mohor
            MasterWbRX <=#Tp 1'b0;
1126
            m_wb_cyc_o <=#Tp 1'b0;
1127
            m_wb_stb_o <=#Tp 1'b0;
1128 226 tadejm
            cyc_cleared<=#Tp 1'b0;
1129 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1130 226 tadejm
            rx_burst_cnt<=#Tp 0;
1131
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1132
            `ifdef ETH_WISHBONE_B3
1133
              m_wb_cti_o <=#Tp 3'b0;
1134
            `endif
1135 39 mohor
          end
1136 226 tadejm
        8'b00_00_00_00:             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1137 127 mohor
          begin
1138 226 tadejm
            tx_burst_cnt<=#Tp 0;
1139
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1140 127 mohor
          end
1141 226 tadejm
        default:                    // Don't touch
1142 82 mohor
          begin
1143
            MasterWbTX <=#Tp MasterWbTX;
1144
            MasterWbRX <=#Tp MasterWbRX;
1145
            m_wb_cyc_o <=#Tp m_wb_cyc_o;
1146
            m_wb_stb_o <=#Tp m_wb_stb_o;
1147 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_o;
1148 150 mohor
            IncrTxPointer<=#Tp IncrTxPointer;
1149 82 mohor
          end
1150 39 mohor
      endcase
1151
    end
1152 38 mohor
end
1153
 
1154 110 mohor
 
1155 39 mohor
wire TxFifoClear;
1156 96 mohor
 
1157 219 mohor
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
1158 38 mohor
 
1159 219 mohor
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
1160 150 mohor
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
1161 96 mohor
          .clk(WB_CLK_I),                                   .reset(Reset),
1162 226 tadejm
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
1163 96 mohor
          .clear(TxFifoClear),                              .full(TxBufferFull),
1164
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
1165 150 mohor
          .empty(TxBufferEmpty),                            .cnt(txfifo_cnt)
1166 96 mohor
        );
1167 39 mohor
 
1168
 
1169
reg StartOccured;
1170
reg TxStartFrm_sync1;
1171
reg TxStartFrm_sync2;
1172
reg TxStartFrm_syncb1;
1173
reg TxStartFrm_syncb2;
1174
 
1175
 
1176
 
1177
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1178 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1179 38 mohor
begin
1180 40 mohor
  if(Reset)
1181 39 mohor
    TxStartFrm_wb <=#Tp 1'b0;
1182 38 mohor
  else
1183 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1184
    TxStartFrm_wb <=#Tp 1'b1;
1185 38 mohor
  else
1186 39 mohor
  if(TxStartFrm_syncb2)
1187
    TxStartFrm_wb <=#Tp 1'b0;
1188 38 mohor
end
1189
 
1190 39 mohor
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
1191 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1192 38 mohor
begin
1193 40 mohor
  if(Reset)
1194 39 mohor
    StartOccured <=#Tp 1'b0;
1195 38 mohor
  else
1196 39 mohor
  if(TxStartFrm_wb)
1197
    StartOccured <=#Tp 1'b1;
1198 38 mohor
  else
1199 39 mohor
  if(ResetTxBDReady)
1200
    StartOccured <=#Tp 1'b0;
1201 38 mohor
end
1202
 
1203 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1204 40 mohor
always @ (posedge MTxClk or posedge Reset)
1205 39 mohor
begin
1206 40 mohor
  if(Reset)
1207 39 mohor
    TxStartFrm_sync1 <=#Tp 1'b0;
1208
  else
1209
    TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
1210
end
1211 38 mohor
 
1212 40 mohor
always @ (posedge MTxClk or posedge Reset)
1213 39 mohor
begin
1214 40 mohor
  if(Reset)
1215 39 mohor
    TxStartFrm_sync2 <=#Tp 1'b0;
1216
  else
1217
    TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
1218
end
1219
 
1220 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1221 38 mohor
begin
1222 40 mohor
  if(Reset)
1223 39 mohor
    TxStartFrm_syncb1 <=#Tp 1'b0;
1224 38 mohor
  else
1225 39 mohor
    TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
1226 38 mohor
end
1227
 
1228 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1229 38 mohor
begin
1230 40 mohor
  if(Reset)
1231 39 mohor
    TxStartFrm_syncb2 <=#Tp 1'b0;
1232 38 mohor
  else
1233 39 mohor
    TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
1234
end
1235
 
1236 40 mohor
always @ (posedge MTxClk or posedge Reset)
1237 39 mohor
begin
1238 40 mohor
  if(Reset)
1239 39 mohor
    TxStartFrm <=#Tp 1'b0;
1240 38 mohor
  else
1241 39 mohor
  if(TxStartFrm_sync2)
1242 61 mohor
    TxStartFrm <=#Tp 1'b1;
1243 39 mohor
  else
1244 61 mohor
  if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry | TxAbort))
1245 39 mohor
    TxStartFrm <=#Tp 1'b0;
1246 38 mohor
end
1247 39 mohor
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1248 38 mohor
 
1249
 
1250 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1251 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1252 38 mohor
begin
1253 40 mohor
  if(Reset)
1254 39 mohor
    TxEndFrm_wb <=#Tp 1'b0;
1255 38 mohor
  else
1256 221 mohor
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
1257 39 mohor
    TxEndFrm_wb <=#Tp 1'b1;
1258 38 mohor
  else
1259 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1260
    TxEndFrm_wb <=#Tp 1'b0;
1261 38 mohor
end
1262
 
1263
 
1264
// Marks which bytes are valid within the word.
1265 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1266 38 mohor
 
1267 39 mohor
reg LatchValidBytes;
1268
reg LatchValidBytes_q;
1269 38 mohor
 
1270 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1271 38 mohor
begin
1272 40 mohor
  if(Reset)
1273 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1274 38 mohor
  else
1275 39 mohor
  if(TxLengthLt4 & TxBDReady)
1276
    LatchValidBytes <=#Tp 1'b1;
1277 38 mohor
  else
1278 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1279 38 mohor
end
1280
 
1281 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1282 38 mohor
begin
1283 40 mohor
  if(Reset)
1284 39 mohor
    LatchValidBytes_q <=#Tp 1'b0;
1285 38 mohor
  else
1286 39 mohor
    LatchValidBytes_q <=#Tp LatchValidBytes;
1287 38 mohor
end
1288
 
1289
 
1290 39 mohor
// Latching valid bytes
1291 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1292 38 mohor
begin
1293 40 mohor
  if(Reset)
1294 39 mohor
    TxValidBytesLatched <=#Tp 2'h0;
1295 38 mohor
  else
1296 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1297
    TxValidBytesLatched <=#Tp TxValidBytes;
1298
  else
1299
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1300
    TxValidBytesLatched <=#Tp 2'h0;
1301 38 mohor
end
1302
 
1303
 
1304
assign TxIRQEn          = TxStatus[14];
1305 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1306
assign PerPacketPad     = TxStatus[12];
1307
assign PerPacketCrcEn   = TxStatus[11];
1308 38 mohor
 
1309
 
1310 77 mohor
assign RxIRQEn         = RxStatus[14];
1311 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1312 38 mohor
 
1313
 
1314
// Temporary Tx and Rx buffer descriptor address 
1315 39 mohor
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite     & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
1316 134 mohor
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum<<1)     | // Using first Rx BD
1317 39 mohor
                              {8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
1318 38 mohor
 
1319
 
1320
// Latching Tx buffer descriptor address
1321 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1322 38 mohor
begin
1323 40 mohor
  if(Reset)
1324 38 mohor
    TxBDAddress <=#Tp 8'h0;
1325
  else
1326
  if(TxStatusWrite)
1327
    TxBDAddress <=#Tp TempTxBDAddress;
1328
end
1329
 
1330
 
1331
// Latching Rx buffer descriptor address
1332 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1333 38 mohor
begin
1334 40 mohor
  if(Reset)
1335 134 mohor
    RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF<<1;
1336 38 mohor
  else
1337 77 mohor
  if(TX_BD_NUM_Wr)                        // When r_TxBDNum is updated, RxBDAddress is also
1338 134 mohor
    RxBDAddress <=#Tp WB_DAT_I[7:0]<<1;
1339 38 mohor
  else
1340
  if(RxStatusWrite)
1341
    RxBDAddress <=#Tp TempRxBDAddress;
1342
end
1343
 
1344 60 mohor
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
1345 38 mohor
 
1346 60 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 6'h0, RxStatusInLatched};
1347
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1348 38 mohor
 
1349 60 mohor
 
1350 38 mohor
// Signals used for various purposes
1351 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1352 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1353
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1354
 
1355
 
1356
 
1357 39 mohor
// Generating delayed signals
1358 40 mohor
always @ (posedge MTxClk or posedge Reset)
1359 38 mohor
begin
1360 40 mohor
  if(Reset)
1361 39 mohor
    begin
1362
      TxAbort_q      <=#Tp 1'b0;
1363
      TxRetry_q      <=#Tp 1'b0;
1364
      TxUsedData_q   <=#Tp 1'b0;
1365
    end
1366 38 mohor
  else
1367 39 mohor
    begin
1368
      TxAbort_q      <=#Tp TxAbort;
1369
      TxRetry_q      <=#Tp TxRetry;
1370
      TxUsedData_q   <=#Tp TxUsedData;
1371
    end
1372 38 mohor
end
1373
 
1374
// Generating delayed signals
1375 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1376 38 mohor
begin
1377 40 mohor
  if(Reset)
1378 38 mohor
    begin
1379 39 mohor
      TxDone_wb_q   <=#Tp 1'b0;
1380
      TxAbort_wb_q  <=#Tp 1'b0;
1381 40 mohor
      TxRetry_wb_q  <=#Tp 1'b0;
1382 38 mohor
    end
1383
  else
1384
    begin
1385 39 mohor
      TxDone_wb_q   <=#Tp TxDone_wb;
1386
      TxAbort_wb_q  <=#Tp TxAbort_wb;
1387 40 mohor
      TxRetry_wb_q  <=#Tp TxRetry_wb;
1388 38 mohor
    end
1389
end
1390
 
1391
 
1392 219 mohor
reg TxAbortPacketBlocked;
1393
always @ (posedge WB_CLK_I or posedge Reset)
1394
begin
1395
  if(Reset)
1396
    TxAbortPacket <=#Tp 1'b0;
1397
  else
1398 226 tadejm
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxAbortPacketBlocked |
1399
     TxAbort_wb & !MasterWbTX & !TxAbortPacketBlocked)
1400 219 mohor
    TxAbortPacket <=#Tp 1'b1;
1401
  else
1402
    TxAbortPacket <=#Tp 1'b0;
1403
end
1404
 
1405
 
1406
always @ (posedge WB_CLK_I or posedge Reset)
1407
begin
1408
  if(Reset)
1409 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1410
  else
1411 226 tadejm
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1412
     TxAbort_wb & !MasterWbTX)
1413 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b1;
1414
  else
1415
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1416
end
1417
 
1418
 
1419
always @ (posedge WB_CLK_I or posedge Reset)
1420
begin
1421
  if(Reset)
1422 219 mohor
    TxAbortPacketBlocked <=#Tp 1'b0;
1423
  else
1424
  if(TxAbortPacket)
1425
    TxAbortPacketBlocked <=#Tp 1'b1;
1426
  else
1427
  if(!TxAbort_wb & TxAbort_wb_q)
1428
    TxAbortPacketBlocked <=#Tp 1'b0;
1429
end
1430
 
1431
 
1432
reg TxRetryPacketBlocked;
1433
always @ (posedge WB_CLK_I or posedge Reset)
1434
begin
1435
  if(Reset)
1436
    TxRetryPacket <=#Tp 1'b0;
1437
  else
1438 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
1439
     TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1440 219 mohor
    TxRetryPacket <=#Tp 1'b1;
1441
  else
1442
    TxRetryPacket <=#Tp 1'b0;
1443
end
1444
 
1445
 
1446
always @ (posedge WB_CLK_I or posedge Reset)
1447
begin
1448
  if(Reset)
1449 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1450
  else
1451 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1452
     TxRetry_wb & !MasterWbTX)
1453 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b1;
1454
  else
1455
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1456
end
1457
 
1458
 
1459
always @ (posedge WB_CLK_I or posedge Reset)
1460
begin
1461
  if(Reset)
1462 219 mohor
    TxRetryPacketBlocked <=#Tp 1'b0;
1463
  else
1464
  if(TxRetryPacket)
1465
    TxRetryPacketBlocked <=#Tp 1'b1;
1466
  else
1467
  if(!TxRetry_wb & TxRetry_wb_q)
1468
    TxRetryPacketBlocked <=#Tp 1'b0;
1469
end
1470
 
1471
 
1472 221 mohor
reg TxDonePacketBlocked;
1473
always @ (posedge WB_CLK_I or posedge Reset)
1474
begin
1475
  if(Reset)
1476
    TxDonePacket <=#Tp 1'b0;
1477
  else
1478 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
1479
     TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
1480 221 mohor
    TxDonePacket <=#Tp 1'b1;
1481
  else
1482
    TxDonePacket <=#Tp 1'b0;
1483
end
1484
 
1485
 
1486
always @ (posedge WB_CLK_I or posedge Reset)
1487
begin
1488
  if(Reset)
1489
    TxDonePacket_NotCleared <=#Tp 1'b0;
1490
  else
1491 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1492
     TxDone_wb & !MasterWbTX)
1493 221 mohor
    TxDonePacket_NotCleared <=#Tp 1'b1;
1494
  else
1495
    TxDonePacket_NotCleared <=#Tp 1'b0;
1496
end
1497
 
1498
 
1499
always @ (posedge WB_CLK_I or posedge Reset)
1500
begin
1501
  if(Reset)
1502
    TxDonePacketBlocked <=#Tp 1'b0;
1503
  else
1504
  if(TxDonePacket)
1505
    TxDonePacketBlocked <=#Tp 1'b1;
1506
  else
1507
  if(!TxDone_wb & TxDone_wb_q)
1508
    TxDonePacketBlocked <=#Tp 1'b0;
1509
end
1510
 
1511
 
1512 38 mohor
// Sinchronizing and evaluating tx data
1513 39 mohor
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
1514 219 mohor
assign SetGotData = (TxStartFrm_wb);
1515 38 mohor
 
1516
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
1517 40 mohor
//assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1518
assign GotDataEvaluate = (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1519 38 mohor
 
1520
 
1521
// Indication of the last word
1522 40 mohor
always @ (posedge MTxClk or posedge Reset)
1523 38 mohor
begin
1524 40 mohor
  if(Reset)
1525 38 mohor
    LastWord <=#Tp 1'b0;
1526
  else
1527
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1528
    LastWord <=#Tp 1'b0;
1529
  else
1530
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1531 39 mohor
    LastWord <=#Tp TxEndFrm_wb;
1532 38 mohor
end
1533
 
1534
 
1535
// Tx end frame generation
1536 40 mohor
always @ (posedge MTxClk or posedge Reset)
1537 38 mohor
begin
1538 40 mohor
  if(Reset)
1539 38 mohor
    TxEndFrm <=#Tp 1'b0;
1540
  else
1541 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1542 38 mohor
    TxEndFrm <=#Tp 1'b0;
1543
  else
1544
  if(Flop & LastWord)
1545
    begin
1546 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1547 38 mohor
        1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
1548
        2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
1549
        3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
1550
 
1551
        default : TxEndFrm <=#Tp 1'b0;
1552
      endcase
1553
    end
1554
end
1555
 
1556
 
1557
// Tx data selection (latching)
1558 40 mohor
always @ (posedge MTxClk or posedge Reset)
1559 38 mohor
begin
1560 40 mohor
  if(Reset)
1561 96 mohor
    TxData <=#Tp 0;
1562 38 mohor
  else
1563 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1564 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1565 96 mohor
      2'h0 : TxData <=#Tp TxData_wb[31:24];                  // Big Endian Byte Ordering
1566
      2'h1 : TxData <=#Tp TxData_wb[23:16];                  // Big Endian Byte Ordering
1567
      2'h2 : TxData <=#Tp TxData_wb[15:08];                  // Big Endian Byte Ordering
1568
      2'h3 : TxData <=#Tp TxData_wb[07:00];                  // Big Endian Byte Ordering
1569
    endcase
1570 38 mohor
  else
1571 159 mohor
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1572 96 mohor
    TxData <=#Tp TxData_wb[31:24];                           // Big Endian Byte Ordering
1573
  else
1574 38 mohor
  if(TxUsedData & Flop)
1575
    begin
1576 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1577 226 tadejm
 
1578 82 mohor
        1 : TxData <=#Tp TxDataLatched[23:16];
1579
        2 : TxData <=#Tp TxDataLatched[15:8];
1580
        3 : TxData <=#Tp TxDataLatched[7:0];
1581 38 mohor
      endcase
1582
    end
1583
end
1584
 
1585
 
1586
// Latching tx data
1587 40 mohor
always @ (posedge MTxClk or posedge Reset)
1588 38 mohor
begin
1589 40 mohor
  if(Reset)
1590 38 mohor
    TxDataLatched[31:0] <=#Tp 32'h0;
1591
  else
1592 96 mohor
 if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1593 39 mohor
    TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
1594 38 mohor
end
1595
 
1596
 
1597
// Tx under run
1598 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1599 38 mohor
begin
1600 40 mohor
  if(Reset)
1601 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1602 38 mohor
  else
1603 39 mohor
  if(TxAbortPulse)
1604 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1605
  else
1606
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1607
    TxUnderRun_wb <=#Tp 1'b1;
1608
end
1609
 
1610
 
1611 159 mohor
reg TxUnderRun_sync1;
1612
 
1613 60 mohor
// Tx under run
1614
always @ (posedge MTxClk or posedge Reset)
1615
begin
1616
  if(Reset)
1617 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b0;
1618 43 mohor
  else
1619 60 mohor
  if(TxUnderRun_wb)
1620 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b1;
1621 60 mohor
  else
1622 159 mohor
  if(BlockingTxStatusWrite_sync2)
1623
    TxUnderRun_sync1 <=#Tp 1'b0;
1624
end
1625
 
1626
// Tx under run
1627
always @ (posedge MTxClk or posedge Reset)
1628
begin
1629
  if(Reset)
1630 60 mohor
    TxUnderRun <=#Tp 1'b0;
1631 159 mohor
  else
1632
  if(BlockingTxStatusWrite_sync2)
1633
    TxUnderRun <=#Tp 1'b0;
1634
  else
1635
  if(TxUnderRun_sync1)
1636
    TxUnderRun <=#Tp 1'b1;
1637 38 mohor
end
1638
 
1639
 
1640
// Tx Byte counter
1641 40 mohor
always @ (posedge MTxClk or posedge Reset)
1642 38 mohor
begin
1643 40 mohor
  if(Reset)
1644 38 mohor
    TxByteCnt <=#Tp 2'h0;
1645
  else
1646
  if(TxAbort_q | TxRetry_q)
1647
    TxByteCnt <=#Tp 2'h0;
1648
  else
1649
  if(TxStartFrm & ~TxUsedData)
1650 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1651 96 mohor
      2'h0 : TxByteCnt <=#Tp 2'h1;
1652
      2'h1 : TxByteCnt <=#Tp 2'h2;
1653
      2'h2 : TxByteCnt <=#Tp 2'h3;
1654
      2'h3 : TxByteCnt <=#Tp 2'h0;
1655
    endcase
1656 38 mohor
  else
1657
  if(TxUsedData & Flop)
1658 96 mohor
    TxByteCnt <=#Tp TxByteCnt + 1'b1;
1659 38 mohor
end
1660
 
1661 39 mohor
 
1662 150 mohor
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1663
reg ReadTxDataFromFifo_sync1;
1664
reg ReadTxDataFromFifo_sync2;
1665
reg ReadTxDataFromFifo_sync3;
1666
reg ReadTxDataFromFifo_syncb1;
1667
reg ReadTxDataFromFifo_syncb2;
1668
reg ReadTxDataFromFifo_syncb3;
1669
 
1670
 
1671
always @ (posedge MTxClk or posedge Reset)
1672
begin
1673
  if(Reset)
1674
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1675
  else
1676 96 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1677 39 mohor
     ReadTxDataFromFifo_tck <=#Tp 1'b1;
1678 150 mohor
  else
1679
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1680
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1681 38 mohor
end
1682
 
1683 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1684 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1685 38 mohor
begin
1686 40 mohor
  if(Reset)
1687 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
1688 38 mohor
  else
1689 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
1690
end
1691 38 mohor
 
1692 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1693 38 mohor
begin
1694 40 mohor
  if(Reset)
1695 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
1696 38 mohor
  else
1697 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
1698 38 mohor
end
1699
 
1700 40 mohor
always @ (posedge MTxClk or posedge Reset)
1701 38 mohor
begin
1702 40 mohor
  if(Reset)
1703 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
1704 38 mohor
  else
1705 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
1706 38 mohor
end
1707
 
1708 40 mohor
always @ (posedge MTxClk or posedge Reset)
1709 38 mohor
begin
1710 40 mohor
  if(Reset)
1711 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
1712 38 mohor
  else
1713 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
1714 38 mohor
end
1715
 
1716 150 mohor
always @ (posedge MTxClk or posedge Reset)
1717
begin
1718
  if(Reset)
1719
    ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
1720
  else
1721
    ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
1722
end
1723
 
1724 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1725 38 mohor
begin
1726 40 mohor
  if(Reset)
1727 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
1728 38 mohor
  else
1729 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
1730 38 mohor
end
1731
 
1732 39 mohor
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
1733
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1734 38 mohor
 
1735
 
1736 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1737 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1738 38 mohor
begin
1739 40 mohor
  if(Reset)
1740 39 mohor
    TxRetrySync1 <=#Tp 1'b0;
1741 38 mohor
  else
1742 39 mohor
    TxRetrySync1 <=#Tp TxRetry;
1743 38 mohor
end
1744
 
1745 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1746 38 mohor
begin
1747 40 mohor
  if(Reset)
1748 39 mohor
    TxRetry_wb <=#Tp 1'b0;
1749 38 mohor
  else
1750 39 mohor
    TxRetry_wb <=#Tp TxRetrySync1;
1751 38 mohor
end
1752
 
1753
 
1754 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1755 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1756 38 mohor
begin
1757 40 mohor
  if(Reset)
1758 39 mohor
    TxDoneSync1 <=#Tp 1'b0;
1759 38 mohor
  else
1760 39 mohor
    TxDoneSync1 <=#Tp TxDone;
1761 38 mohor
end
1762
 
1763 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1764 38 mohor
begin
1765 40 mohor
  if(Reset)
1766 39 mohor
    TxDone_wb <=#Tp 1'b0;
1767 38 mohor
  else
1768 39 mohor
    TxDone_wb <=#Tp TxDoneSync1;
1769 38 mohor
end
1770
 
1771 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1772 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1773 38 mohor
begin
1774 40 mohor
  if(Reset)
1775 39 mohor
    TxAbortSync1 <=#Tp 1'b0;
1776 38 mohor
  else
1777 39 mohor
    TxAbortSync1 <=#Tp TxAbort;
1778 38 mohor
end
1779
 
1780 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1781 38 mohor
begin
1782 40 mohor
  if(Reset)
1783 38 mohor
    TxAbort_wb <=#Tp 1'b0;
1784
  else
1785 39 mohor
    TxAbort_wb <=#Tp TxAbortSync1;
1786 38 mohor
end
1787
 
1788
 
1789 150 mohor
reg RxAbortSync1;
1790
reg RxAbortSync2;
1791
reg RxAbortSync3;
1792
reg RxAbortSync4;
1793
reg RxAbortSyncb1;
1794
reg RxAbortSyncb2;
1795 39 mohor
 
1796 150 mohor
//assign StartRxBDRead = RxStatusWrite | RxAbortLatched;
1797
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
1798
 
1799 40 mohor
// Reading the Rx buffer descriptor
1800
always @ (posedge WB_CLK_I or posedge Reset)
1801
begin
1802
  if(Reset)
1803
    RxBDRead <=#Tp 1'b1;
1804
  else
1805 166 mohor
  if(StartRxBDRead & ~RxReady)
1806 40 mohor
    RxBDRead <=#Tp 1'b1;
1807
  else
1808
  if(RxBDReady)
1809
    RxBDRead <=#Tp 1'b0;
1810
end
1811 39 mohor
 
1812
 
1813 38 mohor
// Reading of the next receive buffer descriptor starts after reception status is
1814
// written to the previous one.
1815
 
1816
// Latching READY status of the Rx buffer descriptor
1817 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1818 38 mohor
begin
1819 40 mohor
  if(Reset)
1820 38 mohor
    RxBDReady <=#Tp 1'b0;
1821
  else
1822 166 mohor
  if(RxPointerRead)
1823 150 mohor
    RxBDReady <=#Tp 1'b0;
1824
  else
1825 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1826
    RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
1827 38 mohor
end
1828
 
1829 40 mohor
// Latching Rx buffer descriptor status
1830
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
1831
always @ (posedge WB_CLK_I or posedge Reset)
1832 38 mohor
begin
1833 40 mohor
  if(Reset)
1834 60 mohor
    RxStatus <=#Tp 2'h0;
1835 38 mohor
  else
1836 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1837 60 mohor
    RxStatus <=#Tp ram_do[14:13];
1838 38 mohor
end
1839
 
1840
 
1841 166 mohor
// RxReady generation
1842
always @ (posedge WB_CLK_I or posedge Reset)
1843
begin
1844
  if(Reset)
1845
    RxReady <=#Tp 1'b0;
1846
  else
1847
  if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3)
1848
    RxReady <=#Tp 1'b0;
1849
  else
1850
  if(RxEn & RxEn_q & RxPointerRead)
1851
    RxReady <=#Tp 1'b1;
1852
end
1853 38 mohor
 
1854
 
1855 40 mohor
// Reading Rx BD pointer
1856
 
1857
 
1858
assign StartRxPointerRead = RxBDRead & RxBDReady;
1859
 
1860
// Reading Tx BD Pointer
1861
always @ (posedge WB_CLK_I or posedge Reset)
1862 38 mohor
begin
1863 40 mohor
  if(Reset)
1864
    RxPointerRead <=#Tp 1'b0;
1865 38 mohor
  else
1866 40 mohor
  if(StartRxPointerRead)
1867
    RxPointerRead <=#Tp 1'b1;
1868 38 mohor
  else
1869 166 mohor
  if(RxEn & RxEn_q)
1870 40 mohor
    RxPointerRead <=#Tp 1'b0;
1871 38 mohor
end
1872
 
1873 113 mohor
 
1874 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
1875
always @ (posedge WB_CLK_I or posedge Reset)
1876
begin
1877
  if(Reset)
1878 159 mohor
    RxPointerMSB <=#Tp 30'h0;
1879 40 mohor
  else
1880
  if(RxEn & RxEn_q & RxPointerRead)
1881 159 mohor
    RxPointerMSB <=#Tp ram_do[31:2];
1882 40 mohor
  else
1883 113 mohor
  if(MasterWbRX & m_wb_ack_i)
1884 159 mohor
      RxPointerMSB <=#Tp RxPointerMSB + 1; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
1885 40 mohor
end
1886 38 mohor
 
1887
 
1888 96 mohor
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
1889 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1890
begin
1891
  if(Reset)
1892 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp 0;
1893 96 mohor
  else
1894 159 mohor
  if(MasterWbRX & m_wb_ack_i)                 // After first write all RxByteSel are active
1895
    RxPointerLSB_rst[1:0] <=#Tp 0;
1896 96 mohor
  else
1897
  if(RxEn & RxEn_q & RxPointerRead)
1898 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
1899 96 mohor
end
1900
 
1901
 
1902 159 mohor
always @ (RxPointerLSB_rst)
1903 96 mohor
begin
1904 159 mohor
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
1905
    2'h0 : RxByteSel[3:0] = 4'hf;
1906
    2'h1 : RxByteSel[3:0] = 4'h7;
1907
    2'h2 : RxByteSel[3:0] = 4'h3;
1908
    2'h3 : RxByteSel[3:0] = 4'h1;
1909 96 mohor
  endcase
1910
end
1911
 
1912
 
1913
always @ (posedge WB_CLK_I or posedge Reset)
1914
begin
1915
  if(Reset)
1916 40 mohor
    RxEn_needed <=#Tp 1'b0;
1917 38 mohor
  else
1918 166 mohor
  if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
1919 40 mohor
    RxEn_needed <=#Tp 1'b1;
1920 38 mohor
  else
1921 40 mohor
  if(RxPointerRead & RxEn & RxEn_q)
1922
    RxEn_needed <=#Tp 1'b0;
1923 38 mohor
end
1924
 
1925
 
1926 40 mohor
// Reception status is written back to the buffer descriptor after the end of frame is detected.
1927
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
1928 38 mohor
 
1929 42 mohor
reg RxStatusWriteLatched;
1930
reg RxStatusWrite_rck;
1931
 
1932
always @ (posedge WB_CLK_I or posedge Reset)
1933
begin
1934
  if(Reset)
1935
    RxStatusWriteLatched <=#Tp 1'b0;
1936
  else
1937 87 mohor
  if(RxStatusWrite & ~RxStatusWrite_rck)
1938 42 mohor
    RxStatusWriteLatched <=#Tp 1'b1;
1939
  else
1940
  if(RxStatusWrite_rck)
1941
    RxStatusWriteLatched <=#Tp 1'b0;
1942
end
1943
 
1944
 
1945
always @ (posedge MRxClk or posedge Reset)
1946
begin
1947
  if(Reset)
1948
    RxStatusWrite_rck <=#Tp 1'b0;
1949
  else
1950 87 mohor
  if(RxStatusWriteLatched)
1951
    RxStatusWrite_rck <=#Tp 1'b1;
1952
  else
1953
    RxStatusWrite_rck <=#Tp 1'b0;
1954 42 mohor
end
1955
 
1956
 
1957 40 mohor
reg RxEnableWindow;
1958 38 mohor
 
1959
// Indicating that last byte is being reveived
1960 40 mohor
always @ (posedge MRxClk or posedge Reset)
1961 38 mohor
begin
1962 40 mohor
  if(Reset)
1963 38 mohor
    LastByteIn <=#Tp 1'b0;
1964
  else
1965 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
1966 38 mohor
    LastByteIn <=#Tp 1'b0;
1967
  else
1968 166 mohor
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
1969 38 mohor
    LastByteIn <=#Tp 1'b1;
1970
end
1971
 
1972 159 mohor
reg ShiftEnded_rck;
1973 40 mohor
reg ShiftEndedSync1;
1974
reg ShiftEndedSync2;
1975 118 mohor
reg ShiftEndedSync3;
1976
reg ShiftEndedSync_c1;
1977
reg ShiftEndedSync_c2;
1978
 
1979 40 mohor
wire StartShiftWillEnd;
1980 96 mohor
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
1981 38 mohor
 
1982
// Indicating that data reception will end
1983 40 mohor
always @ (posedge MRxClk or posedge Reset)
1984 38 mohor
begin
1985 40 mohor
  if(Reset)
1986 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1987
  else
1988 159 mohor
  if(ShiftEnded_rck | RxAbort)
1989 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1990
  else
1991 40 mohor
  if(StartShiftWillEnd)
1992 38 mohor
    ShiftWillEnd <=#Tp 1'b1;
1993
end
1994
 
1995
 
1996 40 mohor
 
1997 38 mohor
// Receive byte counter
1998 40 mohor
always @ (posedge MRxClk or posedge Reset)
1999 38 mohor
begin
2000 40 mohor
  if(Reset)
2001 38 mohor
    RxByteCnt <=#Tp 2'h0;
2002
  else
2003 159 mohor
  if(ShiftEnded_rck | RxAbort)
2004 38 mohor
    RxByteCnt <=#Tp 2'h0;
2005 97 lampret
  else
2006 166 mohor
  if(RxValid & RxStartFrm & RxReady)
2007 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2008 96 mohor
      2'h0 : RxByteCnt <=#Tp 2'h1;
2009
      2'h1 : RxByteCnt <=#Tp 2'h2;
2010
      2'h2 : RxByteCnt <=#Tp 2'h3;
2011
      2'h3 : RxByteCnt <=#Tp 2'h0;
2012
    endcase
2013 38 mohor
  else
2014 166 mohor
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
2015 40 mohor
    RxByteCnt <=#Tp RxByteCnt + 1'b1;
2016 38 mohor
end
2017
 
2018
 
2019
// Indicates how many bytes are valid within the last word
2020 40 mohor
always @ (posedge MRxClk or posedge Reset)
2021 38 mohor
begin
2022 40 mohor
  if(Reset)
2023 38 mohor
    RxValidBytes <=#Tp 2'h1;
2024
  else
2025 96 mohor
  if(RxValid & RxStartFrm)
2026 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2027 96 mohor
      2'h0 : RxValidBytes <=#Tp 2'h1;
2028
      2'h1 : RxValidBytes <=#Tp 2'h2;
2029
      2'h2 : RxValidBytes <=#Tp 2'h3;
2030
      2'h3 : RxValidBytes <=#Tp 2'h0;
2031
    endcase
2032 38 mohor
  else
2033 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
2034 38 mohor
    RxValidBytes <=#Tp RxValidBytes + 1;
2035
end
2036
 
2037
 
2038 40 mohor
always @ (posedge MRxClk or posedge Reset)
2039 38 mohor
begin
2040 40 mohor
  if(Reset)
2041
    RxDataLatched1       <=#Tp 24'h0;
2042 38 mohor
  else
2043 166 mohor
  if(RxValid & RxReady & ~LastByteIn)
2044 96 mohor
    if(RxStartFrm)
2045 40 mohor
    begin
2046 159 mohor
      case(RxPointerLSB_rst)     // synopsys parallel_case
2047 96 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2048
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2049
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2050
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2051
      endcase
2052
    end
2053
    else if (RxEnableWindow)
2054
    begin
2055 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
2056 82 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2057
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2058
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2059 40 mohor
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2060
      endcase
2061
    end
2062 38 mohor
end
2063
 
2064 40 mohor
wire SetWriteRxDataToFifo;
2065 38 mohor
 
2066 40 mohor
// Assembling data that will be written to the rx_fifo
2067
always @ (posedge MRxClk or posedge Reset)
2068 38 mohor
begin
2069 40 mohor
  if(Reset)
2070
    RxDataLatched2 <=#Tp 32'h0;
2071 38 mohor
  else
2072 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
2073 82 mohor
    RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData};              // Big Endian Byte Ordering
2074 38 mohor
  else
2075 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
2076 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
2077 82 mohor
 
2078
      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
2079
      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
2080
      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};
2081 40 mohor
    endcase
2082 38 mohor
end
2083
 
2084
 
2085 40 mohor
reg WriteRxDataToFifoSync1;
2086
reg WriteRxDataToFifoSync2;
2087 150 mohor
reg WriteRxDataToFifoSync3;
2088 38 mohor
 
2089
 
2090 40 mohor
// Indicating start of the reception process
2091 166 mohor
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
2092
                              (RxValid & RxReady &  RxStartFrm & (&RxPointerLSB_rst))           |
2093
                              (ShiftWillEnd & LastByteIn & (&RxByteCnt));
2094 38 mohor
 
2095 150 mohor
always @ (posedge MRxClk or posedge Reset)
2096
begin
2097
  if(Reset)
2098
    WriteRxDataToFifo <=#Tp 1'b0;
2099
  else
2100
  if(SetWriteRxDataToFifo & ~RxAbort)
2101
    WriteRxDataToFifo <=#Tp 1'b1;
2102
  else
2103
  if(WriteRxDataToFifoSync2 | RxAbort)
2104
    WriteRxDataToFifo <=#Tp 1'b0;
2105
end
2106 40 mohor
 
2107 150 mohor
 
2108
 
2109
always @ (posedge WB_CLK_I or posedge Reset)
2110
begin
2111
  if(Reset)
2112
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2113
  else
2114
  if(WriteRxDataToFifo)
2115
    WriteRxDataToFifoSync1 <=#Tp 1'b1;
2116
  else
2117
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2118
end
2119
 
2120
always @ (posedge WB_CLK_I or posedge Reset)
2121
begin
2122
  if(Reset)
2123
    WriteRxDataToFifoSync2 <=#Tp 1'b0;
2124
  else
2125
    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
2126
end
2127
 
2128
always @ (posedge WB_CLK_I or posedge Reset)
2129
begin
2130
  if(Reset)
2131
    WriteRxDataToFifoSync3 <=#Tp 1'b0;
2132
  else
2133
    WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
2134
end
2135
 
2136
wire WriteRxDataToFifo_wb;
2137
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
2138
 
2139
 
2140 90 mohor
reg LatchedRxStartFrm;
2141
reg SyncRxStartFrm;
2142
reg SyncRxStartFrm_q;
2143 150 mohor
reg SyncRxStartFrm_q2;
2144 90 mohor
wire RxFifoReset;
2145 40 mohor
 
2146 90 mohor
always @ (posedge MRxClk or posedge Reset)
2147
begin
2148
  if(Reset)
2149
    LatchedRxStartFrm <=#Tp 0;
2150
  else
2151 150 mohor
  if(RxStartFrm & ~SyncRxStartFrm_q)
2152 90 mohor
    LatchedRxStartFrm <=#Tp 1;
2153
  else
2154 150 mohor
  if(SyncRxStartFrm_q)
2155 90 mohor
    LatchedRxStartFrm <=#Tp 0;
2156
end
2157
 
2158
 
2159
always @ (posedge WB_CLK_I or posedge Reset)
2160
begin
2161
  if(Reset)
2162
    SyncRxStartFrm <=#Tp 0;
2163
  else
2164
  if(LatchedRxStartFrm)
2165
    SyncRxStartFrm <=#Tp 1;
2166
  else
2167
    SyncRxStartFrm <=#Tp 0;
2168
end
2169
 
2170
 
2171
always @ (posedge WB_CLK_I or posedge Reset)
2172
begin
2173
  if(Reset)
2174
    SyncRxStartFrm_q <=#Tp 0;
2175
  else
2176
    SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
2177
end
2178
 
2179 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2180
begin
2181
  if(Reset)
2182
    SyncRxStartFrm_q2 <=#Tp 0;
2183
  else
2184
    SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
2185
end
2186 90 mohor
 
2187
 
2188 150 mohor
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
2189 90 mohor
 
2190 150 mohor
 
2191 219 mohor
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
2192 88 mohor
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
2193
         .clk(WB_CLK_I),                                .reset(Reset),
2194 219 mohor
         .write(WriteRxDataToFifo_wb & ~RxBufferFull),  .read(MasterWbRX & m_wb_ack_i),
2195 90 mohor
         .clear(RxFifoReset),                           .full(RxBufferFull),
2196 118 mohor
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
2197 150 mohor
         .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)
2198 88 mohor
        );
2199 40 mohor
 
2200 226 tadejm
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
2201
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
2202 219 mohor
assign WriteRxDataToMemory = ~RxBufferEmpty;
2203 226 tadejm
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
2204 40 mohor
 
2205
 
2206
// Generation of the end-of-frame signal
2207
always @ (posedge MRxClk or posedge Reset)
2208 38 mohor
begin
2209 40 mohor
  if(Reset)
2210 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2211 38 mohor
  else
2212 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
2213 159 mohor
    ShiftEnded_rck <=#Tp 1'b1;
2214 38 mohor
  else
2215 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
2216 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2217 38 mohor
end
2218
 
2219 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2220
begin
2221
  if(Reset)
2222
    ShiftEndedSync1 <=#Tp 1'b0;
2223
  else
2224 159 mohor
    ShiftEndedSync1 <=#Tp ShiftEnded_rck;
2225 40 mohor
end
2226 38 mohor
 
2227 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2228 38 mohor
begin
2229 40 mohor
  if(Reset)
2230
    ShiftEndedSync2 <=#Tp 1'b0;
2231 38 mohor
  else
2232 90 mohor
    ShiftEndedSync2 <=#Tp ShiftEndedSync1;
2233 40 mohor
end
2234 38 mohor
 
2235 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2236
begin
2237
  if(Reset)
2238
    ShiftEndedSync3 <=#Tp 1'b0;
2239
  else
2240
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
2241
    ShiftEndedSync3 <=#Tp 1'b1;
2242
  else
2243
  if(ShiftEnded)
2244
    ShiftEndedSync3 <=#Tp 1'b0;
2245
end
2246 38 mohor
 
2247 40 mohor
// Generation of the end-of-frame signal
2248
always @ (posedge WB_CLK_I or posedge Reset)
2249 38 mohor
begin
2250 40 mohor
  if(Reset)
2251
    ShiftEnded <=#Tp 1'b0;
2252 38 mohor
  else
2253 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2254 40 mohor
    ShiftEnded <=#Tp 1'b1;
2255 38 mohor
  else
2256 40 mohor
  if(RxStatusWrite)
2257
    ShiftEnded <=#Tp 1'b0;
2258 38 mohor
end
2259
 
2260 118 mohor
always @ (posedge MRxClk or posedge Reset)
2261
begin
2262
  if(Reset)
2263
    ShiftEndedSync_c1 <=#Tp 1'b0;
2264
  else
2265
    ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
2266
end
2267 38 mohor
 
2268 118 mohor
always @ (posedge MRxClk or posedge Reset)
2269
begin
2270
  if(Reset)
2271
    ShiftEndedSync_c2 <=#Tp 1'b0;
2272
  else
2273
    ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
2274
end
2275
 
2276 40 mohor
// Generation of the end-of-frame signal
2277
always @ (posedge MRxClk or posedge Reset)
2278 38 mohor
begin
2279 40 mohor
  if(Reset)
2280
    RxEnableWindow <=#Tp 1'b0;
2281 38 mohor
  else
2282 40 mohor
  if(RxStartFrm)
2283
    RxEnableWindow <=#Tp 1'b1;
2284 38 mohor
  else
2285 40 mohor
  if(RxEndFrm | RxAbort)
2286
    RxEnableWindow <=#Tp 1'b0;
2287 38 mohor
end
2288
 
2289
 
2290 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2291 38 mohor
begin
2292 40 mohor
  if(Reset)
2293
    RxAbortSync1 <=#Tp 1'b0;
2294 38 mohor
  else
2295 150 mohor
    RxAbortSync1 <=#Tp RxAbortLatched;
2296 40 mohor
end
2297
 
2298
always @ (posedge WB_CLK_I or posedge Reset)
2299
begin
2300
  if(Reset)
2301
    RxAbortSync2 <=#Tp 1'b0;
2302 38 mohor
  else
2303 40 mohor
    RxAbortSync2 <=#Tp RxAbortSync1;
2304 38 mohor
end
2305
 
2306 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2307
begin
2308
  if(Reset)
2309
    RxAbortSync3 <=#Tp 1'b0;
2310
  else
2311
    RxAbortSync3 <=#Tp RxAbortSync2;
2312
end
2313
 
2314
always @ (posedge WB_CLK_I or posedge Reset)
2315
begin
2316
  if(Reset)
2317
    RxAbortSync4 <=#Tp 1'b0;
2318
  else
2319
    RxAbortSync4 <=#Tp RxAbortSync3;
2320
end
2321
 
2322 40 mohor
always @ (posedge MRxClk or posedge Reset)
2323
begin
2324
  if(Reset)
2325
    RxAbortSyncb1 <=#Tp 1'b0;
2326
  else
2327
    RxAbortSyncb1 <=#Tp RxAbortSync2;
2328
end
2329 38 mohor
 
2330 40 mohor
always @ (posedge MRxClk or posedge Reset)
2331 38 mohor
begin
2332 40 mohor
  if(Reset)
2333
    RxAbortSyncb2 <=#Tp 1'b0;
2334 38 mohor
  else
2335 40 mohor
    RxAbortSyncb2 <=#Tp RxAbortSyncb1;
2336 38 mohor
end
2337
 
2338
 
2339 64 mohor
always @ (posedge MRxClk or posedge Reset)
2340
begin
2341
  if(Reset)
2342
    RxAbortLatched <=#Tp 1'b0;
2343
  else
2344 150 mohor
  if(RxAbortSyncb2)
2345
    RxAbortLatched <=#Tp 1'b0;
2346
  else
2347 64 mohor
  if(RxAbort)
2348
    RxAbortLatched <=#Tp 1'b1;
2349
end
2350 40 mohor
 
2351 64 mohor
 
2352 42 mohor
always @ (posedge MRxClk or posedge Reset)
2353
begin
2354
  if(Reset)
2355
    LatchedRxLength[15:0] <=#Tp 16'h0;
2356
  else
2357 150 mohor
  if(LoadRxStatus)
2358 42 mohor
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
2359
end
2360
 
2361
 
2362 60 mohor
assign RxStatusIn = {RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
2363 42 mohor
 
2364
always @ (posedge MRxClk or posedge Reset)
2365
begin
2366
  if(Reset)
2367
    RxStatusInLatched <=#Tp 'h0;
2368
  else
2369 150 mohor
  if(LoadRxStatus)
2370 42 mohor
    RxStatusInLatched <=#Tp RxStatusIn;
2371
end
2372
 
2373
 
2374 60 mohor
// Rx overrun
2375
always @ (posedge WB_CLK_I or posedge Reset)
2376
begin
2377
  if(Reset)
2378
    RxOverrun <=#Tp 1'b0;
2379
  else
2380
  if(RxStatusWrite)
2381
    RxOverrun <=#Tp 1'b0;
2382
  else
2383
  if(RxBufferFull & WriteRxDataToFifo_wb)
2384
    RxOverrun <=#Tp 1'b1;
2385
end
2386 48 mohor
 
2387 77 mohor
 
2388
 
2389
wire TxError;
2390
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2391
 
2392
wire RxError;
2393
 
2394 239 tadejm
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
2395
// are aborted when signal r_RecSmall is set to 0 in MODER register.
2396
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
2397
 
2398 77 mohor
// Tx Done Interrupt
2399
always @ (posedge WB_CLK_I or posedge Reset)
2400
begin
2401
  if(Reset)
2402
    TxB_IRQ <=#Tp 1'b0;
2403
  else
2404
  if(TxStatusWrite & TxIRQEn)
2405
    TxB_IRQ <=#Tp ~TxError;
2406
  else
2407
    TxB_IRQ <=#Tp 1'b0;
2408
end
2409
 
2410
 
2411
// Tx Error Interrupt
2412
always @ (posedge WB_CLK_I or posedge Reset)
2413
begin
2414
  if(Reset)
2415
    TxE_IRQ <=#Tp 1'b0;
2416
  else
2417
  if(TxStatusWrite & TxIRQEn)
2418
    TxE_IRQ <=#Tp TxError;
2419
  else
2420
    TxE_IRQ <=#Tp 1'b0;
2421
end
2422
 
2423
 
2424
// Rx Done Interrupt
2425
always @ (posedge WB_CLK_I or posedge Reset)
2426
begin
2427
  if(Reset)
2428
    RxB_IRQ <=#Tp 1'b0;
2429
  else
2430
  if(RxStatusWrite & RxIRQEn)
2431 167 mohor
    RxB_IRQ <=#Tp ReceivedPacketGood & ~RxError;
2432 77 mohor
  else
2433
    RxB_IRQ <=#Tp 1'b0;
2434
end
2435
 
2436
 
2437
// Rx Error Interrupt
2438
always @ (posedge WB_CLK_I or posedge Reset)
2439
begin
2440
  if(Reset)
2441
    RxE_IRQ <=#Tp 1'b0;
2442
  else
2443
  if(RxStatusWrite & RxIRQEn)
2444
    RxE_IRQ <=#Tp RxError;
2445
  else
2446
    RxE_IRQ <=#Tp 1'b0;
2447
end
2448
 
2449
 
2450 166 mohor
// Busy Interrupt
2451 77 mohor
 
2452 166 mohor
reg Busy_IRQ_rck;
2453
reg Busy_IRQ_sync1;
2454
reg Busy_IRQ_sync2;
2455
reg Busy_IRQ_sync3;
2456
reg Busy_IRQ_syncb1;
2457
reg Busy_IRQ_syncb2;
2458 77 mohor
 
2459
 
2460 166 mohor
always @ (posedge MRxClk or posedge Reset)
2461
begin
2462
  if(Reset)
2463
    Busy_IRQ_rck <=#Tp 1'b0;
2464
  else
2465
  if(RxValid & RxStartFrm & ~RxReady)
2466
    Busy_IRQ_rck <=#Tp 1'b1;
2467
  else
2468
  if(Busy_IRQ_syncb2)
2469
    Busy_IRQ_rck <=#Tp 1'b0;
2470
end
2471 77 mohor
 
2472 166 mohor
always @ (posedge WB_CLK_I)
2473
begin
2474
    Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
2475
    Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
2476
    Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
2477
end
2478
 
2479
always @ (posedge MRxClk)
2480
begin
2481
    Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
2482
    Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
2483
end
2484
 
2485
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
2486
 
2487
 
2488 60 mohor
 
2489
// TX
2490 61 mohor
// bit 15 ready
2491
// bit 14 interrupt
2492
// bit 13 wrap
2493
// bit 12 pad
2494
// bit 11 crc
2495
// bit 10 last
2496
// bit 9  pause request (control frame)
2497
// bit 8  TxUnderRun          
2498
// bit 7-4 RetryCntLatched    
2499
// bit 3  retransmittion limit
2500
// bit 2  LateCollLatched        
2501
// bit 1  DeferLatched        
2502
// bit 0  CarrierSenseLost    
2503 60 mohor
 
2504
 
2505
// RX
2506
// bit 15 od rx je empty
2507 61 mohor
// bit 14 od rx je interrupt
2508 60 mohor
// bit 13 od rx je wrap
2509
// bit 12 od rx je reserved
2510
// bit 11 od rx je reserved
2511
// bit 10 od rx je reserved
2512
// bit 9  od rx je reserved
2513
// bit 8  od rx je reserved
2514 110 mohor
// bit 7  od rx je Miss
2515 60 mohor
// bit 6  od rx je RxOverrun
2516
// bit 5  od rx je InvalidSymbol
2517
// bit 4  od rx je DribbleNibble
2518
// bit 3  od rx je ReceivedPacketTooBig
2519
// bit 2  od rx je ShortFrame
2520
// bit 1  od rx je LatchedCrcError
2521
// bit 0  od rx je RxLateCollision
2522
 
2523 110 mohor
 
2524 38 mohor
endmodule
2525
 

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