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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 261

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1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 166 mohor
////  All additional information is available in the Readme.txt   ////
12 38 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 261 mohor
// Revision 1.45  2002/11/19 17:33:34  mohor
45
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
46
// that a frame was received because of the promiscous mode.
47
//
48 250 mohor
// Revision 1.44  2002/11/13 22:21:40  tadejm
49
// RxError is not generated when small frame reception is enabled and small
50
// frames are received.
51
//
52 239 tadejm
// Revision 1.43  2002/10/18 20:53:34  mohor
53
// case changed to casex.
54
//
55 229 mohor
// Revision 1.42  2002/10/18 17:04:20  tadejm
56
// Changed BIST scan signals.
57
//
58 227 tadejm
// Revision 1.41  2002/10/18 15:42:09  tadejm
59
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
60
//
61 226 tadejm
// Revision 1.40  2002/10/14 16:07:02  mohor
62
// TxStatus is written after last access to the TX fifo is finished (in case of abort
63
// or retry). TxDone is fixed.
64
//
65 221 mohor
// Revision 1.39  2002/10/11 15:35:20  mohor
66
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
67
// TxDone and TxRetry are generated after the current WISHBONE access is
68
// finished.
69
//
70 219 mohor
// Revision 1.38  2002/10/10 16:29:30  mohor
71
// BIST added.
72
//
73 210 mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
74
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
75
//
76 167 mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
77
// Reception is possible after RxPointer is read and not after BD is read. For
78
// that reason RxBDReady is changed to RxReady.
79
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
80
// comes, interrupt is generated.
81
//
82 166 mohor
// Revision 1.35  2002/09/10 10:35:23  mohor
83
// Ethernet debug registers removed.
84
//
85 164 mohor
// Revision 1.34  2002/09/08 16:31:49  mohor
86
// Async reset for WB_ACK_O removed (when core was in reset, it was
87
// impossible to access BDs).
88
// RxPointers and TxPointers names changed to be more descriptive.
89
// TxUnderRun synchronized.
90
//
91 159 mohor
// Revision 1.33  2002/09/04 18:47:57  mohor
92
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
93
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
94
// was not used OK.
95
//
96 150 mohor
// Revision 1.32  2002/08/14 19:31:48  mohor
97
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
98
// need to multiply or devide any more.
99
//
100 134 mohor
// Revision 1.31  2002/07/25 18:29:01  mohor
101
// WriteRxDataToMemory signal changed so end of frame (when last word is
102
// written to fifo) is changed.
103
//
104 127 mohor
// Revision 1.30  2002/07/23 15:28:31  mohor
105
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
106
//
107 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
108
// ShiftEnded synchronization changed.
109
//
110 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
111
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
112
//
113 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
114
// RxPointer bug fixed.
115
//
116 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
117
// Previous bug wasn't succesfully removed. Now fixed.
118
//
119 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
120
// Master state machine had a bug when switching from master write to
121
// master read.
122
//
123 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
124
// m_wb_cyc_o signal released after every single transfer.
125
//
126 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
127
// Outputs registered. Reset changed for eth_wishbone module.
128
//
129 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
130
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
131
// bug fixed.
132
//
133 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
134
// Small typo fixed.
135
//
136 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
137
// Any address can be used for Tx and Rx BD pointers. Address does not need
138
// to be aligned.
139
//
140 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
141
// Comments in Slovene language removed.
142
//
143 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
144
// casex changed with case, fifo reset changed.
145
//
146 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
147
// rx_fifo was not always cleared ok. Fixed.
148
//
149 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
150
// Status was not latched correctly sometimes. Fixed.
151
//
152 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
153
// Big Endian problem when sending frames fixed.
154
//
155 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
156
// Byte ordering changed (Big Endian used). casex changed with case because
157
// Xilinx Foundation had problems. Tested in HW. It WORKS.
158
//
159 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
160
// Small fixes for external/internal DMA missmatches.
161
//
162 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
163
// Interrupts changed
164
//
165 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
166
// Status was not written correctly when frames were discarted because of
167
// address mismatch.
168
//
169 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
170
// RxStartFrm cleared when abort or retry comes.
171
//
172 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
173
// Changes that were lost when updating from 1.5 to 1.8 fixed.
174
//
175 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
176
// Addition  of new module eth_addrcheck.v
177
//
178
// Revision 1.7  2002/02/12 17:03:47  mohor
179
// RxOverRun added to statuses.
180
//
181
// Revision 1.6  2002/02/11 09:18:22  mohor
182
// Tx status is written back to the BD.
183
//
184 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
185
// Rx status is written back to the BD.
186
//
187 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
188
// non-DMA host interface added. Select the right configutation in eth_defines.
189
//
190 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
191
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
192
// MHz. Statuses, overrun, control frame transmission and reception still  need
193
// to be fixed.
194
//
195 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
196
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
197
// added.
198
//
199 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
200
// Initial version. Equals to eth_wishbonedma.v at this moment.
201 38 mohor
//
202
//
203
//
204
 
205
`include "eth_defines.v"
206
`include "timescale.v"
207
 
208
 
209
module eth_wishbone
210
   (
211
 
212
    // WISHBONE common
213 40 mohor
    WB_CLK_I, WB_DAT_I, WB_DAT_O,
214 38 mohor
 
215
    // WISHBONE slave
216 77 mohor
                WB_ADR_I, WB_WE_I, WB_ACK_O,
217 40 mohor
    BDCs,
218 38 mohor
 
219 40 mohor
    Reset,
220
 
221 39 mohor
    // WISHBONE master
222
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
223
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
224
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
225
 
226 219 mohor
`ifdef ETH_WISHBONE_B3
227
    m_wb_cti_o, m_wb_bte_o,
228
`endif
229
 
230 38 mohor
    //TX
231 60 mohor
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
232 150 mohor
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
233 38 mohor
    PerPacketPad,
234
 
235
    //RX
236 40 mohor
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
237 38 mohor
 
238
    // Register
239 261 mohor
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RxFlow,
240 38 mohor
 
241
    // Interrupts
242 150 mohor
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
243 42 mohor
 
244 60 mohor
    // Rx Status
245 42 mohor
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
246 250 mohor
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
247 261 mohor
    ReceivedPauseFrm,
248 60 mohor
 
249
    // Tx Status
250 164 mohor
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
251
 
252 210 mohor
    // Bist
253
`ifdef ETH_BIST
254 227 tadejm
    ,
255
    // debug chain signals
256
    scanb_rst,      // bist scan reset
257
    scanb_clk,      // bist scan clock
258
    scanb_si,       // bist scan serial in
259
    scanb_so,       // bist scan serial out
260
    scanb_en        // bist scan shift enable
261 210 mohor
`endif
262
 
263
 
264
 
265 38 mohor
                );
266
 
267
 
268
parameter Tp = 1;
269
 
270 150 mohor
 
271 38 mohor
// WISHBONE common
272
input           WB_CLK_I;       // WISHBONE clock
273
input  [31:0]   WB_DAT_I;       // WISHBONE data input
274
output [31:0]   WB_DAT_O;       // WISHBONE data output
275
 
276
// WISHBONE slave
277
input   [9:2]   WB_ADR_I;       // WISHBONE address input
278
input           WB_WE_I;        // WISHBONE write enable input
279
input           BDCs;           // Buffer descriptors are selected
280
output          WB_ACK_O;       // WISHBONE acknowledge output
281
 
282 39 mohor
// WISHBONE master
283
output  [31:0]  m_wb_adr_o;     // 
284
output   [3:0]  m_wb_sel_o;     // 
285
output          m_wb_we_o;      // 
286
output  [31:0]  m_wb_dat_o;     // 
287
output          m_wb_cyc_o;     // 
288
output          m_wb_stb_o;     // 
289
input   [31:0]  m_wb_dat_i;     // 
290
input           m_wb_ack_i;     // 
291
input           m_wb_err_i;     // 
292
 
293 219 mohor
`ifdef ETH_WISHBONE_B3
294
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
295
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
296
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
297
`endif
298
 
299 40 mohor
input           Reset;       // Reset signal
300 39 mohor
 
301 60 mohor
// Rx Status signals
302 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
303
input           LatchedCrcError;  // CRC error
304
input           RxLateCollision;  // Late collision occured while receiving frame
305
input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
306
input           DribbleNibble;    // Extra nibble received
307
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
308
input    [15:0] RxLength;         // Length of the incoming frame
309
input           LoadRxStatus;     // Rx status was loaded
310 77 mohor
input           ReceivedPacketGood;// Received packet's length and CRC are good
311 250 mohor
input           AddressMiss;      // When a packet is received AddressMiss status is written to the Rx BD
312 261 mohor
input           r_RxFlow;
313
input           ReceivedPauseFrm;
314 39 mohor
 
315 60 mohor
// Tx Status signals
316
input     [3:0] RetryCntLatched;  // Latched Retry Counter
317
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
318
input           LateCollLatched;  // Late collision occured
319
input           DeferLatched;     // Defer indication (Frame was defered before sucessfully sent)
320
input           CarrierSenseLost; // Carrier Sense was lost during the frame transmission
321
 
322 38 mohor
// Tx
323
input           MTxClk;         // Transmit clock (from PHY)
324
input           TxUsedData;     // Transmit packet used data
325
input           TxRetry;        // Transmit packet retry
326
input           TxAbort;        // Transmit packet abort
327
input           TxDone;         // Transmission ended
328
output          TxStartFrm;     // Transmit packet start frame
329
output          TxEndFrm;       // Transmit packet end frame
330
output  [7:0]   TxData;         // Transmit packet data byte
331
output          TxUnderRun;     // Transmit packet under-run
332
output          PerPacketCrcEn; // Per packet crc enable
333
output          PerPacketPad;   // Per packet pading
334
 
335
// Rx
336
input           MRxClk;         // Receive clock (from PHY)
337
input   [7:0]   RxData;         // Received data byte (from PHY)
338
input           RxValid;        // 
339
input           RxStartFrm;     // 
340
input           RxEndFrm;       // 
341 40 mohor
input           RxAbort;        // This signal is set when address doesn't match.
342 38 mohor
 
343
//Register
344
input           r_TxEn;         // Transmit enable
345
input           r_RxEn;         // Receive enable
346
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
347
input           TX_BD_NUM_Wr;   // RxBDNumber written
348
 
349
// Interrupts
350
output TxB_IRQ;
351
output TxE_IRQ;
352
output RxB_IRQ;
353 77 mohor
output RxE_IRQ;
354 38 mohor
output Busy_IRQ;
355
 
356 77 mohor
 
357 210 mohor
// Bist
358
`ifdef ETH_BIST
359 227 tadejm
input   scanb_rst;      // bist scan reset
360
input   scanb_clk;      // bist scan clock
361
input   scanb_si;       // bist scan serial in
362
output  scanb_so;       // bist scan serial out
363
input   scanb_en;       // bist scan shift enable
364 210 mohor
`endif
365
 
366 77 mohor
reg TxB_IRQ;
367
reg TxE_IRQ;
368
reg RxB_IRQ;
369
reg RxE_IRQ;
370
 
371 38 mohor
reg             TxStartFrm;
372
reg             TxEndFrm;
373
reg     [7:0]   TxData;
374
 
375
reg             TxUnderRun;
376 60 mohor
reg             TxUnderRun_wb;
377 38 mohor
 
378
reg             TxBDRead;
379 39 mohor
wire            TxStatusWrite;
380 38 mohor
 
381
reg     [1:0]   TxValidBytesLatched;
382
 
383
reg    [15:0]   TxLength;
384 60 mohor
reg    [15:0]   LatchedTxLength;
385
reg   [14:11]   TxStatus;
386 38 mohor
 
387 60 mohor
reg   [14:13]   RxStatus;
388 38 mohor
 
389
reg             TxStartFrm_wb;
390
reg             TxRetry_wb;
391 39 mohor
reg             TxAbort_wb;
392 38 mohor
reg             TxDone_wb;
393
 
394
reg             TxDone_wb_q;
395
reg             TxAbort_wb_q;
396 39 mohor
reg             TxRetry_wb_q;
397 219 mohor
reg             TxRetryPacket;
398 221 mohor
reg             TxRetryPacket_NotCleared;
399
reg             TxDonePacket;
400
reg             TxDonePacket_NotCleared;
401 219 mohor
reg             TxAbortPacket;
402 221 mohor
reg             TxAbortPacket_NotCleared;
403 38 mohor
reg             RxBDReady;
404 166 mohor
reg             RxReady;
405 38 mohor
reg             TxBDReady;
406
 
407
reg             RxBDRead;
408 40 mohor
wire            RxStatusWrite;
409 38 mohor
 
410
reg    [31:0]   TxDataLatched;
411
reg     [1:0]   TxByteCnt;
412
reg             LastWord;
413 39 mohor
reg             ReadTxDataFromFifo_tck;
414 38 mohor
 
415
reg             BlockingTxStatusWrite;
416
reg             BlockingTxBDRead;
417
 
418 40 mohor
reg             Flop;
419 38 mohor
 
420
reg     [7:0]   TxBDAddress;
421
reg     [7:0]   RxBDAddress;
422
 
423
reg             TxRetrySync1;
424
reg             TxAbortSync1;
425 39 mohor
reg             TxDoneSync1;
426 38 mohor
 
427
reg             TxAbort_q;
428
reg             TxRetry_q;
429
reg             TxUsedData_q;
430
 
431
reg    [31:0]   RxDataLatched2;
432 82 mohor
 
433
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
434
 
435 38 mohor
reg     [1:0]   RxValidBytes;
436
reg     [1:0]   RxByteCnt;
437
reg             LastByteIn;
438
reg             ShiftWillEnd;
439
 
440 40 mohor
reg             WriteRxDataToFifo;
441 42 mohor
reg    [15:0]   LatchedRxLength;
442 64 mohor
reg             RxAbortLatched;
443 38 mohor
 
444 40 mohor
reg             ShiftEnded;
445 60 mohor
reg             RxOverrun;
446 38 mohor
 
447 40 mohor
reg             BDWrite;                    // BD Write Enable for access from WISHBONE side
448
reg             BDRead;                     // BD Read access from WISHBONE side
449 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
450
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
451 38 mohor
 
452 39 mohor
reg             TxEndFrm_wb;
453 38 mohor
 
454 39 mohor
wire            TxRetryPulse;
455 38 mohor
wire            TxDonePulse;
456
wire            TxAbortPulse;
457
 
458
wire            StartRxBDRead;
459
 
460
wire            StartTxBDRead;
461
 
462
wire            TxIRQEn;
463
wire            WrapTxStatusBit;
464
 
465 77 mohor
wire            RxIRQEn;
466 38 mohor
wire            WrapRxStatusBit;
467
 
468
wire    [1:0]   TxValidBytes;
469
 
470
wire    [7:0]   TempTxBDAddress;
471
wire    [7:0]   TempRxBDAddress;
472
 
473
wire            SetGotData;
474
wire            GotDataEvaluate;
475
 
476 106 mohor
reg             WB_ACK_O;
477 38 mohor
 
478 261 mohor
wire    [8:0]   RxStatusIn;
479
reg     [8:0]   RxStatusInLatched;
480 42 mohor
 
481 39 mohor
reg WbEn, WbEn_q;
482
reg RxEn, RxEn_q;
483
reg TxEn, TxEn_q;
484 38 mohor
 
485 39 mohor
wire ram_ce;
486
wire ram_we;
487
wire ram_oe;
488
reg [7:0]   ram_addr;
489
reg [31:0]  ram_di;
490
wire [31:0] ram_do;
491 38 mohor
 
492 39 mohor
wire StartTxPointerRead;
493
reg  TxPointerRead;
494
reg TxEn_needed;
495 40 mohor
reg RxEn_needed;
496 38 mohor
 
497 40 mohor
wire StartRxPointerRead;
498
reg RxPointerRead;
499 38 mohor
 
500 219 mohor
`ifdef ETH_WISHBONE_B3
501
assign m_wb_bte_o = 2'b00;    // Linear burst
502
`endif
503 39 mohor
 
504 219 mohor
 
505 159 mohor
always @ (posedge WB_CLK_I)
506 40 mohor
begin
507 159 mohor
  WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
508 40 mohor
end
509 39 mohor
 
510 106 mohor
assign WB_DAT_O = ram_do;
511 39 mohor
 
512 41 mohor
// Generic synchronous single-port RAM interface
513 119 mohor
eth_spram_256x32 bd_ram (
514 226 tadejm
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
515 210 mohor
`ifdef ETH_BIST
516 227 tadejm
  ,
517
  .scanb_rst      (scanb_rst),
518
  .scanb_clk      (scanb_clk),
519
  .scanb_si       (scanb_si),
520
  .scanb_so       (scanb_so),
521
  .scanb_en       (scanb_en)
522 210 mohor
`endif
523 39 mohor
);
524 41 mohor
 
525 39 mohor
assign ram_ce = 1'b1;
526 40 mohor
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
527 61 mohor
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
528 39 mohor
 
529
 
530 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
531 38 mohor
begin
532 40 mohor
  if(Reset)
533 39 mohor
    TxEn_needed <=#Tp 1'b0;
534 38 mohor
  else
535 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
536 39 mohor
    TxEn_needed <=#Tp 1'b1;
537
  else
538
  if(TxPointerRead & TxEn & TxEn_q)
539
    TxEn_needed <=#Tp 1'b0;
540 38 mohor
end
541
 
542 39 mohor
// Enabling access to the RAM for three devices.
543 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
544 39 mohor
begin
545 40 mohor
  if(Reset)
546 39 mohor
    begin
547
      WbEn <=#Tp 1'b1;
548
      RxEn <=#Tp 1'b0;
549
      TxEn <=#Tp 1'b0;
550
      ram_addr <=#Tp 8'h0;
551
      ram_di <=#Tp 32'h0;
552 77 mohor
      BDRead <=#Tp 1'b0;
553
      BDWrite <=#Tp 1'b0;
554 39 mohor
    end
555
  else
556
    begin
557
      // Switching between three stages depends on enable signals
558 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
559
        5'b100_10, 5'b100_11 :
560 39 mohor
          begin
561
            WbEn <=#Tp 1'b0;
562
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
563
            TxEn <=#Tp 1'b0;
564 40 mohor
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
565 39 mohor
            ram_di <=#Tp RxBDDataIn;
566
          end
567
        5'b100_01 :
568
          begin
569
            WbEn <=#Tp 1'b0;
570
            RxEn <=#Tp 1'b0;
571
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
572
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
573
            ram_di <=#Tp TxBDDataIn;
574
          end
575 90 mohor
        5'b010_00, 5'b010_10 :
576 39 mohor
          begin
577
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
578
            RxEn <=#Tp 1'b0;
579
            TxEn <=#Tp 1'b0;
580
            ram_addr <=#Tp WB_ADR_I[9:2];
581
            ram_di <=#Tp WB_DAT_I;
582 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
583
            BDRead <=#Tp BDCs & ~WB_WE_I;
584 39 mohor
          end
585 90 mohor
        5'b010_01, 5'b010_11 :
586 39 mohor
          begin
587
            WbEn <=#Tp 1'b0;
588
            RxEn <=#Tp 1'b0;
589
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
590
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
591
            ram_di <=#Tp TxBDDataIn;
592
          end
593 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
594 39 mohor
          begin
595
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
596
            RxEn <=#Tp 1'b0;
597
            TxEn <=#Tp 1'b0;
598
            ram_addr <=#Tp WB_ADR_I[9:2];
599
            ram_di <=#Tp WB_DAT_I;
600 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
601
            BDRead <=#Tp BDCs & ~WB_WE_I;
602 39 mohor
          end
603
        5'b100_00 :
604
          begin
605
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
606
          end
607
        5'b000_00 :
608
          begin
609
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
610
            RxEn <=#Tp 1'b0;
611
            TxEn <=#Tp 1'b0;
612
            ram_addr <=#Tp WB_ADR_I[9:2];
613
            ram_di <=#Tp WB_DAT_I;
614 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
615
            BDRead <=#Tp BDCs & ~WB_WE_I;
616 39 mohor
          end
617
      endcase
618
    end
619
end
620
 
621
 
622
// Delayed stage signals
623 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
624 39 mohor
begin
625 40 mohor
  if(Reset)
626 39 mohor
    begin
627
      WbEn_q <=#Tp 1'b0;
628
      RxEn_q <=#Tp 1'b0;
629
      TxEn_q <=#Tp 1'b0;
630
    end
631
  else
632
    begin
633
      WbEn_q <=#Tp WbEn;
634
      RxEn_q <=#Tp RxEn;
635
      TxEn_q <=#Tp TxEn;
636
    end
637
end
638
 
639 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
640 40 mohor
always @ (posedge MTxClk or posedge Reset)
641 38 mohor
begin
642 40 mohor
  if(Reset)
643 38 mohor
    Flop <=#Tp 1'b0;
644
  else
645
  if(TxDone | TxAbort | TxRetry_q)
646
    Flop <=#Tp 1'b0;
647
  else
648
  if(TxUsedData)
649
    Flop <=#Tp ~Flop;
650
end
651
 
652 39 mohor
wire ResetTxBDReady;
653
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
654 38 mohor
 
655
// Latching READY status of the Tx buffer descriptor
656 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
657 38 mohor
begin
658 40 mohor
  if(Reset)
659 38 mohor
    TxBDReady <=#Tp 1'b0;
660
  else
661 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
662
    TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
663
  else                                                // Only packets larger then 4 bytes are transmitted.
664 39 mohor
  if(ResetTxBDReady)
665 38 mohor
    TxBDReady <=#Tp 1'b0;
666
end
667
 
668
 
669 39 mohor
// Reading the Tx buffer descriptor
670 221 mohor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
671 39 mohor
 
672 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
673 38 mohor
begin
674 40 mohor
  if(Reset)
675 39 mohor
    TxBDRead <=#Tp 1'b1;
676 38 mohor
  else
677 110 mohor
  if(StartTxBDRead)
678 39 mohor
    TxBDRead <=#Tp 1'b1;
679 38 mohor
  else
680 39 mohor
  if(TxBDReady)
681
    TxBDRead <=#Tp 1'b0;
682 38 mohor
end
683
 
684
 
685 39 mohor
// Reading Tx BD pointer
686
assign StartTxPointerRead = TxBDRead & TxBDReady;
687 38 mohor
 
688 39 mohor
// Reading Tx BD Pointer
689 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
690 38 mohor
begin
691 40 mohor
  if(Reset)
692 39 mohor
    TxPointerRead <=#Tp 1'b0;
693 38 mohor
  else
694 39 mohor
  if(StartTxPointerRead)
695
    TxPointerRead <=#Tp 1'b1;
696 38 mohor
  else
697 39 mohor
  if(TxEn_q)
698
    TxPointerRead <=#Tp 1'b0;
699 38 mohor
end
700
 
701
 
702 39 mohor
// Writing status back to the Tx buffer descriptor
703 221 mohor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
704 38 mohor
 
705
 
706
 
707 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
708 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
709 38 mohor
begin
710 40 mohor
  if(Reset)
711 39 mohor
    BlockingTxStatusWrite <=#Tp 1'b0;
712 38 mohor
  else
713 39 mohor
  if(TxStatusWrite)
714
    BlockingTxStatusWrite <=#Tp 1'b1;
715 38 mohor
  else
716 39 mohor
  if(~TxDone_wb & ~TxAbort_wb)
717
    BlockingTxStatusWrite <=#Tp 1'b0;
718 38 mohor
end
719
 
720
 
721 159 mohor
reg BlockingTxStatusWrite_sync1;
722
reg BlockingTxStatusWrite_sync2;
723
 
724
// Synchronizing BlockingTxStatusWrite to MTxClk
725
always @ (posedge MTxClk or posedge Reset)
726
begin
727
  if(Reset)
728
    BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
729
  else
730
    BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
731
end
732
 
733
// Synchronizing BlockingTxStatusWrite to MTxClk
734
always @ (posedge MTxClk or posedge Reset)
735
begin
736
  if(Reset)
737
    BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
738
  else
739
    BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
740
end
741
 
742
 
743 39 mohor
// TxBDRead state is activated only once. 
744 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
745 39 mohor
begin
746 40 mohor
  if(Reset)
747 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
748
  else
749 110 mohor
  if(StartTxBDRead)
750 39 mohor
    BlockingTxBDRead <=#Tp 1'b1;
751
  else
752 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
753 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
754
end
755 38 mohor
 
756
 
757 39 mohor
// Latching status from the tx buffer descriptor
758
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
759 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
760 38 mohor
begin
761 40 mohor
  if(Reset)
762 60 mohor
    TxStatus <=#Tp 4'h0;
763 38 mohor
  else
764 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
765 60 mohor
    TxStatus <=#Tp ram_do[14:11];
766 38 mohor
end
767
 
768 40 mohor
reg ReadTxDataFromMemory;
769
wire WriteRxDataToMemory;
770 38 mohor
 
771 39 mohor
reg MasterWbTX;
772
reg MasterWbRX;
773
 
774
reg [31:0] m_wb_adr_o;
775
reg        m_wb_cyc_o;
776
reg        m_wb_stb_o;
777 96 mohor
reg  [3:0] m_wb_sel_o;
778 39 mohor
reg        m_wb_we_o;
779 40 mohor
 
780 39 mohor
wire TxLengthEq0;
781
wire TxLengthLt4;
782
 
783 150 mohor
reg BlockingIncrementTxPointer;
784 159 mohor
reg [31:2] TxPointerMSB;
785
reg [1:0]  TxPointerLSB;
786
reg [1:0]  TxPointerLSB_rst;
787
reg [31:2] RxPointerMSB;
788
reg [1:0]  RxPointerLSB_rst;
789 39 mohor
 
790 150 mohor
wire RxBurstAcc;
791
wire RxWordAcc;
792
wire RxHalfAcc;
793
wire RxByteAcc;
794
 
795 39 mohor
//Latching length from the buffer descriptor;
796 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
797 38 mohor
begin
798 40 mohor
  if(Reset)
799 39 mohor
    TxLength <=#Tp 16'h0;
800 38 mohor
  else
801 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
802
    TxLength <=#Tp ram_do[31:16];
803 38 mohor
  else
804 39 mohor
  if(MasterWbTX & m_wb_ack_i)
805
    begin
806
      if(TxLengthLt4)
807
        TxLength <=#Tp 16'h0;
808 150 mohor
      else
809 159 mohor
      if(TxPointerLSB_rst==2'h0)
810 96 mohor
        TxLength <=#Tp TxLength - 3'h4;    // Length is subtracted at the data request
811 39 mohor
      else
812 159 mohor
      if(TxPointerLSB_rst==2'h1)
813 150 mohor
        TxLength <=#Tp TxLength - 3'h3;    // Length is subtracted at the data request
814
      else
815 159 mohor
      if(TxPointerLSB_rst==2'h2)
816 150 mohor
        TxLength <=#Tp TxLength - 3'h2;    // Length is subtracted at the data request
817
      else
818 159 mohor
      if(TxPointerLSB_rst==2'h3)
819 150 mohor
        TxLength <=#Tp TxLength - 3'h1;    // Length is subtracted at the data request
820 39 mohor
    end
821 38 mohor
end
822
 
823 96 mohor
 
824
 
825 60 mohor
//Latching length from the buffer descriptor;
826
always @ (posedge WB_CLK_I or posedge Reset)
827
begin
828
  if(Reset)
829
    LatchedTxLength <=#Tp 16'h0;
830
  else
831
  if(TxEn & TxEn_q & TxBDRead)
832
    LatchedTxLength <=#Tp ram_do[31:16];
833
end
834
 
835 39 mohor
assign TxLengthEq0 = TxLength == 0;
836
assign TxLengthLt4 = TxLength < 4;
837 38 mohor
 
838 150 mohor
reg cyc_cleared;
839
reg IncrTxPointer;
840 39 mohor
 
841
 
842 159 mohor
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
843
// because TxPointerMSB is only used for word-aligned accesses.
844 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
845 38 mohor
begin
846 40 mohor
  if(Reset)
847 159 mohor
    TxPointerMSB <=#Tp 30'h0;
848 38 mohor
  else
849 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
850 159 mohor
    TxPointerMSB <=#Tp ram_do[31:2];
851 38 mohor
  else
852 150 mohor
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
853 159 mohor
    TxPointerMSB <=#Tp TxPointerMSB + 1'b1;     // TxPointer is word-aligned
854 38 mohor
end
855
 
856 96 mohor
 
857 159 mohor
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
858
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
859
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
860
// set by this two bits.
861 96 mohor
always @ (posedge WB_CLK_I or posedge Reset)
862
begin
863
  if(Reset)
864 159 mohor
    TxPointerLSB[1:0] <=#Tp 0;
865 96 mohor
  else
866
  if(TxEn & TxEn_q & TxPointerRead)
867 159 mohor
    TxPointerLSB[1:0] <=#Tp ram_do[1:0];
868 96 mohor
end
869
 
870
 
871 159 mohor
// Latching 2 MSB bits of the buffer descriptor. 
872
// After the read access, TxLength needs to be decremented for the number of the valid
873
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are 
874
// valid so this two bits are reset to zero. 
875 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
876
begin
877
  if(Reset)
878 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
879 150 mohor
  else
880
  if(TxEn & TxEn_q & TxPointerRead)
881 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
882 150 mohor
  else
883
  if(MasterWbTX & m_wb_ack_i)                 // After first access pointer is word alligned
884 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
885 150 mohor
end
886 96 mohor
 
887 150 mohor
 
888 159 mohor
reg  [3:0] RxByteSel;
889 39 mohor
wire MasterAccessFinished;
890 38 mohor
 
891 39 mohor
 
892 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
893 38 mohor
begin
894 40 mohor
  if(Reset)
895 39 mohor
    BlockingIncrementTxPointer <=#Tp 0;
896 38 mohor
  else
897 39 mohor
  if(MasterAccessFinished)
898
    BlockingIncrementTxPointer <=#Tp 0;
899 38 mohor
  else
900 150 mohor
  if(IncrTxPointer)
901 39 mohor
    BlockingIncrementTxPointer <=#Tp 1'b1;
902 38 mohor
end
903
 
904
 
905 39 mohor
wire TxBufferAlmostFull;
906
wire TxBufferFull;
907
wire TxBufferEmpty;
908
wire TxBufferAlmostEmpty;
909 40 mohor
wire SetReadTxDataFromMemory;
910 39 mohor
 
911 40 mohor
reg BlockReadTxDataFromMemory;
912 39 mohor
 
913 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
914 39 mohor
 
915 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
916 38 mohor
begin
917 40 mohor
  if(Reset)
918
    ReadTxDataFromMemory <=#Tp 1'b0;
919 38 mohor
  else
920 219 mohor
  if(TxLengthEq0 | TxAbortPacket | TxRetryPacket)
921 40 mohor
    ReadTxDataFromMemory <=#Tp 1'b0;
922 39 mohor
  else
923 40 mohor
  if(SetReadTxDataFromMemory)
924
    ReadTxDataFromMemory <=#Tp 1'b1;
925 38 mohor
end
926
 
927 226 tadejm
reg tx_burst_en;
928
reg rx_burst_en;
929 221 mohor
reg BlockingLastReadOn_Abort_Retry;
930
 
931
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory & ~BlockingLastReadOn_Abort_Retry;
932 226 tadejm
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
933 221 mohor
 
934 39 mohor
wire [31:0] TxData_wb;
935
wire ReadTxDataFromFifo_wb;
936 38 mohor
 
937 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
938 38 mohor
begin
939 40 mohor
  if(Reset)
940
    BlockReadTxDataFromMemory <=#Tp 1'b0;
941 38 mohor
  else
942 221 mohor
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (!(TxAbortPacket | TxRetryPacket)))
943 40 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b1;
944 219 mohor
  else
945 221 mohor
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
946 219 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b0;
947 39 mohor
end
948
 
949
 
950 221 mohor
always @ (posedge WB_CLK_I or posedge Reset)
951
begin
952
  if(Reset)
953
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
954
  else
955
  if(TxAbortPacket | TxRetryPacket)
956
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
957
  else
958
  if(((TxAbort_wb & !TxAbortPacket_NotCleared) | (TxRetry_wb & !TxRetryPacket_NotCleared)) & !TxBDReady)
959
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b1;
960
end
961 39 mohor
 
962 221 mohor
 
963
 
964
 
965 39 mohor
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
966 219 mohor
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
967
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
968 226 tadejm
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
969
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
970 159 mohor
 
971 226 tadejm
wire rx_burst;
972
wire enough_data_in_rxfifo_for_burst;
973
wire enough_data_in_rxfifo_for_burst_plus1;
974 229 mohor
 
975 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
976 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
977 39 mohor
begin
978 40 mohor
  if(Reset)
979 38 mohor
    begin
980 39 mohor
      MasterWbTX <=#Tp 1'b0;
981
      MasterWbRX <=#Tp 1'b0;
982
      m_wb_adr_o <=#Tp 32'h0;
983
      m_wb_cyc_o <=#Tp 1'b0;
984
      m_wb_stb_o <=#Tp 1'b0;
985
      m_wb_we_o  <=#Tp 1'b0;
986 96 mohor
      m_wb_sel_o <=#Tp 4'h0;
987 110 mohor
      cyc_cleared<=#Tp 1'b0;
988 226 tadejm
      tx_burst_cnt<=#Tp 0;
989
      rx_burst_cnt<=#Tp 0;
990 150 mohor
      IncrTxPointer<=#Tp 1'b0;
991 226 tadejm
      tx_burst_en<=#Tp 1'b1;
992
      rx_burst_en<=#Tp 1'b0;
993
      `ifdef ETH_WISHBONE_B3
994
        m_wb_cti_o <=#Tp 3'b0;
995
      `endif
996 38 mohor
    end
997 39 mohor
  else
998
    begin
999
      // Switching between two stages depends on enable signals
1000 229 mohor
      casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst})  // synopsys parallel_case
1001 226 tadejm
        8'b00_10_00_10,             // Idle and MRB needed
1002 229 mohor
        8'b10_1x_10_1x,             // MRB continues
1003 226 tadejm
        8'b10_10_01_10,             // Clear (previously MR) and MRB needed
1004 229 mohor
        8'b01_1x_01_1x :            // Clear (previously MW) and MRB needed
1005 39 mohor
          begin
1006 226 tadejm
            MasterWbTX <=#Tp 1'b1;  // tx burst
1007
            MasterWbRX <=#Tp 1'b0;
1008
            m_wb_cyc_o <=#Tp 1'b1;
1009
            m_wb_stb_o <=#Tp 1'b1;
1010
            m_wb_we_o  <=#Tp 1'b0;
1011
            m_wb_sel_o <=#Tp 4'hf;
1012
            cyc_cleared<=#Tp 1'b0;
1013
            IncrTxPointer<=#Tp 1'b1;
1014
            tx_burst_cnt <=#Tp tx_burst_cnt+1;
1015
            if(tx_burst_cnt==0)
1016
              m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1017
            else
1018
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1019
 
1020
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
1021
              begin
1022
                tx_burst_en<=#Tp 1'b0;
1023
              `ifdef ETH_WISHBONE_B3
1024
                m_wb_cti_o <=#Tp 3'b111;
1025
              `endif
1026
              end
1027
            else
1028
              begin
1029
              `ifdef ETH_WISHBONE_B3
1030
                m_wb_cti_o <=#Tp 3'b010;
1031
              `endif
1032
              end
1033
          end
1034 229 mohor
        8'b00_x1_00_x1,             // Idle and MWB needed
1035
        8'b01_x1_10_x1,             // MWB continues
1036 226 tadejm
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
1037 229 mohor
        8'b10_x1_01_x1 :            // Clear (previously MR) and MWB needed
1038 226 tadejm
          begin
1039
            MasterWbTX <=#Tp 1'b0;  // rx burst
1040 39 mohor
            MasterWbRX <=#Tp 1'b1;
1041 226 tadejm
            m_wb_cyc_o <=#Tp 1'b1;
1042
            m_wb_stb_o <=#Tp 1'b1;
1043
            m_wb_we_o  <=#Tp 1'b1;
1044
            m_wb_sel_o <=#Tp RxByteSel;
1045
            IncrTxPointer<=#Tp 1'b0;
1046
            cyc_cleared<=#Tp 1'b0;
1047
            rx_burst_cnt <=#Tp rx_burst_cnt+1;
1048
 
1049
            if(rx_burst_cnt==0)
1050
              m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1051
            else
1052
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1053
 
1054
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
1055
              begin
1056
                rx_burst_en<=#Tp 1'b0;
1057
              `ifdef ETH_WISHBONE_B3
1058
                m_wb_cti_o <=#Tp 3'b111;
1059
              `endif
1060
              end
1061
            else
1062
              begin
1063
              `ifdef ETH_WISHBONE_B3
1064
                m_wb_cti_o <=#Tp 3'b010;
1065
              `endif
1066
              end
1067
          end
1068 229 mohor
        8'b00_x1_00_x0 :            // idle and MW is needed (data write to rx buffer)
1069 226 tadejm
          begin
1070
            MasterWbTX <=#Tp 1'b0;
1071
            MasterWbRX <=#Tp 1'b1;
1072 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1073 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1074
            m_wb_stb_o <=#Tp 1'b1;
1075
            m_wb_we_o  <=#Tp 1'b1;
1076 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1077 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1078 39 mohor
          end
1079 226 tadejm
        8'b00_10_00_00 :            // idle and MR is needed (data read from tx buffer)
1080 39 mohor
          begin
1081 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1082 39 mohor
            MasterWbRX <=#Tp 1'b0;
1083 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1084 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1085
            m_wb_stb_o <=#Tp 1'b1;
1086
            m_wb_we_o  <=#Tp 1'b0;
1087 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1088
            IncrTxPointer<=#Tp 1'b1;
1089 39 mohor
          end
1090 226 tadejm
        8'b10_10_01_00,             // MR and MR is needed (data read from tx buffer)
1091 229 mohor
        8'b01_1x_01_0x  :           // MW and MR is needed (data read from tx buffer)
1092 39 mohor
          begin
1093 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1094 39 mohor
            MasterWbRX <=#Tp 1'b0;
1095 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1096 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1097
            m_wb_stb_o <=#Tp 1'b1;
1098
            m_wb_we_o  <=#Tp 1'b0;
1099 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1100 110 mohor
            cyc_cleared<=#Tp 1'b0;
1101 150 mohor
            IncrTxPointer<=#Tp 1'b1;
1102 39 mohor
          end
1103 226 tadejm
        8'b01_01_01_00,             // MW and MW needed (data write to rx buffer)
1104 229 mohor
        8'b10_x1_01_x0  :           // MR and MW is needed (data write to rx buffer)
1105 39 mohor
          begin
1106 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1107 39 mohor
            MasterWbRX <=#Tp 1'b1;
1108 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1109 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1110
            m_wb_stb_o <=#Tp 1'b1;
1111 39 mohor
            m_wb_we_o  <=#Tp 1'b1;
1112 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1113 110 mohor
            cyc_cleared<=#Tp 1'b0;
1114 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1115 39 mohor
          end
1116 226 tadejm
        8'b01_01_10_00,             // MW and MW needed (cycle is cleared between previous and next access)
1117 229 mohor
        8'b01_1x_10_x0,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
1118 226 tadejm
        8'b10_10_10_00,             // MR and MR needed (cycle is cleared between previous and next access)
1119 229 mohor
        8'b10_x1_10_0x :            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
1120 39 mohor
          begin
1121 110 mohor
            m_wb_cyc_o <=#Tp 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
1122
            m_wb_stb_o <=#Tp 1'b0;
1123
            cyc_cleared<=#Tp 1'b1;
1124 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1125 226 tadejm
            tx_burst_cnt<=#Tp 0;
1126
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1127
            rx_burst_cnt<=#Tp 0;
1128
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1129
            `ifdef ETH_WISHBONE_B3
1130
              m_wb_cti_o <=#Tp 3'b0;
1131
            `endif
1132 110 mohor
          end
1133 229 mohor
        8'bxx_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1134
        8'bxx_00_01_00 :            // Between cyc_cleared request was cleared
1135 110 mohor
          begin
1136 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1137 39 mohor
            MasterWbRX <=#Tp 1'b0;
1138
            m_wb_cyc_o <=#Tp 1'b0;
1139
            m_wb_stb_o <=#Tp 1'b0;
1140 226 tadejm
            cyc_cleared<=#Tp 1'b0;
1141 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1142 226 tadejm
            rx_burst_cnt<=#Tp 0;
1143
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1144
            `ifdef ETH_WISHBONE_B3
1145
              m_wb_cti_o <=#Tp 3'b0;
1146
            `endif
1147 39 mohor
          end
1148 226 tadejm
        8'b00_00_00_00:             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1149 127 mohor
          begin
1150 226 tadejm
            tx_burst_cnt<=#Tp 0;
1151
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1152 127 mohor
          end
1153 226 tadejm
        default:                    // Don't touch
1154 82 mohor
          begin
1155
            MasterWbTX <=#Tp MasterWbTX;
1156
            MasterWbRX <=#Tp MasterWbRX;
1157
            m_wb_cyc_o <=#Tp m_wb_cyc_o;
1158
            m_wb_stb_o <=#Tp m_wb_stb_o;
1159 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_o;
1160 150 mohor
            IncrTxPointer<=#Tp IncrTxPointer;
1161 82 mohor
          end
1162 39 mohor
      endcase
1163
    end
1164 38 mohor
end
1165
 
1166 110 mohor
 
1167 39 mohor
wire TxFifoClear;
1168 96 mohor
 
1169 219 mohor
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
1170 38 mohor
 
1171 219 mohor
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
1172 150 mohor
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
1173 96 mohor
          .clk(WB_CLK_I),                                   .reset(Reset),
1174 226 tadejm
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
1175 96 mohor
          .clear(TxFifoClear),                              .full(TxBufferFull),
1176
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
1177 150 mohor
          .empty(TxBufferEmpty),                            .cnt(txfifo_cnt)
1178 96 mohor
        );
1179 39 mohor
 
1180
 
1181
reg StartOccured;
1182
reg TxStartFrm_sync1;
1183
reg TxStartFrm_sync2;
1184
reg TxStartFrm_syncb1;
1185
reg TxStartFrm_syncb2;
1186
 
1187
 
1188
 
1189
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1190 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1191 38 mohor
begin
1192 40 mohor
  if(Reset)
1193 39 mohor
    TxStartFrm_wb <=#Tp 1'b0;
1194 38 mohor
  else
1195 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1196
    TxStartFrm_wb <=#Tp 1'b1;
1197 38 mohor
  else
1198 39 mohor
  if(TxStartFrm_syncb2)
1199
    TxStartFrm_wb <=#Tp 1'b0;
1200 38 mohor
end
1201
 
1202 39 mohor
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
1203 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1204 38 mohor
begin
1205 40 mohor
  if(Reset)
1206 39 mohor
    StartOccured <=#Tp 1'b0;
1207 38 mohor
  else
1208 39 mohor
  if(TxStartFrm_wb)
1209
    StartOccured <=#Tp 1'b1;
1210 38 mohor
  else
1211 39 mohor
  if(ResetTxBDReady)
1212
    StartOccured <=#Tp 1'b0;
1213 38 mohor
end
1214
 
1215 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1216 40 mohor
always @ (posedge MTxClk or posedge Reset)
1217 39 mohor
begin
1218 40 mohor
  if(Reset)
1219 39 mohor
    TxStartFrm_sync1 <=#Tp 1'b0;
1220
  else
1221
    TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
1222
end
1223 38 mohor
 
1224 40 mohor
always @ (posedge MTxClk or posedge Reset)
1225 39 mohor
begin
1226 40 mohor
  if(Reset)
1227 39 mohor
    TxStartFrm_sync2 <=#Tp 1'b0;
1228
  else
1229
    TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
1230
end
1231
 
1232 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1233 38 mohor
begin
1234 40 mohor
  if(Reset)
1235 39 mohor
    TxStartFrm_syncb1 <=#Tp 1'b0;
1236 38 mohor
  else
1237 39 mohor
    TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
1238 38 mohor
end
1239
 
1240 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1241 38 mohor
begin
1242 40 mohor
  if(Reset)
1243 39 mohor
    TxStartFrm_syncb2 <=#Tp 1'b0;
1244 38 mohor
  else
1245 39 mohor
    TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
1246
end
1247
 
1248 40 mohor
always @ (posedge MTxClk or posedge Reset)
1249 39 mohor
begin
1250 40 mohor
  if(Reset)
1251 39 mohor
    TxStartFrm <=#Tp 1'b0;
1252 38 mohor
  else
1253 39 mohor
  if(TxStartFrm_sync2)
1254 61 mohor
    TxStartFrm <=#Tp 1'b1;
1255 39 mohor
  else
1256 61 mohor
  if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry | TxAbort))
1257 39 mohor
    TxStartFrm <=#Tp 1'b0;
1258 38 mohor
end
1259 39 mohor
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1260 38 mohor
 
1261
 
1262 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1263 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1264 38 mohor
begin
1265 40 mohor
  if(Reset)
1266 39 mohor
    TxEndFrm_wb <=#Tp 1'b0;
1267 38 mohor
  else
1268 221 mohor
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
1269 39 mohor
    TxEndFrm_wb <=#Tp 1'b1;
1270 38 mohor
  else
1271 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1272
    TxEndFrm_wb <=#Tp 1'b0;
1273 38 mohor
end
1274
 
1275
 
1276
// Marks which bytes are valid within the word.
1277 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1278 38 mohor
 
1279 39 mohor
reg LatchValidBytes;
1280
reg LatchValidBytes_q;
1281 38 mohor
 
1282 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1283 38 mohor
begin
1284 40 mohor
  if(Reset)
1285 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1286 38 mohor
  else
1287 39 mohor
  if(TxLengthLt4 & TxBDReady)
1288
    LatchValidBytes <=#Tp 1'b1;
1289 38 mohor
  else
1290 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1291 38 mohor
end
1292
 
1293 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1294 38 mohor
begin
1295 40 mohor
  if(Reset)
1296 39 mohor
    LatchValidBytes_q <=#Tp 1'b0;
1297 38 mohor
  else
1298 39 mohor
    LatchValidBytes_q <=#Tp LatchValidBytes;
1299 38 mohor
end
1300
 
1301
 
1302 39 mohor
// Latching valid bytes
1303 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1304 38 mohor
begin
1305 40 mohor
  if(Reset)
1306 39 mohor
    TxValidBytesLatched <=#Tp 2'h0;
1307 38 mohor
  else
1308 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1309
    TxValidBytesLatched <=#Tp TxValidBytes;
1310
  else
1311
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1312
    TxValidBytesLatched <=#Tp 2'h0;
1313 38 mohor
end
1314
 
1315
 
1316
assign TxIRQEn          = TxStatus[14];
1317 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1318
assign PerPacketPad     = TxStatus[12];
1319
assign PerPacketCrcEn   = TxStatus[11];
1320 38 mohor
 
1321
 
1322 77 mohor
assign RxIRQEn         = RxStatus[14];
1323 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1324 38 mohor
 
1325
 
1326
// Temporary Tx and Rx buffer descriptor address 
1327 39 mohor
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite     & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
1328 134 mohor
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum<<1)     | // Using first Rx BD
1329 39 mohor
                              {8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
1330 38 mohor
 
1331
 
1332
// Latching Tx buffer descriptor address
1333 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1334 38 mohor
begin
1335 40 mohor
  if(Reset)
1336 38 mohor
    TxBDAddress <=#Tp 8'h0;
1337
  else
1338
  if(TxStatusWrite)
1339
    TxBDAddress <=#Tp TempTxBDAddress;
1340
end
1341
 
1342
 
1343
// Latching Rx buffer descriptor address
1344 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1345 38 mohor
begin
1346 40 mohor
  if(Reset)
1347 134 mohor
    RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF<<1;
1348 38 mohor
  else
1349 77 mohor
  if(TX_BD_NUM_Wr)                        // When r_TxBDNum is updated, RxBDAddress is also
1350 134 mohor
    RxBDAddress <=#Tp WB_DAT_I[7:0]<<1;
1351 38 mohor
  else
1352
  if(RxStatusWrite)
1353
    RxBDAddress <=#Tp TempRxBDAddress;
1354
end
1355
 
1356 60 mohor
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
1357 38 mohor
 
1358 261 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
1359 60 mohor
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1360 38 mohor
 
1361 60 mohor
 
1362 38 mohor
// Signals used for various purposes
1363 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1364 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1365
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1366
 
1367
 
1368
 
1369 39 mohor
// Generating delayed signals
1370 40 mohor
always @ (posedge MTxClk or posedge Reset)
1371 38 mohor
begin
1372 40 mohor
  if(Reset)
1373 39 mohor
    begin
1374
      TxAbort_q      <=#Tp 1'b0;
1375
      TxRetry_q      <=#Tp 1'b0;
1376
      TxUsedData_q   <=#Tp 1'b0;
1377
    end
1378 38 mohor
  else
1379 39 mohor
    begin
1380
      TxAbort_q      <=#Tp TxAbort;
1381
      TxRetry_q      <=#Tp TxRetry;
1382
      TxUsedData_q   <=#Tp TxUsedData;
1383
    end
1384 38 mohor
end
1385
 
1386
// Generating delayed signals
1387 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1388 38 mohor
begin
1389 40 mohor
  if(Reset)
1390 38 mohor
    begin
1391 39 mohor
      TxDone_wb_q   <=#Tp 1'b0;
1392
      TxAbort_wb_q  <=#Tp 1'b0;
1393 40 mohor
      TxRetry_wb_q  <=#Tp 1'b0;
1394 38 mohor
    end
1395
  else
1396
    begin
1397 39 mohor
      TxDone_wb_q   <=#Tp TxDone_wb;
1398
      TxAbort_wb_q  <=#Tp TxAbort_wb;
1399 40 mohor
      TxRetry_wb_q  <=#Tp TxRetry_wb;
1400 38 mohor
    end
1401
end
1402
 
1403
 
1404 219 mohor
reg TxAbortPacketBlocked;
1405
always @ (posedge WB_CLK_I or posedge Reset)
1406
begin
1407
  if(Reset)
1408
    TxAbortPacket <=#Tp 1'b0;
1409
  else
1410 226 tadejm
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxAbortPacketBlocked |
1411
     TxAbort_wb & !MasterWbTX & !TxAbortPacketBlocked)
1412 219 mohor
    TxAbortPacket <=#Tp 1'b1;
1413
  else
1414
    TxAbortPacket <=#Tp 1'b0;
1415
end
1416
 
1417
 
1418
always @ (posedge WB_CLK_I or posedge Reset)
1419
begin
1420
  if(Reset)
1421 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1422
  else
1423 226 tadejm
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1424
     TxAbort_wb & !MasterWbTX)
1425 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b1;
1426
  else
1427
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1428
end
1429
 
1430
 
1431
always @ (posedge WB_CLK_I or posedge Reset)
1432
begin
1433
  if(Reset)
1434 219 mohor
    TxAbortPacketBlocked <=#Tp 1'b0;
1435
  else
1436
  if(TxAbortPacket)
1437
    TxAbortPacketBlocked <=#Tp 1'b1;
1438
  else
1439
  if(!TxAbort_wb & TxAbort_wb_q)
1440
    TxAbortPacketBlocked <=#Tp 1'b0;
1441
end
1442
 
1443
 
1444
reg TxRetryPacketBlocked;
1445
always @ (posedge WB_CLK_I or posedge Reset)
1446
begin
1447
  if(Reset)
1448
    TxRetryPacket <=#Tp 1'b0;
1449
  else
1450 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
1451
     TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1452 219 mohor
    TxRetryPacket <=#Tp 1'b1;
1453
  else
1454
    TxRetryPacket <=#Tp 1'b0;
1455
end
1456
 
1457
 
1458
always @ (posedge WB_CLK_I or posedge Reset)
1459
begin
1460
  if(Reset)
1461 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1462
  else
1463 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1464
     TxRetry_wb & !MasterWbTX)
1465 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b1;
1466
  else
1467
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1468
end
1469
 
1470
 
1471
always @ (posedge WB_CLK_I or posedge Reset)
1472
begin
1473
  if(Reset)
1474 219 mohor
    TxRetryPacketBlocked <=#Tp 1'b0;
1475
  else
1476
  if(TxRetryPacket)
1477
    TxRetryPacketBlocked <=#Tp 1'b1;
1478
  else
1479
  if(!TxRetry_wb & TxRetry_wb_q)
1480
    TxRetryPacketBlocked <=#Tp 1'b0;
1481
end
1482
 
1483
 
1484 221 mohor
reg TxDonePacketBlocked;
1485
always @ (posedge WB_CLK_I or posedge Reset)
1486
begin
1487
  if(Reset)
1488
    TxDonePacket <=#Tp 1'b0;
1489
  else
1490 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
1491
     TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
1492 221 mohor
    TxDonePacket <=#Tp 1'b1;
1493
  else
1494
    TxDonePacket <=#Tp 1'b0;
1495
end
1496
 
1497
 
1498
always @ (posedge WB_CLK_I or posedge Reset)
1499
begin
1500
  if(Reset)
1501
    TxDonePacket_NotCleared <=#Tp 1'b0;
1502
  else
1503 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1504
     TxDone_wb & !MasterWbTX)
1505 221 mohor
    TxDonePacket_NotCleared <=#Tp 1'b1;
1506
  else
1507
    TxDonePacket_NotCleared <=#Tp 1'b0;
1508
end
1509
 
1510
 
1511
always @ (posedge WB_CLK_I or posedge Reset)
1512
begin
1513
  if(Reset)
1514
    TxDonePacketBlocked <=#Tp 1'b0;
1515
  else
1516
  if(TxDonePacket)
1517
    TxDonePacketBlocked <=#Tp 1'b1;
1518
  else
1519
  if(!TxDone_wb & TxDone_wb_q)
1520
    TxDonePacketBlocked <=#Tp 1'b0;
1521
end
1522
 
1523
 
1524 38 mohor
// Sinchronizing and evaluating tx data
1525 39 mohor
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
1526 219 mohor
assign SetGotData = (TxStartFrm_wb);
1527 38 mohor
 
1528
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
1529 40 mohor
//assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1530
assign GotDataEvaluate = (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1531 38 mohor
 
1532
 
1533
// Indication of the last word
1534 40 mohor
always @ (posedge MTxClk or posedge Reset)
1535 38 mohor
begin
1536 40 mohor
  if(Reset)
1537 38 mohor
    LastWord <=#Tp 1'b0;
1538
  else
1539
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1540
    LastWord <=#Tp 1'b0;
1541
  else
1542
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1543 39 mohor
    LastWord <=#Tp TxEndFrm_wb;
1544 38 mohor
end
1545
 
1546
 
1547
// Tx end frame generation
1548 40 mohor
always @ (posedge MTxClk or posedge Reset)
1549 38 mohor
begin
1550 40 mohor
  if(Reset)
1551 38 mohor
    TxEndFrm <=#Tp 1'b0;
1552
  else
1553 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1554 38 mohor
    TxEndFrm <=#Tp 1'b0;
1555
  else
1556
  if(Flop & LastWord)
1557
    begin
1558 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1559 38 mohor
        1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
1560
        2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
1561
        3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
1562
 
1563
        default : TxEndFrm <=#Tp 1'b0;
1564
      endcase
1565
    end
1566
end
1567
 
1568
 
1569
// Tx data selection (latching)
1570 40 mohor
always @ (posedge MTxClk or posedge Reset)
1571 38 mohor
begin
1572 40 mohor
  if(Reset)
1573 96 mohor
    TxData <=#Tp 0;
1574 38 mohor
  else
1575 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1576 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1577 96 mohor
      2'h0 : TxData <=#Tp TxData_wb[31:24];                  // Big Endian Byte Ordering
1578
      2'h1 : TxData <=#Tp TxData_wb[23:16];                  // Big Endian Byte Ordering
1579
      2'h2 : TxData <=#Tp TxData_wb[15:08];                  // Big Endian Byte Ordering
1580
      2'h3 : TxData <=#Tp TxData_wb[07:00];                  // Big Endian Byte Ordering
1581
    endcase
1582 38 mohor
  else
1583 159 mohor
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1584 96 mohor
    TxData <=#Tp TxData_wb[31:24];                           // Big Endian Byte Ordering
1585
  else
1586 38 mohor
  if(TxUsedData & Flop)
1587
    begin
1588 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1589 226 tadejm
 
1590 82 mohor
        1 : TxData <=#Tp TxDataLatched[23:16];
1591
        2 : TxData <=#Tp TxDataLatched[15:8];
1592
        3 : TxData <=#Tp TxDataLatched[7:0];
1593 38 mohor
      endcase
1594
    end
1595
end
1596
 
1597
 
1598
// Latching tx data
1599 40 mohor
always @ (posedge MTxClk or posedge Reset)
1600 38 mohor
begin
1601 40 mohor
  if(Reset)
1602 38 mohor
    TxDataLatched[31:0] <=#Tp 32'h0;
1603
  else
1604 96 mohor
 if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1605 39 mohor
    TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
1606 38 mohor
end
1607
 
1608
 
1609
// Tx under run
1610 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1611 38 mohor
begin
1612 40 mohor
  if(Reset)
1613 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1614 38 mohor
  else
1615 39 mohor
  if(TxAbortPulse)
1616 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1617
  else
1618
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1619
    TxUnderRun_wb <=#Tp 1'b1;
1620
end
1621
 
1622
 
1623 159 mohor
reg TxUnderRun_sync1;
1624
 
1625 60 mohor
// Tx under run
1626
always @ (posedge MTxClk or posedge Reset)
1627
begin
1628
  if(Reset)
1629 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b0;
1630 43 mohor
  else
1631 60 mohor
  if(TxUnderRun_wb)
1632 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b1;
1633 60 mohor
  else
1634 159 mohor
  if(BlockingTxStatusWrite_sync2)
1635
    TxUnderRun_sync1 <=#Tp 1'b0;
1636
end
1637
 
1638
// Tx under run
1639
always @ (posedge MTxClk or posedge Reset)
1640
begin
1641
  if(Reset)
1642 60 mohor
    TxUnderRun <=#Tp 1'b0;
1643 159 mohor
  else
1644
  if(BlockingTxStatusWrite_sync2)
1645
    TxUnderRun <=#Tp 1'b0;
1646
  else
1647
  if(TxUnderRun_sync1)
1648
    TxUnderRun <=#Tp 1'b1;
1649 38 mohor
end
1650
 
1651
 
1652
// Tx Byte counter
1653 40 mohor
always @ (posedge MTxClk or posedge Reset)
1654 38 mohor
begin
1655 40 mohor
  if(Reset)
1656 38 mohor
    TxByteCnt <=#Tp 2'h0;
1657
  else
1658
  if(TxAbort_q | TxRetry_q)
1659
    TxByteCnt <=#Tp 2'h0;
1660
  else
1661
  if(TxStartFrm & ~TxUsedData)
1662 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1663 96 mohor
      2'h0 : TxByteCnt <=#Tp 2'h1;
1664
      2'h1 : TxByteCnt <=#Tp 2'h2;
1665
      2'h2 : TxByteCnt <=#Tp 2'h3;
1666
      2'h3 : TxByteCnt <=#Tp 2'h0;
1667
    endcase
1668 38 mohor
  else
1669
  if(TxUsedData & Flop)
1670 96 mohor
    TxByteCnt <=#Tp TxByteCnt + 1'b1;
1671 38 mohor
end
1672
 
1673 39 mohor
 
1674 150 mohor
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1675
reg ReadTxDataFromFifo_sync1;
1676
reg ReadTxDataFromFifo_sync2;
1677
reg ReadTxDataFromFifo_sync3;
1678
reg ReadTxDataFromFifo_syncb1;
1679
reg ReadTxDataFromFifo_syncb2;
1680
reg ReadTxDataFromFifo_syncb3;
1681
 
1682
 
1683
always @ (posedge MTxClk or posedge Reset)
1684
begin
1685
  if(Reset)
1686
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1687
  else
1688 96 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1689 39 mohor
     ReadTxDataFromFifo_tck <=#Tp 1'b1;
1690 150 mohor
  else
1691
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1692
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1693 38 mohor
end
1694
 
1695 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1696 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1697 38 mohor
begin
1698 40 mohor
  if(Reset)
1699 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
1700 38 mohor
  else
1701 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
1702
end
1703 38 mohor
 
1704 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1705 38 mohor
begin
1706 40 mohor
  if(Reset)
1707 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
1708 38 mohor
  else
1709 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
1710 38 mohor
end
1711
 
1712 40 mohor
always @ (posedge MTxClk or posedge Reset)
1713 38 mohor
begin
1714 40 mohor
  if(Reset)
1715 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
1716 38 mohor
  else
1717 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
1718 38 mohor
end
1719
 
1720 40 mohor
always @ (posedge MTxClk or posedge Reset)
1721 38 mohor
begin
1722 40 mohor
  if(Reset)
1723 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
1724 38 mohor
  else
1725 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
1726 38 mohor
end
1727
 
1728 150 mohor
always @ (posedge MTxClk or posedge Reset)
1729
begin
1730
  if(Reset)
1731
    ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
1732
  else
1733
    ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
1734
end
1735
 
1736 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1737 38 mohor
begin
1738 40 mohor
  if(Reset)
1739 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
1740 38 mohor
  else
1741 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
1742 38 mohor
end
1743
 
1744 39 mohor
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
1745
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1746 38 mohor
 
1747
 
1748 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1749 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1750 38 mohor
begin
1751 40 mohor
  if(Reset)
1752 39 mohor
    TxRetrySync1 <=#Tp 1'b0;
1753 38 mohor
  else
1754 39 mohor
    TxRetrySync1 <=#Tp TxRetry;
1755 38 mohor
end
1756
 
1757 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1758 38 mohor
begin
1759 40 mohor
  if(Reset)
1760 39 mohor
    TxRetry_wb <=#Tp 1'b0;
1761 38 mohor
  else
1762 39 mohor
    TxRetry_wb <=#Tp TxRetrySync1;
1763 38 mohor
end
1764
 
1765
 
1766 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1767 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1768 38 mohor
begin
1769 40 mohor
  if(Reset)
1770 39 mohor
    TxDoneSync1 <=#Tp 1'b0;
1771 38 mohor
  else
1772 39 mohor
    TxDoneSync1 <=#Tp TxDone;
1773 38 mohor
end
1774
 
1775 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1776 38 mohor
begin
1777 40 mohor
  if(Reset)
1778 39 mohor
    TxDone_wb <=#Tp 1'b0;
1779 38 mohor
  else
1780 39 mohor
    TxDone_wb <=#Tp TxDoneSync1;
1781 38 mohor
end
1782
 
1783 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1784 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1785 38 mohor
begin
1786 40 mohor
  if(Reset)
1787 39 mohor
    TxAbortSync1 <=#Tp 1'b0;
1788 38 mohor
  else
1789 39 mohor
    TxAbortSync1 <=#Tp TxAbort;
1790 38 mohor
end
1791
 
1792 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1793 38 mohor
begin
1794 40 mohor
  if(Reset)
1795 38 mohor
    TxAbort_wb <=#Tp 1'b0;
1796
  else
1797 39 mohor
    TxAbort_wb <=#Tp TxAbortSync1;
1798 38 mohor
end
1799
 
1800
 
1801 150 mohor
reg RxAbortSync1;
1802
reg RxAbortSync2;
1803
reg RxAbortSync3;
1804
reg RxAbortSync4;
1805
reg RxAbortSyncb1;
1806
reg RxAbortSyncb2;
1807 39 mohor
 
1808 150 mohor
//assign StartRxBDRead = RxStatusWrite | RxAbortLatched;
1809
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
1810
 
1811 40 mohor
// Reading the Rx buffer descriptor
1812
always @ (posedge WB_CLK_I or posedge Reset)
1813
begin
1814
  if(Reset)
1815
    RxBDRead <=#Tp 1'b1;
1816
  else
1817 166 mohor
  if(StartRxBDRead & ~RxReady)
1818 40 mohor
    RxBDRead <=#Tp 1'b1;
1819
  else
1820
  if(RxBDReady)
1821
    RxBDRead <=#Tp 1'b0;
1822
end
1823 39 mohor
 
1824
 
1825 38 mohor
// Reading of the next receive buffer descriptor starts after reception status is
1826
// written to the previous one.
1827
 
1828
// Latching READY status of the Rx buffer descriptor
1829 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1830 38 mohor
begin
1831 40 mohor
  if(Reset)
1832 38 mohor
    RxBDReady <=#Tp 1'b0;
1833
  else
1834 166 mohor
  if(RxPointerRead)
1835 150 mohor
    RxBDReady <=#Tp 1'b0;
1836
  else
1837 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1838
    RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
1839 38 mohor
end
1840
 
1841 40 mohor
// Latching Rx buffer descriptor status
1842
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
1843
always @ (posedge WB_CLK_I or posedge Reset)
1844 38 mohor
begin
1845 40 mohor
  if(Reset)
1846 60 mohor
    RxStatus <=#Tp 2'h0;
1847 38 mohor
  else
1848 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1849 60 mohor
    RxStatus <=#Tp ram_do[14:13];
1850 38 mohor
end
1851
 
1852
 
1853 166 mohor
// RxReady generation
1854
always @ (posedge WB_CLK_I or posedge Reset)
1855
begin
1856
  if(Reset)
1857
    RxReady <=#Tp 1'b0;
1858
  else
1859
  if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3)
1860
    RxReady <=#Tp 1'b0;
1861
  else
1862
  if(RxEn & RxEn_q & RxPointerRead)
1863
    RxReady <=#Tp 1'b1;
1864
end
1865 38 mohor
 
1866
 
1867 40 mohor
// Reading Rx BD pointer
1868
 
1869
 
1870
assign StartRxPointerRead = RxBDRead & RxBDReady;
1871
 
1872
// Reading Tx BD Pointer
1873
always @ (posedge WB_CLK_I or posedge Reset)
1874 38 mohor
begin
1875 40 mohor
  if(Reset)
1876
    RxPointerRead <=#Tp 1'b0;
1877 38 mohor
  else
1878 40 mohor
  if(StartRxPointerRead)
1879
    RxPointerRead <=#Tp 1'b1;
1880 38 mohor
  else
1881 166 mohor
  if(RxEn & RxEn_q)
1882 40 mohor
    RxPointerRead <=#Tp 1'b0;
1883 38 mohor
end
1884
 
1885 113 mohor
 
1886 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
1887
always @ (posedge WB_CLK_I or posedge Reset)
1888
begin
1889
  if(Reset)
1890 159 mohor
    RxPointerMSB <=#Tp 30'h0;
1891 40 mohor
  else
1892
  if(RxEn & RxEn_q & RxPointerRead)
1893 159 mohor
    RxPointerMSB <=#Tp ram_do[31:2];
1894 40 mohor
  else
1895 113 mohor
  if(MasterWbRX & m_wb_ack_i)
1896 159 mohor
      RxPointerMSB <=#Tp RxPointerMSB + 1; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
1897 40 mohor
end
1898 38 mohor
 
1899
 
1900 96 mohor
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
1901 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1902
begin
1903
  if(Reset)
1904 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp 0;
1905 96 mohor
  else
1906 159 mohor
  if(MasterWbRX & m_wb_ack_i)                 // After first write all RxByteSel are active
1907
    RxPointerLSB_rst[1:0] <=#Tp 0;
1908 96 mohor
  else
1909
  if(RxEn & RxEn_q & RxPointerRead)
1910 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
1911 96 mohor
end
1912
 
1913
 
1914 159 mohor
always @ (RxPointerLSB_rst)
1915 96 mohor
begin
1916 159 mohor
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
1917
    2'h0 : RxByteSel[3:0] = 4'hf;
1918
    2'h1 : RxByteSel[3:0] = 4'h7;
1919
    2'h2 : RxByteSel[3:0] = 4'h3;
1920
    2'h3 : RxByteSel[3:0] = 4'h1;
1921 96 mohor
  endcase
1922
end
1923
 
1924
 
1925
always @ (posedge WB_CLK_I or posedge Reset)
1926
begin
1927
  if(Reset)
1928 40 mohor
    RxEn_needed <=#Tp 1'b0;
1929 38 mohor
  else
1930 166 mohor
  if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
1931 40 mohor
    RxEn_needed <=#Tp 1'b1;
1932 38 mohor
  else
1933 40 mohor
  if(RxPointerRead & RxEn & RxEn_q)
1934
    RxEn_needed <=#Tp 1'b0;
1935 38 mohor
end
1936
 
1937
 
1938 40 mohor
// Reception status is written back to the buffer descriptor after the end of frame is detected.
1939
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
1940 38 mohor
 
1941 42 mohor
reg RxStatusWriteLatched;
1942
reg RxStatusWrite_rck;
1943
 
1944
always @ (posedge WB_CLK_I or posedge Reset)
1945
begin
1946
  if(Reset)
1947
    RxStatusWriteLatched <=#Tp 1'b0;
1948
  else
1949 87 mohor
  if(RxStatusWrite & ~RxStatusWrite_rck)
1950 42 mohor
    RxStatusWriteLatched <=#Tp 1'b1;
1951
  else
1952
  if(RxStatusWrite_rck)
1953
    RxStatusWriteLatched <=#Tp 1'b0;
1954
end
1955
 
1956
 
1957
always @ (posedge MRxClk or posedge Reset)
1958
begin
1959
  if(Reset)
1960
    RxStatusWrite_rck <=#Tp 1'b0;
1961
  else
1962 87 mohor
  if(RxStatusWriteLatched)
1963
    RxStatusWrite_rck <=#Tp 1'b1;
1964
  else
1965
    RxStatusWrite_rck <=#Tp 1'b0;
1966 42 mohor
end
1967
 
1968
 
1969 40 mohor
reg RxEnableWindow;
1970 38 mohor
 
1971
// Indicating that last byte is being reveived
1972 40 mohor
always @ (posedge MRxClk or posedge Reset)
1973 38 mohor
begin
1974 40 mohor
  if(Reset)
1975 38 mohor
    LastByteIn <=#Tp 1'b0;
1976
  else
1977 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
1978 38 mohor
    LastByteIn <=#Tp 1'b0;
1979
  else
1980 166 mohor
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
1981 38 mohor
    LastByteIn <=#Tp 1'b1;
1982
end
1983
 
1984 159 mohor
reg ShiftEnded_rck;
1985 40 mohor
reg ShiftEndedSync1;
1986
reg ShiftEndedSync2;
1987 118 mohor
reg ShiftEndedSync3;
1988
reg ShiftEndedSync_c1;
1989
reg ShiftEndedSync_c2;
1990
 
1991 40 mohor
wire StartShiftWillEnd;
1992 96 mohor
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
1993 38 mohor
 
1994
// Indicating that data reception will end
1995 40 mohor
always @ (posedge MRxClk or posedge Reset)
1996 38 mohor
begin
1997 40 mohor
  if(Reset)
1998 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1999
  else
2000 159 mohor
  if(ShiftEnded_rck | RxAbort)
2001 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
2002
  else
2003 40 mohor
  if(StartShiftWillEnd)
2004 38 mohor
    ShiftWillEnd <=#Tp 1'b1;
2005
end
2006
 
2007
 
2008 40 mohor
 
2009 38 mohor
// Receive byte counter
2010 40 mohor
always @ (posedge MRxClk or posedge Reset)
2011 38 mohor
begin
2012 40 mohor
  if(Reset)
2013 38 mohor
    RxByteCnt <=#Tp 2'h0;
2014
  else
2015 159 mohor
  if(ShiftEnded_rck | RxAbort)
2016 38 mohor
    RxByteCnt <=#Tp 2'h0;
2017 97 lampret
  else
2018 166 mohor
  if(RxValid & RxStartFrm & RxReady)
2019 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2020 96 mohor
      2'h0 : RxByteCnt <=#Tp 2'h1;
2021
      2'h1 : RxByteCnt <=#Tp 2'h2;
2022
      2'h2 : RxByteCnt <=#Tp 2'h3;
2023
      2'h3 : RxByteCnt <=#Tp 2'h0;
2024
    endcase
2025 38 mohor
  else
2026 166 mohor
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
2027 40 mohor
    RxByteCnt <=#Tp RxByteCnt + 1'b1;
2028 38 mohor
end
2029
 
2030
 
2031
// Indicates how many bytes are valid within the last word
2032 40 mohor
always @ (posedge MRxClk or posedge Reset)
2033 38 mohor
begin
2034 40 mohor
  if(Reset)
2035 38 mohor
    RxValidBytes <=#Tp 2'h1;
2036
  else
2037 96 mohor
  if(RxValid & RxStartFrm)
2038 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2039 96 mohor
      2'h0 : RxValidBytes <=#Tp 2'h1;
2040
      2'h1 : RxValidBytes <=#Tp 2'h2;
2041
      2'h2 : RxValidBytes <=#Tp 2'h3;
2042
      2'h3 : RxValidBytes <=#Tp 2'h0;
2043
    endcase
2044 38 mohor
  else
2045 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
2046 38 mohor
    RxValidBytes <=#Tp RxValidBytes + 1;
2047
end
2048
 
2049
 
2050 40 mohor
always @ (posedge MRxClk or posedge Reset)
2051 38 mohor
begin
2052 40 mohor
  if(Reset)
2053
    RxDataLatched1       <=#Tp 24'h0;
2054 38 mohor
  else
2055 166 mohor
  if(RxValid & RxReady & ~LastByteIn)
2056 96 mohor
    if(RxStartFrm)
2057 40 mohor
    begin
2058 159 mohor
      case(RxPointerLSB_rst)     // synopsys parallel_case
2059 96 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2060
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2061
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2062
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2063
      endcase
2064
    end
2065
    else if (RxEnableWindow)
2066
    begin
2067 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
2068 82 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2069
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2070
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2071 40 mohor
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2072
      endcase
2073
    end
2074 38 mohor
end
2075
 
2076 40 mohor
wire SetWriteRxDataToFifo;
2077 38 mohor
 
2078 40 mohor
// Assembling data that will be written to the rx_fifo
2079
always @ (posedge MRxClk or posedge Reset)
2080 38 mohor
begin
2081 40 mohor
  if(Reset)
2082
    RxDataLatched2 <=#Tp 32'h0;
2083 38 mohor
  else
2084 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
2085 82 mohor
    RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData};              // Big Endian Byte Ordering
2086 38 mohor
  else
2087 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
2088 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
2089 82 mohor
 
2090
      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
2091
      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
2092
      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};
2093 40 mohor
    endcase
2094 38 mohor
end
2095
 
2096
 
2097 40 mohor
reg WriteRxDataToFifoSync1;
2098
reg WriteRxDataToFifoSync2;
2099 150 mohor
reg WriteRxDataToFifoSync3;
2100 38 mohor
 
2101
 
2102 40 mohor
// Indicating start of the reception process
2103 166 mohor
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
2104
                              (RxValid & RxReady &  RxStartFrm & (&RxPointerLSB_rst))           |
2105
                              (ShiftWillEnd & LastByteIn & (&RxByteCnt));
2106 38 mohor
 
2107 150 mohor
always @ (posedge MRxClk or posedge Reset)
2108
begin
2109
  if(Reset)
2110
    WriteRxDataToFifo <=#Tp 1'b0;
2111
  else
2112
  if(SetWriteRxDataToFifo & ~RxAbort)
2113
    WriteRxDataToFifo <=#Tp 1'b1;
2114
  else
2115
  if(WriteRxDataToFifoSync2 | RxAbort)
2116
    WriteRxDataToFifo <=#Tp 1'b0;
2117
end
2118 40 mohor
 
2119 150 mohor
 
2120
 
2121
always @ (posedge WB_CLK_I or posedge Reset)
2122
begin
2123
  if(Reset)
2124
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2125
  else
2126
  if(WriteRxDataToFifo)
2127
    WriteRxDataToFifoSync1 <=#Tp 1'b1;
2128
  else
2129
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2130
end
2131
 
2132
always @ (posedge WB_CLK_I or posedge Reset)
2133
begin
2134
  if(Reset)
2135
    WriteRxDataToFifoSync2 <=#Tp 1'b0;
2136
  else
2137
    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
2138
end
2139
 
2140
always @ (posedge WB_CLK_I or posedge Reset)
2141
begin
2142
  if(Reset)
2143
    WriteRxDataToFifoSync3 <=#Tp 1'b0;
2144
  else
2145
    WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
2146
end
2147
 
2148
wire WriteRxDataToFifo_wb;
2149
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
2150
 
2151
 
2152 90 mohor
reg LatchedRxStartFrm;
2153
reg SyncRxStartFrm;
2154
reg SyncRxStartFrm_q;
2155 150 mohor
reg SyncRxStartFrm_q2;
2156 90 mohor
wire RxFifoReset;
2157 40 mohor
 
2158 90 mohor
always @ (posedge MRxClk or posedge Reset)
2159
begin
2160
  if(Reset)
2161
    LatchedRxStartFrm <=#Tp 0;
2162
  else
2163 150 mohor
  if(RxStartFrm & ~SyncRxStartFrm_q)
2164 90 mohor
    LatchedRxStartFrm <=#Tp 1;
2165
  else
2166 150 mohor
  if(SyncRxStartFrm_q)
2167 90 mohor
    LatchedRxStartFrm <=#Tp 0;
2168
end
2169
 
2170
 
2171
always @ (posedge WB_CLK_I or posedge Reset)
2172
begin
2173
  if(Reset)
2174
    SyncRxStartFrm <=#Tp 0;
2175
  else
2176
  if(LatchedRxStartFrm)
2177
    SyncRxStartFrm <=#Tp 1;
2178
  else
2179
    SyncRxStartFrm <=#Tp 0;
2180
end
2181
 
2182
 
2183
always @ (posedge WB_CLK_I or posedge Reset)
2184
begin
2185
  if(Reset)
2186
    SyncRxStartFrm_q <=#Tp 0;
2187
  else
2188
    SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
2189
end
2190
 
2191 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2192
begin
2193
  if(Reset)
2194
    SyncRxStartFrm_q2 <=#Tp 0;
2195
  else
2196
    SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
2197
end
2198 90 mohor
 
2199
 
2200 150 mohor
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
2201 90 mohor
 
2202 150 mohor
 
2203 219 mohor
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
2204 88 mohor
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
2205
         .clk(WB_CLK_I),                                .reset(Reset),
2206 219 mohor
         .write(WriteRxDataToFifo_wb & ~RxBufferFull),  .read(MasterWbRX & m_wb_ack_i),
2207 90 mohor
         .clear(RxFifoReset),                           .full(RxBufferFull),
2208 118 mohor
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
2209 150 mohor
         .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)
2210 88 mohor
        );
2211 40 mohor
 
2212 226 tadejm
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
2213
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
2214 219 mohor
assign WriteRxDataToMemory = ~RxBufferEmpty;
2215 226 tadejm
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
2216 40 mohor
 
2217
 
2218
// Generation of the end-of-frame signal
2219
always @ (posedge MRxClk or posedge Reset)
2220 38 mohor
begin
2221 40 mohor
  if(Reset)
2222 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2223 38 mohor
  else
2224 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
2225 159 mohor
    ShiftEnded_rck <=#Tp 1'b1;
2226 38 mohor
  else
2227 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
2228 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2229 38 mohor
end
2230
 
2231 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2232
begin
2233
  if(Reset)
2234
    ShiftEndedSync1 <=#Tp 1'b0;
2235
  else
2236 159 mohor
    ShiftEndedSync1 <=#Tp ShiftEnded_rck;
2237 40 mohor
end
2238 38 mohor
 
2239 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2240 38 mohor
begin
2241 40 mohor
  if(Reset)
2242
    ShiftEndedSync2 <=#Tp 1'b0;
2243 38 mohor
  else
2244 90 mohor
    ShiftEndedSync2 <=#Tp ShiftEndedSync1;
2245 40 mohor
end
2246 38 mohor
 
2247 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2248
begin
2249
  if(Reset)
2250
    ShiftEndedSync3 <=#Tp 1'b0;
2251
  else
2252
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
2253
    ShiftEndedSync3 <=#Tp 1'b1;
2254
  else
2255
  if(ShiftEnded)
2256
    ShiftEndedSync3 <=#Tp 1'b0;
2257
end
2258 38 mohor
 
2259 40 mohor
// Generation of the end-of-frame signal
2260
always @ (posedge WB_CLK_I or posedge Reset)
2261 38 mohor
begin
2262 40 mohor
  if(Reset)
2263
    ShiftEnded <=#Tp 1'b0;
2264 38 mohor
  else
2265 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2266 40 mohor
    ShiftEnded <=#Tp 1'b1;
2267 38 mohor
  else
2268 40 mohor
  if(RxStatusWrite)
2269
    ShiftEnded <=#Tp 1'b0;
2270 38 mohor
end
2271
 
2272 118 mohor
always @ (posedge MRxClk or posedge Reset)
2273
begin
2274
  if(Reset)
2275
    ShiftEndedSync_c1 <=#Tp 1'b0;
2276
  else
2277
    ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
2278
end
2279 38 mohor
 
2280 118 mohor
always @ (posedge MRxClk or posedge Reset)
2281
begin
2282
  if(Reset)
2283
    ShiftEndedSync_c2 <=#Tp 1'b0;
2284
  else
2285
    ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
2286
end
2287
 
2288 40 mohor
// Generation of the end-of-frame signal
2289
always @ (posedge MRxClk or posedge Reset)
2290 38 mohor
begin
2291 40 mohor
  if(Reset)
2292
    RxEnableWindow <=#Tp 1'b0;
2293 38 mohor
  else
2294 40 mohor
  if(RxStartFrm)
2295
    RxEnableWindow <=#Tp 1'b1;
2296 38 mohor
  else
2297 40 mohor
  if(RxEndFrm | RxAbort)
2298
    RxEnableWindow <=#Tp 1'b0;
2299 38 mohor
end
2300
 
2301
 
2302 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2303 38 mohor
begin
2304 40 mohor
  if(Reset)
2305
    RxAbortSync1 <=#Tp 1'b0;
2306 38 mohor
  else
2307 150 mohor
    RxAbortSync1 <=#Tp RxAbortLatched;
2308 40 mohor
end
2309
 
2310
always @ (posedge WB_CLK_I or posedge Reset)
2311
begin
2312
  if(Reset)
2313
    RxAbortSync2 <=#Tp 1'b0;
2314 38 mohor
  else
2315 40 mohor
    RxAbortSync2 <=#Tp RxAbortSync1;
2316 38 mohor
end
2317
 
2318 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2319
begin
2320
  if(Reset)
2321
    RxAbortSync3 <=#Tp 1'b0;
2322
  else
2323
    RxAbortSync3 <=#Tp RxAbortSync2;
2324
end
2325
 
2326
always @ (posedge WB_CLK_I or posedge Reset)
2327
begin
2328
  if(Reset)
2329
    RxAbortSync4 <=#Tp 1'b0;
2330
  else
2331
    RxAbortSync4 <=#Tp RxAbortSync3;
2332
end
2333
 
2334 40 mohor
always @ (posedge MRxClk or posedge Reset)
2335
begin
2336
  if(Reset)
2337
    RxAbortSyncb1 <=#Tp 1'b0;
2338
  else
2339
    RxAbortSyncb1 <=#Tp RxAbortSync2;
2340
end
2341 38 mohor
 
2342 40 mohor
always @ (posedge MRxClk or posedge Reset)
2343 38 mohor
begin
2344 40 mohor
  if(Reset)
2345
    RxAbortSyncb2 <=#Tp 1'b0;
2346 38 mohor
  else
2347 40 mohor
    RxAbortSyncb2 <=#Tp RxAbortSyncb1;
2348 38 mohor
end
2349
 
2350
 
2351 64 mohor
always @ (posedge MRxClk or posedge Reset)
2352
begin
2353
  if(Reset)
2354
    RxAbortLatched <=#Tp 1'b0;
2355
  else
2356 150 mohor
  if(RxAbortSyncb2)
2357
    RxAbortLatched <=#Tp 1'b0;
2358
  else
2359 64 mohor
  if(RxAbort)
2360
    RxAbortLatched <=#Tp 1'b1;
2361
end
2362 40 mohor
 
2363 64 mohor
 
2364 42 mohor
always @ (posedge MRxClk or posedge Reset)
2365
begin
2366
  if(Reset)
2367
    LatchedRxLength[15:0] <=#Tp 16'h0;
2368
  else
2369 150 mohor
  if(LoadRxStatus)
2370 42 mohor
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
2371
end
2372
 
2373
 
2374 261 mohor
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
2375 42 mohor
 
2376
always @ (posedge MRxClk or posedge Reset)
2377
begin
2378
  if(Reset)
2379
    RxStatusInLatched <=#Tp 'h0;
2380
  else
2381 150 mohor
  if(LoadRxStatus)
2382 42 mohor
    RxStatusInLatched <=#Tp RxStatusIn;
2383
end
2384
 
2385
 
2386 60 mohor
// Rx overrun
2387
always @ (posedge WB_CLK_I or posedge Reset)
2388
begin
2389
  if(Reset)
2390
    RxOverrun <=#Tp 1'b0;
2391
  else
2392
  if(RxStatusWrite)
2393
    RxOverrun <=#Tp 1'b0;
2394
  else
2395
  if(RxBufferFull & WriteRxDataToFifo_wb)
2396
    RxOverrun <=#Tp 1'b1;
2397
end
2398 48 mohor
 
2399 77 mohor
 
2400
 
2401
wire TxError;
2402
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2403
 
2404
wire RxError;
2405
 
2406 239 tadejm
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
2407 250 mohor
// are aborted when signal r_RecSmall is set to 0 in MODER register. 
2408
// AddressMiss is identifying that a frame was received because of the promiscous
2409
// mode and is not an error
2410 239 tadejm
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
2411
 
2412 77 mohor
// Tx Done Interrupt
2413
always @ (posedge WB_CLK_I or posedge Reset)
2414
begin
2415
  if(Reset)
2416
    TxB_IRQ <=#Tp 1'b0;
2417
  else
2418
  if(TxStatusWrite & TxIRQEn)
2419
    TxB_IRQ <=#Tp ~TxError;
2420
  else
2421
    TxB_IRQ <=#Tp 1'b0;
2422
end
2423
 
2424
 
2425
// Tx Error Interrupt
2426
always @ (posedge WB_CLK_I or posedge Reset)
2427
begin
2428
  if(Reset)
2429
    TxE_IRQ <=#Tp 1'b0;
2430
  else
2431
  if(TxStatusWrite & TxIRQEn)
2432
    TxE_IRQ <=#Tp TxError;
2433
  else
2434
    TxE_IRQ <=#Tp 1'b0;
2435
end
2436
 
2437
 
2438
// Rx Done Interrupt
2439
always @ (posedge WB_CLK_I or posedge Reset)
2440
begin
2441
  if(Reset)
2442
    RxB_IRQ <=#Tp 1'b0;
2443
  else
2444
  if(RxStatusWrite & RxIRQEn)
2445 261 mohor
    RxB_IRQ <=#Tp ReceivedPacketGood & (~RxError) & (~r_RxFlow); // When r_RxFlow is set, RXC irq is set.
2446 77 mohor
  else
2447
    RxB_IRQ <=#Tp 1'b0;
2448
end
2449
 
2450
 
2451
// Rx Error Interrupt
2452
always @ (posedge WB_CLK_I or posedge Reset)
2453
begin
2454
  if(Reset)
2455
    RxE_IRQ <=#Tp 1'b0;
2456
  else
2457
  if(RxStatusWrite & RxIRQEn)
2458
    RxE_IRQ <=#Tp RxError;
2459
  else
2460
    RxE_IRQ <=#Tp 1'b0;
2461
end
2462
 
2463
 
2464 166 mohor
// Busy Interrupt
2465 77 mohor
 
2466 166 mohor
reg Busy_IRQ_rck;
2467
reg Busy_IRQ_sync1;
2468
reg Busy_IRQ_sync2;
2469
reg Busy_IRQ_sync3;
2470
reg Busy_IRQ_syncb1;
2471
reg Busy_IRQ_syncb2;
2472 77 mohor
 
2473
 
2474 166 mohor
always @ (posedge MRxClk or posedge Reset)
2475
begin
2476
  if(Reset)
2477
    Busy_IRQ_rck <=#Tp 1'b0;
2478
  else
2479
  if(RxValid & RxStartFrm & ~RxReady)
2480
    Busy_IRQ_rck <=#Tp 1'b1;
2481
  else
2482
  if(Busy_IRQ_syncb2)
2483
    Busy_IRQ_rck <=#Tp 1'b0;
2484
end
2485 77 mohor
 
2486 166 mohor
always @ (posedge WB_CLK_I)
2487
begin
2488
    Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
2489
    Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
2490
    Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
2491
end
2492
 
2493
always @ (posedge MRxClk)
2494
begin
2495
    Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
2496
    Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
2497
end
2498
 
2499
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
2500
 
2501
 
2502 60 mohor
 
2503
// TX
2504 61 mohor
// bit 15 ready
2505
// bit 14 interrupt
2506
// bit 13 wrap
2507
// bit 12 pad
2508
// bit 11 crc
2509
// bit 10 last
2510
// bit 9  pause request (control frame)
2511
// bit 8  TxUnderRun          
2512
// bit 7-4 RetryCntLatched    
2513
// bit 3  retransmittion limit
2514
// bit 2  LateCollLatched        
2515
// bit 1  DeferLatched        
2516
// bit 0  CarrierSenseLost    
2517 60 mohor
 
2518
 
2519
// RX
2520
// bit 15 od rx je empty
2521 61 mohor
// bit 14 od rx je interrupt
2522 60 mohor
// bit 13 od rx je wrap
2523
// bit 12 od rx je reserved
2524
// bit 11 od rx je reserved
2525
// bit 10 od rx je reserved
2526
// bit 9  od rx je reserved
2527
// bit 8  od rx je reserved
2528 110 mohor
// bit 7  od rx je Miss
2529 60 mohor
// bit 6  od rx je RxOverrun
2530
// bit 5  od rx je InvalidSymbol
2531
// bit 4  od rx je DribbleNibble
2532
// bit 3  od rx je ReceivedPacketTooBig
2533
// bit 2  od rx je ShortFrame
2534
// bit 1  od rx je LatchedCrcError
2535
// bit 0  od rx je RxLateCollision
2536
 
2537 110 mohor
 
2538 38 mohor
endmodule
2539
 

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