OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 269

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 166 mohor
////  All additional information is available in the Readme.txt   ////
12 38 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 269 mohor
// Revision 1.47  2002/11/22 13:26:21  mohor
45
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
46
// anywhere. Removed.
47
//
48 264 mohor
// Revision 1.46  2002/11/22 01:57:06  mohor
49
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
50
// synchronized.
51
//
52 261 mohor
// Revision 1.45  2002/11/19 17:33:34  mohor
53
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
54
// that a frame was received because of the promiscous mode.
55
//
56 250 mohor
// Revision 1.44  2002/11/13 22:21:40  tadejm
57
// RxError is not generated when small frame reception is enabled and small
58
// frames are received.
59
//
60 239 tadejm
// Revision 1.43  2002/10/18 20:53:34  mohor
61
// case changed to casex.
62
//
63 229 mohor
// Revision 1.42  2002/10/18 17:04:20  tadejm
64
// Changed BIST scan signals.
65
//
66 227 tadejm
// Revision 1.41  2002/10/18 15:42:09  tadejm
67
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
68
//
69 226 tadejm
// Revision 1.40  2002/10/14 16:07:02  mohor
70
// TxStatus is written after last access to the TX fifo is finished (in case of abort
71
// or retry). TxDone is fixed.
72
//
73 221 mohor
// Revision 1.39  2002/10/11 15:35:20  mohor
74
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
75
// TxDone and TxRetry are generated after the current WISHBONE access is
76
// finished.
77
//
78 219 mohor
// Revision 1.38  2002/10/10 16:29:30  mohor
79
// BIST added.
80
//
81 210 mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
82
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
83
//
84 167 mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
85
// Reception is possible after RxPointer is read and not after BD is read. For
86
// that reason RxBDReady is changed to RxReady.
87
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
88
// comes, interrupt is generated.
89
//
90 166 mohor
// Revision 1.35  2002/09/10 10:35:23  mohor
91
// Ethernet debug registers removed.
92
//
93 164 mohor
// Revision 1.34  2002/09/08 16:31:49  mohor
94
// Async reset for WB_ACK_O removed (when core was in reset, it was
95
// impossible to access BDs).
96
// RxPointers and TxPointers names changed to be more descriptive.
97
// TxUnderRun synchronized.
98
//
99 159 mohor
// Revision 1.33  2002/09/04 18:47:57  mohor
100
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
101
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
102
// was not used OK.
103
//
104 150 mohor
// Revision 1.32  2002/08/14 19:31:48  mohor
105
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
106
// need to multiply or devide any more.
107
//
108 134 mohor
// Revision 1.31  2002/07/25 18:29:01  mohor
109
// WriteRxDataToMemory signal changed so end of frame (when last word is
110
// written to fifo) is changed.
111
//
112 127 mohor
// Revision 1.30  2002/07/23 15:28:31  mohor
113
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
114
//
115 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
116
// ShiftEnded synchronization changed.
117
//
118 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
119
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
120
//
121 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
122
// RxPointer bug fixed.
123
//
124 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
125
// Previous bug wasn't succesfully removed. Now fixed.
126
//
127 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
128
// Master state machine had a bug when switching from master write to
129
// master read.
130
//
131 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
132
// m_wb_cyc_o signal released after every single transfer.
133
//
134 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
135
// Outputs registered. Reset changed for eth_wishbone module.
136
//
137 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
138
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
139
// bug fixed.
140
//
141 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
142
// Small typo fixed.
143
//
144 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
145
// Any address can be used for Tx and Rx BD pointers. Address does not need
146
// to be aligned.
147
//
148 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
149
// Comments in Slovene language removed.
150
//
151 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
152
// casex changed with case, fifo reset changed.
153
//
154 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
155
// rx_fifo was not always cleared ok. Fixed.
156
//
157 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
158
// Status was not latched correctly sometimes. Fixed.
159
//
160 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
161
// Big Endian problem when sending frames fixed.
162
//
163 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
164
// Byte ordering changed (Big Endian used). casex changed with case because
165
// Xilinx Foundation had problems. Tested in HW. It WORKS.
166
//
167 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
168
// Small fixes for external/internal DMA missmatches.
169
//
170 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
171
// Interrupts changed
172
//
173 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
174
// Status was not written correctly when frames were discarted because of
175
// address mismatch.
176
//
177 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
178
// RxStartFrm cleared when abort or retry comes.
179
//
180 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
181
// Changes that were lost when updating from 1.5 to 1.8 fixed.
182
//
183 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
184
// Addition  of new module eth_addrcheck.v
185
//
186
// Revision 1.7  2002/02/12 17:03:47  mohor
187
// RxOverRun added to statuses.
188
//
189
// Revision 1.6  2002/02/11 09:18:22  mohor
190
// Tx status is written back to the BD.
191
//
192 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
193
// Rx status is written back to the BD.
194
//
195 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
196
// non-DMA host interface added. Select the right configutation in eth_defines.
197
//
198 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
199
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
200
// MHz. Statuses, overrun, control frame transmission and reception still  need
201
// to be fixed.
202
//
203 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
204
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
205
// added.
206
//
207 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
208
// Initial version. Equals to eth_wishbonedma.v at this moment.
209 38 mohor
//
210
//
211
//
212
 
213
`include "eth_defines.v"
214
`include "timescale.v"
215
 
216
 
217
module eth_wishbone
218
   (
219
 
220
    // WISHBONE common
221 40 mohor
    WB_CLK_I, WB_DAT_I, WB_DAT_O,
222 38 mohor
 
223
    // WISHBONE slave
224 77 mohor
                WB_ADR_I, WB_WE_I, WB_ACK_O,
225 40 mohor
    BDCs,
226 38 mohor
 
227 40 mohor
    Reset,
228
 
229 39 mohor
    // WISHBONE master
230
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
231
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
232
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
233
 
234 219 mohor
`ifdef ETH_WISHBONE_B3
235
    m_wb_cti_o, m_wb_bte_o,
236
`endif
237
 
238 38 mohor
    //TX
239 60 mohor
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
240 150 mohor
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
241 38 mohor
    PerPacketPad,
242
 
243
    //RX
244 40 mohor
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
245 38 mohor
 
246
    // Register
247 261 mohor
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RxFlow,
248 38 mohor
 
249
    // Interrupts
250 150 mohor
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
251 42 mohor
 
252 60 mohor
    // Rx Status
253 42 mohor
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
254 250 mohor
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
255 261 mohor
    ReceivedPauseFrm,
256 60 mohor
 
257
    // Tx Status
258 164 mohor
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
259
 
260 210 mohor
    // Bist
261
`ifdef ETH_BIST
262 227 tadejm
    ,
263
    // debug chain signals
264
    scanb_rst,      // bist scan reset
265
    scanb_clk,      // bist scan clock
266
    scanb_si,       // bist scan serial in
267
    scanb_so,       // bist scan serial out
268
    scanb_en        // bist scan shift enable
269 210 mohor
`endif
270
 
271
 
272
 
273 38 mohor
                );
274
 
275
 
276
parameter Tp = 1;
277
 
278 150 mohor
 
279 38 mohor
// WISHBONE common
280
input           WB_CLK_I;       // WISHBONE clock
281
input  [31:0]   WB_DAT_I;       // WISHBONE data input
282
output [31:0]   WB_DAT_O;       // WISHBONE data output
283
 
284
// WISHBONE slave
285
input   [9:2]   WB_ADR_I;       // WISHBONE address input
286
input           WB_WE_I;        // WISHBONE write enable input
287
input           BDCs;           // Buffer descriptors are selected
288
output          WB_ACK_O;       // WISHBONE acknowledge output
289
 
290 39 mohor
// WISHBONE master
291
output  [31:0]  m_wb_adr_o;     // 
292
output   [3:0]  m_wb_sel_o;     // 
293
output          m_wb_we_o;      // 
294
output  [31:0]  m_wb_dat_o;     // 
295
output          m_wb_cyc_o;     // 
296
output          m_wb_stb_o;     // 
297
input   [31:0]  m_wb_dat_i;     // 
298
input           m_wb_ack_i;     // 
299
input           m_wb_err_i;     // 
300
 
301 219 mohor
`ifdef ETH_WISHBONE_B3
302
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
303
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
304
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
305
`endif
306
 
307 40 mohor
input           Reset;       // Reset signal
308 39 mohor
 
309 60 mohor
// Rx Status signals
310 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
311
input           LatchedCrcError;  // CRC error
312
input           RxLateCollision;  // Late collision occured while receiving frame
313
input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
314
input           DribbleNibble;    // Extra nibble received
315
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
316
input    [15:0] RxLength;         // Length of the incoming frame
317
input           LoadRxStatus;     // Rx status was loaded
318 77 mohor
input           ReceivedPacketGood;// Received packet's length and CRC are good
319 250 mohor
input           AddressMiss;      // When a packet is received AddressMiss status is written to the Rx BD
320 261 mohor
input           r_RxFlow;
321
input           ReceivedPauseFrm;
322 39 mohor
 
323 60 mohor
// Tx Status signals
324
input     [3:0] RetryCntLatched;  // Latched Retry Counter
325
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
326
input           LateCollLatched;  // Late collision occured
327
input           DeferLatched;     // Defer indication (Frame was defered before sucessfully sent)
328
input           CarrierSenseLost; // Carrier Sense was lost during the frame transmission
329
 
330 38 mohor
// Tx
331
input           MTxClk;         // Transmit clock (from PHY)
332
input           TxUsedData;     // Transmit packet used data
333
input           TxRetry;        // Transmit packet retry
334
input           TxAbort;        // Transmit packet abort
335
input           TxDone;         // Transmission ended
336
output          TxStartFrm;     // Transmit packet start frame
337
output          TxEndFrm;       // Transmit packet end frame
338
output  [7:0]   TxData;         // Transmit packet data byte
339
output          TxUnderRun;     // Transmit packet under-run
340
output          PerPacketCrcEn; // Per packet crc enable
341
output          PerPacketPad;   // Per packet pading
342
 
343
// Rx
344
input           MRxClk;         // Receive clock (from PHY)
345
input   [7:0]   RxData;         // Received data byte (from PHY)
346
input           RxValid;        // 
347
input           RxStartFrm;     // 
348
input           RxEndFrm;       // 
349 40 mohor
input           RxAbort;        // This signal is set when address doesn't match.
350 38 mohor
 
351
//Register
352
input           r_TxEn;         // Transmit enable
353
input           r_RxEn;         // Receive enable
354
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
355
input           TX_BD_NUM_Wr;   // RxBDNumber written
356
 
357
// Interrupts
358
output TxB_IRQ;
359
output TxE_IRQ;
360
output RxB_IRQ;
361 77 mohor
output RxE_IRQ;
362 38 mohor
output Busy_IRQ;
363
 
364 77 mohor
 
365 210 mohor
// Bist
366
`ifdef ETH_BIST
367 227 tadejm
input   scanb_rst;      // bist scan reset
368
input   scanb_clk;      // bist scan clock
369
input   scanb_si;       // bist scan serial in
370
output  scanb_so;       // bist scan serial out
371
input   scanb_en;       // bist scan shift enable
372 210 mohor
`endif
373
 
374 77 mohor
reg TxB_IRQ;
375
reg TxE_IRQ;
376
reg RxB_IRQ;
377
reg RxE_IRQ;
378
 
379 38 mohor
reg             TxStartFrm;
380
reg             TxEndFrm;
381
reg     [7:0]   TxData;
382
 
383
reg             TxUnderRun;
384 60 mohor
reg             TxUnderRun_wb;
385 38 mohor
 
386
reg             TxBDRead;
387 39 mohor
wire            TxStatusWrite;
388 38 mohor
 
389
reg     [1:0]   TxValidBytesLatched;
390
 
391
reg    [15:0]   TxLength;
392 60 mohor
reg    [15:0]   LatchedTxLength;
393
reg   [14:11]   TxStatus;
394 38 mohor
 
395 60 mohor
reg   [14:13]   RxStatus;
396 38 mohor
 
397
reg             TxStartFrm_wb;
398
reg             TxRetry_wb;
399 39 mohor
reg             TxAbort_wb;
400 38 mohor
reg             TxDone_wb;
401
 
402
reg             TxDone_wb_q;
403
reg             TxAbort_wb_q;
404 39 mohor
reg             TxRetry_wb_q;
405 219 mohor
reg             TxRetryPacket;
406 221 mohor
reg             TxRetryPacket_NotCleared;
407
reg             TxDonePacket;
408
reg             TxDonePacket_NotCleared;
409 219 mohor
reg             TxAbortPacket;
410 221 mohor
reg             TxAbortPacket_NotCleared;
411 38 mohor
reg             RxBDReady;
412 166 mohor
reg             RxReady;
413 38 mohor
reg             TxBDReady;
414
 
415
reg             RxBDRead;
416 40 mohor
wire            RxStatusWrite;
417 38 mohor
 
418
reg    [31:0]   TxDataLatched;
419
reg     [1:0]   TxByteCnt;
420
reg             LastWord;
421 39 mohor
reg             ReadTxDataFromFifo_tck;
422 38 mohor
 
423
reg             BlockingTxStatusWrite;
424
reg             BlockingTxBDRead;
425
 
426 40 mohor
reg             Flop;
427 38 mohor
 
428
reg     [7:0]   TxBDAddress;
429
reg     [7:0]   RxBDAddress;
430
 
431
reg             TxRetrySync1;
432
reg             TxAbortSync1;
433 39 mohor
reg             TxDoneSync1;
434 38 mohor
 
435
reg             TxAbort_q;
436
reg             TxRetry_q;
437
reg             TxUsedData_q;
438
 
439
reg    [31:0]   RxDataLatched2;
440 82 mohor
 
441
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
442
 
443 38 mohor
reg     [1:0]   RxValidBytes;
444
reg     [1:0]   RxByteCnt;
445
reg             LastByteIn;
446
reg             ShiftWillEnd;
447
 
448 40 mohor
reg             WriteRxDataToFifo;
449 42 mohor
reg    [15:0]   LatchedRxLength;
450 64 mohor
reg             RxAbortLatched;
451 38 mohor
 
452 40 mohor
reg             ShiftEnded;
453 60 mohor
reg             RxOverrun;
454 38 mohor
 
455 40 mohor
reg             BDWrite;                    // BD Write Enable for access from WISHBONE side
456
reg             BDRead;                     // BD Read access from WISHBONE side
457 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
458
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
459 38 mohor
 
460 39 mohor
reg             TxEndFrm_wb;
461 38 mohor
 
462 39 mohor
wire            TxRetryPulse;
463 38 mohor
wire            TxDonePulse;
464
wire            TxAbortPulse;
465
 
466
wire            StartRxBDRead;
467
 
468
wire            StartTxBDRead;
469
 
470
wire            TxIRQEn;
471
wire            WrapTxStatusBit;
472
 
473 77 mohor
wire            RxIRQEn;
474 38 mohor
wire            WrapRxStatusBit;
475
 
476
wire    [1:0]   TxValidBytes;
477
 
478
wire    [7:0]   TempTxBDAddress;
479
wire    [7:0]   TempRxBDAddress;
480
 
481
wire            SetGotData;
482
wire            GotDataEvaluate;
483
 
484 106 mohor
reg             WB_ACK_O;
485 38 mohor
 
486 261 mohor
wire    [8:0]   RxStatusIn;
487
reg     [8:0]   RxStatusInLatched;
488 42 mohor
 
489 39 mohor
reg WbEn, WbEn_q;
490
reg RxEn, RxEn_q;
491
reg TxEn, TxEn_q;
492 38 mohor
 
493 39 mohor
wire ram_ce;
494
wire ram_we;
495
wire ram_oe;
496
reg [7:0]   ram_addr;
497
reg [31:0]  ram_di;
498
wire [31:0] ram_do;
499 38 mohor
 
500 39 mohor
wire StartTxPointerRead;
501
reg  TxPointerRead;
502
reg TxEn_needed;
503 40 mohor
reg RxEn_needed;
504 38 mohor
 
505 40 mohor
wire StartRxPointerRead;
506
reg RxPointerRead;
507 38 mohor
 
508 219 mohor
`ifdef ETH_WISHBONE_B3
509
assign m_wb_bte_o = 2'b00;    // Linear burst
510
`endif
511 39 mohor
 
512 219 mohor
 
513 159 mohor
always @ (posedge WB_CLK_I)
514 40 mohor
begin
515 159 mohor
  WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
516 40 mohor
end
517 39 mohor
 
518 106 mohor
assign WB_DAT_O = ram_do;
519 39 mohor
 
520 41 mohor
// Generic synchronous single-port RAM interface
521 119 mohor
eth_spram_256x32 bd_ram (
522 226 tadejm
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
523 210 mohor
`ifdef ETH_BIST
524 227 tadejm
  ,
525
  .scanb_rst      (scanb_rst),
526
  .scanb_clk      (scanb_clk),
527
  .scanb_si       (scanb_si),
528
  .scanb_so       (scanb_so),
529
  .scanb_en       (scanb_en)
530 210 mohor
`endif
531 39 mohor
);
532 41 mohor
 
533 39 mohor
assign ram_ce = 1'b1;
534 40 mohor
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
535 61 mohor
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
536 39 mohor
 
537
 
538 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
539 38 mohor
begin
540 40 mohor
  if(Reset)
541 39 mohor
    TxEn_needed <=#Tp 1'b0;
542 38 mohor
  else
543 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
544 39 mohor
    TxEn_needed <=#Tp 1'b1;
545
  else
546
  if(TxPointerRead & TxEn & TxEn_q)
547
    TxEn_needed <=#Tp 1'b0;
548 38 mohor
end
549
 
550 39 mohor
// Enabling access to the RAM for three devices.
551 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
552 39 mohor
begin
553 40 mohor
  if(Reset)
554 39 mohor
    begin
555
      WbEn <=#Tp 1'b1;
556
      RxEn <=#Tp 1'b0;
557
      TxEn <=#Tp 1'b0;
558
      ram_addr <=#Tp 8'h0;
559
      ram_di <=#Tp 32'h0;
560 77 mohor
      BDRead <=#Tp 1'b0;
561
      BDWrite <=#Tp 1'b0;
562 39 mohor
    end
563
  else
564
    begin
565
      // Switching between three stages depends on enable signals
566 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
567
        5'b100_10, 5'b100_11 :
568 39 mohor
          begin
569
            WbEn <=#Tp 1'b0;
570
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
571
            TxEn <=#Tp 1'b0;
572 40 mohor
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
573 39 mohor
            ram_di <=#Tp RxBDDataIn;
574
          end
575
        5'b100_01 :
576
          begin
577
            WbEn <=#Tp 1'b0;
578
            RxEn <=#Tp 1'b0;
579
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
580
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
581
            ram_di <=#Tp TxBDDataIn;
582
          end
583 90 mohor
        5'b010_00, 5'b010_10 :
584 39 mohor
          begin
585
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
586
            RxEn <=#Tp 1'b0;
587
            TxEn <=#Tp 1'b0;
588
            ram_addr <=#Tp WB_ADR_I[9:2];
589
            ram_di <=#Tp WB_DAT_I;
590 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
591
            BDRead <=#Tp BDCs & ~WB_WE_I;
592 39 mohor
          end
593 90 mohor
        5'b010_01, 5'b010_11 :
594 39 mohor
          begin
595
            WbEn <=#Tp 1'b0;
596
            RxEn <=#Tp 1'b0;
597
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
598
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
599
            ram_di <=#Tp TxBDDataIn;
600
          end
601 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
602 39 mohor
          begin
603
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
604
            RxEn <=#Tp 1'b0;
605
            TxEn <=#Tp 1'b0;
606
            ram_addr <=#Tp WB_ADR_I[9:2];
607
            ram_di <=#Tp WB_DAT_I;
608 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
609
            BDRead <=#Tp BDCs & ~WB_WE_I;
610 39 mohor
          end
611
        5'b100_00 :
612
          begin
613
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
614
          end
615
        5'b000_00 :
616
          begin
617
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
618
            RxEn <=#Tp 1'b0;
619
            TxEn <=#Tp 1'b0;
620
            ram_addr <=#Tp WB_ADR_I[9:2];
621
            ram_di <=#Tp WB_DAT_I;
622 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
623
            BDRead <=#Tp BDCs & ~WB_WE_I;
624 39 mohor
          end
625
      endcase
626
    end
627
end
628
 
629
 
630
// Delayed stage signals
631 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
632 39 mohor
begin
633 40 mohor
  if(Reset)
634 39 mohor
    begin
635
      WbEn_q <=#Tp 1'b0;
636
      RxEn_q <=#Tp 1'b0;
637
      TxEn_q <=#Tp 1'b0;
638
    end
639
  else
640
    begin
641
      WbEn_q <=#Tp WbEn;
642
      RxEn_q <=#Tp RxEn;
643
      TxEn_q <=#Tp TxEn;
644
    end
645
end
646
 
647 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
648 40 mohor
always @ (posedge MTxClk or posedge Reset)
649 38 mohor
begin
650 40 mohor
  if(Reset)
651 38 mohor
    Flop <=#Tp 1'b0;
652
  else
653
  if(TxDone | TxAbort | TxRetry_q)
654
    Flop <=#Tp 1'b0;
655
  else
656
  if(TxUsedData)
657
    Flop <=#Tp ~Flop;
658
end
659
 
660 39 mohor
wire ResetTxBDReady;
661
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
662 38 mohor
 
663
// Latching READY status of the Tx buffer descriptor
664 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
665 38 mohor
begin
666 40 mohor
  if(Reset)
667 38 mohor
    TxBDReady <=#Tp 1'b0;
668
  else
669 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
670
    TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
671
  else                                                // Only packets larger then 4 bytes are transmitted.
672 39 mohor
  if(ResetTxBDReady)
673 38 mohor
    TxBDReady <=#Tp 1'b0;
674
end
675
 
676
 
677 39 mohor
// Reading the Tx buffer descriptor
678 221 mohor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
679 39 mohor
 
680 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
681 38 mohor
begin
682 40 mohor
  if(Reset)
683 39 mohor
    TxBDRead <=#Tp 1'b1;
684 38 mohor
  else
685 110 mohor
  if(StartTxBDRead)
686 39 mohor
    TxBDRead <=#Tp 1'b1;
687 38 mohor
  else
688 39 mohor
  if(TxBDReady)
689
    TxBDRead <=#Tp 1'b0;
690 38 mohor
end
691
 
692
 
693 39 mohor
// Reading Tx BD pointer
694
assign StartTxPointerRead = TxBDRead & TxBDReady;
695 38 mohor
 
696 39 mohor
// Reading Tx BD Pointer
697 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
698 38 mohor
begin
699 40 mohor
  if(Reset)
700 39 mohor
    TxPointerRead <=#Tp 1'b0;
701 38 mohor
  else
702 39 mohor
  if(StartTxPointerRead)
703
    TxPointerRead <=#Tp 1'b1;
704 38 mohor
  else
705 39 mohor
  if(TxEn_q)
706
    TxPointerRead <=#Tp 1'b0;
707 38 mohor
end
708
 
709
 
710 39 mohor
// Writing status back to the Tx buffer descriptor
711 221 mohor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
712 38 mohor
 
713
 
714
 
715 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
716 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
717 38 mohor
begin
718 40 mohor
  if(Reset)
719 39 mohor
    BlockingTxStatusWrite <=#Tp 1'b0;
720 38 mohor
  else
721 39 mohor
  if(TxStatusWrite)
722
    BlockingTxStatusWrite <=#Tp 1'b1;
723 38 mohor
  else
724 39 mohor
  if(~TxDone_wb & ~TxAbort_wb)
725
    BlockingTxStatusWrite <=#Tp 1'b0;
726 38 mohor
end
727
 
728
 
729 159 mohor
reg BlockingTxStatusWrite_sync1;
730
reg BlockingTxStatusWrite_sync2;
731
 
732
// Synchronizing BlockingTxStatusWrite to MTxClk
733
always @ (posedge MTxClk or posedge Reset)
734
begin
735
  if(Reset)
736
    BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
737
  else
738
    BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
739
end
740
 
741
// Synchronizing BlockingTxStatusWrite to MTxClk
742
always @ (posedge MTxClk or posedge Reset)
743
begin
744
  if(Reset)
745
    BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
746
  else
747
    BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
748
end
749
 
750
 
751 39 mohor
// TxBDRead state is activated only once. 
752 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
753 39 mohor
begin
754 40 mohor
  if(Reset)
755 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
756
  else
757 110 mohor
  if(StartTxBDRead)
758 39 mohor
    BlockingTxBDRead <=#Tp 1'b1;
759
  else
760 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
761 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
762
end
763 38 mohor
 
764
 
765 39 mohor
// Latching status from the tx buffer descriptor
766
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
767 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
768 38 mohor
begin
769 40 mohor
  if(Reset)
770 60 mohor
    TxStatus <=#Tp 4'h0;
771 38 mohor
  else
772 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
773 60 mohor
    TxStatus <=#Tp ram_do[14:11];
774 38 mohor
end
775
 
776 40 mohor
reg ReadTxDataFromMemory;
777
wire WriteRxDataToMemory;
778 38 mohor
 
779 39 mohor
reg MasterWbTX;
780
reg MasterWbRX;
781
 
782
reg [31:0] m_wb_adr_o;
783
reg        m_wb_cyc_o;
784
reg        m_wb_stb_o;
785 96 mohor
reg  [3:0] m_wb_sel_o;
786 39 mohor
reg        m_wb_we_o;
787 40 mohor
 
788 39 mohor
wire TxLengthEq0;
789
wire TxLengthLt4;
790
 
791 150 mohor
reg BlockingIncrementTxPointer;
792 159 mohor
reg [31:2] TxPointerMSB;
793
reg [1:0]  TxPointerLSB;
794
reg [1:0]  TxPointerLSB_rst;
795
reg [31:2] RxPointerMSB;
796
reg [1:0]  RxPointerLSB_rst;
797 39 mohor
 
798 150 mohor
wire RxBurstAcc;
799
wire RxWordAcc;
800
wire RxHalfAcc;
801
wire RxByteAcc;
802
 
803 39 mohor
//Latching length from the buffer descriptor;
804 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
805 38 mohor
begin
806 40 mohor
  if(Reset)
807 39 mohor
    TxLength <=#Tp 16'h0;
808 38 mohor
  else
809 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
810
    TxLength <=#Tp ram_do[31:16];
811 38 mohor
  else
812 39 mohor
  if(MasterWbTX & m_wb_ack_i)
813
    begin
814
      if(TxLengthLt4)
815
        TxLength <=#Tp 16'h0;
816 150 mohor
      else
817 159 mohor
      if(TxPointerLSB_rst==2'h0)
818 96 mohor
        TxLength <=#Tp TxLength - 3'h4;    // Length is subtracted at the data request
819 39 mohor
      else
820 159 mohor
      if(TxPointerLSB_rst==2'h1)
821 150 mohor
        TxLength <=#Tp TxLength - 3'h3;    // Length is subtracted at the data request
822
      else
823 159 mohor
      if(TxPointerLSB_rst==2'h2)
824 150 mohor
        TxLength <=#Tp TxLength - 3'h2;    // Length is subtracted at the data request
825
      else
826 159 mohor
      if(TxPointerLSB_rst==2'h3)
827 150 mohor
        TxLength <=#Tp TxLength - 3'h1;    // Length is subtracted at the data request
828 39 mohor
    end
829 38 mohor
end
830
 
831 96 mohor
 
832
 
833 60 mohor
//Latching length from the buffer descriptor;
834
always @ (posedge WB_CLK_I or posedge Reset)
835
begin
836
  if(Reset)
837
    LatchedTxLength <=#Tp 16'h0;
838
  else
839
  if(TxEn & TxEn_q & TxBDRead)
840
    LatchedTxLength <=#Tp ram_do[31:16];
841
end
842
 
843 39 mohor
assign TxLengthEq0 = TxLength == 0;
844
assign TxLengthLt4 = TxLength < 4;
845 38 mohor
 
846 150 mohor
reg cyc_cleared;
847
reg IncrTxPointer;
848 39 mohor
 
849
 
850 159 mohor
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
851
// because TxPointerMSB is only used for word-aligned accesses.
852 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
853 38 mohor
begin
854 40 mohor
  if(Reset)
855 159 mohor
    TxPointerMSB <=#Tp 30'h0;
856 38 mohor
  else
857 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
858 159 mohor
    TxPointerMSB <=#Tp ram_do[31:2];
859 38 mohor
  else
860 150 mohor
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
861 159 mohor
    TxPointerMSB <=#Tp TxPointerMSB + 1'b1;     // TxPointer is word-aligned
862 38 mohor
end
863
 
864 96 mohor
 
865 159 mohor
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
866
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
867
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
868
// set by this two bits.
869 96 mohor
always @ (posedge WB_CLK_I or posedge Reset)
870
begin
871
  if(Reset)
872 159 mohor
    TxPointerLSB[1:0] <=#Tp 0;
873 96 mohor
  else
874
  if(TxEn & TxEn_q & TxPointerRead)
875 159 mohor
    TxPointerLSB[1:0] <=#Tp ram_do[1:0];
876 96 mohor
end
877
 
878
 
879 159 mohor
// Latching 2 MSB bits of the buffer descriptor. 
880
// After the read access, TxLength needs to be decremented for the number of the valid
881
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are 
882
// valid so this two bits are reset to zero. 
883 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
884
begin
885
  if(Reset)
886 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
887 150 mohor
  else
888
  if(TxEn & TxEn_q & TxPointerRead)
889 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
890 150 mohor
  else
891
  if(MasterWbTX & m_wb_ack_i)                 // After first access pointer is word alligned
892 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
893 150 mohor
end
894 96 mohor
 
895 150 mohor
 
896 159 mohor
reg  [3:0] RxByteSel;
897 39 mohor
wire MasterAccessFinished;
898 38 mohor
 
899 39 mohor
 
900 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
901 38 mohor
begin
902 40 mohor
  if(Reset)
903 39 mohor
    BlockingIncrementTxPointer <=#Tp 0;
904 38 mohor
  else
905 39 mohor
  if(MasterAccessFinished)
906
    BlockingIncrementTxPointer <=#Tp 0;
907 38 mohor
  else
908 150 mohor
  if(IncrTxPointer)
909 39 mohor
    BlockingIncrementTxPointer <=#Tp 1'b1;
910 38 mohor
end
911
 
912
 
913 39 mohor
wire TxBufferAlmostFull;
914
wire TxBufferFull;
915
wire TxBufferEmpty;
916
wire TxBufferAlmostEmpty;
917 40 mohor
wire SetReadTxDataFromMemory;
918 39 mohor
 
919 40 mohor
reg BlockReadTxDataFromMemory;
920 39 mohor
 
921 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
922 39 mohor
 
923 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
924 38 mohor
begin
925 40 mohor
  if(Reset)
926
    ReadTxDataFromMemory <=#Tp 1'b0;
927 38 mohor
  else
928 219 mohor
  if(TxLengthEq0 | TxAbortPacket | TxRetryPacket)
929 40 mohor
    ReadTxDataFromMemory <=#Tp 1'b0;
930 39 mohor
  else
931 40 mohor
  if(SetReadTxDataFromMemory)
932
    ReadTxDataFromMemory <=#Tp 1'b1;
933 38 mohor
end
934
 
935 226 tadejm
reg tx_burst_en;
936
reg rx_burst_en;
937 221 mohor
reg BlockingLastReadOn_Abort_Retry;
938
 
939
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory & ~BlockingLastReadOn_Abort_Retry;
940 226 tadejm
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
941 221 mohor
 
942 39 mohor
wire [31:0] TxData_wb;
943
wire ReadTxDataFromFifo_wb;
944 38 mohor
 
945 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
946 38 mohor
begin
947 40 mohor
  if(Reset)
948
    BlockReadTxDataFromMemory <=#Tp 1'b0;
949 38 mohor
  else
950 269 mohor
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket | TxRetryPacket)))
951 40 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b1;
952 219 mohor
  else
953 221 mohor
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
954 219 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b0;
955 39 mohor
end
956
 
957
 
958 221 mohor
always @ (posedge WB_CLK_I or posedge Reset)
959
begin
960
  if(Reset)
961
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
962
  else
963
  if(TxAbortPacket | TxRetryPacket)
964
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
965
  else
966
  if(((TxAbort_wb & !TxAbortPacket_NotCleared) | (TxRetry_wb & !TxRetryPacket_NotCleared)) & !TxBDReady)
967
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b1;
968
end
969 39 mohor
 
970 221 mohor
 
971
 
972
 
973 39 mohor
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
974 219 mohor
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
975
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
976 226 tadejm
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
977
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
978 159 mohor
 
979 226 tadejm
wire rx_burst;
980
wire enough_data_in_rxfifo_for_burst;
981
wire enough_data_in_rxfifo_for_burst_plus1;
982 229 mohor
 
983 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
984 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
985 39 mohor
begin
986 40 mohor
  if(Reset)
987 38 mohor
    begin
988 39 mohor
      MasterWbTX <=#Tp 1'b0;
989
      MasterWbRX <=#Tp 1'b0;
990
      m_wb_adr_o <=#Tp 32'h0;
991
      m_wb_cyc_o <=#Tp 1'b0;
992
      m_wb_stb_o <=#Tp 1'b0;
993
      m_wb_we_o  <=#Tp 1'b0;
994 96 mohor
      m_wb_sel_o <=#Tp 4'h0;
995 110 mohor
      cyc_cleared<=#Tp 1'b0;
996 226 tadejm
      tx_burst_cnt<=#Tp 0;
997
      rx_burst_cnt<=#Tp 0;
998 150 mohor
      IncrTxPointer<=#Tp 1'b0;
999 226 tadejm
      tx_burst_en<=#Tp 1'b1;
1000
      rx_burst_en<=#Tp 1'b0;
1001
      `ifdef ETH_WISHBONE_B3
1002
        m_wb_cti_o <=#Tp 3'b0;
1003
      `endif
1004 38 mohor
    end
1005 39 mohor
  else
1006
    begin
1007
      // Switching between two stages depends on enable signals
1008 229 mohor
      casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst})  // synopsys parallel_case
1009 226 tadejm
        8'b00_10_00_10,             // Idle and MRB needed
1010 229 mohor
        8'b10_1x_10_1x,             // MRB continues
1011 226 tadejm
        8'b10_10_01_10,             // Clear (previously MR) and MRB needed
1012 229 mohor
        8'b01_1x_01_1x :            // Clear (previously MW) and MRB needed
1013 39 mohor
          begin
1014 226 tadejm
            MasterWbTX <=#Tp 1'b1;  // tx burst
1015
            MasterWbRX <=#Tp 1'b0;
1016
            m_wb_cyc_o <=#Tp 1'b1;
1017
            m_wb_stb_o <=#Tp 1'b1;
1018
            m_wb_we_o  <=#Tp 1'b0;
1019
            m_wb_sel_o <=#Tp 4'hf;
1020
            cyc_cleared<=#Tp 1'b0;
1021
            IncrTxPointer<=#Tp 1'b1;
1022
            tx_burst_cnt <=#Tp tx_burst_cnt+1;
1023
            if(tx_burst_cnt==0)
1024
              m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1025
            else
1026
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1027
 
1028
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
1029
              begin
1030
                tx_burst_en<=#Tp 1'b0;
1031
              `ifdef ETH_WISHBONE_B3
1032
                m_wb_cti_o <=#Tp 3'b111;
1033
              `endif
1034
              end
1035
            else
1036
              begin
1037
              `ifdef ETH_WISHBONE_B3
1038
                m_wb_cti_o <=#Tp 3'b010;
1039
              `endif
1040
              end
1041
          end
1042 229 mohor
        8'b00_x1_00_x1,             // Idle and MWB needed
1043
        8'b01_x1_10_x1,             // MWB continues
1044 226 tadejm
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
1045 229 mohor
        8'b10_x1_01_x1 :            // Clear (previously MR) and MWB needed
1046 226 tadejm
          begin
1047
            MasterWbTX <=#Tp 1'b0;  // rx burst
1048 39 mohor
            MasterWbRX <=#Tp 1'b1;
1049 226 tadejm
            m_wb_cyc_o <=#Tp 1'b1;
1050
            m_wb_stb_o <=#Tp 1'b1;
1051
            m_wb_we_o  <=#Tp 1'b1;
1052
            m_wb_sel_o <=#Tp RxByteSel;
1053
            IncrTxPointer<=#Tp 1'b0;
1054
            cyc_cleared<=#Tp 1'b0;
1055
            rx_burst_cnt <=#Tp rx_burst_cnt+1;
1056
 
1057
            if(rx_burst_cnt==0)
1058
              m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1059
            else
1060
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1061
 
1062
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
1063
              begin
1064
                rx_burst_en<=#Tp 1'b0;
1065
              `ifdef ETH_WISHBONE_B3
1066
                m_wb_cti_o <=#Tp 3'b111;
1067
              `endif
1068
              end
1069
            else
1070
              begin
1071
              `ifdef ETH_WISHBONE_B3
1072
                m_wb_cti_o <=#Tp 3'b010;
1073
              `endif
1074
              end
1075
          end
1076 229 mohor
        8'b00_x1_00_x0 :            // idle and MW is needed (data write to rx buffer)
1077 226 tadejm
          begin
1078
            MasterWbTX <=#Tp 1'b0;
1079
            MasterWbRX <=#Tp 1'b1;
1080 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1081 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1082
            m_wb_stb_o <=#Tp 1'b1;
1083
            m_wb_we_o  <=#Tp 1'b1;
1084 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1085 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1086 39 mohor
          end
1087 226 tadejm
        8'b00_10_00_00 :            // idle and MR is needed (data read from tx buffer)
1088 39 mohor
          begin
1089 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1090 39 mohor
            MasterWbRX <=#Tp 1'b0;
1091 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1092 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1093
            m_wb_stb_o <=#Tp 1'b1;
1094
            m_wb_we_o  <=#Tp 1'b0;
1095 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1096
            IncrTxPointer<=#Tp 1'b1;
1097 39 mohor
          end
1098 226 tadejm
        8'b10_10_01_00,             // MR and MR is needed (data read from tx buffer)
1099 229 mohor
        8'b01_1x_01_0x  :           // MW and MR is needed (data read from tx buffer)
1100 39 mohor
          begin
1101 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1102 39 mohor
            MasterWbRX <=#Tp 1'b0;
1103 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1104 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1105
            m_wb_stb_o <=#Tp 1'b1;
1106
            m_wb_we_o  <=#Tp 1'b0;
1107 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1108 110 mohor
            cyc_cleared<=#Tp 1'b0;
1109 150 mohor
            IncrTxPointer<=#Tp 1'b1;
1110 39 mohor
          end
1111 226 tadejm
        8'b01_01_01_00,             // MW and MW needed (data write to rx buffer)
1112 229 mohor
        8'b10_x1_01_x0  :           // MR and MW is needed (data write to rx buffer)
1113 39 mohor
          begin
1114 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1115 39 mohor
            MasterWbRX <=#Tp 1'b1;
1116 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1117 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1118
            m_wb_stb_o <=#Tp 1'b1;
1119 39 mohor
            m_wb_we_o  <=#Tp 1'b1;
1120 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1121 110 mohor
            cyc_cleared<=#Tp 1'b0;
1122 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1123 39 mohor
          end
1124 226 tadejm
        8'b01_01_10_00,             // MW and MW needed (cycle is cleared between previous and next access)
1125 229 mohor
        8'b01_1x_10_x0,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
1126 226 tadejm
        8'b10_10_10_00,             // MR and MR needed (cycle is cleared between previous and next access)
1127 229 mohor
        8'b10_x1_10_0x :            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
1128 39 mohor
          begin
1129 110 mohor
            m_wb_cyc_o <=#Tp 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
1130
            m_wb_stb_o <=#Tp 1'b0;
1131
            cyc_cleared<=#Tp 1'b1;
1132 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1133 226 tadejm
            tx_burst_cnt<=#Tp 0;
1134
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1135
            rx_burst_cnt<=#Tp 0;
1136
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1137
            `ifdef ETH_WISHBONE_B3
1138
              m_wb_cti_o <=#Tp 3'b0;
1139
            `endif
1140 110 mohor
          end
1141 229 mohor
        8'bxx_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1142
        8'bxx_00_01_00 :            // Between cyc_cleared request was cleared
1143 110 mohor
          begin
1144 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1145 39 mohor
            MasterWbRX <=#Tp 1'b0;
1146
            m_wb_cyc_o <=#Tp 1'b0;
1147
            m_wb_stb_o <=#Tp 1'b0;
1148 226 tadejm
            cyc_cleared<=#Tp 1'b0;
1149 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1150 226 tadejm
            rx_burst_cnt<=#Tp 0;
1151
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1152
            `ifdef ETH_WISHBONE_B3
1153
              m_wb_cti_o <=#Tp 3'b0;
1154
            `endif
1155 39 mohor
          end
1156 226 tadejm
        8'b00_00_00_00:             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1157 127 mohor
          begin
1158 226 tadejm
            tx_burst_cnt<=#Tp 0;
1159
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1160 127 mohor
          end
1161 226 tadejm
        default:                    // Don't touch
1162 82 mohor
          begin
1163
            MasterWbTX <=#Tp MasterWbTX;
1164
            MasterWbRX <=#Tp MasterWbRX;
1165
            m_wb_cyc_o <=#Tp m_wb_cyc_o;
1166
            m_wb_stb_o <=#Tp m_wb_stb_o;
1167 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_o;
1168 150 mohor
            IncrTxPointer<=#Tp IncrTxPointer;
1169 82 mohor
          end
1170 39 mohor
      endcase
1171
    end
1172 38 mohor
end
1173
 
1174 110 mohor
 
1175 39 mohor
wire TxFifoClear;
1176 96 mohor
 
1177 219 mohor
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
1178 38 mohor
 
1179 219 mohor
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
1180 150 mohor
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
1181 96 mohor
          .clk(WB_CLK_I),                                   .reset(Reset),
1182 226 tadejm
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
1183 96 mohor
          .clear(TxFifoClear),                              .full(TxBufferFull),
1184
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
1185 150 mohor
          .empty(TxBufferEmpty),                            .cnt(txfifo_cnt)
1186 96 mohor
        );
1187 39 mohor
 
1188
 
1189
reg StartOccured;
1190
reg TxStartFrm_sync1;
1191
reg TxStartFrm_sync2;
1192
reg TxStartFrm_syncb1;
1193
reg TxStartFrm_syncb2;
1194
 
1195
 
1196
 
1197
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1198 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1199 38 mohor
begin
1200 40 mohor
  if(Reset)
1201 39 mohor
    TxStartFrm_wb <=#Tp 1'b0;
1202 38 mohor
  else
1203 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1204
    TxStartFrm_wb <=#Tp 1'b1;
1205 38 mohor
  else
1206 39 mohor
  if(TxStartFrm_syncb2)
1207
    TxStartFrm_wb <=#Tp 1'b0;
1208 38 mohor
end
1209
 
1210 39 mohor
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
1211 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1212 38 mohor
begin
1213 40 mohor
  if(Reset)
1214 39 mohor
    StartOccured <=#Tp 1'b0;
1215 38 mohor
  else
1216 39 mohor
  if(TxStartFrm_wb)
1217
    StartOccured <=#Tp 1'b1;
1218 38 mohor
  else
1219 39 mohor
  if(ResetTxBDReady)
1220
    StartOccured <=#Tp 1'b0;
1221 38 mohor
end
1222
 
1223 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1224 40 mohor
always @ (posedge MTxClk or posedge Reset)
1225 39 mohor
begin
1226 40 mohor
  if(Reset)
1227 39 mohor
    TxStartFrm_sync1 <=#Tp 1'b0;
1228
  else
1229
    TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
1230
end
1231 38 mohor
 
1232 40 mohor
always @ (posedge MTxClk or posedge Reset)
1233 39 mohor
begin
1234 40 mohor
  if(Reset)
1235 39 mohor
    TxStartFrm_sync2 <=#Tp 1'b0;
1236
  else
1237
    TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
1238
end
1239
 
1240 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1241 38 mohor
begin
1242 40 mohor
  if(Reset)
1243 39 mohor
    TxStartFrm_syncb1 <=#Tp 1'b0;
1244 38 mohor
  else
1245 39 mohor
    TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
1246 38 mohor
end
1247
 
1248 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1249 38 mohor
begin
1250 40 mohor
  if(Reset)
1251 39 mohor
    TxStartFrm_syncb2 <=#Tp 1'b0;
1252 38 mohor
  else
1253 39 mohor
    TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
1254
end
1255
 
1256 40 mohor
always @ (posedge MTxClk or posedge Reset)
1257 39 mohor
begin
1258 40 mohor
  if(Reset)
1259 39 mohor
    TxStartFrm <=#Tp 1'b0;
1260 38 mohor
  else
1261 39 mohor
  if(TxStartFrm_sync2)
1262 61 mohor
    TxStartFrm <=#Tp 1'b1;
1263 39 mohor
  else
1264 61 mohor
  if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry | TxAbort))
1265 39 mohor
    TxStartFrm <=#Tp 1'b0;
1266 38 mohor
end
1267 39 mohor
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1268 38 mohor
 
1269
 
1270 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1271 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1272 38 mohor
begin
1273 40 mohor
  if(Reset)
1274 39 mohor
    TxEndFrm_wb <=#Tp 1'b0;
1275 38 mohor
  else
1276 221 mohor
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
1277 39 mohor
    TxEndFrm_wb <=#Tp 1'b1;
1278 38 mohor
  else
1279 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1280
    TxEndFrm_wb <=#Tp 1'b0;
1281 38 mohor
end
1282
 
1283
 
1284
// Marks which bytes are valid within the word.
1285 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1286 38 mohor
 
1287 39 mohor
reg LatchValidBytes;
1288
reg LatchValidBytes_q;
1289 38 mohor
 
1290 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1291 38 mohor
begin
1292 40 mohor
  if(Reset)
1293 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1294 38 mohor
  else
1295 39 mohor
  if(TxLengthLt4 & TxBDReady)
1296
    LatchValidBytes <=#Tp 1'b1;
1297 38 mohor
  else
1298 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1299 38 mohor
end
1300
 
1301 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1302 38 mohor
begin
1303 40 mohor
  if(Reset)
1304 39 mohor
    LatchValidBytes_q <=#Tp 1'b0;
1305 38 mohor
  else
1306 39 mohor
    LatchValidBytes_q <=#Tp LatchValidBytes;
1307 38 mohor
end
1308
 
1309
 
1310 39 mohor
// Latching valid bytes
1311 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1312 38 mohor
begin
1313 40 mohor
  if(Reset)
1314 39 mohor
    TxValidBytesLatched <=#Tp 2'h0;
1315 38 mohor
  else
1316 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1317
    TxValidBytesLatched <=#Tp TxValidBytes;
1318
  else
1319
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1320
    TxValidBytesLatched <=#Tp 2'h0;
1321 38 mohor
end
1322
 
1323
 
1324
assign TxIRQEn          = TxStatus[14];
1325 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1326
assign PerPacketPad     = TxStatus[12];
1327
assign PerPacketCrcEn   = TxStatus[11];
1328 38 mohor
 
1329
 
1330 77 mohor
assign RxIRQEn         = RxStatus[14];
1331 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1332 38 mohor
 
1333
 
1334
// Temporary Tx and Rx buffer descriptor address 
1335 39 mohor
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite     & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
1336 134 mohor
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum<<1)     | // Using first Rx BD
1337 39 mohor
                              {8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
1338 38 mohor
 
1339
 
1340
// Latching Tx buffer descriptor address
1341 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1342 38 mohor
begin
1343 40 mohor
  if(Reset)
1344 38 mohor
    TxBDAddress <=#Tp 8'h0;
1345
  else
1346
  if(TxStatusWrite)
1347
    TxBDAddress <=#Tp TempTxBDAddress;
1348
end
1349
 
1350
 
1351
// Latching Rx buffer descriptor address
1352 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1353 38 mohor
begin
1354 40 mohor
  if(Reset)
1355 134 mohor
    RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF<<1;
1356 38 mohor
  else
1357 77 mohor
  if(TX_BD_NUM_Wr)                        // When r_TxBDNum is updated, RxBDAddress is also
1358 134 mohor
    RxBDAddress <=#Tp WB_DAT_I[7:0]<<1;
1359 38 mohor
  else
1360
  if(RxStatusWrite)
1361
    RxBDAddress <=#Tp TempRxBDAddress;
1362
end
1363
 
1364 60 mohor
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
1365 38 mohor
 
1366 261 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
1367 60 mohor
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1368 38 mohor
 
1369 60 mohor
 
1370 38 mohor
// Signals used for various purposes
1371 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1372 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1373
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1374
 
1375
 
1376
 
1377 39 mohor
// Generating delayed signals
1378 40 mohor
always @ (posedge MTxClk or posedge Reset)
1379 38 mohor
begin
1380 40 mohor
  if(Reset)
1381 39 mohor
    begin
1382
      TxAbort_q      <=#Tp 1'b0;
1383
      TxRetry_q      <=#Tp 1'b0;
1384
      TxUsedData_q   <=#Tp 1'b0;
1385
    end
1386 38 mohor
  else
1387 39 mohor
    begin
1388
      TxAbort_q      <=#Tp TxAbort;
1389
      TxRetry_q      <=#Tp TxRetry;
1390
      TxUsedData_q   <=#Tp TxUsedData;
1391
    end
1392 38 mohor
end
1393
 
1394
// Generating delayed signals
1395 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1396 38 mohor
begin
1397 40 mohor
  if(Reset)
1398 38 mohor
    begin
1399 39 mohor
      TxDone_wb_q   <=#Tp 1'b0;
1400
      TxAbort_wb_q  <=#Tp 1'b0;
1401 40 mohor
      TxRetry_wb_q  <=#Tp 1'b0;
1402 38 mohor
    end
1403
  else
1404
    begin
1405 39 mohor
      TxDone_wb_q   <=#Tp TxDone_wb;
1406
      TxAbort_wb_q  <=#Tp TxAbort_wb;
1407 40 mohor
      TxRetry_wb_q  <=#Tp TxRetry_wb;
1408 38 mohor
    end
1409
end
1410
 
1411
 
1412 219 mohor
reg TxAbortPacketBlocked;
1413
always @ (posedge WB_CLK_I or posedge Reset)
1414
begin
1415
  if(Reset)
1416
    TxAbortPacket <=#Tp 1'b0;
1417
  else
1418 226 tadejm
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxAbortPacketBlocked |
1419
     TxAbort_wb & !MasterWbTX & !TxAbortPacketBlocked)
1420 219 mohor
    TxAbortPacket <=#Tp 1'b1;
1421
  else
1422
    TxAbortPacket <=#Tp 1'b0;
1423
end
1424
 
1425
 
1426
always @ (posedge WB_CLK_I or posedge Reset)
1427
begin
1428
  if(Reset)
1429 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1430
  else
1431 226 tadejm
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1432
     TxAbort_wb & !MasterWbTX)
1433 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b1;
1434
  else
1435
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1436
end
1437
 
1438
 
1439
always @ (posedge WB_CLK_I or posedge Reset)
1440
begin
1441
  if(Reset)
1442 219 mohor
    TxAbortPacketBlocked <=#Tp 1'b0;
1443
  else
1444
  if(TxAbortPacket)
1445
    TxAbortPacketBlocked <=#Tp 1'b1;
1446
  else
1447
  if(!TxAbort_wb & TxAbort_wb_q)
1448
    TxAbortPacketBlocked <=#Tp 1'b0;
1449
end
1450
 
1451
 
1452
reg TxRetryPacketBlocked;
1453
always @ (posedge WB_CLK_I or posedge Reset)
1454
begin
1455
  if(Reset)
1456
    TxRetryPacket <=#Tp 1'b0;
1457
  else
1458 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
1459
     TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1460 219 mohor
    TxRetryPacket <=#Tp 1'b1;
1461
  else
1462
    TxRetryPacket <=#Tp 1'b0;
1463
end
1464
 
1465
 
1466
always @ (posedge WB_CLK_I or posedge Reset)
1467
begin
1468
  if(Reset)
1469 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1470
  else
1471 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1472
     TxRetry_wb & !MasterWbTX)
1473 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b1;
1474
  else
1475
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1476
end
1477
 
1478
 
1479
always @ (posedge WB_CLK_I or posedge Reset)
1480
begin
1481
  if(Reset)
1482 219 mohor
    TxRetryPacketBlocked <=#Tp 1'b0;
1483
  else
1484
  if(TxRetryPacket)
1485
    TxRetryPacketBlocked <=#Tp 1'b1;
1486
  else
1487
  if(!TxRetry_wb & TxRetry_wb_q)
1488
    TxRetryPacketBlocked <=#Tp 1'b0;
1489
end
1490
 
1491
 
1492 221 mohor
reg TxDonePacketBlocked;
1493
always @ (posedge WB_CLK_I or posedge Reset)
1494
begin
1495
  if(Reset)
1496
    TxDonePacket <=#Tp 1'b0;
1497
  else
1498 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
1499
     TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
1500 221 mohor
    TxDonePacket <=#Tp 1'b1;
1501
  else
1502
    TxDonePacket <=#Tp 1'b0;
1503
end
1504
 
1505
 
1506
always @ (posedge WB_CLK_I or posedge Reset)
1507
begin
1508
  if(Reset)
1509
    TxDonePacket_NotCleared <=#Tp 1'b0;
1510
  else
1511 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
1512
     TxDone_wb & !MasterWbTX)
1513 221 mohor
    TxDonePacket_NotCleared <=#Tp 1'b1;
1514
  else
1515
    TxDonePacket_NotCleared <=#Tp 1'b0;
1516
end
1517
 
1518
 
1519
always @ (posedge WB_CLK_I or posedge Reset)
1520
begin
1521
  if(Reset)
1522
    TxDonePacketBlocked <=#Tp 1'b0;
1523
  else
1524
  if(TxDonePacket)
1525
    TxDonePacketBlocked <=#Tp 1'b1;
1526
  else
1527
  if(!TxDone_wb & TxDone_wb_q)
1528
    TxDonePacketBlocked <=#Tp 1'b0;
1529
end
1530
 
1531
 
1532 38 mohor
// Sinchronizing and evaluating tx data
1533 39 mohor
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
1534 219 mohor
assign SetGotData = (TxStartFrm_wb);
1535 38 mohor
 
1536
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
1537 40 mohor
//assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1538
assign GotDataEvaluate = (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1539 38 mohor
 
1540
 
1541
// Indication of the last word
1542 40 mohor
always @ (posedge MTxClk or posedge Reset)
1543 38 mohor
begin
1544 40 mohor
  if(Reset)
1545 38 mohor
    LastWord <=#Tp 1'b0;
1546
  else
1547
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1548
    LastWord <=#Tp 1'b0;
1549
  else
1550
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1551 39 mohor
    LastWord <=#Tp TxEndFrm_wb;
1552 38 mohor
end
1553
 
1554
 
1555
// Tx end frame generation
1556 40 mohor
always @ (posedge MTxClk or posedge Reset)
1557 38 mohor
begin
1558 40 mohor
  if(Reset)
1559 38 mohor
    TxEndFrm <=#Tp 1'b0;
1560
  else
1561 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1562 38 mohor
    TxEndFrm <=#Tp 1'b0;
1563
  else
1564
  if(Flop & LastWord)
1565
    begin
1566 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1567 38 mohor
        1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
1568
        2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
1569
        3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
1570
 
1571
        default : TxEndFrm <=#Tp 1'b0;
1572
      endcase
1573
    end
1574
end
1575
 
1576
 
1577
// Tx data selection (latching)
1578 40 mohor
always @ (posedge MTxClk or posedge Reset)
1579 38 mohor
begin
1580 40 mohor
  if(Reset)
1581 96 mohor
    TxData <=#Tp 0;
1582 38 mohor
  else
1583 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1584 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1585 96 mohor
      2'h0 : TxData <=#Tp TxData_wb[31:24];                  // Big Endian Byte Ordering
1586
      2'h1 : TxData <=#Tp TxData_wb[23:16];                  // Big Endian Byte Ordering
1587
      2'h2 : TxData <=#Tp TxData_wb[15:08];                  // Big Endian Byte Ordering
1588
      2'h3 : TxData <=#Tp TxData_wb[07:00];                  // Big Endian Byte Ordering
1589
    endcase
1590 38 mohor
  else
1591 159 mohor
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1592 96 mohor
    TxData <=#Tp TxData_wb[31:24];                           // Big Endian Byte Ordering
1593
  else
1594 38 mohor
  if(TxUsedData & Flop)
1595
    begin
1596 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1597 226 tadejm
 
1598 82 mohor
        1 : TxData <=#Tp TxDataLatched[23:16];
1599
        2 : TxData <=#Tp TxDataLatched[15:8];
1600
        3 : TxData <=#Tp TxDataLatched[7:0];
1601 38 mohor
      endcase
1602
    end
1603
end
1604
 
1605
 
1606
// Latching tx data
1607 40 mohor
always @ (posedge MTxClk or posedge Reset)
1608 38 mohor
begin
1609 40 mohor
  if(Reset)
1610 38 mohor
    TxDataLatched[31:0] <=#Tp 32'h0;
1611
  else
1612 96 mohor
 if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1613 39 mohor
    TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
1614 38 mohor
end
1615
 
1616
 
1617
// Tx under run
1618 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1619 38 mohor
begin
1620 40 mohor
  if(Reset)
1621 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1622 38 mohor
  else
1623 39 mohor
  if(TxAbortPulse)
1624 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1625
  else
1626
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1627
    TxUnderRun_wb <=#Tp 1'b1;
1628
end
1629
 
1630
 
1631 159 mohor
reg TxUnderRun_sync1;
1632
 
1633 60 mohor
// Tx under run
1634
always @ (posedge MTxClk or posedge Reset)
1635
begin
1636
  if(Reset)
1637 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b0;
1638 43 mohor
  else
1639 60 mohor
  if(TxUnderRun_wb)
1640 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b1;
1641 60 mohor
  else
1642 159 mohor
  if(BlockingTxStatusWrite_sync2)
1643
    TxUnderRun_sync1 <=#Tp 1'b0;
1644
end
1645
 
1646
// Tx under run
1647
always @ (posedge MTxClk or posedge Reset)
1648
begin
1649
  if(Reset)
1650 60 mohor
    TxUnderRun <=#Tp 1'b0;
1651 159 mohor
  else
1652
  if(BlockingTxStatusWrite_sync2)
1653
    TxUnderRun <=#Tp 1'b0;
1654
  else
1655
  if(TxUnderRun_sync1)
1656
    TxUnderRun <=#Tp 1'b1;
1657 38 mohor
end
1658
 
1659
 
1660
// Tx Byte counter
1661 40 mohor
always @ (posedge MTxClk or posedge Reset)
1662 38 mohor
begin
1663 40 mohor
  if(Reset)
1664 38 mohor
    TxByteCnt <=#Tp 2'h0;
1665
  else
1666
  if(TxAbort_q | TxRetry_q)
1667
    TxByteCnt <=#Tp 2'h0;
1668
  else
1669
  if(TxStartFrm & ~TxUsedData)
1670 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1671 96 mohor
      2'h0 : TxByteCnt <=#Tp 2'h1;
1672
      2'h1 : TxByteCnt <=#Tp 2'h2;
1673
      2'h2 : TxByteCnt <=#Tp 2'h3;
1674
      2'h3 : TxByteCnt <=#Tp 2'h0;
1675
    endcase
1676 38 mohor
  else
1677
  if(TxUsedData & Flop)
1678 96 mohor
    TxByteCnt <=#Tp TxByteCnt + 1'b1;
1679 38 mohor
end
1680
 
1681 39 mohor
 
1682 150 mohor
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1683
reg ReadTxDataFromFifo_sync1;
1684
reg ReadTxDataFromFifo_sync2;
1685
reg ReadTxDataFromFifo_sync3;
1686
reg ReadTxDataFromFifo_syncb1;
1687
reg ReadTxDataFromFifo_syncb2;
1688
reg ReadTxDataFromFifo_syncb3;
1689
 
1690
 
1691
always @ (posedge MTxClk or posedge Reset)
1692
begin
1693
  if(Reset)
1694
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1695
  else
1696 96 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1697 39 mohor
     ReadTxDataFromFifo_tck <=#Tp 1'b1;
1698 150 mohor
  else
1699
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1700
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1701 38 mohor
end
1702
 
1703 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1704 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1705 38 mohor
begin
1706 40 mohor
  if(Reset)
1707 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
1708 38 mohor
  else
1709 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
1710
end
1711 38 mohor
 
1712 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1713 38 mohor
begin
1714 40 mohor
  if(Reset)
1715 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
1716 38 mohor
  else
1717 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
1718 38 mohor
end
1719
 
1720 40 mohor
always @ (posedge MTxClk or posedge Reset)
1721 38 mohor
begin
1722 40 mohor
  if(Reset)
1723 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
1724 38 mohor
  else
1725 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
1726 38 mohor
end
1727
 
1728 40 mohor
always @ (posedge MTxClk or posedge Reset)
1729 38 mohor
begin
1730 40 mohor
  if(Reset)
1731 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
1732 38 mohor
  else
1733 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
1734 38 mohor
end
1735
 
1736 150 mohor
always @ (posedge MTxClk or posedge Reset)
1737
begin
1738
  if(Reset)
1739
    ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
1740
  else
1741
    ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
1742
end
1743
 
1744 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1745 38 mohor
begin
1746 40 mohor
  if(Reset)
1747 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
1748 38 mohor
  else
1749 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
1750 38 mohor
end
1751
 
1752 39 mohor
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
1753
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1754 38 mohor
 
1755
 
1756 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1757 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1758 38 mohor
begin
1759 40 mohor
  if(Reset)
1760 39 mohor
    TxRetrySync1 <=#Tp 1'b0;
1761 38 mohor
  else
1762 39 mohor
    TxRetrySync1 <=#Tp TxRetry;
1763 38 mohor
end
1764
 
1765 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1766 38 mohor
begin
1767 40 mohor
  if(Reset)
1768 39 mohor
    TxRetry_wb <=#Tp 1'b0;
1769 38 mohor
  else
1770 39 mohor
    TxRetry_wb <=#Tp TxRetrySync1;
1771 38 mohor
end
1772
 
1773
 
1774 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1775 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1776 38 mohor
begin
1777 40 mohor
  if(Reset)
1778 39 mohor
    TxDoneSync1 <=#Tp 1'b0;
1779 38 mohor
  else
1780 39 mohor
    TxDoneSync1 <=#Tp TxDone;
1781 38 mohor
end
1782
 
1783 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1784 38 mohor
begin
1785 40 mohor
  if(Reset)
1786 39 mohor
    TxDone_wb <=#Tp 1'b0;
1787 38 mohor
  else
1788 39 mohor
    TxDone_wb <=#Tp TxDoneSync1;
1789 38 mohor
end
1790
 
1791 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1792 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1793 38 mohor
begin
1794 40 mohor
  if(Reset)
1795 39 mohor
    TxAbortSync1 <=#Tp 1'b0;
1796 38 mohor
  else
1797 39 mohor
    TxAbortSync1 <=#Tp TxAbort;
1798 38 mohor
end
1799
 
1800 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1801 38 mohor
begin
1802 40 mohor
  if(Reset)
1803 38 mohor
    TxAbort_wb <=#Tp 1'b0;
1804
  else
1805 39 mohor
    TxAbort_wb <=#Tp TxAbortSync1;
1806 38 mohor
end
1807
 
1808
 
1809 150 mohor
reg RxAbortSync1;
1810
reg RxAbortSync2;
1811
reg RxAbortSync3;
1812
reg RxAbortSync4;
1813
reg RxAbortSyncb1;
1814
reg RxAbortSyncb2;
1815 39 mohor
 
1816 150 mohor
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
1817
 
1818 40 mohor
// Reading the Rx buffer descriptor
1819
always @ (posedge WB_CLK_I or posedge Reset)
1820
begin
1821
  if(Reset)
1822
    RxBDRead <=#Tp 1'b1;
1823
  else
1824 166 mohor
  if(StartRxBDRead & ~RxReady)
1825 40 mohor
    RxBDRead <=#Tp 1'b1;
1826
  else
1827
  if(RxBDReady)
1828
    RxBDRead <=#Tp 1'b0;
1829
end
1830 39 mohor
 
1831
 
1832 38 mohor
// Reading of the next receive buffer descriptor starts after reception status is
1833
// written to the previous one.
1834
 
1835
// Latching READY status of the Rx buffer descriptor
1836 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1837 38 mohor
begin
1838 40 mohor
  if(Reset)
1839 38 mohor
    RxBDReady <=#Tp 1'b0;
1840
  else
1841 166 mohor
  if(RxPointerRead)
1842 150 mohor
    RxBDReady <=#Tp 1'b0;
1843
  else
1844 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1845
    RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
1846 38 mohor
end
1847
 
1848 40 mohor
// Latching Rx buffer descriptor status
1849
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
1850
always @ (posedge WB_CLK_I or posedge Reset)
1851 38 mohor
begin
1852 40 mohor
  if(Reset)
1853 60 mohor
    RxStatus <=#Tp 2'h0;
1854 38 mohor
  else
1855 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1856 60 mohor
    RxStatus <=#Tp ram_do[14:13];
1857 38 mohor
end
1858
 
1859
 
1860 166 mohor
// RxReady generation
1861
always @ (posedge WB_CLK_I or posedge Reset)
1862
begin
1863
  if(Reset)
1864
    RxReady <=#Tp 1'b0;
1865
  else
1866
  if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3)
1867
    RxReady <=#Tp 1'b0;
1868
  else
1869
  if(RxEn & RxEn_q & RxPointerRead)
1870
    RxReady <=#Tp 1'b1;
1871
end
1872 38 mohor
 
1873
 
1874 40 mohor
// Reading Rx BD pointer
1875
 
1876
 
1877
assign StartRxPointerRead = RxBDRead & RxBDReady;
1878
 
1879
// Reading Tx BD Pointer
1880
always @ (posedge WB_CLK_I or posedge Reset)
1881 38 mohor
begin
1882 40 mohor
  if(Reset)
1883
    RxPointerRead <=#Tp 1'b0;
1884 38 mohor
  else
1885 40 mohor
  if(StartRxPointerRead)
1886
    RxPointerRead <=#Tp 1'b1;
1887 38 mohor
  else
1888 166 mohor
  if(RxEn & RxEn_q)
1889 40 mohor
    RxPointerRead <=#Tp 1'b0;
1890 38 mohor
end
1891
 
1892 113 mohor
 
1893 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
1894
always @ (posedge WB_CLK_I or posedge Reset)
1895
begin
1896
  if(Reset)
1897 159 mohor
    RxPointerMSB <=#Tp 30'h0;
1898 40 mohor
  else
1899
  if(RxEn & RxEn_q & RxPointerRead)
1900 159 mohor
    RxPointerMSB <=#Tp ram_do[31:2];
1901 40 mohor
  else
1902 113 mohor
  if(MasterWbRX & m_wb_ack_i)
1903 159 mohor
      RxPointerMSB <=#Tp RxPointerMSB + 1; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
1904 40 mohor
end
1905 38 mohor
 
1906
 
1907 96 mohor
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
1908 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1909
begin
1910
  if(Reset)
1911 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp 0;
1912 96 mohor
  else
1913 159 mohor
  if(MasterWbRX & m_wb_ack_i)                 // After first write all RxByteSel are active
1914
    RxPointerLSB_rst[1:0] <=#Tp 0;
1915 96 mohor
  else
1916
  if(RxEn & RxEn_q & RxPointerRead)
1917 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
1918 96 mohor
end
1919
 
1920
 
1921 159 mohor
always @ (RxPointerLSB_rst)
1922 96 mohor
begin
1923 159 mohor
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
1924
    2'h0 : RxByteSel[3:0] = 4'hf;
1925
    2'h1 : RxByteSel[3:0] = 4'h7;
1926
    2'h2 : RxByteSel[3:0] = 4'h3;
1927
    2'h3 : RxByteSel[3:0] = 4'h1;
1928 96 mohor
  endcase
1929
end
1930
 
1931
 
1932
always @ (posedge WB_CLK_I or posedge Reset)
1933
begin
1934
  if(Reset)
1935 40 mohor
    RxEn_needed <=#Tp 1'b0;
1936 38 mohor
  else
1937 166 mohor
  if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
1938 40 mohor
    RxEn_needed <=#Tp 1'b1;
1939 38 mohor
  else
1940 40 mohor
  if(RxPointerRead & RxEn & RxEn_q)
1941
    RxEn_needed <=#Tp 1'b0;
1942 38 mohor
end
1943
 
1944
 
1945 40 mohor
// Reception status is written back to the buffer descriptor after the end of frame is detected.
1946
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
1947 38 mohor
 
1948 40 mohor
reg RxEnableWindow;
1949 38 mohor
 
1950
// Indicating that last byte is being reveived
1951 40 mohor
always @ (posedge MRxClk or posedge Reset)
1952 38 mohor
begin
1953 40 mohor
  if(Reset)
1954 38 mohor
    LastByteIn <=#Tp 1'b0;
1955
  else
1956 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
1957 38 mohor
    LastByteIn <=#Tp 1'b0;
1958
  else
1959 166 mohor
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
1960 38 mohor
    LastByteIn <=#Tp 1'b1;
1961
end
1962
 
1963 159 mohor
reg ShiftEnded_rck;
1964 40 mohor
reg ShiftEndedSync1;
1965
reg ShiftEndedSync2;
1966 118 mohor
reg ShiftEndedSync3;
1967
reg ShiftEndedSync_c1;
1968
reg ShiftEndedSync_c2;
1969
 
1970 40 mohor
wire StartShiftWillEnd;
1971 96 mohor
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
1972 38 mohor
 
1973
// Indicating that data reception will end
1974 40 mohor
always @ (posedge MRxClk or posedge Reset)
1975 38 mohor
begin
1976 40 mohor
  if(Reset)
1977 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1978
  else
1979 159 mohor
  if(ShiftEnded_rck | RxAbort)
1980 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1981
  else
1982 40 mohor
  if(StartShiftWillEnd)
1983 38 mohor
    ShiftWillEnd <=#Tp 1'b1;
1984
end
1985
 
1986
 
1987 40 mohor
 
1988 38 mohor
// Receive byte counter
1989 40 mohor
always @ (posedge MRxClk or posedge Reset)
1990 38 mohor
begin
1991 40 mohor
  if(Reset)
1992 38 mohor
    RxByteCnt <=#Tp 2'h0;
1993
  else
1994 159 mohor
  if(ShiftEnded_rck | RxAbort)
1995 38 mohor
    RxByteCnt <=#Tp 2'h0;
1996 97 lampret
  else
1997 166 mohor
  if(RxValid & RxStartFrm & RxReady)
1998 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
1999 96 mohor
      2'h0 : RxByteCnt <=#Tp 2'h1;
2000
      2'h1 : RxByteCnt <=#Tp 2'h2;
2001
      2'h2 : RxByteCnt <=#Tp 2'h3;
2002
      2'h3 : RxByteCnt <=#Tp 2'h0;
2003
    endcase
2004 38 mohor
  else
2005 166 mohor
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
2006 40 mohor
    RxByteCnt <=#Tp RxByteCnt + 1'b1;
2007 38 mohor
end
2008
 
2009
 
2010
// Indicates how many bytes are valid within the last word
2011 40 mohor
always @ (posedge MRxClk or posedge Reset)
2012 38 mohor
begin
2013 40 mohor
  if(Reset)
2014 38 mohor
    RxValidBytes <=#Tp 2'h1;
2015
  else
2016 96 mohor
  if(RxValid & RxStartFrm)
2017 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2018 96 mohor
      2'h0 : RxValidBytes <=#Tp 2'h1;
2019
      2'h1 : RxValidBytes <=#Tp 2'h2;
2020
      2'h2 : RxValidBytes <=#Tp 2'h3;
2021
      2'h3 : RxValidBytes <=#Tp 2'h0;
2022
    endcase
2023 38 mohor
  else
2024 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
2025 38 mohor
    RxValidBytes <=#Tp RxValidBytes + 1;
2026
end
2027
 
2028
 
2029 40 mohor
always @ (posedge MRxClk or posedge Reset)
2030 38 mohor
begin
2031 40 mohor
  if(Reset)
2032
    RxDataLatched1       <=#Tp 24'h0;
2033 38 mohor
  else
2034 166 mohor
  if(RxValid & RxReady & ~LastByteIn)
2035 96 mohor
    if(RxStartFrm)
2036 40 mohor
    begin
2037 159 mohor
      case(RxPointerLSB_rst)     // synopsys parallel_case
2038 96 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2039
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2040
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2041
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2042
      endcase
2043
    end
2044
    else if (RxEnableWindow)
2045
    begin
2046 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
2047 82 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2048
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2049
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2050 40 mohor
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2051
      endcase
2052
    end
2053 38 mohor
end
2054
 
2055 40 mohor
wire SetWriteRxDataToFifo;
2056 38 mohor
 
2057 40 mohor
// Assembling data that will be written to the rx_fifo
2058
always @ (posedge MRxClk or posedge Reset)
2059 38 mohor
begin
2060 40 mohor
  if(Reset)
2061
    RxDataLatched2 <=#Tp 32'h0;
2062 38 mohor
  else
2063 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
2064 82 mohor
    RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData};              // Big Endian Byte Ordering
2065 38 mohor
  else
2066 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
2067 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
2068 82 mohor
 
2069
      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
2070
      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
2071
      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};
2072 40 mohor
    endcase
2073 38 mohor
end
2074
 
2075
 
2076 40 mohor
reg WriteRxDataToFifoSync1;
2077
reg WriteRxDataToFifoSync2;
2078 150 mohor
reg WriteRxDataToFifoSync3;
2079 38 mohor
 
2080
 
2081 40 mohor
// Indicating start of the reception process
2082 166 mohor
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
2083
                              (RxValid & RxReady &  RxStartFrm & (&RxPointerLSB_rst))           |
2084
                              (ShiftWillEnd & LastByteIn & (&RxByteCnt));
2085 38 mohor
 
2086 150 mohor
always @ (posedge MRxClk or posedge Reset)
2087
begin
2088
  if(Reset)
2089
    WriteRxDataToFifo <=#Tp 1'b0;
2090
  else
2091
  if(SetWriteRxDataToFifo & ~RxAbort)
2092
    WriteRxDataToFifo <=#Tp 1'b1;
2093
  else
2094
  if(WriteRxDataToFifoSync2 | RxAbort)
2095
    WriteRxDataToFifo <=#Tp 1'b0;
2096
end
2097 40 mohor
 
2098 150 mohor
 
2099
 
2100
always @ (posedge WB_CLK_I or posedge Reset)
2101
begin
2102
  if(Reset)
2103
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2104
  else
2105
  if(WriteRxDataToFifo)
2106
    WriteRxDataToFifoSync1 <=#Tp 1'b1;
2107
  else
2108
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2109
end
2110
 
2111
always @ (posedge WB_CLK_I or posedge Reset)
2112
begin
2113
  if(Reset)
2114
    WriteRxDataToFifoSync2 <=#Tp 1'b0;
2115
  else
2116
    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
2117
end
2118
 
2119
always @ (posedge WB_CLK_I or posedge Reset)
2120
begin
2121
  if(Reset)
2122
    WriteRxDataToFifoSync3 <=#Tp 1'b0;
2123
  else
2124
    WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
2125
end
2126
 
2127
wire WriteRxDataToFifo_wb;
2128
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
2129
 
2130
 
2131 90 mohor
reg LatchedRxStartFrm;
2132
reg SyncRxStartFrm;
2133
reg SyncRxStartFrm_q;
2134 150 mohor
reg SyncRxStartFrm_q2;
2135 90 mohor
wire RxFifoReset;
2136 40 mohor
 
2137 90 mohor
always @ (posedge MRxClk or posedge Reset)
2138
begin
2139
  if(Reset)
2140
    LatchedRxStartFrm <=#Tp 0;
2141
  else
2142 150 mohor
  if(RxStartFrm & ~SyncRxStartFrm_q)
2143 90 mohor
    LatchedRxStartFrm <=#Tp 1;
2144
  else
2145 150 mohor
  if(SyncRxStartFrm_q)
2146 90 mohor
    LatchedRxStartFrm <=#Tp 0;
2147
end
2148
 
2149
 
2150
always @ (posedge WB_CLK_I or posedge Reset)
2151
begin
2152
  if(Reset)
2153
    SyncRxStartFrm <=#Tp 0;
2154
  else
2155
  if(LatchedRxStartFrm)
2156
    SyncRxStartFrm <=#Tp 1;
2157
  else
2158
    SyncRxStartFrm <=#Tp 0;
2159
end
2160
 
2161
 
2162
always @ (posedge WB_CLK_I or posedge Reset)
2163
begin
2164
  if(Reset)
2165
    SyncRxStartFrm_q <=#Tp 0;
2166
  else
2167
    SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
2168
end
2169
 
2170 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2171
begin
2172
  if(Reset)
2173
    SyncRxStartFrm_q2 <=#Tp 0;
2174
  else
2175
    SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
2176
end
2177 90 mohor
 
2178
 
2179 150 mohor
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
2180 90 mohor
 
2181 150 mohor
 
2182 219 mohor
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
2183 88 mohor
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
2184
         .clk(WB_CLK_I),                                .reset(Reset),
2185 219 mohor
         .write(WriteRxDataToFifo_wb & ~RxBufferFull),  .read(MasterWbRX & m_wb_ack_i),
2186 90 mohor
         .clear(RxFifoReset),                           .full(RxBufferFull),
2187 118 mohor
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
2188 150 mohor
         .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)
2189 88 mohor
        );
2190 40 mohor
 
2191 226 tadejm
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
2192
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
2193 219 mohor
assign WriteRxDataToMemory = ~RxBufferEmpty;
2194 226 tadejm
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
2195 40 mohor
 
2196
 
2197
// Generation of the end-of-frame signal
2198
always @ (posedge MRxClk or posedge Reset)
2199 38 mohor
begin
2200 40 mohor
  if(Reset)
2201 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2202 38 mohor
  else
2203 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
2204 159 mohor
    ShiftEnded_rck <=#Tp 1'b1;
2205 38 mohor
  else
2206 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
2207 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2208 38 mohor
end
2209
 
2210 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2211
begin
2212
  if(Reset)
2213
    ShiftEndedSync1 <=#Tp 1'b0;
2214
  else
2215 159 mohor
    ShiftEndedSync1 <=#Tp ShiftEnded_rck;
2216 40 mohor
end
2217 38 mohor
 
2218 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2219 38 mohor
begin
2220 40 mohor
  if(Reset)
2221
    ShiftEndedSync2 <=#Tp 1'b0;
2222 38 mohor
  else
2223 90 mohor
    ShiftEndedSync2 <=#Tp ShiftEndedSync1;
2224 40 mohor
end
2225 38 mohor
 
2226 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2227
begin
2228
  if(Reset)
2229
    ShiftEndedSync3 <=#Tp 1'b0;
2230
  else
2231
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
2232
    ShiftEndedSync3 <=#Tp 1'b1;
2233
  else
2234
  if(ShiftEnded)
2235
    ShiftEndedSync3 <=#Tp 1'b0;
2236
end
2237 38 mohor
 
2238 40 mohor
// Generation of the end-of-frame signal
2239
always @ (posedge WB_CLK_I or posedge Reset)
2240 38 mohor
begin
2241 40 mohor
  if(Reset)
2242
    ShiftEnded <=#Tp 1'b0;
2243 38 mohor
  else
2244 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2245 40 mohor
    ShiftEnded <=#Tp 1'b1;
2246 38 mohor
  else
2247 40 mohor
  if(RxStatusWrite)
2248
    ShiftEnded <=#Tp 1'b0;
2249 38 mohor
end
2250
 
2251 118 mohor
always @ (posedge MRxClk or posedge Reset)
2252
begin
2253
  if(Reset)
2254
    ShiftEndedSync_c1 <=#Tp 1'b0;
2255
  else
2256
    ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
2257
end
2258 38 mohor
 
2259 118 mohor
always @ (posedge MRxClk or posedge Reset)
2260
begin
2261
  if(Reset)
2262
    ShiftEndedSync_c2 <=#Tp 1'b0;
2263
  else
2264
    ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
2265
end
2266
 
2267 40 mohor
// Generation of the end-of-frame signal
2268
always @ (posedge MRxClk or posedge Reset)
2269 38 mohor
begin
2270 40 mohor
  if(Reset)
2271
    RxEnableWindow <=#Tp 1'b0;
2272 38 mohor
  else
2273 40 mohor
  if(RxStartFrm)
2274
    RxEnableWindow <=#Tp 1'b1;
2275 38 mohor
  else
2276 40 mohor
  if(RxEndFrm | RxAbort)
2277
    RxEnableWindow <=#Tp 1'b0;
2278 38 mohor
end
2279
 
2280
 
2281 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2282 38 mohor
begin
2283 40 mohor
  if(Reset)
2284
    RxAbortSync1 <=#Tp 1'b0;
2285 38 mohor
  else
2286 150 mohor
    RxAbortSync1 <=#Tp RxAbortLatched;
2287 40 mohor
end
2288
 
2289
always @ (posedge WB_CLK_I or posedge Reset)
2290
begin
2291
  if(Reset)
2292
    RxAbortSync2 <=#Tp 1'b0;
2293 38 mohor
  else
2294 40 mohor
    RxAbortSync2 <=#Tp RxAbortSync1;
2295 38 mohor
end
2296
 
2297 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2298
begin
2299
  if(Reset)
2300
    RxAbortSync3 <=#Tp 1'b0;
2301
  else
2302
    RxAbortSync3 <=#Tp RxAbortSync2;
2303
end
2304
 
2305
always @ (posedge WB_CLK_I or posedge Reset)
2306
begin
2307
  if(Reset)
2308
    RxAbortSync4 <=#Tp 1'b0;
2309
  else
2310
    RxAbortSync4 <=#Tp RxAbortSync3;
2311
end
2312
 
2313 40 mohor
always @ (posedge MRxClk or posedge Reset)
2314
begin
2315
  if(Reset)
2316
    RxAbortSyncb1 <=#Tp 1'b0;
2317
  else
2318
    RxAbortSyncb1 <=#Tp RxAbortSync2;
2319
end
2320 38 mohor
 
2321 40 mohor
always @ (posedge MRxClk or posedge Reset)
2322 38 mohor
begin
2323 40 mohor
  if(Reset)
2324
    RxAbortSyncb2 <=#Tp 1'b0;
2325 38 mohor
  else
2326 40 mohor
    RxAbortSyncb2 <=#Tp RxAbortSyncb1;
2327 38 mohor
end
2328
 
2329
 
2330 64 mohor
always @ (posedge MRxClk or posedge Reset)
2331
begin
2332
  if(Reset)
2333
    RxAbortLatched <=#Tp 1'b0;
2334
  else
2335 150 mohor
  if(RxAbortSyncb2)
2336
    RxAbortLatched <=#Tp 1'b0;
2337
  else
2338 64 mohor
  if(RxAbort)
2339
    RxAbortLatched <=#Tp 1'b1;
2340
end
2341 40 mohor
 
2342 64 mohor
 
2343 42 mohor
always @ (posedge MRxClk or posedge Reset)
2344
begin
2345
  if(Reset)
2346
    LatchedRxLength[15:0] <=#Tp 16'h0;
2347
  else
2348 150 mohor
  if(LoadRxStatus)
2349 42 mohor
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
2350
end
2351
 
2352
 
2353 261 mohor
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
2354 42 mohor
 
2355
always @ (posedge MRxClk or posedge Reset)
2356
begin
2357
  if(Reset)
2358
    RxStatusInLatched <=#Tp 'h0;
2359
  else
2360 150 mohor
  if(LoadRxStatus)
2361 42 mohor
    RxStatusInLatched <=#Tp RxStatusIn;
2362
end
2363
 
2364
 
2365 60 mohor
// Rx overrun
2366
always @ (posedge WB_CLK_I or posedge Reset)
2367
begin
2368
  if(Reset)
2369
    RxOverrun <=#Tp 1'b0;
2370
  else
2371
  if(RxStatusWrite)
2372
    RxOverrun <=#Tp 1'b0;
2373
  else
2374
  if(RxBufferFull & WriteRxDataToFifo_wb)
2375
    RxOverrun <=#Tp 1'b1;
2376
end
2377 48 mohor
 
2378 77 mohor
 
2379
 
2380
wire TxError;
2381
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2382
 
2383
wire RxError;
2384
 
2385 239 tadejm
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
2386 250 mohor
// are aborted when signal r_RecSmall is set to 0 in MODER register. 
2387
// AddressMiss is identifying that a frame was received because of the promiscous
2388
// mode and is not an error
2389 239 tadejm
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
2390
 
2391 77 mohor
// Tx Done Interrupt
2392
always @ (posedge WB_CLK_I or posedge Reset)
2393
begin
2394
  if(Reset)
2395
    TxB_IRQ <=#Tp 1'b0;
2396
  else
2397
  if(TxStatusWrite & TxIRQEn)
2398
    TxB_IRQ <=#Tp ~TxError;
2399
  else
2400
    TxB_IRQ <=#Tp 1'b0;
2401
end
2402
 
2403
 
2404
// Tx Error Interrupt
2405
always @ (posedge WB_CLK_I or posedge Reset)
2406
begin
2407
  if(Reset)
2408
    TxE_IRQ <=#Tp 1'b0;
2409
  else
2410
  if(TxStatusWrite & TxIRQEn)
2411
    TxE_IRQ <=#Tp TxError;
2412
  else
2413
    TxE_IRQ <=#Tp 1'b0;
2414
end
2415
 
2416
 
2417
// Rx Done Interrupt
2418
always @ (posedge WB_CLK_I or posedge Reset)
2419
begin
2420
  if(Reset)
2421
    RxB_IRQ <=#Tp 1'b0;
2422
  else
2423
  if(RxStatusWrite & RxIRQEn)
2424 261 mohor
    RxB_IRQ <=#Tp ReceivedPacketGood & (~RxError) & (~r_RxFlow); // When r_RxFlow is set, RXC irq is set.
2425 77 mohor
  else
2426
    RxB_IRQ <=#Tp 1'b0;
2427
end
2428
 
2429
 
2430
// Rx Error Interrupt
2431
always @ (posedge WB_CLK_I or posedge Reset)
2432
begin
2433
  if(Reset)
2434
    RxE_IRQ <=#Tp 1'b0;
2435
  else
2436
  if(RxStatusWrite & RxIRQEn)
2437
    RxE_IRQ <=#Tp RxError;
2438
  else
2439
    RxE_IRQ <=#Tp 1'b0;
2440
end
2441
 
2442
 
2443 166 mohor
// Busy Interrupt
2444 77 mohor
 
2445 166 mohor
reg Busy_IRQ_rck;
2446
reg Busy_IRQ_sync1;
2447
reg Busy_IRQ_sync2;
2448
reg Busy_IRQ_sync3;
2449
reg Busy_IRQ_syncb1;
2450
reg Busy_IRQ_syncb2;
2451 77 mohor
 
2452
 
2453 166 mohor
always @ (posedge MRxClk or posedge Reset)
2454
begin
2455
  if(Reset)
2456
    Busy_IRQ_rck <=#Tp 1'b0;
2457
  else
2458
  if(RxValid & RxStartFrm & ~RxReady)
2459
    Busy_IRQ_rck <=#Tp 1'b1;
2460
  else
2461
  if(Busy_IRQ_syncb2)
2462
    Busy_IRQ_rck <=#Tp 1'b0;
2463
end
2464 77 mohor
 
2465 166 mohor
always @ (posedge WB_CLK_I)
2466
begin
2467
    Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
2468
    Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
2469
    Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
2470
end
2471
 
2472
always @ (posedge MRxClk)
2473
begin
2474
    Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
2475
    Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
2476
end
2477
 
2478
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
2479
 
2480
 
2481 60 mohor
 
2482
// TX
2483 61 mohor
// bit 15 ready
2484
// bit 14 interrupt
2485
// bit 13 wrap
2486
// bit 12 pad
2487
// bit 11 crc
2488
// bit 10 last
2489
// bit 9  pause request (control frame)
2490
// bit 8  TxUnderRun          
2491
// bit 7-4 RetryCntLatched    
2492
// bit 3  retransmittion limit
2493
// bit 2  LateCollLatched        
2494
// bit 1  DeferLatched        
2495
// bit 0  CarrierSenseLost    
2496 60 mohor
 
2497
 
2498
// RX
2499
// bit 15 od rx je empty
2500 61 mohor
// bit 14 od rx je interrupt
2501 60 mohor
// bit 13 od rx je wrap
2502
// bit 12 od rx je reserved
2503
// bit 11 od rx je reserved
2504
// bit 10 od rx je reserved
2505
// bit 9  od rx je reserved
2506
// bit 8  od rx je reserved
2507 110 mohor
// bit 7  od rx je Miss
2508 60 mohor
// bit 6  od rx je RxOverrun
2509
// bit 5  od rx je InvalidSymbol
2510
// bit 4  od rx je DribbleNibble
2511
// bit 3  od rx je ReceivedPacketTooBig
2512
// bit 2  od rx je ShortFrame
2513
// bit 1  od rx je LatchedCrcError
2514
// bit 0  od rx je RxLateCollision
2515
 
2516 110 mohor
 
2517 38 mohor
endmodule
2518
 

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.