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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 304

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1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 166 mohor
////  All additional information is available in the Readme.txt   ////
12 38 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 304 tadejm
// Revision 1.53  2003/10/17 07:46:17  markom
45
// mbist signals updated according to newest convention
46
//
47 302 markom
// Revision 1.52  2003/01/30 14:51:31  mohor
48
// Reset has priority in some flipflops.
49
//
50 280 mohor
// Revision 1.51  2003/01/30 13:36:22  mohor
51
// A new bug (entered with previous update) fixed. When abort occured sometimes
52
// data transmission was blocked.
53
//
54 278 mohor
// Revision 1.50  2003/01/22 13:49:26  tadejm
55
// When control packets were received, they were ignored in some cases.
56
//
57 272 tadejm
// Revision 1.49  2003/01/21 12:09:40  mohor
58
// When receiving normal data frame and RxFlow control was switched on, RXB
59
// interrupt was not set.
60
//
61 270 mohor
// Revision 1.48  2003/01/20 12:05:26  mohor
62
// When in full duplex, transmit was sometimes blocked. Fixed.
63
//
64 269 mohor
// Revision 1.47  2002/11/22 13:26:21  mohor
65
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
66
// anywhere. Removed.
67
//
68 264 mohor
// Revision 1.46  2002/11/22 01:57:06  mohor
69
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
70
// synchronized.
71
//
72 261 mohor
// Revision 1.45  2002/11/19 17:33:34  mohor
73
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
74
// that a frame was received because of the promiscous mode.
75
//
76 250 mohor
// Revision 1.44  2002/11/13 22:21:40  tadejm
77
// RxError is not generated when small frame reception is enabled and small
78
// frames are received.
79
//
80 239 tadejm
// Revision 1.43  2002/10/18 20:53:34  mohor
81
// case changed to casex.
82
//
83 229 mohor
// Revision 1.42  2002/10/18 17:04:20  tadejm
84
// Changed BIST scan signals.
85
//
86 227 tadejm
// Revision 1.41  2002/10/18 15:42:09  tadejm
87
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
88
//
89 226 tadejm
// Revision 1.40  2002/10/14 16:07:02  mohor
90
// TxStatus is written after last access to the TX fifo is finished (in case of abort
91
// or retry). TxDone is fixed.
92
//
93 221 mohor
// Revision 1.39  2002/10/11 15:35:20  mohor
94
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
95
// TxDone and TxRetry are generated after the current WISHBONE access is
96
// finished.
97
//
98 219 mohor
// Revision 1.38  2002/10/10 16:29:30  mohor
99
// BIST added.
100
//
101 210 mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
102
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
103
//
104 167 mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
105
// Reception is possible after RxPointer is read and not after BD is read. For
106
// that reason RxBDReady is changed to RxReady.
107
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
108
// comes, interrupt is generated.
109
//
110 166 mohor
// Revision 1.35  2002/09/10 10:35:23  mohor
111
// Ethernet debug registers removed.
112
//
113 164 mohor
// Revision 1.34  2002/09/08 16:31:49  mohor
114
// Async reset for WB_ACK_O removed (when core was in reset, it was
115
// impossible to access BDs).
116
// RxPointers and TxPointers names changed to be more descriptive.
117
// TxUnderRun synchronized.
118
//
119 159 mohor
// Revision 1.33  2002/09/04 18:47:57  mohor
120
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
121
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
122
// was not used OK.
123
//
124 150 mohor
// Revision 1.32  2002/08/14 19:31:48  mohor
125
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
126
// need to multiply or devide any more.
127
//
128 134 mohor
// Revision 1.31  2002/07/25 18:29:01  mohor
129
// WriteRxDataToMemory signal changed so end of frame (when last word is
130
// written to fifo) is changed.
131
//
132 127 mohor
// Revision 1.30  2002/07/23 15:28:31  mohor
133
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
134
//
135 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
136
// ShiftEnded synchronization changed.
137
//
138 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
139
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
140
//
141 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
142
// RxPointer bug fixed.
143
//
144 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
145
// Previous bug wasn't succesfully removed. Now fixed.
146
//
147 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
148
// Master state machine had a bug when switching from master write to
149
// master read.
150
//
151 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
152
// m_wb_cyc_o signal released after every single transfer.
153
//
154 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
155
// Outputs registered. Reset changed for eth_wishbone module.
156
//
157 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
158
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
159
// bug fixed.
160
//
161 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
162
// Small typo fixed.
163
//
164 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
165
// Any address can be used for Tx and Rx BD pointers. Address does not need
166
// to be aligned.
167
//
168 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
169
// Comments in Slovene language removed.
170
//
171 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
172
// casex changed with case, fifo reset changed.
173
//
174 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
175
// rx_fifo was not always cleared ok. Fixed.
176
//
177 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
178
// Status was not latched correctly sometimes. Fixed.
179
//
180 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
181
// Big Endian problem when sending frames fixed.
182
//
183 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
184
// Byte ordering changed (Big Endian used). casex changed with case because
185
// Xilinx Foundation had problems. Tested in HW. It WORKS.
186
//
187 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
188
// Small fixes for external/internal DMA missmatches.
189
//
190 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
191
// Interrupts changed
192
//
193 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
194
// Status was not written correctly when frames were discarted because of
195
// address mismatch.
196
//
197 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
198
// RxStartFrm cleared when abort or retry comes.
199
//
200 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
201
// Changes that were lost when updating from 1.5 to 1.8 fixed.
202
//
203 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
204
// Addition  of new module eth_addrcheck.v
205
//
206
// Revision 1.7  2002/02/12 17:03:47  mohor
207
// RxOverRun added to statuses.
208
//
209
// Revision 1.6  2002/02/11 09:18:22  mohor
210
// Tx status is written back to the BD.
211
//
212 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
213
// Rx status is written back to the BD.
214
//
215 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
216
// non-DMA host interface added. Select the right configutation in eth_defines.
217
//
218 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
219
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
220
// MHz. Statuses, overrun, control frame transmission and reception still  need
221
// to be fixed.
222
//
223 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
224
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
225
// added.
226
//
227 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
228
// Initial version. Equals to eth_wishbonedma.v at this moment.
229 38 mohor
//
230
//
231
//
232
 
233
`include "eth_defines.v"
234
`include "timescale.v"
235
 
236
 
237
module eth_wishbone
238
   (
239
 
240
    // WISHBONE common
241 40 mohor
    WB_CLK_I, WB_DAT_I, WB_DAT_O,
242 38 mohor
 
243
    // WISHBONE slave
244 77 mohor
                WB_ADR_I, WB_WE_I, WB_ACK_O,
245 40 mohor
    BDCs,
246 38 mohor
 
247 40 mohor
    Reset,
248
 
249 39 mohor
    // WISHBONE master
250
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
251
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
252
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
253
 
254 219 mohor
`ifdef ETH_WISHBONE_B3
255
    m_wb_cti_o, m_wb_bte_o,
256
`endif
257
 
258 38 mohor
    //TX
259 60 mohor
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
260 150 mohor
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
261 38 mohor
    PerPacketPad,
262
 
263
    //RX
264 272 tadejm
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
265 38 mohor
 
266
    // Register
267 270 mohor
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RxFlow, r_PassAll,
268 38 mohor
 
269
    // Interrupts
270 150 mohor
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
271 42 mohor
 
272 60 mohor
    // Rx Status
273 42 mohor
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
274 250 mohor
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
275 261 mohor
    ReceivedPauseFrm,
276 60 mohor
 
277
    // Tx Status
278 164 mohor
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
279
 
280 210 mohor
    // Bist
281
`ifdef ETH_BIST
282 227 tadejm
    ,
283
    // debug chain signals
284 302 markom
    mbist_si_i,       // bist scan serial in
285
    mbist_so_o,       // bist scan serial out
286
    mbist_ctrl_i        // bist chain shift control
287 210 mohor
`endif
288
 
289
 
290
 
291 38 mohor
                );
292
 
293
 
294
parameter Tp = 1;
295
 
296 150 mohor
 
297 38 mohor
// WISHBONE common
298
input           WB_CLK_I;       // WISHBONE clock
299
input  [31:0]   WB_DAT_I;       // WISHBONE data input
300
output [31:0]   WB_DAT_O;       // WISHBONE data output
301
 
302
// WISHBONE slave
303
input   [9:2]   WB_ADR_I;       // WISHBONE address input
304
input           WB_WE_I;        // WISHBONE write enable input
305 304 tadejm
input   [3:0]   BDCs;           // Buffer descriptors are selected
306 38 mohor
output          WB_ACK_O;       // WISHBONE acknowledge output
307
 
308 39 mohor
// WISHBONE master
309
output  [31:0]  m_wb_adr_o;     // 
310
output   [3:0]  m_wb_sel_o;     // 
311
output          m_wb_we_o;      // 
312
output  [31:0]  m_wb_dat_o;     // 
313
output          m_wb_cyc_o;     // 
314
output          m_wb_stb_o;     // 
315
input   [31:0]  m_wb_dat_i;     // 
316
input           m_wb_ack_i;     // 
317
input           m_wb_err_i;     // 
318
 
319 219 mohor
`ifdef ETH_WISHBONE_B3
320
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
321
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
322
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
323
`endif
324
 
325 40 mohor
input           Reset;       // Reset signal
326 39 mohor
 
327 60 mohor
// Rx Status signals
328 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
329
input           LatchedCrcError;  // CRC error
330
input           RxLateCollision;  // Late collision occured while receiving frame
331
input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
332
input           DribbleNibble;    // Extra nibble received
333
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
334
input    [15:0] RxLength;         // Length of the incoming frame
335
input           LoadRxStatus;     // Rx status was loaded
336 77 mohor
input           ReceivedPacketGood;// Received packet's length and CRC are good
337 250 mohor
input           AddressMiss;      // When a packet is received AddressMiss status is written to the Rx BD
338 261 mohor
input           r_RxFlow;
339 270 mohor
input           r_PassAll;
340 261 mohor
input           ReceivedPauseFrm;
341 39 mohor
 
342 60 mohor
// Tx Status signals
343
input     [3:0] RetryCntLatched;  // Latched Retry Counter
344
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
345
input           LateCollLatched;  // Late collision occured
346
input           DeferLatched;     // Defer indication (Frame was defered before sucessfully sent)
347
input           CarrierSenseLost; // Carrier Sense was lost during the frame transmission
348
 
349 38 mohor
// Tx
350
input           MTxClk;         // Transmit clock (from PHY)
351
input           TxUsedData;     // Transmit packet used data
352
input           TxRetry;        // Transmit packet retry
353
input           TxAbort;        // Transmit packet abort
354
input           TxDone;         // Transmission ended
355
output          TxStartFrm;     // Transmit packet start frame
356
output          TxEndFrm;       // Transmit packet end frame
357
output  [7:0]   TxData;         // Transmit packet data byte
358
output          TxUnderRun;     // Transmit packet under-run
359
output          PerPacketCrcEn; // Per packet crc enable
360
output          PerPacketPad;   // Per packet pading
361
 
362
// Rx
363
input           MRxClk;         // Receive clock (from PHY)
364
input   [7:0]   RxData;         // Received data byte (from PHY)
365
input           RxValid;        // 
366
input           RxStartFrm;     // 
367
input           RxEndFrm;       // 
368 40 mohor
input           RxAbort;        // This signal is set when address doesn't match.
369 272 tadejm
output          RxStatusWriteLatched_sync2;
370 38 mohor
 
371
//Register
372
input           r_TxEn;         // Transmit enable
373
input           r_RxEn;         // Receive enable
374
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
375
input           TX_BD_NUM_Wr;   // RxBDNumber written
376
 
377
// Interrupts
378
output TxB_IRQ;
379
output TxE_IRQ;
380
output RxB_IRQ;
381 77 mohor
output RxE_IRQ;
382 38 mohor
output Busy_IRQ;
383
 
384 77 mohor
 
385 210 mohor
// Bist
386
`ifdef ETH_BIST
387 302 markom
input   mbist_si_i;       // bist scan serial in
388
output  mbist_so_o;       // bist scan serial out
389
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
390 210 mohor
`endif
391
 
392 77 mohor
reg TxB_IRQ;
393
reg TxE_IRQ;
394
reg RxB_IRQ;
395
reg RxE_IRQ;
396
 
397 38 mohor
reg             TxStartFrm;
398
reg             TxEndFrm;
399
reg     [7:0]   TxData;
400
 
401
reg             TxUnderRun;
402 60 mohor
reg             TxUnderRun_wb;
403 38 mohor
 
404
reg             TxBDRead;
405 39 mohor
wire            TxStatusWrite;
406 38 mohor
 
407
reg     [1:0]   TxValidBytesLatched;
408
 
409
reg    [15:0]   TxLength;
410 60 mohor
reg    [15:0]   LatchedTxLength;
411
reg   [14:11]   TxStatus;
412 38 mohor
 
413 60 mohor
reg   [14:13]   RxStatus;
414 38 mohor
 
415
reg             TxStartFrm_wb;
416
reg             TxRetry_wb;
417 39 mohor
reg             TxAbort_wb;
418 38 mohor
reg             TxDone_wb;
419
 
420
reg             TxDone_wb_q;
421
reg             TxAbort_wb_q;
422 39 mohor
reg             TxRetry_wb_q;
423 219 mohor
reg             TxRetryPacket;
424 221 mohor
reg             TxRetryPacket_NotCleared;
425
reg             TxDonePacket;
426
reg             TxDonePacket_NotCleared;
427 219 mohor
reg             TxAbortPacket;
428 221 mohor
reg             TxAbortPacket_NotCleared;
429 38 mohor
reg             RxBDReady;
430 166 mohor
reg             RxReady;
431 38 mohor
reg             TxBDReady;
432
 
433
reg             RxBDRead;
434
 
435
reg    [31:0]   TxDataLatched;
436
reg     [1:0]   TxByteCnt;
437
reg             LastWord;
438 39 mohor
reg             ReadTxDataFromFifo_tck;
439 38 mohor
 
440
reg             BlockingTxStatusWrite;
441
reg             BlockingTxBDRead;
442
 
443 40 mohor
reg             Flop;
444 38 mohor
 
445
reg     [7:0]   TxBDAddress;
446
reg     [7:0]   RxBDAddress;
447
 
448
reg             TxRetrySync1;
449
reg             TxAbortSync1;
450 39 mohor
reg             TxDoneSync1;
451 38 mohor
 
452
reg             TxAbort_q;
453
reg             TxRetry_q;
454
reg             TxUsedData_q;
455
 
456
reg    [31:0]   RxDataLatched2;
457 82 mohor
 
458
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
459
 
460 38 mohor
reg     [1:0]   RxValidBytes;
461
reg     [1:0]   RxByteCnt;
462
reg             LastByteIn;
463
reg             ShiftWillEnd;
464
 
465 40 mohor
reg             WriteRxDataToFifo;
466 42 mohor
reg    [15:0]   LatchedRxLength;
467 64 mohor
reg             RxAbortLatched;
468 38 mohor
 
469 40 mohor
reg             ShiftEnded;
470 60 mohor
reg             RxOverrun;
471 38 mohor
 
472 304 tadejm
reg     [3:0]   BDWrite;                    // BD Write Enable for access from WISHBONE side
473 40 mohor
reg             BDRead;                     // BD Read access from WISHBONE side
474 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
475
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
476 38 mohor
 
477 39 mohor
reg             TxEndFrm_wb;
478 38 mohor
 
479 39 mohor
wire            TxRetryPulse;
480 38 mohor
wire            TxDonePulse;
481
wire            TxAbortPulse;
482
 
483
wire            StartRxBDRead;
484
 
485
wire            StartTxBDRead;
486
 
487
wire            TxIRQEn;
488
wire            WrapTxStatusBit;
489
 
490 77 mohor
wire            RxIRQEn;
491 38 mohor
wire            WrapRxStatusBit;
492
 
493
wire    [1:0]   TxValidBytes;
494
 
495
wire    [7:0]   TempTxBDAddress;
496
wire    [7:0]   TempRxBDAddress;
497
 
498 272 tadejm
wire            RxStatusWrite;
499
 
500 106 mohor
reg             WB_ACK_O;
501 38 mohor
 
502 261 mohor
wire    [8:0]   RxStatusIn;
503
reg     [8:0]   RxStatusInLatched;
504 42 mohor
 
505 39 mohor
reg WbEn, WbEn_q;
506
reg RxEn, RxEn_q;
507
reg TxEn, TxEn_q;
508 38 mohor
 
509 39 mohor
wire ram_ce;
510 304 tadejm
wire [3:0]  ram_we;
511 39 mohor
wire ram_oe;
512
reg [7:0]   ram_addr;
513
reg [31:0]  ram_di;
514
wire [31:0] ram_do;
515 38 mohor
 
516 39 mohor
wire StartTxPointerRead;
517
reg  TxPointerRead;
518
reg TxEn_needed;
519 40 mohor
reg RxEn_needed;
520 38 mohor
 
521 40 mohor
wire StartRxPointerRead;
522
reg RxPointerRead;
523 38 mohor
 
524 219 mohor
`ifdef ETH_WISHBONE_B3
525
assign m_wb_bte_o = 2'b00;    // Linear burst
526
`endif
527 39 mohor
 
528 219 mohor
 
529 159 mohor
always @ (posedge WB_CLK_I)
530 40 mohor
begin
531 304 tadejm
  WB_ACK_O <=#Tp (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
532 40 mohor
end
533 39 mohor
 
534 106 mohor
assign WB_DAT_O = ram_do;
535 39 mohor
 
536 41 mohor
// Generic synchronous single-port RAM interface
537 119 mohor
eth_spram_256x32 bd_ram (
538 226 tadejm
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
539 210 mohor
`ifdef ETH_BIST
540 227 tadejm
  ,
541 302 markom
  .mbist_si_i       (mbist_si_i),
542
  .mbist_so_o       (mbist_so_o),
543
  .mbist_ctrl_i       (mbist_ctrl_i)
544 210 mohor
`endif
545 39 mohor
);
546 41 mohor
 
547 39 mohor
assign ram_ce = 1'b1;
548 304 tadejm
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) | {4{(TxStatusWrite | RxStatusWrite)}};
549 61 mohor
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
550 39 mohor
 
551
 
552 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
553 38 mohor
begin
554 40 mohor
  if(Reset)
555 39 mohor
    TxEn_needed <=#Tp 1'b0;
556 38 mohor
  else
557 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
558 39 mohor
    TxEn_needed <=#Tp 1'b1;
559
  else
560
  if(TxPointerRead & TxEn & TxEn_q)
561
    TxEn_needed <=#Tp 1'b0;
562 38 mohor
end
563
 
564 39 mohor
// Enabling access to the RAM for three devices.
565 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
566 39 mohor
begin
567 40 mohor
  if(Reset)
568 39 mohor
    begin
569
      WbEn <=#Tp 1'b1;
570
      RxEn <=#Tp 1'b0;
571
      TxEn <=#Tp 1'b0;
572
      ram_addr <=#Tp 8'h0;
573
      ram_di <=#Tp 32'h0;
574 77 mohor
      BDRead <=#Tp 1'b0;
575
      BDWrite <=#Tp 1'b0;
576 39 mohor
    end
577
  else
578
    begin
579
      // Switching between three stages depends on enable signals
580 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
581
        5'b100_10, 5'b100_11 :
582 39 mohor
          begin
583
            WbEn <=#Tp 1'b0;
584
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
585
            TxEn <=#Tp 1'b0;
586 40 mohor
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
587 39 mohor
            ram_di <=#Tp RxBDDataIn;
588
          end
589
        5'b100_01 :
590
          begin
591
            WbEn <=#Tp 1'b0;
592
            RxEn <=#Tp 1'b0;
593
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
594
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
595
            ram_di <=#Tp TxBDDataIn;
596
          end
597 90 mohor
        5'b010_00, 5'b010_10 :
598 39 mohor
          begin
599
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
600
            RxEn <=#Tp 1'b0;
601
            TxEn <=#Tp 1'b0;
602
            ram_addr <=#Tp WB_ADR_I[9:2];
603
            ram_di <=#Tp WB_DAT_I;
604 304 tadejm
            BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
605
            BDRead <=#Tp (|BDCs) & ~WB_WE_I;
606 39 mohor
          end
607 90 mohor
        5'b010_01, 5'b010_11 :
608 39 mohor
          begin
609
            WbEn <=#Tp 1'b0;
610
            RxEn <=#Tp 1'b0;
611
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
612
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
613
            ram_di <=#Tp TxBDDataIn;
614
          end
615 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
616 39 mohor
          begin
617
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
618
            RxEn <=#Tp 1'b0;
619
            TxEn <=#Tp 1'b0;
620
            ram_addr <=#Tp WB_ADR_I[9:2];
621
            ram_di <=#Tp WB_DAT_I;
622 304 tadejm
            BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
623
            BDRead <=#Tp (|BDCs) & ~WB_WE_I;
624 39 mohor
          end
625
        5'b100_00 :
626
          begin
627
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
628
          end
629
        5'b000_00 :
630
          begin
631
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
632
            RxEn <=#Tp 1'b0;
633
            TxEn <=#Tp 1'b0;
634
            ram_addr <=#Tp WB_ADR_I[9:2];
635
            ram_di <=#Tp WB_DAT_I;
636 304 tadejm
            BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
637
            BDRead <=#Tp (|BDCs) & ~WB_WE_I;
638 39 mohor
          end
639
      endcase
640
    end
641
end
642
 
643
 
644
// Delayed stage signals
645 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
646 39 mohor
begin
647 40 mohor
  if(Reset)
648 39 mohor
    begin
649
      WbEn_q <=#Tp 1'b0;
650
      RxEn_q <=#Tp 1'b0;
651
      TxEn_q <=#Tp 1'b0;
652
    end
653
  else
654
    begin
655
      WbEn_q <=#Tp WbEn;
656
      RxEn_q <=#Tp RxEn;
657
      TxEn_q <=#Tp TxEn;
658
    end
659
end
660
 
661 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
662 40 mohor
always @ (posedge MTxClk or posedge Reset)
663 38 mohor
begin
664 40 mohor
  if(Reset)
665 38 mohor
    Flop <=#Tp 1'b0;
666
  else
667
  if(TxDone | TxAbort | TxRetry_q)
668
    Flop <=#Tp 1'b0;
669
  else
670
  if(TxUsedData)
671
    Flop <=#Tp ~Flop;
672
end
673
 
674 39 mohor
wire ResetTxBDReady;
675
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
676 38 mohor
 
677
// Latching READY status of the Tx buffer descriptor
678 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
679 38 mohor
begin
680 40 mohor
  if(Reset)
681 38 mohor
    TxBDReady <=#Tp 1'b0;
682
  else
683 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
684
    TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
685
  else                                                // Only packets larger then 4 bytes are transmitted.
686 39 mohor
  if(ResetTxBDReady)
687 38 mohor
    TxBDReady <=#Tp 1'b0;
688
end
689
 
690
 
691 39 mohor
// Reading the Tx buffer descriptor
692 221 mohor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
693 39 mohor
 
694 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
695 38 mohor
begin
696 40 mohor
  if(Reset)
697 39 mohor
    TxBDRead <=#Tp 1'b1;
698 38 mohor
  else
699 110 mohor
  if(StartTxBDRead)
700 39 mohor
    TxBDRead <=#Tp 1'b1;
701 38 mohor
  else
702 39 mohor
  if(TxBDReady)
703
    TxBDRead <=#Tp 1'b0;
704 38 mohor
end
705
 
706
 
707 39 mohor
// Reading Tx BD pointer
708
assign StartTxPointerRead = TxBDRead & TxBDReady;
709 38 mohor
 
710 39 mohor
// Reading Tx BD Pointer
711 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
712 38 mohor
begin
713 40 mohor
  if(Reset)
714 39 mohor
    TxPointerRead <=#Tp 1'b0;
715 38 mohor
  else
716 39 mohor
  if(StartTxPointerRead)
717
    TxPointerRead <=#Tp 1'b1;
718 38 mohor
  else
719 39 mohor
  if(TxEn_q)
720
    TxPointerRead <=#Tp 1'b0;
721 38 mohor
end
722
 
723
 
724 39 mohor
// Writing status back to the Tx buffer descriptor
725 221 mohor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
726 38 mohor
 
727
 
728
 
729 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
730 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
731 38 mohor
begin
732 40 mohor
  if(Reset)
733 39 mohor
    BlockingTxStatusWrite <=#Tp 1'b0;
734 38 mohor
  else
735 272 tadejm
  if(~TxDone_wb & ~TxAbort_wb)
736
    BlockingTxStatusWrite <=#Tp 1'b0;
737
  else
738 39 mohor
  if(TxStatusWrite)
739
    BlockingTxStatusWrite <=#Tp 1'b1;
740 38 mohor
end
741
 
742
 
743 159 mohor
reg BlockingTxStatusWrite_sync1;
744
reg BlockingTxStatusWrite_sync2;
745
 
746
// Synchronizing BlockingTxStatusWrite to MTxClk
747
always @ (posedge MTxClk or posedge Reset)
748
begin
749
  if(Reset)
750
    BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
751
  else
752
    BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
753
end
754
 
755
// Synchronizing BlockingTxStatusWrite to MTxClk
756
always @ (posedge MTxClk or posedge Reset)
757
begin
758
  if(Reset)
759
    BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
760
  else
761
    BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
762
end
763
 
764
 
765 39 mohor
// TxBDRead state is activated only once. 
766 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
767 39 mohor
begin
768 40 mohor
  if(Reset)
769 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
770
  else
771 110 mohor
  if(StartTxBDRead)
772 39 mohor
    BlockingTxBDRead <=#Tp 1'b1;
773
  else
774 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
775 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
776
end
777 38 mohor
 
778
 
779 39 mohor
// Latching status from the tx buffer descriptor
780
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
781 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
782 38 mohor
begin
783 40 mohor
  if(Reset)
784 60 mohor
    TxStatus <=#Tp 4'h0;
785 38 mohor
  else
786 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
787 60 mohor
    TxStatus <=#Tp ram_do[14:11];
788 38 mohor
end
789
 
790 40 mohor
reg ReadTxDataFromMemory;
791
wire WriteRxDataToMemory;
792 38 mohor
 
793 39 mohor
reg MasterWbTX;
794
reg MasterWbRX;
795
 
796
reg [31:0] m_wb_adr_o;
797
reg        m_wb_cyc_o;
798
reg        m_wb_stb_o;
799 96 mohor
reg  [3:0] m_wb_sel_o;
800 39 mohor
reg        m_wb_we_o;
801 40 mohor
 
802 39 mohor
wire TxLengthEq0;
803
wire TxLengthLt4;
804
 
805 150 mohor
reg BlockingIncrementTxPointer;
806 159 mohor
reg [31:2] TxPointerMSB;
807
reg [1:0]  TxPointerLSB;
808
reg [1:0]  TxPointerLSB_rst;
809
reg [31:2] RxPointerMSB;
810
reg [1:0]  RxPointerLSB_rst;
811 39 mohor
 
812 150 mohor
wire RxBurstAcc;
813
wire RxWordAcc;
814
wire RxHalfAcc;
815
wire RxByteAcc;
816
 
817 39 mohor
//Latching length from the buffer descriptor;
818 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
819 38 mohor
begin
820 40 mohor
  if(Reset)
821 39 mohor
    TxLength <=#Tp 16'h0;
822 38 mohor
  else
823 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
824
    TxLength <=#Tp ram_do[31:16];
825 38 mohor
  else
826 39 mohor
  if(MasterWbTX & m_wb_ack_i)
827
    begin
828
      if(TxLengthLt4)
829
        TxLength <=#Tp 16'h0;
830 150 mohor
      else
831 159 mohor
      if(TxPointerLSB_rst==2'h0)
832 96 mohor
        TxLength <=#Tp TxLength - 3'h4;    // Length is subtracted at the data request
833 39 mohor
      else
834 159 mohor
      if(TxPointerLSB_rst==2'h1)
835 150 mohor
        TxLength <=#Tp TxLength - 3'h3;    // Length is subtracted at the data request
836
      else
837 159 mohor
      if(TxPointerLSB_rst==2'h2)
838 150 mohor
        TxLength <=#Tp TxLength - 3'h2;    // Length is subtracted at the data request
839
      else
840 159 mohor
      if(TxPointerLSB_rst==2'h3)
841 150 mohor
        TxLength <=#Tp TxLength - 3'h1;    // Length is subtracted at the data request
842 39 mohor
    end
843 38 mohor
end
844
 
845 96 mohor
 
846
 
847 60 mohor
//Latching length from the buffer descriptor;
848
always @ (posedge WB_CLK_I or posedge Reset)
849
begin
850
  if(Reset)
851
    LatchedTxLength <=#Tp 16'h0;
852
  else
853
  if(TxEn & TxEn_q & TxBDRead)
854
    LatchedTxLength <=#Tp ram_do[31:16];
855
end
856
 
857 39 mohor
assign TxLengthEq0 = TxLength == 0;
858
assign TxLengthLt4 = TxLength < 4;
859 38 mohor
 
860 150 mohor
reg cyc_cleared;
861
reg IncrTxPointer;
862 39 mohor
 
863
 
864 159 mohor
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
865
// because TxPointerMSB is only used for word-aligned accesses.
866 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
867 38 mohor
begin
868 40 mohor
  if(Reset)
869 159 mohor
    TxPointerMSB <=#Tp 30'h0;
870 38 mohor
  else
871 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
872 159 mohor
    TxPointerMSB <=#Tp ram_do[31:2];
873 38 mohor
  else
874 150 mohor
  if(IncrTxPointer & ~BlockingIncrementTxPointer)
875 159 mohor
    TxPointerMSB <=#Tp TxPointerMSB + 1'b1;     // TxPointer is word-aligned
876 38 mohor
end
877
 
878 96 mohor
 
879 159 mohor
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
880
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
881
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
882
// set by this two bits.
883 96 mohor
always @ (posedge WB_CLK_I or posedge Reset)
884
begin
885
  if(Reset)
886 159 mohor
    TxPointerLSB[1:0] <=#Tp 0;
887 96 mohor
  else
888
  if(TxEn & TxEn_q & TxPointerRead)
889 159 mohor
    TxPointerLSB[1:0] <=#Tp ram_do[1:0];
890 96 mohor
end
891
 
892
 
893 159 mohor
// Latching 2 MSB bits of the buffer descriptor. 
894
// After the read access, TxLength needs to be decremented for the number of the valid
895
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are 
896
// valid so this two bits are reset to zero. 
897 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
898
begin
899
  if(Reset)
900 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
901 150 mohor
  else
902
  if(TxEn & TxEn_q & TxPointerRead)
903 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
904 150 mohor
  else
905
  if(MasterWbTX & m_wb_ack_i)                 // After first access pointer is word alligned
906 159 mohor
    TxPointerLSB_rst[1:0] <=#Tp 0;
907 150 mohor
end
908 96 mohor
 
909 150 mohor
 
910 159 mohor
reg  [3:0] RxByteSel;
911 39 mohor
wire MasterAccessFinished;
912 38 mohor
 
913 39 mohor
 
914 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
915 38 mohor
begin
916 40 mohor
  if(Reset)
917 39 mohor
    BlockingIncrementTxPointer <=#Tp 0;
918 38 mohor
  else
919 39 mohor
  if(MasterAccessFinished)
920
    BlockingIncrementTxPointer <=#Tp 0;
921 38 mohor
  else
922 150 mohor
  if(IncrTxPointer)
923 39 mohor
    BlockingIncrementTxPointer <=#Tp 1'b1;
924 38 mohor
end
925
 
926
 
927 39 mohor
wire TxBufferAlmostFull;
928
wire TxBufferFull;
929
wire TxBufferEmpty;
930
wire TxBufferAlmostEmpty;
931 40 mohor
wire SetReadTxDataFromMemory;
932 39 mohor
 
933 40 mohor
reg BlockReadTxDataFromMemory;
934 39 mohor
 
935 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
936 39 mohor
 
937 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
938 38 mohor
begin
939 40 mohor
  if(Reset)
940
    ReadTxDataFromMemory <=#Tp 1'b0;
941 38 mohor
  else
942 278 mohor
  if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
943 40 mohor
    ReadTxDataFromMemory <=#Tp 1'b0;
944 39 mohor
  else
945 40 mohor
  if(SetReadTxDataFromMemory)
946
    ReadTxDataFromMemory <=#Tp 1'b1;
947 38 mohor
end
948
 
949 226 tadejm
reg tx_burst_en;
950
reg rx_burst_en;
951 221 mohor
 
952 278 mohor
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory;
953 226 tadejm
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
954 221 mohor
 
955 39 mohor
wire [31:0] TxData_wb;
956
wire ReadTxDataFromFifo_wb;
957 38 mohor
 
958 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
959 38 mohor
begin
960 40 mohor
  if(Reset)
961
    BlockReadTxDataFromMemory <=#Tp 1'b0;
962 38 mohor
  else
963 278 mohor
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared)))
964 40 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b1;
965 219 mohor
  else
966 221 mohor
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
967 219 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b0;
968 39 mohor
end
969
 
970
 
971
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
972 219 mohor
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
973
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
974 226 tadejm
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
975
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
976 159 mohor
 
977 226 tadejm
wire rx_burst;
978
wire enough_data_in_rxfifo_for_burst;
979
wire enough_data_in_rxfifo_for_burst_plus1;
980 229 mohor
 
981 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
982 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
983 39 mohor
begin
984 40 mohor
  if(Reset)
985 38 mohor
    begin
986 39 mohor
      MasterWbTX <=#Tp 1'b0;
987
      MasterWbRX <=#Tp 1'b0;
988
      m_wb_adr_o <=#Tp 32'h0;
989
      m_wb_cyc_o <=#Tp 1'b0;
990
      m_wb_stb_o <=#Tp 1'b0;
991
      m_wb_we_o  <=#Tp 1'b0;
992 96 mohor
      m_wb_sel_o <=#Tp 4'h0;
993 110 mohor
      cyc_cleared<=#Tp 1'b0;
994 226 tadejm
      tx_burst_cnt<=#Tp 0;
995
      rx_burst_cnt<=#Tp 0;
996 150 mohor
      IncrTxPointer<=#Tp 1'b0;
997 226 tadejm
      tx_burst_en<=#Tp 1'b1;
998
      rx_burst_en<=#Tp 1'b0;
999
      `ifdef ETH_WISHBONE_B3
1000
        m_wb_cti_o <=#Tp 3'b0;
1001
      `endif
1002 38 mohor
    end
1003 39 mohor
  else
1004
    begin
1005
      // Switching between two stages depends on enable signals
1006 229 mohor
      casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst})  // synopsys parallel_case
1007 226 tadejm
        8'b00_10_00_10,             // Idle and MRB needed
1008 229 mohor
        8'b10_1x_10_1x,             // MRB continues
1009 226 tadejm
        8'b10_10_01_10,             // Clear (previously MR) and MRB needed
1010 229 mohor
        8'b01_1x_01_1x :            // Clear (previously MW) and MRB needed
1011 39 mohor
          begin
1012 226 tadejm
            MasterWbTX <=#Tp 1'b1;  // tx burst
1013
            MasterWbRX <=#Tp 1'b0;
1014
            m_wb_cyc_o <=#Tp 1'b1;
1015
            m_wb_stb_o <=#Tp 1'b1;
1016
            m_wb_we_o  <=#Tp 1'b0;
1017
            m_wb_sel_o <=#Tp 4'hf;
1018
            cyc_cleared<=#Tp 1'b0;
1019
            IncrTxPointer<=#Tp 1'b1;
1020
            tx_burst_cnt <=#Tp tx_burst_cnt+1;
1021
            if(tx_burst_cnt==0)
1022
              m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1023
            else
1024
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1025
 
1026
            if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
1027
              begin
1028
                tx_burst_en<=#Tp 1'b0;
1029
              `ifdef ETH_WISHBONE_B3
1030
                m_wb_cti_o <=#Tp 3'b111;
1031
              `endif
1032
              end
1033
            else
1034
              begin
1035
              `ifdef ETH_WISHBONE_B3
1036
                m_wb_cti_o <=#Tp 3'b010;
1037
              `endif
1038
              end
1039
          end
1040 229 mohor
        8'b00_x1_00_x1,             // Idle and MWB needed
1041
        8'b01_x1_10_x1,             // MWB continues
1042 226 tadejm
        8'b01_01_01_01,             // Clear (previously MW) and MWB needed
1043 229 mohor
        8'b10_x1_01_x1 :            // Clear (previously MR) and MWB needed
1044 226 tadejm
          begin
1045
            MasterWbTX <=#Tp 1'b0;  // rx burst
1046 39 mohor
            MasterWbRX <=#Tp 1'b1;
1047 226 tadejm
            m_wb_cyc_o <=#Tp 1'b1;
1048
            m_wb_stb_o <=#Tp 1'b1;
1049
            m_wb_we_o  <=#Tp 1'b1;
1050
            m_wb_sel_o <=#Tp RxByteSel;
1051
            IncrTxPointer<=#Tp 1'b0;
1052
            cyc_cleared<=#Tp 1'b0;
1053
            rx_burst_cnt <=#Tp rx_burst_cnt+1;
1054
 
1055
            if(rx_burst_cnt==0)
1056
              m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1057
            else
1058
              m_wb_adr_o <=#Tp m_wb_adr_o+3'h4;
1059
 
1060
            if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
1061
              begin
1062
                rx_burst_en<=#Tp 1'b0;
1063
              `ifdef ETH_WISHBONE_B3
1064
                m_wb_cti_o <=#Tp 3'b111;
1065
              `endif
1066
              end
1067
            else
1068
              begin
1069
              `ifdef ETH_WISHBONE_B3
1070
                m_wb_cti_o <=#Tp 3'b010;
1071
              `endif
1072
              end
1073
          end
1074 229 mohor
        8'b00_x1_00_x0 :            // idle and MW is needed (data write to rx buffer)
1075 226 tadejm
          begin
1076
            MasterWbTX <=#Tp 1'b0;
1077
            MasterWbRX <=#Tp 1'b1;
1078 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1079 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1080
            m_wb_stb_o <=#Tp 1'b1;
1081
            m_wb_we_o  <=#Tp 1'b1;
1082 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1083 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1084 39 mohor
          end
1085 226 tadejm
        8'b00_10_00_00 :            // idle and MR is needed (data read from tx buffer)
1086 39 mohor
          begin
1087 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1088 39 mohor
            MasterWbRX <=#Tp 1'b0;
1089 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1090 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1091
            m_wb_stb_o <=#Tp 1'b1;
1092
            m_wb_we_o  <=#Tp 1'b0;
1093 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1094
            IncrTxPointer<=#Tp 1'b1;
1095 39 mohor
          end
1096 226 tadejm
        8'b10_10_01_00,             // MR and MR is needed (data read from tx buffer)
1097 229 mohor
        8'b01_1x_01_0x  :           // MW and MR is needed (data read from tx buffer)
1098 39 mohor
          begin
1099 226 tadejm
            MasterWbTX <=#Tp 1'b1;
1100 39 mohor
            MasterWbRX <=#Tp 1'b0;
1101 159 mohor
            m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
1102 39 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1103
            m_wb_stb_o <=#Tp 1'b1;
1104
            m_wb_we_o  <=#Tp 1'b0;
1105 150 mohor
            m_wb_sel_o <=#Tp 4'hf;
1106 110 mohor
            cyc_cleared<=#Tp 1'b0;
1107 150 mohor
            IncrTxPointer<=#Tp 1'b1;
1108 39 mohor
          end
1109 226 tadejm
        8'b01_01_01_00,             // MW and MW needed (data write to rx buffer)
1110 229 mohor
        8'b10_x1_01_x0  :           // MR and MW is needed (data write to rx buffer)
1111 39 mohor
          begin
1112 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1113 39 mohor
            MasterWbRX <=#Tp 1'b1;
1114 159 mohor
            m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
1115 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
1116
            m_wb_stb_o <=#Tp 1'b1;
1117 39 mohor
            m_wb_we_o  <=#Tp 1'b1;
1118 159 mohor
            m_wb_sel_o <=#Tp RxByteSel;
1119 110 mohor
            cyc_cleared<=#Tp 1'b0;
1120 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1121 39 mohor
          end
1122 226 tadejm
        8'b01_01_10_00,             // MW and MW needed (cycle is cleared between previous and next access)
1123 229 mohor
        8'b01_1x_10_x0,             // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
1124 226 tadejm
        8'b10_10_10_00,             // MR and MR needed (cycle is cleared between previous and next access)
1125 229 mohor
        8'b10_x1_10_0x :            // MR and MR or MW or MWB (cycle is cleared between previous and next access)
1126 39 mohor
          begin
1127 110 mohor
            m_wb_cyc_o <=#Tp 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
1128
            m_wb_stb_o <=#Tp 1'b0;
1129
            cyc_cleared<=#Tp 1'b1;
1130 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1131 226 tadejm
            tx_burst_cnt<=#Tp 0;
1132
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1133
            rx_burst_cnt<=#Tp 0;
1134
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1135
            `ifdef ETH_WISHBONE_B3
1136
              m_wb_cti_o <=#Tp 3'b0;
1137
            `endif
1138 110 mohor
          end
1139 229 mohor
        8'bxx_00_10_00,             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1140
        8'bxx_00_01_00 :            // Between cyc_cleared request was cleared
1141 110 mohor
          begin
1142 226 tadejm
            MasterWbTX <=#Tp 1'b0;
1143 39 mohor
            MasterWbRX <=#Tp 1'b0;
1144
            m_wb_cyc_o <=#Tp 1'b0;
1145
            m_wb_stb_o <=#Tp 1'b0;
1146 226 tadejm
            cyc_cleared<=#Tp 1'b0;
1147 150 mohor
            IncrTxPointer<=#Tp 1'b0;
1148 226 tadejm
            rx_burst_cnt<=#Tp 0;
1149
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
1150
            `ifdef ETH_WISHBONE_B3
1151
              m_wb_cti_o <=#Tp 3'b0;
1152
            `endif
1153 39 mohor
          end
1154 226 tadejm
        8'b00_00_00_00:             // whatever and no master read or write is needed (ack or err comes finishing previous access)
1155 127 mohor
          begin
1156 226 tadejm
            tx_burst_cnt<=#Tp 0;
1157
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
1158 127 mohor
          end
1159 226 tadejm
        default:                    // Don't touch
1160 82 mohor
          begin
1161
            MasterWbTX <=#Tp MasterWbTX;
1162
            MasterWbRX <=#Tp MasterWbRX;
1163
            m_wb_cyc_o <=#Tp m_wb_cyc_o;
1164
            m_wb_stb_o <=#Tp m_wb_stb_o;
1165 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_o;
1166 150 mohor
            IncrTxPointer<=#Tp IncrTxPointer;
1167 82 mohor
          end
1168 39 mohor
      endcase
1169
    end
1170 38 mohor
end
1171
 
1172 110 mohor
 
1173 39 mohor
wire TxFifoClear;
1174 96 mohor
 
1175 219 mohor
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
1176 38 mohor
 
1177 219 mohor
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
1178 150 mohor
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
1179 96 mohor
          .clk(WB_CLK_I),                                   .reset(Reset),
1180 226 tadejm
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
1181 96 mohor
          .clear(TxFifoClear),                              .full(TxBufferFull),
1182
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
1183 150 mohor
          .empty(TxBufferEmpty),                            .cnt(txfifo_cnt)
1184 96 mohor
        );
1185 39 mohor
 
1186
 
1187
reg StartOccured;
1188
reg TxStartFrm_sync1;
1189
reg TxStartFrm_sync2;
1190
reg TxStartFrm_syncb1;
1191
reg TxStartFrm_syncb2;
1192
 
1193
 
1194
 
1195
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1196 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1197 38 mohor
begin
1198 40 mohor
  if(Reset)
1199 39 mohor
    TxStartFrm_wb <=#Tp 1'b0;
1200 38 mohor
  else
1201 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
1202
    TxStartFrm_wb <=#Tp 1'b1;
1203 38 mohor
  else
1204 39 mohor
  if(TxStartFrm_syncb2)
1205
    TxStartFrm_wb <=#Tp 1'b0;
1206 38 mohor
end
1207
 
1208 39 mohor
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
1209 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1210 38 mohor
begin
1211 40 mohor
  if(Reset)
1212 39 mohor
    StartOccured <=#Tp 1'b0;
1213 38 mohor
  else
1214 39 mohor
  if(TxStartFrm_wb)
1215
    StartOccured <=#Tp 1'b1;
1216 38 mohor
  else
1217 39 mohor
  if(ResetTxBDReady)
1218
    StartOccured <=#Tp 1'b0;
1219 38 mohor
end
1220
 
1221 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1222 40 mohor
always @ (posedge MTxClk or posedge Reset)
1223 39 mohor
begin
1224 40 mohor
  if(Reset)
1225 39 mohor
    TxStartFrm_sync1 <=#Tp 1'b0;
1226
  else
1227
    TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
1228
end
1229 38 mohor
 
1230 40 mohor
always @ (posedge MTxClk or posedge Reset)
1231 39 mohor
begin
1232 40 mohor
  if(Reset)
1233 39 mohor
    TxStartFrm_sync2 <=#Tp 1'b0;
1234
  else
1235
    TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
1236
end
1237
 
1238 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1239 38 mohor
begin
1240 40 mohor
  if(Reset)
1241 39 mohor
    TxStartFrm_syncb1 <=#Tp 1'b0;
1242 38 mohor
  else
1243 39 mohor
    TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
1244 38 mohor
end
1245
 
1246 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1247 38 mohor
begin
1248 40 mohor
  if(Reset)
1249 39 mohor
    TxStartFrm_syncb2 <=#Tp 1'b0;
1250 38 mohor
  else
1251 39 mohor
    TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
1252
end
1253
 
1254 40 mohor
always @ (posedge MTxClk or posedge Reset)
1255 39 mohor
begin
1256 40 mohor
  if(Reset)
1257 39 mohor
    TxStartFrm <=#Tp 1'b0;
1258 38 mohor
  else
1259 39 mohor
  if(TxStartFrm_sync2)
1260 61 mohor
    TxStartFrm <=#Tp 1'b1;
1261 39 mohor
  else
1262 278 mohor
  if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
1263 39 mohor
    TxStartFrm <=#Tp 1'b0;
1264 38 mohor
end
1265 39 mohor
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1266 38 mohor
 
1267
 
1268 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1269 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1270 38 mohor
begin
1271 40 mohor
  if(Reset)
1272 39 mohor
    TxEndFrm_wb <=#Tp 1'b0;
1273 38 mohor
  else
1274 221 mohor
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
1275 39 mohor
    TxEndFrm_wb <=#Tp 1'b1;
1276 38 mohor
  else
1277 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1278
    TxEndFrm_wb <=#Tp 1'b0;
1279 38 mohor
end
1280
 
1281
 
1282
// Marks which bytes are valid within the word.
1283 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1284 38 mohor
 
1285 39 mohor
reg LatchValidBytes;
1286
reg LatchValidBytes_q;
1287 38 mohor
 
1288 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1289 38 mohor
begin
1290 40 mohor
  if(Reset)
1291 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1292 38 mohor
  else
1293 39 mohor
  if(TxLengthLt4 & TxBDReady)
1294
    LatchValidBytes <=#Tp 1'b1;
1295 38 mohor
  else
1296 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1297 38 mohor
end
1298
 
1299 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1300 38 mohor
begin
1301 40 mohor
  if(Reset)
1302 39 mohor
    LatchValidBytes_q <=#Tp 1'b0;
1303 38 mohor
  else
1304 39 mohor
    LatchValidBytes_q <=#Tp LatchValidBytes;
1305 38 mohor
end
1306
 
1307
 
1308 39 mohor
// Latching valid bytes
1309 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1310 38 mohor
begin
1311 40 mohor
  if(Reset)
1312 39 mohor
    TxValidBytesLatched <=#Tp 2'h0;
1313 38 mohor
  else
1314 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1315
    TxValidBytesLatched <=#Tp TxValidBytes;
1316
  else
1317
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1318
    TxValidBytesLatched <=#Tp 2'h0;
1319 38 mohor
end
1320
 
1321
 
1322
assign TxIRQEn          = TxStatus[14];
1323 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1324
assign PerPacketPad     = TxStatus[12];
1325
assign PerPacketCrcEn   = TxStatus[11];
1326 38 mohor
 
1327
 
1328 77 mohor
assign RxIRQEn         = RxStatus[14];
1329 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1330 38 mohor
 
1331
 
1332
// Temporary Tx and Rx buffer descriptor address 
1333 39 mohor
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite     & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
1334 134 mohor
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum<<1)     | // Using first Rx BD
1335 39 mohor
                              {8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
1336 38 mohor
 
1337
 
1338
// Latching Tx buffer descriptor address
1339 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1340 38 mohor
begin
1341 40 mohor
  if(Reset)
1342 38 mohor
    TxBDAddress <=#Tp 8'h0;
1343
  else
1344
  if(TxStatusWrite)
1345
    TxBDAddress <=#Tp TempTxBDAddress;
1346
end
1347
 
1348
 
1349
// Latching Rx buffer descriptor address
1350 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1351 38 mohor
begin
1352 40 mohor
  if(Reset)
1353 304 tadejm
    RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF_0 << 1;
1354 38 mohor
  else
1355 77 mohor
  if(TX_BD_NUM_Wr)                        // When r_TxBDNum is updated, RxBDAddress is also
1356 304 tadejm
    RxBDAddress <=#Tp WB_DAT_I[7:0] << 1;
1357 38 mohor
  else
1358
  if(RxStatusWrite)
1359
    RxBDAddress <=#Tp TempRxBDAddress;
1360
end
1361
 
1362 60 mohor
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
1363 38 mohor
 
1364 261 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
1365 60 mohor
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1366 38 mohor
 
1367 60 mohor
 
1368 38 mohor
// Signals used for various purposes
1369 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1370 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1371
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1372
 
1373
 
1374
 
1375 39 mohor
// Generating delayed signals
1376 40 mohor
always @ (posedge MTxClk or posedge Reset)
1377 38 mohor
begin
1378 40 mohor
  if(Reset)
1379 39 mohor
    begin
1380
      TxAbort_q      <=#Tp 1'b0;
1381
      TxRetry_q      <=#Tp 1'b0;
1382
      TxUsedData_q   <=#Tp 1'b0;
1383
    end
1384 38 mohor
  else
1385 39 mohor
    begin
1386
      TxAbort_q      <=#Tp TxAbort;
1387
      TxRetry_q      <=#Tp TxRetry;
1388
      TxUsedData_q   <=#Tp TxUsedData;
1389
    end
1390 38 mohor
end
1391
 
1392
// Generating delayed signals
1393 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1394 38 mohor
begin
1395 40 mohor
  if(Reset)
1396 38 mohor
    begin
1397 39 mohor
      TxDone_wb_q   <=#Tp 1'b0;
1398
      TxAbort_wb_q  <=#Tp 1'b0;
1399 40 mohor
      TxRetry_wb_q  <=#Tp 1'b0;
1400 38 mohor
    end
1401
  else
1402
    begin
1403 39 mohor
      TxDone_wb_q   <=#Tp TxDone_wb;
1404
      TxAbort_wb_q  <=#Tp TxAbort_wb;
1405 40 mohor
      TxRetry_wb_q  <=#Tp TxRetry_wb;
1406 38 mohor
    end
1407
end
1408
 
1409
 
1410 219 mohor
reg TxAbortPacketBlocked;
1411
always @ (posedge WB_CLK_I or posedge Reset)
1412
begin
1413
  if(Reset)
1414
    TxAbortPacket <=#Tp 1'b0;
1415
  else
1416 278 mohor
  if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
1417
     TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
1418 219 mohor
    TxAbortPacket <=#Tp 1'b1;
1419
  else
1420
    TxAbortPacket <=#Tp 1'b0;
1421
end
1422
 
1423
 
1424
always @ (posedge WB_CLK_I or posedge Reset)
1425
begin
1426
  if(Reset)
1427 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1428
  else
1429 272 tadejm
  if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
1430
    TxAbortPacket_NotCleared <=#Tp 1'b0;
1431
  else
1432 278 mohor
  if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
1433
     TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
1434 221 mohor
    TxAbortPacket_NotCleared <=#Tp 1'b1;
1435
end
1436
 
1437
 
1438
always @ (posedge WB_CLK_I or posedge Reset)
1439
begin
1440
  if(Reset)
1441 219 mohor
    TxAbortPacketBlocked <=#Tp 1'b0;
1442
  else
1443 280 mohor
  if(!TxAbort_wb & TxAbort_wb_q)
1444
    TxAbortPacketBlocked <=#Tp 1'b0;
1445
  else
1446 219 mohor
  if(TxAbortPacket)
1447
    TxAbortPacketBlocked <=#Tp 1'b1;
1448
end
1449
 
1450
 
1451
reg TxRetryPacketBlocked;
1452
always @ (posedge WB_CLK_I or posedge Reset)
1453
begin
1454
  if(Reset)
1455
    TxRetryPacket <=#Tp 1'b0;
1456
  else
1457 226 tadejm
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
1458
     TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1459 219 mohor
    TxRetryPacket <=#Tp 1'b1;
1460
  else
1461
    TxRetryPacket <=#Tp 1'b0;
1462
end
1463
 
1464
 
1465
always @ (posedge WB_CLK_I or posedge Reset)
1466
begin
1467
  if(Reset)
1468 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1469
  else
1470 272 tadejm
  if(StartTxBDRead)
1471
    TxRetryPacket_NotCleared <=#Tp 1'b0;
1472
  else
1473 278 mohor
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
1474
     TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
1475 221 mohor
    TxRetryPacket_NotCleared <=#Tp 1'b1;
1476
end
1477
 
1478
 
1479
always @ (posedge WB_CLK_I or posedge Reset)
1480
begin
1481
  if(Reset)
1482 219 mohor
    TxRetryPacketBlocked <=#Tp 1'b0;
1483
  else
1484 280 mohor
  if(!TxRetry_wb & TxRetry_wb_q)
1485
    TxRetryPacketBlocked <=#Tp 1'b0;
1486
  else
1487 219 mohor
  if(TxRetryPacket)
1488
    TxRetryPacketBlocked <=#Tp 1'b1;
1489
end
1490
 
1491
 
1492 221 mohor
reg TxDonePacketBlocked;
1493
always @ (posedge WB_CLK_I or posedge Reset)
1494
begin
1495
  if(Reset)
1496
    TxDonePacket <=#Tp 1'b0;
1497
  else
1498 226 tadejm
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
1499
     TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
1500 221 mohor
    TxDonePacket <=#Tp 1'b1;
1501
  else
1502
    TxDonePacket <=#Tp 1'b0;
1503
end
1504
 
1505
 
1506
always @ (posedge WB_CLK_I or posedge Reset)
1507
begin
1508
  if(Reset)
1509
    TxDonePacket_NotCleared <=#Tp 1'b0;
1510
  else
1511 272 tadejm
  if(TxEn & TxEn_q & TxDonePacket_NotCleared)
1512
    TxDonePacket_NotCleared <=#Tp 1'b0;
1513
  else
1514 278 mohor
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & (~TxDonePacketBlocked) |
1515
     TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked))
1516 221 mohor
    TxDonePacket_NotCleared <=#Tp 1'b1;
1517
end
1518
 
1519
 
1520
always @ (posedge WB_CLK_I or posedge Reset)
1521
begin
1522
  if(Reset)
1523
    TxDonePacketBlocked <=#Tp 1'b0;
1524
  else
1525 280 mohor
  if(!TxDone_wb & TxDone_wb_q)
1526
    TxDonePacketBlocked <=#Tp 1'b0;
1527
  else
1528 221 mohor
  if(TxDonePacket)
1529
    TxDonePacketBlocked <=#Tp 1'b1;
1530
end
1531
 
1532
 
1533 38 mohor
// Indication of the last word
1534 40 mohor
always @ (posedge MTxClk or posedge Reset)
1535 38 mohor
begin
1536 40 mohor
  if(Reset)
1537 38 mohor
    LastWord <=#Tp 1'b0;
1538
  else
1539
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1540
    LastWord <=#Tp 1'b0;
1541
  else
1542
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1543 39 mohor
    LastWord <=#Tp TxEndFrm_wb;
1544 38 mohor
end
1545
 
1546
 
1547
// Tx end frame generation
1548 40 mohor
always @ (posedge MTxClk or posedge Reset)
1549 38 mohor
begin
1550 40 mohor
  if(Reset)
1551 38 mohor
    TxEndFrm <=#Tp 1'b0;
1552
  else
1553 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1554 38 mohor
    TxEndFrm <=#Tp 1'b0;
1555
  else
1556
  if(Flop & LastWord)
1557
    begin
1558 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1559 38 mohor
        1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
1560
        2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
1561
        3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
1562
 
1563
        default : TxEndFrm <=#Tp 1'b0;
1564
      endcase
1565
    end
1566
end
1567
 
1568
 
1569
// Tx data selection (latching)
1570 40 mohor
always @ (posedge MTxClk or posedge Reset)
1571 38 mohor
begin
1572 40 mohor
  if(Reset)
1573 96 mohor
    TxData <=#Tp 0;
1574 38 mohor
  else
1575 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1576 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1577 96 mohor
      2'h0 : TxData <=#Tp TxData_wb[31:24];                  // Big Endian Byte Ordering
1578
      2'h1 : TxData <=#Tp TxData_wb[23:16];                  // Big Endian Byte Ordering
1579
      2'h2 : TxData <=#Tp TxData_wb[15:08];                  // Big Endian Byte Ordering
1580
      2'h3 : TxData <=#Tp TxData_wb[07:00];                  // Big Endian Byte Ordering
1581
    endcase
1582 38 mohor
  else
1583 159 mohor
  if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
1584 96 mohor
    TxData <=#Tp TxData_wb[31:24];                           // Big Endian Byte Ordering
1585
  else
1586 38 mohor
  if(TxUsedData & Flop)
1587
    begin
1588 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1589 226 tadejm
 
1590 82 mohor
        1 : TxData <=#Tp TxDataLatched[23:16];
1591
        2 : TxData <=#Tp TxDataLatched[15:8];
1592
        3 : TxData <=#Tp TxDataLatched[7:0];
1593 38 mohor
      endcase
1594
    end
1595
end
1596
 
1597
 
1598
// Latching tx data
1599 40 mohor
always @ (posedge MTxClk or posedge Reset)
1600 38 mohor
begin
1601 40 mohor
  if(Reset)
1602 38 mohor
    TxDataLatched[31:0] <=#Tp 32'h0;
1603
  else
1604 96 mohor
 if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1605 39 mohor
    TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
1606 38 mohor
end
1607
 
1608
 
1609
// Tx under run
1610 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1611 38 mohor
begin
1612 40 mohor
  if(Reset)
1613 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1614 38 mohor
  else
1615 39 mohor
  if(TxAbortPulse)
1616 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1617
  else
1618
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1619
    TxUnderRun_wb <=#Tp 1'b1;
1620
end
1621
 
1622
 
1623 159 mohor
reg TxUnderRun_sync1;
1624
 
1625 60 mohor
// Tx under run
1626
always @ (posedge MTxClk or posedge Reset)
1627
begin
1628
  if(Reset)
1629 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b0;
1630 43 mohor
  else
1631 60 mohor
  if(TxUnderRun_wb)
1632 159 mohor
    TxUnderRun_sync1 <=#Tp 1'b1;
1633 60 mohor
  else
1634 159 mohor
  if(BlockingTxStatusWrite_sync2)
1635
    TxUnderRun_sync1 <=#Tp 1'b0;
1636
end
1637
 
1638
// Tx under run
1639
always @ (posedge MTxClk or posedge Reset)
1640
begin
1641
  if(Reset)
1642 60 mohor
    TxUnderRun <=#Tp 1'b0;
1643 159 mohor
  else
1644
  if(BlockingTxStatusWrite_sync2)
1645
    TxUnderRun <=#Tp 1'b0;
1646
  else
1647
  if(TxUnderRun_sync1)
1648
    TxUnderRun <=#Tp 1'b1;
1649 38 mohor
end
1650
 
1651
 
1652
// Tx Byte counter
1653 40 mohor
always @ (posedge MTxClk or posedge Reset)
1654 38 mohor
begin
1655 40 mohor
  if(Reset)
1656 38 mohor
    TxByteCnt <=#Tp 2'h0;
1657
  else
1658
  if(TxAbort_q | TxRetry_q)
1659
    TxByteCnt <=#Tp 2'h0;
1660
  else
1661
  if(TxStartFrm & ~TxUsedData)
1662 159 mohor
    case(TxPointerLSB)  // synopsys parallel_case
1663 96 mohor
      2'h0 : TxByteCnt <=#Tp 2'h1;
1664
      2'h1 : TxByteCnt <=#Tp 2'h2;
1665
      2'h2 : TxByteCnt <=#Tp 2'h3;
1666
      2'h3 : TxByteCnt <=#Tp 2'h0;
1667
    endcase
1668 38 mohor
  else
1669
  if(TxUsedData & Flop)
1670 96 mohor
    TxByteCnt <=#Tp TxByteCnt + 1'b1;
1671 38 mohor
end
1672
 
1673 39 mohor
 
1674 150 mohor
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1675
reg ReadTxDataFromFifo_sync1;
1676
reg ReadTxDataFromFifo_sync2;
1677
reg ReadTxDataFromFifo_sync3;
1678
reg ReadTxDataFromFifo_syncb1;
1679
reg ReadTxDataFromFifo_syncb2;
1680
reg ReadTxDataFromFifo_syncb3;
1681
 
1682
 
1683
always @ (posedge MTxClk or posedge Reset)
1684
begin
1685
  if(Reset)
1686
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1687
  else
1688 96 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1689 39 mohor
     ReadTxDataFromFifo_tck <=#Tp 1'b1;
1690 150 mohor
  else
1691
  if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
1692
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1693 38 mohor
end
1694
 
1695 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1696 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1697 38 mohor
begin
1698 40 mohor
  if(Reset)
1699 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
1700 38 mohor
  else
1701 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
1702
end
1703 38 mohor
 
1704 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1705 38 mohor
begin
1706 40 mohor
  if(Reset)
1707 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
1708 38 mohor
  else
1709 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
1710 38 mohor
end
1711
 
1712 40 mohor
always @ (posedge MTxClk or posedge Reset)
1713 38 mohor
begin
1714 40 mohor
  if(Reset)
1715 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
1716 38 mohor
  else
1717 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
1718 38 mohor
end
1719
 
1720 40 mohor
always @ (posedge MTxClk or posedge Reset)
1721 38 mohor
begin
1722 40 mohor
  if(Reset)
1723 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
1724 38 mohor
  else
1725 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
1726 38 mohor
end
1727
 
1728 150 mohor
always @ (posedge MTxClk or posedge Reset)
1729
begin
1730
  if(Reset)
1731
    ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
1732
  else
1733
    ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
1734
end
1735
 
1736 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1737 38 mohor
begin
1738 40 mohor
  if(Reset)
1739 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
1740 38 mohor
  else
1741 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
1742 38 mohor
end
1743
 
1744 39 mohor
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
1745
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1746 38 mohor
 
1747
 
1748 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1749 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1750 38 mohor
begin
1751 40 mohor
  if(Reset)
1752 39 mohor
    TxRetrySync1 <=#Tp 1'b0;
1753 38 mohor
  else
1754 39 mohor
    TxRetrySync1 <=#Tp TxRetry;
1755 38 mohor
end
1756
 
1757 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1758 38 mohor
begin
1759 40 mohor
  if(Reset)
1760 39 mohor
    TxRetry_wb <=#Tp 1'b0;
1761 38 mohor
  else
1762 39 mohor
    TxRetry_wb <=#Tp TxRetrySync1;
1763 38 mohor
end
1764
 
1765
 
1766 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1767 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1768 38 mohor
begin
1769 40 mohor
  if(Reset)
1770 39 mohor
    TxDoneSync1 <=#Tp 1'b0;
1771 38 mohor
  else
1772 39 mohor
    TxDoneSync1 <=#Tp TxDone;
1773 38 mohor
end
1774
 
1775 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1776 38 mohor
begin
1777 40 mohor
  if(Reset)
1778 39 mohor
    TxDone_wb <=#Tp 1'b0;
1779 38 mohor
  else
1780 39 mohor
    TxDone_wb <=#Tp TxDoneSync1;
1781 38 mohor
end
1782
 
1783 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1784 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1785 38 mohor
begin
1786 40 mohor
  if(Reset)
1787 39 mohor
    TxAbortSync1 <=#Tp 1'b0;
1788 38 mohor
  else
1789 39 mohor
    TxAbortSync1 <=#Tp TxAbort;
1790 38 mohor
end
1791
 
1792 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1793 38 mohor
begin
1794 40 mohor
  if(Reset)
1795 38 mohor
    TxAbort_wb <=#Tp 1'b0;
1796
  else
1797 39 mohor
    TxAbort_wb <=#Tp TxAbortSync1;
1798 38 mohor
end
1799
 
1800
 
1801 150 mohor
reg RxAbortSync1;
1802
reg RxAbortSync2;
1803
reg RxAbortSync3;
1804
reg RxAbortSync4;
1805
reg RxAbortSyncb1;
1806
reg RxAbortSyncb2;
1807 39 mohor
 
1808 150 mohor
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
1809
 
1810 40 mohor
// Reading the Rx buffer descriptor
1811
always @ (posedge WB_CLK_I or posedge Reset)
1812
begin
1813
  if(Reset)
1814
    RxBDRead <=#Tp 1'b1;
1815
  else
1816 166 mohor
  if(StartRxBDRead & ~RxReady)
1817 40 mohor
    RxBDRead <=#Tp 1'b1;
1818
  else
1819
  if(RxBDReady)
1820
    RxBDRead <=#Tp 1'b0;
1821
end
1822 39 mohor
 
1823
 
1824 38 mohor
// Reading of the next receive buffer descriptor starts after reception status is
1825
// written to the previous one.
1826
 
1827
// Latching READY status of the Rx buffer descriptor
1828 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1829 38 mohor
begin
1830 40 mohor
  if(Reset)
1831 38 mohor
    RxBDReady <=#Tp 1'b0;
1832
  else
1833 166 mohor
  if(RxPointerRead)
1834 150 mohor
    RxBDReady <=#Tp 1'b0;
1835
  else
1836 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1837
    RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
1838 38 mohor
end
1839
 
1840 40 mohor
// Latching Rx buffer descriptor status
1841
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
1842
always @ (posedge WB_CLK_I or posedge Reset)
1843 38 mohor
begin
1844 40 mohor
  if(Reset)
1845 60 mohor
    RxStatus <=#Tp 2'h0;
1846 38 mohor
  else
1847 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1848 60 mohor
    RxStatus <=#Tp ram_do[14:13];
1849 38 mohor
end
1850
 
1851
 
1852 166 mohor
// RxReady generation
1853
always @ (posedge WB_CLK_I or posedge Reset)
1854
begin
1855
  if(Reset)
1856
    RxReady <=#Tp 1'b0;
1857
  else
1858
  if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3)
1859
    RxReady <=#Tp 1'b0;
1860
  else
1861
  if(RxEn & RxEn_q & RxPointerRead)
1862
    RxReady <=#Tp 1'b1;
1863
end
1864 38 mohor
 
1865
 
1866 40 mohor
// Reading Rx BD pointer
1867
 
1868
 
1869
assign StartRxPointerRead = RxBDRead & RxBDReady;
1870
 
1871
// Reading Tx BD Pointer
1872
always @ (posedge WB_CLK_I or posedge Reset)
1873 38 mohor
begin
1874 40 mohor
  if(Reset)
1875
    RxPointerRead <=#Tp 1'b0;
1876 38 mohor
  else
1877 40 mohor
  if(StartRxPointerRead)
1878
    RxPointerRead <=#Tp 1'b1;
1879 38 mohor
  else
1880 166 mohor
  if(RxEn & RxEn_q)
1881 40 mohor
    RxPointerRead <=#Tp 1'b0;
1882 38 mohor
end
1883
 
1884 113 mohor
 
1885 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
1886
always @ (posedge WB_CLK_I or posedge Reset)
1887
begin
1888
  if(Reset)
1889 159 mohor
    RxPointerMSB <=#Tp 30'h0;
1890 40 mohor
  else
1891
  if(RxEn & RxEn_q & RxPointerRead)
1892 159 mohor
    RxPointerMSB <=#Tp ram_do[31:2];
1893 40 mohor
  else
1894 113 mohor
  if(MasterWbRX & m_wb_ack_i)
1895 159 mohor
      RxPointerMSB <=#Tp RxPointerMSB + 1; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
1896 40 mohor
end
1897 38 mohor
 
1898
 
1899 96 mohor
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
1900 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1901
begin
1902
  if(Reset)
1903 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp 0;
1904 96 mohor
  else
1905 159 mohor
  if(MasterWbRX & m_wb_ack_i)                 // After first write all RxByteSel are active
1906
    RxPointerLSB_rst[1:0] <=#Tp 0;
1907 96 mohor
  else
1908
  if(RxEn & RxEn_q & RxPointerRead)
1909 159 mohor
    RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
1910 96 mohor
end
1911
 
1912
 
1913 159 mohor
always @ (RxPointerLSB_rst)
1914 96 mohor
begin
1915 159 mohor
  case(RxPointerLSB_rst[1:0])  // synopsys parallel_case
1916
    2'h0 : RxByteSel[3:0] = 4'hf;
1917
    2'h1 : RxByteSel[3:0] = 4'h7;
1918
    2'h2 : RxByteSel[3:0] = 4'h3;
1919
    2'h3 : RxByteSel[3:0] = 4'h1;
1920 96 mohor
  endcase
1921
end
1922
 
1923
 
1924
always @ (posedge WB_CLK_I or posedge Reset)
1925
begin
1926
  if(Reset)
1927 40 mohor
    RxEn_needed <=#Tp 1'b0;
1928 38 mohor
  else
1929 166 mohor
  if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
1930 40 mohor
    RxEn_needed <=#Tp 1'b1;
1931 38 mohor
  else
1932 40 mohor
  if(RxPointerRead & RxEn & RxEn_q)
1933
    RxEn_needed <=#Tp 1'b0;
1934 38 mohor
end
1935
 
1936
 
1937 40 mohor
// Reception status is written back to the buffer descriptor after the end of frame is detected.
1938
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
1939 38 mohor
 
1940 40 mohor
reg RxEnableWindow;
1941 38 mohor
 
1942
// Indicating that last byte is being reveived
1943 40 mohor
always @ (posedge MRxClk or posedge Reset)
1944 38 mohor
begin
1945 40 mohor
  if(Reset)
1946 38 mohor
    LastByteIn <=#Tp 1'b0;
1947
  else
1948 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
1949 38 mohor
    LastByteIn <=#Tp 1'b0;
1950
  else
1951 166 mohor
  if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
1952 38 mohor
    LastByteIn <=#Tp 1'b1;
1953
end
1954
 
1955 159 mohor
reg ShiftEnded_rck;
1956 40 mohor
reg ShiftEndedSync1;
1957
reg ShiftEndedSync2;
1958 118 mohor
reg ShiftEndedSync3;
1959
reg ShiftEndedSync_c1;
1960
reg ShiftEndedSync_c2;
1961
 
1962 40 mohor
wire StartShiftWillEnd;
1963 96 mohor
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
1964 38 mohor
 
1965
// Indicating that data reception will end
1966 40 mohor
always @ (posedge MRxClk or posedge Reset)
1967 38 mohor
begin
1968 40 mohor
  if(Reset)
1969 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1970
  else
1971 159 mohor
  if(ShiftEnded_rck | RxAbort)
1972 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1973
  else
1974 40 mohor
  if(StartShiftWillEnd)
1975 38 mohor
    ShiftWillEnd <=#Tp 1'b1;
1976
end
1977
 
1978
 
1979 40 mohor
 
1980 38 mohor
// Receive byte counter
1981 40 mohor
always @ (posedge MRxClk or posedge Reset)
1982 38 mohor
begin
1983 40 mohor
  if(Reset)
1984 38 mohor
    RxByteCnt <=#Tp 2'h0;
1985
  else
1986 159 mohor
  if(ShiftEnded_rck | RxAbort)
1987 38 mohor
    RxByteCnt <=#Tp 2'h0;
1988 97 lampret
  else
1989 166 mohor
  if(RxValid & RxStartFrm & RxReady)
1990 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
1991 96 mohor
      2'h0 : RxByteCnt <=#Tp 2'h1;
1992
      2'h1 : RxByteCnt <=#Tp 2'h2;
1993
      2'h2 : RxByteCnt <=#Tp 2'h3;
1994
      2'h3 : RxByteCnt <=#Tp 2'h0;
1995
    endcase
1996 38 mohor
  else
1997 166 mohor
  if(RxValid & RxEnableWindow & RxReady | LastByteIn)
1998 40 mohor
    RxByteCnt <=#Tp RxByteCnt + 1'b1;
1999 38 mohor
end
2000
 
2001
 
2002
// Indicates how many bytes are valid within the last word
2003 40 mohor
always @ (posedge MRxClk or posedge Reset)
2004 38 mohor
begin
2005 40 mohor
  if(Reset)
2006 38 mohor
    RxValidBytes <=#Tp 2'h1;
2007
  else
2008 96 mohor
  if(RxValid & RxStartFrm)
2009 159 mohor
    case(RxPointerLSB_rst)  // synopsys parallel_case
2010 96 mohor
      2'h0 : RxValidBytes <=#Tp 2'h1;
2011
      2'h1 : RxValidBytes <=#Tp 2'h2;
2012
      2'h2 : RxValidBytes <=#Tp 2'h3;
2013
      2'h3 : RxValidBytes <=#Tp 2'h0;
2014
    endcase
2015 38 mohor
  else
2016 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
2017 38 mohor
    RxValidBytes <=#Tp RxValidBytes + 1;
2018
end
2019
 
2020
 
2021 40 mohor
always @ (posedge MRxClk or posedge Reset)
2022 38 mohor
begin
2023 40 mohor
  if(Reset)
2024
    RxDataLatched1       <=#Tp 24'h0;
2025 38 mohor
  else
2026 166 mohor
  if(RxValid & RxReady & ~LastByteIn)
2027 96 mohor
    if(RxStartFrm)
2028 40 mohor
    begin
2029 159 mohor
      case(RxPointerLSB_rst)     // synopsys parallel_case
2030 96 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2031
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2032
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2033
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2034
      endcase
2035
    end
2036
    else if (RxEnableWindow)
2037
    begin
2038 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
2039 82 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
2040
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
2041
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
2042 40 mohor
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
2043
      endcase
2044
    end
2045 38 mohor
end
2046
 
2047 40 mohor
wire SetWriteRxDataToFifo;
2048 38 mohor
 
2049 40 mohor
// Assembling data that will be written to the rx_fifo
2050
always @ (posedge MRxClk or posedge Reset)
2051 38 mohor
begin
2052 40 mohor
  if(Reset)
2053
    RxDataLatched2 <=#Tp 32'h0;
2054 38 mohor
  else
2055 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
2056 82 mohor
    RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData};              // Big Endian Byte Ordering
2057 38 mohor
  else
2058 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
2059 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
2060 82 mohor
 
2061
      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
2062
      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
2063
      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};
2064 40 mohor
    endcase
2065 38 mohor
end
2066
 
2067
 
2068 40 mohor
reg WriteRxDataToFifoSync1;
2069
reg WriteRxDataToFifoSync2;
2070 150 mohor
reg WriteRxDataToFifoSync3;
2071 38 mohor
 
2072
 
2073 40 mohor
// Indicating start of the reception process
2074 166 mohor
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
2075
                              (RxValid & RxReady &  RxStartFrm & (&RxPointerLSB_rst))           |
2076
                              (ShiftWillEnd & LastByteIn & (&RxByteCnt));
2077 38 mohor
 
2078 150 mohor
always @ (posedge MRxClk or posedge Reset)
2079
begin
2080
  if(Reset)
2081
    WriteRxDataToFifo <=#Tp 1'b0;
2082
  else
2083
  if(SetWriteRxDataToFifo & ~RxAbort)
2084
    WriteRxDataToFifo <=#Tp 1'b1;
2085
  else
2086
  if(WriteRxDataToFifoSync2 | RxAbort)
2087
    WriteRxDataToFifo <=#Tp 1'b0;
2088
end
2089 40 mohor
 
2090 150 mohor
 
2091
 
2092
always @ (posedge WB_CLK_I or posedge Reset)
2093
begin
2094
  if(Reset)
2095
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2096
  else
2097
  if(WriteRxDataToFifo)
2098
    WriteRxDataToFifoSync1 <=#Tp 1'b1;
2099
  else
2100
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
2101
end
2102
 
2103
always @ (posedge WB_CLK_I or posedge Reset)
2104
begin
2105
  if(Reset)
2106
    WriteRxDataToFifoSync2 <=#Tp 1'b0;
2107
  else
2108
    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
2109
end
2110
 
2111
always @ (posedge WB_CLK_I or posedge Reset)
2112
begin
2113
  if(Reset)
2114
    WriteRxDataToFifoSync3 <=#Tp 1'b0;
2115
  else
2116
    WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
2117
end
2118
 
2119
wire WriteRxDataToFifo_wb;
2120
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
2121
 
2122
 
2123 90 mohor
reg LatchedRxStartFrm;
2124
reg SyncRxStartFrm;
2125
reg SyncRxStartFrm_q;
2126 150 mohor
reg SyncRxStartFrm_q2;
2127 90 mohor
wire RxFifoReset;
2128 40 mohor
 
2129 90 mohor
always @ (posedge MRxClk or posedge Reset)
2130
begin
2131
  if(Reset)
2132
    LatchedRxStartFrm <=#Tp 0;
2133
  else
2134 150 mohor
  if(RxStartFrm & ~SyncRxStartFrm_q)
2135 90 mohor
    LatchedRxStartFrm <=#Tp 1;
2136
  else
2137 150 mohor
  if(SyncRxStartFrm_q)
2138 90 mohor
    LatchedRxStartFrm <=#Tp 0;
2139
end
2140
 
2141
 
2142
always @ (posedge WB_CLK_I or posedge Reset)
2143
begin
2144
  if(Reset)
2145
    SyncRxStartFrm <=#Tp 0;
2146
  else
2147
  if(LatchedRxStartFrm)
2148
    SyncRxStartFrm <=#Tp 1;
2149
  else
2150
    SyncRxStartFrm <=#Tp 0;
2151
end
2152
 
2153
 
2154
always @ (posedge WB_CLK_I or posedge Reset)
2155
begin
2156
  if(Reset)
2157
    SyncRxStartFrm_q <=#Tp 0;
2158
  else
2159
    SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
2160
end
2161
 
2162 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2163
begin
2164
  if(Reset)
2165
    SyncRxStartFrm_q2 <=#Tp 0;
2166
  else
2167
    SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
2168
end
2169 90 mohor
 
2170
 
2171 150 mohor
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
2172 90 mohor
 
2173 150 mohor
 
2174 219 mohor
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
2175 88 mohor
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
2176
         .clk(WB_CLK_I),                                .reset(Reset),
2177 219 mohor
         .write(WriteRxDataToFifo_wb & ~RxBufferFull),  .read(MasterWbRX & m_wb_ack_i),
2178 90 mohor
         .clear(RxFifoReset),                           .full(RxBufferFull),
2179 118 mohor
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
2180 150 mohor
         .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)
2181 88 mohor
        );
2182 40 mohor
 
2183 226 tadejm
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
2184
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
2185 219 mohor
assign WriteRxDataToMemory = ~RxBufferEmpty;
2186 226 tadejm
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
2187 40 mohor
 
2188
 
2189
// Generation of the end-of-frame signal
2190
always @ (posedge MRxClk or posedge Reset)
2191 38 mohor
begin
2192 40 mohor
  if(Reset)
2193 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2194 38 mohor
  else
2195 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
2196 159 mohor
    ShiftEnded_rck <=#Tp 1'b1;
2197 38 mohor
  else
2198 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
2199 159 mohor
    ShiftEnded_rck <=#Tp 1'b0;
2200 38 mohor
end
2201
 
2202 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2203
begin
2204
  if(Reset)
2205
    ShiftEndedSync1 <=#Tp 1'b0;
2206
  else
2207 159 mohor
    ShiftEndedSync1 <=#Tp ShiftEnded_rck;
2208 40 mohor
end
2209 38 mohor
 
2210 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2211 38 mohor
begin
2212 40 mohor
  if(Reset)
2213
    ShiftEndedSync2 <=#Tp 1'b0;
2214 38 mohor
  else
2215 90 mohor
    ShiftEndedSync2 <=#Tp ShiftEndedSync1;
2216 40 mohor
end
2217 38 mohor
 
2218 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2219
begin
2220
  if(Reset)
2221
    ShiftEndedSync3 <=#Tp 1'b0;
2222
  else
2223
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
2224
    ShiftEndedSync3 <=#Tp 1'b1;
2225
  else
2226
  if(ShiftEnded)
2227
    ShiftEndedSync3 <=#Tp 1'b0;
2228
end
2229 38 mohor
 
2230 40 mohor
// Generation of the end-of-frame signal
2231
always @ (posedge WB_CLK_I or posedge Reset)
2232 38 mohor
begin
2233 40 mohor
  if(Reset)
2234
    ShiftEnded <=#Tp 1'b0;
2235 38 mohor
  else
2236 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
2237 40 mohor
    ShiftEnded <=#Tp 1'b1;
2238 38 mohor
  else
2239 40 mohor
  if(RxStatusWrite)
2240
    ShiftEnded <=#Tp 1'b0;
2241 38 mohor
end
2242
 
2243 118 mohor
always @ (posedge MRxClk or posedge Reset)
2244
begin
2245
  if(Reset)
2246
    ShiftEndedSync_c1 <=#Tp 1'b0;
2247
  else
2248
    ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
2249
end
2250 38 mohor
 
2251 118 mohor
always @ (posedge MRxClk or posedge Reset)
2252
begin
2253
  if(Reset)
2254
    ShiftEndedSync_c2 <=#Tp 1'b0;
2255
  else
2256
    ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
2257
end
2258
 
2259 40 mohor
// Generation of the end-of-frame signal
2260
always @ (posedge MRxClk or posedge Reset)
2261 38 mohor
begin
2262 40 mohor
  if(Reset)
2263
    RxEnableWindow <=#Tp 1'b0;
2264 38 mohor
  else
2265 40 mohor
  if(RxStartFrm)
2266
    RxEnableWindow <=#Tp 1'b1;
2267 38 mohor
  else
2268 40 mohor
  if(RxEndFrm | RxAbort)
2269
    RxEnableWindow <=#Tp 1'b0;
2270 38 mohor
end
2271
 
2272
 
2273 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2274 38 mohor
begin
2275 40 mohor
  if(Reset)
2276
    RxAbortSync1 <=#Tp 1'b0;
2277 38 mohor
  else
2278 150 mohor
    RxAbortSync1 <=#Tp RxAbortLatched;
2279 40 mohor
end
2280
 
2281
always @ (posedge WB_CLK_I or posedge Reset)
2282
begin
2283
  if(Reset)
2284
    RxAbortSync2 <=#Tp 1'b0;
2285 38 mohor
  else
2286 40 mohor
    RxAbortSync2 <=#Tp RxAbortSync1;
2287 38 mohor
end
2288
 
2289 150 mohor
always @ (posedge WB_CLK_I or posedge Reset)
2290
begin
2291
  if(Reset)
2292
    RxAbortSync3 <=#Tp 1'b0;
2293
  else
2294
    RxAbortSync3 <=#Tp RxAbortSync2;
2295
end
2296
 
2297
always @ (posedge WB_CLK_I or posedge Reset)
2298
begin
2299
  if(Reset)
2300
    RxAbortSync4 <=#Tp 1'b0;
2301
  else
2302
    RxAbortSync4 <=#Tp RxAbortSync3;
2303
end
2304
 
2305 40 mohor
always @ (posedge MRxClk or posedge Reset)
2306
begin
2307
  if(Reset)
2308
    RxAbortSyncb1 <=#Tp 1'b0;
2309
  else
2310
    RxAbortSyncb1 <=#Tp RxAbortSync2;
2311
end
2312 38 mohor
 
2313 40 mohor
always @ (posedge MRxClk or posedge Reset)
2314 38 mohor
begin
2315 40 mohor
  if(Reset)
2316
    RxAbortSyncb2 <=#Tp 1'b0;
2317 38 mohor
  else
2318 40 mohor
    RxAbortSyncb2 <=#Tp RxAbortSyncb1;
2319 38 mohor
end
2320
 
2321
 
2322 64 mohor
always @ (posedge MRxClk or posedge Reset)
2323
begin
2324
  if(Reset)
2325
    RxAbortLatched <=#Tp 1'b0;
2326
  else
2327 150 mohor
  if(RxAbortSyncb2)
2328
    RxAbortLatched <=#Tp 1'b0;
2329
  else
2330 64 mohor
  if(RxAbort)
2331
    RxAbortLatched <=#Tp 1'b1;
2332
end
2333 40 mohor
 
2334 64 mohor
 
2335 42 mohor
always @ (posedge MRxClk or posedge Reset)
2336
begin
2337
  if(Reset)
2338
    LatchedRxLength[15:0] <=#Tp 16'h0;
2339
  else
2340 150 mohor
  if(LoadRxStatus)
2341 42 mohor
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
2342
end
2343
 
2344
 
2345 261 mohor
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
2346 42 mohor
 
2347
always @ (posedge MRxClk or posedge Reset)
2348
begin
2349
  if(Reset)
2350
    RxStatusInLatched <=#Tp 'h0;
2351
  else
2352 150 mohor
  if(LoadRxStatus)
2353 42 mohor
    RxStatusInLatched <=#Tp RxStatusIn;
2354
end
2355
 
2356
 
2357 60 mohor
// Rx overrun
2358
always @ (posedge WB_CLK_I or posedge Reset)
2359
begin
2360
  if(Reset)
2361
    RxOverrun <=#Tp 1'b0;
2362
  else
2363
  if(RxStatusWrite)
2364
    RxOverrun <=#Tp 1'b0;
2365
  else
2366
  if(RxBufferFull & WriteRxDataToFifo_wb)
2367
    RxOverrun <=#Tp 1'b1;
2368
end
2369 48 mohor
 
2370 77 mohor
 
2371
 
2372
wire TxError;
2373
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2374
 
2375
wire RxError;
2376
 
2377 239 tadejm
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
2378 250 mohor
// are aborted when signal r_RecSmall is set to 0 in MODER register. 
2379
// AddressMiss is identifying that a frame was received because of the promiscous
2380
// mode and is not an error
2381 239 tadejm
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
2382
 
2383 272 tadejm
 
2384
 
2385
reg RxStatusWriteLatched;
2386
reg RxStatusWriteLatched_sync1;
2387
reg RxStatusWriteLatched_sync2;
2388
reg RxStatusWriteLatched_syncb1;
2389
reg RxStatusWriteLatched_syncb2;
2390
 
2391
 
2392
// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
2393
always @ (posedge WB_CLK_I or posedge Reset)
2394
begin
2395
  if(Reset)
2396
    RxStatusWriteLatched <=#Tp 1'b0;
2397
  else
2398
  if(RxStatusWriteLatched_syncb2)
2399
    RxStatusWriteLatched <=#Tp 1'b0;
2400
  else
2401
  if(RxStatusWrite)
2402
    RxStatusWriteLatched <=#Tp 1'b1;
2403
end
2404
 
2405
 
2406
always @ (posedge MRxClk or posedge Reset)
2407
begin
2408
  if(Reset)
2409
    begin
2410
      RxStatusWriteLatched_sync1 <=#Tp 1'b0;
2411
      RxStatusWriteLatched_sync2 <=#Tp 1'b0;
2412
    end
2413
  else
2414
    begin
2415
      RxStatusWriteLatched_sync1 <=#Tp RxStatusWriteLatched;
2416
      RxStatusWriteLatched_sync2 <=#Tp RxStatusWriteLatched_sync1;
2417
    end
2418
end
2419
 
2420
 
2421
always @ (posedge WB_CLK_I or posedge Reset)
2422
begin
2423
  if(Reset)
2424
    begin
2425
      RxStatusWriteLatched_syncb1 <=#Tp 1'b0;
2426
      RxStatusWriteLatched_syncb2 <=#Tp 1'b0;
2427
    end
2428
  else
2429
    begin
2430
      RxStatusWriteLatched_syncb1 <=#Tp RxStatusWriteLatched_sync2;
2431
      RxStatusWriteLatched_syncb2 <=#Tp RxStatusWriteLatched_syncb1;
2432
    end
2433
end
2434
 
2435
 
2436
 
2437 77 mohor
// Tx Done Interrupt
2438
always @ (posedge WB_CLK_I or posedge Reset)
2439
begin
2440
  if(Reset)
2441
    TxB_IRQ <=#Tp 1'b0;
2442
  else
2443
  if(TxStatusWrite & TxIRQEn)
2444
    TxB_IRQ <=#Tp ~TxError;
2445
  else
2446
    TxB_IRQ <=#Tp 1'b0;
2447
end
2448
 
2449
 
2450
// Tx Error Interrupt
2451
always @ (posedge WB_CLK_I or posedge Reset)
2452
begin
2453
  if(Reset)
2454
    TxE_IRQ <=#Tp 1'b0;
2455
  else
2456
  if(TxStatusWrite & TxIRQEn)
2457
    TxE_IRQ <=#Tp TxError;
2458
  else
2459
    TxE_IRQ <=#Tp 1'b0;
2460
end
2461
 
2462
 
2463
// Rx Done Interrupt
2464
always @ (posedge WB_CLK_I or posedge Reset)
2465
begin
2466
  if(Reset)
2467
    RxB_IRQ <=#Tp 1'b0;
2468
  else
2469 270 mohor
  if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
2470
    RxB_IRQ <=#Tp (~RxError);
2471 77 mohor
  else
2472
    RxB_IRQ <=#Tp 1'b0;
2473
end
2474
 
2475
 
2476
// Rx Error Interrupt
2477
always @ (posedge WB_CLK_I or posedge Reset)
2478
begin
2479
  if(Reset)
2480
    RxE_IRQ <=#Tp 1'b0;
2481
  else
2482 270 mohor
  if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
2483 77 mohor
    RxE_IRQ <=#Tp RxError;
2484
  else
2485
    RxE_IRQ <=#Tp 1'b0;
2486
end
2487
 
2488
 
2489 166 mohor
// Busy Interrupt
2490 77 mohor
 
2491 166 mohor
reg Busy_IRQ_rck;
2492
reg Busy_IRQ_sync1;
2493
reg Busy_IRQ_sync2;
2494
reg Busy_IRQ_sync3;
2495
reg Busy_IRQ_syncb1;
2496
reg Busy_IRQ_syncb2;
2497 77 mohor
 
2498
 
2499 166 mohor
always @ (posedge MRxClk or posedge Reset)
2500
begin
2501
  if(Reset)
2502
    Busy_IRQ_rck <=#Tp 1'b0;
2503
  else
2504
  if(RxValid & RxStartFrm & ~RxReady)
2505
    Busy_IRQ_rck <=#Tp 1'b1;
2506
  else
2507
  if(Busy_IRQ_syncb2)
2508
    Busy_IRQ_rck <=#Tp 1'b0;
2509
end
2510 77 mohor
 
2511 166 mohor
always @ (posedge WB_CLK_I)
2512
begin
2513
    Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
2514
    Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
2515
    Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
2516
end
2517
 
2518
always @ (posedge MRxClk)
2519
begin
2520
    Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
2521
    Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
2522
end
2523
 
2524
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
2525
 
2526
 
2527 60 mohor
 
2528
 
2529
 
2530 38 mohor
endmodule

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